[deliverable/linux.git] / sound / soc / codecs / uda134x.c

/*
 * uda134x.c  --  UDA134X ALSA SoC Codec driver
 *
 * Modifications by Christian Pellegrin <chripell@evolware.org>
 *
 * Copyright 2007 Dension Audio Systems Ltd.
 * Author: Zoltan Devai
 *
 * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/initval.h>

#include <sound/uda134x.h>
#include <sound/l3.h>

#include "uda134x.h"


#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
		SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)

struct uda134x_priv {
	int sysclk;
	int dai_fmt;

	struct snd_pcm_substream *master_substream;
	struct snd_pcm_substream *slave_substream;
};

/* In-data addresses are hard-coded into the reg-cache values */
static const char uda134x_reg[UDA134X_REGS_NUM] = {
	/* Extended address registers */
	0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* Status, data regs */
	0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
};

/*
 * The codec has no support for reading its registers except for peak level...
 */
static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
	unsigned int reg)
{
	u8 *cache = codec->reg_cache;

	if (reg >= UDA134X_REGS_NUM)
		return -1;
	return cache[reg];
}

/*
 * Write the register cache
 */
static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
	u8 reg, unsigned int value)
{
	u8 *cache = codec->reg_cache;

	if (reg >= UDA134X_REGS_NUM)
		return;
	cache[reg] = value;
}

/*
 * Write to the uda134x registers
 *
 */
static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
	unsigned int value)
{
	int ret;
	u8 addr;
	u8 data = value;
	struct uda134x_platform_data *pd = codec->control_data;

	pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);

	if (reg >= UDA134X_REGS_NUM) {
		printk(KERN_ERR "%s unknown register: reg: %u",
		       __func__, reg);
		return -EINVAL;
	}

	uda134x_write_reg_cache(codec, reg, value);

	switch (reg) {
	case UDA134X_STATUS0:
	case UDA134X_STATUS1:
		addr = UDA134X_STATUS_ADDR;
		break;
	case UDA134X_DATA000:
	case UDA134X_DATA001:
	case UDA134X_DATA010:
	case UDA134X_DATA011:
		addr = UDA134X_DATA0_ADDR;
		break;
	case UDA134X_DATA1:
		addr = UDA134X_DATA1_ADDR;
		break;
	default:
		/* It's an extended address register */
		addr =  (reg | UDA134X_EXTADDR_PREFIX);

		ret = l3_write(&pd->l3,
			       UDA134X_DATA0_ADDR, &addr, 1);
		if (ret != 1)
			return -EIO;

		addr = UDA134X_DATA0_ADDR;
		data = (value | UDA134X_EXTDATA_PREFIX);
		break;
	}

	ret = l3_write(&pd->l3,
		       addr, &data, 1);
	if (ret != 1)
		return -EIO;

	return 0;
}

static inline void uda134x_reset(struct snd_soc_codec *codec)
{
	u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	uda134x_write(codec, UDA134X_STATUS0, reset_reg | (1<<6));
	msleep(1);
	uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
}

static int uda134x_mute(struct snd_soc_dai *dai, int mute)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);

	pr_debug("%s mute: %d\n", __func__, mute);

	if (mute)
		mute_reg |= (1<<2);
	else
		mute_reg &= ~(1<<2);

	uda134x_write(codec, UDA134X_DATA010, mute_reg);

	return 0;
}

static int uda134x_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	struct snd_pcm_runtime *master_runtime;

	if (uda134x->master_substream) {
		master_runtime = uda134x->master_substream->runtime;

		pr_debug("%s constraining to %d bits at %d\n", __func__,
			 master_runtime->sample_bits,
			 master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_RATE,
					     master_runtime->rate,
					     master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
					     master_runtime->sample_bits,
					     master_runtime->sample_bits);

		uda134x->slave_substream = substream;
	} else
		uda134x->master_substream = substream;

	return 0;
}

static void uda134x_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	if (uda134x->master_substream == substream)
		uda134x->master_substream = uda134x->slave_substream;

	uda134x->slave_substream = NULL;
}

static int uda134x_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params,
	struct snd_soc_dai *dai)
{
	struct snd_soc_codec *codec = dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	u8 hw_params;

	if (substream == uda134x->slave_substream) {
		pr_debug("%s ignoring hw_params for slave substream\n",
			 __func__);
		return 0;
	}

	hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	hw_params &= STATUS0_SYSCLK_MASK;
	hw_params &= STATUS0_DAIFMT_MASK;

	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
		 uda134x->sysclk, params_rate(params));

	/* set SYSCLK / fs ratio */
	switch (uda134x->sysclk / params_rate(params)) {
	case 512:
		break;
	case 384:
		hw_params |= (1<<4);
		break;
	case 256:
		hw_params |= (1<<5);
		break;
	default:
		printk(KERN_ERR "%s unsupported fs\n", __func__);
		return -EINVAL;
	}

	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
		 uda134x->dai_fmt, params_format(params));

	/* set DAI format and word length */
	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		switch (params_width(params)) {
		case 16:
			hw_params |= (1<<1);
			break;
		case 18:
			hw_params |= (1<<2);
			break;
		case 20:
			hw_params |= ((1<<2) | (1<<1));
			break;
		default:
			printk(KERN_ERR "%s unsupported format (right)\n",
			       __func__);
			return -EINVAL;
		}
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		hw_params |= (1<<3);
		break;
	default:
		printk(KERN_ERR "%s unsupported format\n", __func__);
		return -EINVAL;
	}

	uda134x_write(codec, UDA134X_STATUS0, hw_params);

	return 0;
}

static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
		 clk_id, freq, dir);

	/* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
	   because the codec is slave. Of course limitations of the clock
	   master (the IIS controller) apply.
	   We'll error out on set_hw_params if it's not OK */
	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
		uda134x->sysclk = freq;
		return 0;
	}

	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	return -EINVAL;
}

static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
			       unsigned int fmt)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s fmt: %08X\n", __func__, fmt);

	/* codec supports only full slave mode */
	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
		printk(KERN_ERR "%s unsupported slave mode\n", __func__);
		return -EINVAL;
	}

	/* no support for clock inversion */
	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
		printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
		return -EINVAL;
	}

	/* We can't setup DAI format here as it depends on the word bit num */
	/* so let's just store the value for later */
	uda134x->dai_fmt = fmt;

	return 0;
}

static int uda134x_set_bias_level(struct snd_soc_codec *codec,
				  enum snd_soc_bias_level level)
{
	struct uda134x_platform_data *pd = codec->control_data;
	int i;
	u8 *cache = codec->reg_cache;

	pr_debug("%s bias level %d\n", __func__, level);

	switch (level) {
	case SND_SOC_BIAS_ON:
		break;
	case SND_SOC_BIAS_PREPARE:
		/* power on */
		if (pd->power) {
			pd->power(1);
			/* Sync reg_cache with the hardware */
			for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
				codec->driver->write(codec, i, *cache++);
		}
		break;
	case SND_SOC_BIAS_STANDBY:
		break;
	case SND_SOC_BIAS_OFF:
		/* power off */
		if (pd->power)
			pd->power(0);
		break;
	}
	return 0;
}

static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
					    "Minimum2", "Maximum"};
static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const char *uda134x_mixmode[] = {"Differential", "Analog1",
					"Analog2", "Both"};

static const struct soc_enum uda134x_mixer_enum[] = {
SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
};

static const struct snd_kcontrol_new uda1341_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),

SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),

SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),

SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1340_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1345_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

/* UDA1341 has the DAC/ADC power down in STATUS1 */
static const struct snd_soc_dapm_widget uda1341_dapm_widgets[] = {
	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_STATUS1, 0, 0),
	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_STATUS1, 1, 0),
};

/* UDA1340/4/5 has the DAC/ADC pwoer down in DATA0 11 */
static const struct snd_soc_dapm_widget uda1340_dapm_widgets[] = {
	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_DATA011, 0, 0),
	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_DATA011, 1, 0),
};

/* Common DAPM widgets */
static const struct snd_soc_dapm_widget uda134x_dapm_widgets[] = {
	SND_SOC_DAPM_INPUT("VINL1"),
	SND_SOC_DAPM_INPUT("VINR1"),
	SND_SOC_DAPM_INPUT("VINL2"),
	SND_SOC_DAPM_INPUT("VINR2"),
	SND_SOC_DAPM_OUTPUT("VOUTL"),
	SND_SOC_DAPM_OUTPUT("VOUTR"),
};

static const struct snd_soc_dapm_route uda134x_dapm_routes[] = {
	{ "ADC", NULL, "VINL1" },
	{ "ADC", NULL, "VINR1" },
	{ "ADC", NULL, "VINL2" },
	{ "ADC", NULL, "VINR2" },
	{ "VOUTL", NULL, "DAC" },
	{ "VOUTR", NULL, "DAC" },
};

static const struct snd_soc_dai_ops uda134x_dai_ops = {
	.startup	= uda134x_startup,
	.shutdown	= uda134x_shutdown,
	.hw_params	= uda134x_hw_params,
	.digital_mute	= uda134x_mute,
	.set_sysclk	= uda134x_set_dai_sysclk,
	.set_fmt	= uda134x_set_dai_fmt,
};

static struct snd_soc_dai_driver uda134x_dai = {
	.name = "uda134x-hifi",
	/* playback capabilities */
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* capture capabilities */
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* pcm operations */
	.ops = &uda134x_dai_ops,
};

static int uda134x_soc_probe(struct snd_soc_codec *codec)
{
	struct uda134x_priv *uda134x;
	struct uda134x_platform_data *pd = codec->component.card->dev->platform_data;
	const struct snd_soc_dapm_widget *widgets;
	unsigned num_widgets;

	int ret;

	printk(KERN_INFO "UDA134X SoC Audio Codec\n");

	if (!pd) {
		printk(KERN_ERR "UDA134X SoC codec: "
		       "missing L3 bitbang function\n");
		return -ENODEV;
	}

	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1341:
	case UDA134X_UDA1344:
	case UDA134X_UDA1345:
		break;
	default:
		printk(KERN_ERR "UDA134X SoC codec: "
		       "unsupported model %d\n",
			pd->model);
		return -EINVAL;
	}

	uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
	if (uda134x == NULL)
		return -ENOMEM;
	snd_soc_codec_set_drvdata(codec, uda134x);

	codec->control_data = pd;

	if (pd->power)
		pd->power(1);

	uda134x_reset(codec);

	if (pd->model == UDA134X_UDA1341) {
		widgets = uda1341_dapm_widgets;
		num_widgets = ARRAY_SIZE(uda1341_dapm_widgets);
	} else {
		widgets = uda1340_dapm_widgets;
		num_widgets = ARRAY_SIZE(uda1340_dapm_widgets);
	}

	ret = snd_soc_dapm_new_controls(&codec->dapm, widgets, num_widgets);
	if (ret) {
		printk(KERN_ERR "%s failed to register dapm controls: %d",
			__func__, ret);
		kfree(uda134x);
		return ret;
	}

	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1344:
		ret = snd_soc_add_codec_controls(codec, uda1340_snd_controls,
					ARRAY_SIZE(uda1340_snd_controls));
	break;
	case UDA134X_UDA1341:
		ret = snd_soc_add_codec_controls(codec, uda1341_snd_controls,
					ARRAY_SIZE(uda1341_snd_controls));
	break;
	case UDA134X_UDA1345:
		ret = snd_soc_add_codec_controls(codec, uda1345_snd_controls,
					ARRAY_SIZE(uda1345_snd_controls));
	break;
	default:
		printk(KERN_ERR "%s unknown codec type: %d",
			__func__, pd->model);
		kfree(uda134x);
		return -EINVAL;
	}

	if (ret < 0) {
		printk(KERN_ERR "UDA134X: failed to register controls\n");
		kfree(uda134x);
		return ret;
	}

	return 0;
}

/* power down chip */
static int uda134x_soc_remove(struct snd_soc_codec *codec)
{
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	kfree(uda134x);
	return 0;
}

static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
	.probe =        uda134x_soc_probe,
	.remove =       uda134x_soc_remove,
	.reg_cache_size = sizeof(uda134x_reg),
	.reg_word_size = sizeof(u8),
	.reg_cache_default = uda134x_reg,
	.reg_cache_step = 1,
	.read = uda134x_read_reg_cache,
	.set_bias_level = uda134x_set_bias_level,
	.suspend_bias_off = true,

	.dapm_widgets = uda134x_dapm_widgets,
	.num_dapm_widgets = ARRAY_SIZE(uda134x_dapm_widgets),
	.dapm_routes = uda134x_dapm_routes,
	.num_dapm_routes = ARRAY_SIZE(uda134x_dapm_routes),
};

static int uda134x_codec_probe(struct platform_device *pdev)
{
	return snd_soc_register_codec(&pdev->dev,
			&soc_codec_dev_uda134x, &uda134x_dai, 1);
}

static int uda134x_codec_remove(struct platform_device *pdev)
{
	snd_soc_unregister_codec(&pdev->dev);
	return 0;
}

static struct platform_driver uda134x_codec_driver = {
	.driver = {
		.name = "uda134x-codec",
	},
	.probe = uda134x_codec_probe,
	.remove = uda134x_codec_remove,
};

module_platform_driver(uda134x_codec_driver);

MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
1cad1de1 CP	1	/*
	2	* uda134x.c -- UDA134X ALSA SoC Codec driver
	3	*
	4	* Modifications by Christian Pellegrin <chripell@evolware.org>
	5	*
	6	* Copyright 2007 Dension Audio Systems Ltd.
	7	* Author: Zoltan Devai
	8	*
	9	* Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/delay.h>
5a0e3ad6	18	#include <linux/slab.h>
1cad1de1 CP	19	#include <sound/pcm.h>
	20	#include <sound/pcm_params.h>
	21	#include <sound/soc.h>
1cad1de1 CP	22	#include <sound/initval.h>
	23
	24	#include <sound/uda134x.h>
	25	#include <sound/l3.h>
	26
72f2b894	27	#include "uda134x.h"
1cad1de1 CP	28
1cad1de1 CP	29
1cad1de1 CP	30	#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
	31	#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE \| \
	32	SNDRV_PCM_FMTBIT_S18_3LE \| SNDRV_PCM_FMTBIT_S20_3LE)
	33
	34	struct uda134x_priv {
	35	int sysclk;
	36	int dai_fmt;
	37
	38	struct snd_pcm_substream *master_substream;
	39	struct snd_pcm_substream *slave_substream;
	40	};
	41
	42	/* In-data addresses are hard-coded into the reg-cache values */
	43	static const char uda134x_reg[UDA134X_REGS_NUM] = {
	44	/* Extended address registers */
	45	0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
	46	/* Status, data regs */
ed632ad3	47	0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
1cad1de1 CP	48	};
	49
	50	/*
	51	* The codec has no support for reading its registers except for peak level...
	52	*/
	53	static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
	54	unsigned int reg)
	55	{
	56	u8 *cache = codec->reg_cache;
	57
	58	if (reg >= UDA134X_REGS_NUM)
	59	return -1;
	60	return cache[reg];
	61	}
	62
	63	/*
	64	* Write the register cache
	65	*/
	66	static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
	67	u8 reg, unsigned int value)
	68	{
	69	u8 *cache = codec->reg_cache;
	70
	71	if (reg >= UDA134X_REGS_NUM)
	72	return;
	73	cache[reg] = value;
	74	}
	75
	76	/*
	77	* Write to the uda134x registers
	78	*
	79	*/
	80	static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
	81	unsigned int value)
	82	{
	83	int ret;
	84	u8 addr;
	85	u8 data = value;
	86	struct uda134x_platform_data *pd = codec->control_data;
	87
	88	pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
	89
	90	if (reg >= UDA134X_REGS_NUM) {
af901ca1	91	printk(KERN_ERR "%s unknown register: reg: %u",
1cad1de1 CP	92	__func__, reg);
	93	return -EINVAL;
	94	}
	95
	96	uda134x_write_reg_cache(codec, reg, value);
	97
	98	switch (reg) {
	99	case UDA134X_STATUS0:
	100	case UDA134X_STATUS1:
	101	addr = UDA134X_STATUS_ADDR;
	102	break;
	103	case UDA134X_DATA000:
	104	case UDA134X_DATA001:
	105	case UDA134X_DATA010:
ed632ad3	106	case UDA134X_DATA011:
1cad1de1 CP	107	addr = UDA134X_DATA0_ADDR;
	108	break;
	109	case UDA134X_DATA1:
	110	addr = UDA134X_DATA1_ADDR;
	111	break;
	112	default:
	113	/* It's an extended address register */
	114	addr = (reg \| UDA134X_EXTADDR_PREFIX);
	115
	116	ret = l3_write(&pd->l3,
	117	UDA134X_DATA0_ADDR, &addr, 1);
	118	if (ret != 1)
	119	return -EIO;
	120
	121	addr = UDA134X_DATA0_ADDR;
	122	data = (value \| UDA134X_EXTDATA_PREFIX);
	123	break;
	124	}
	125
	126	ret = l3_write(&pd->l3,
	127	addr, &data, 1);
	128	if (ret != 1)
	129	return -EIO;
	130
	131	return 0;
	132	}
	133
	134	static inline void uda134x_reset(struct snd_soc_codec *codec)
	135	{
	136	u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	137	uda134x_write(codec, UDA134X_STATUS0, reset_reg \| (1<<6));
	138	msleep(1);
	139	uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
	140	}
	141
	142	static int uda134x_mute(struct snd_soc_dai *dai, int mute)
	143	{
	144	struct snd_soc_codec *codec = dai->codec;
	145	u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);
	146
	147	pr_debug("%s mute: %d\n", __func__, mute);
	148
	149	if (mute)
	150	mute_reg \|= (1<<2);
	151	else
	152	mute_reg &= ~(1<<2);
	153
0c093fb5	154	uda134x_write(codec, UDA134X_DATA010, mute_reg);
1cad1de1 CP	155
	156	return 0;
	157	}
	158
dee89c4d MB	159	static int uda134x_startup(struct snd_pcm_substream *substream,
dee89c4d MB	160	struct snd_soc_dai *dai)
1cad1de1	161	{
e6968a17	162	struct snd_soc_codec *codec = dai->codec;
b2c812e2	163	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	164	struct snd_pcm_runtime *master_runtime;
	165
	166	if (uda134x->master_substream) {
	167	master_runtime = uda134x->master_substream->runtime;
	168
	169	pr_debug("%s constraining to %d bits at %d\n", __func__,
	170	master_runtime->sample_bits,
	171	master_runtime->rate);
	172
	173	snd_pcm_hw_constraint_minmax(substream->runtime,
	174	SNDRV_PCM_HW_PARAM_RATE,
	175	master_runtime->rate,
	176	master_runtime->rate);
	177
	178	snd_pcm_hw_constraint_minmax(substream->runtime,
	179	SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
	180	master_runtime->sample_bits,
	181	master_runtime->sample_bits);
	182
	183	uda134x->slave_substream = substream;
	184	} else
	185	uda134x->master_substream = substream;
	186
	187	return 0;
	188	}
	189
dee89c4d MB	190	static void uda134x_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	191	struct snd_soc_dai *dai)
1cad1de1	192	{
e6968a17	193	struct snd_soc_codec *codec = dai->codec;
b2c812e2	194	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	195
	196	if (uda134x->master_substream == substream)
	197	uda134x->master_substream = uda134x->slave_substream;
	198
	199	uda134x->slave_substream = NULL;
	200	}
	201
	202	static int uda134x_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	203	struct snd_pcm_hw_params *params,
dee89c4d MB	204	struct snd_soc_dai *dai)
1cad1de1	205	{
ab64246c	206	struct snd_soc_codec *codec = dai->codec;
b2c812e2	207	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	208	u8 hw_params;
	209
	210	if (substream == uda134x->slave_substream) {
	211	pr_debug("%s ignoring hw_params for slave substream\n",
	212	__func__);
	213	return 0;
	214	}
	215
	216	hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	217	hw_params &= STATUS0_SYSCLK_MASK;
	218	hw_params &= STATUS0_DAIFMT_MASK;
	219
	220	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
	221	uda134x->sysclk, params_rate(params));
	222
	223	/* set SYSCLK / fs ratio */
	224	switch (uda134x->sysclk / params_rate(params)) {
	225	case 512:
	226	break;
	227	case 384:
	228	hw_params \|= (1<<4);
	229	break;
	230	case 256:
	231	hw_params \|= (1<<5);
	232	break;
	233	default:
	234	printk(KERN_ERR "%s unsupported fs\n", __func__);
	235	return -EINVAL;
	236	}
	237
	238	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
	239	uda134x->dai_fmt, params_format(params));
	240
	241	/* set DAI format and word length */
	242	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	243	case SND_SOC_DAIFMT_I2S:
	244	break;
	245	case SND_SOC_DAIFMT_RIGHT_J:
aa9ffad6 MB	246	switch (params_width(params)) {
aa9ffad6 MB	247	case 16:
1cad1de1 CP	248	hw_params \|= (1<<1);
1cad1de1 CP	249	break;
aa9ffad6	250	case 18:
1cad1de1 CP	251	hw_params \|= (1<<2);
1cad1de1 CP	252	break;
aa9ffad6	253	case 20:
1cad1de1 CP	254	hw_params \|= ((1<<2) \| (1<<1));
	255	break;
	256	default:
	257	printk(KERN_ERR "%s unsupported format (right)\n",
	258	__func__);
	259	return -EINVAL;
	260	}
	261	break;
	262	case SND_SOC_DAIFMT_LEFT_J:
	263	hw_params \|= (1<<3);
	264	break;
	265	default:
	266	printk(KERN_ERR "%s unsupported format\n", __func__);
	267	return -EINVAL;
	268	}
	269
	270	uda134x_write(codec, UDA134X_STATUS0, hw_params);
	271
	272	return 0;
	273	}
	274
	275	static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
	276	int clk_id, unsigned int freq, int dir)
	277	{
	278	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	279	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1	280
449bd54d	281	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
1cad1de1 CP	282	clk_id, freq, dir);
	283
	284	/* Anything between 256fs8Khz and 512fs48Khz should be acceptable
	285	because the codec is slave. Of course limitations of the clock
	286	master (the IIS controller) apply.
	287	We'll error out on set_hw_params if it's not OK */
	288	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
	289	uda134x->sysclk = freq;
	290	return 0;
	291	}
	292
	293	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	294	return -EINVAL;
	295	}
	296
	297	static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
	298	unsigned int fmt)
	299	{
	300	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	301	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	302
	303	pr_debug("%s fmt: %08X\n", __func__, fmt);
	304
	305	/* codec supports only full slave mode */
	306	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
	307	printk(KERN_ERR "%s unsupported slave mode\n", __func__);
	308	return -EINVAL;
	309	}
	310
	311	/* no support for clock inversion */
	312	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
	313	printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
	314	return -EINVAL;
	315	}
	316
	317	/* We can't setup DAI format here as it depends on the word bit num */
	318	/* so let's just store the value for later */
	319	uda134x->dai_fmt = fmt;
	320
	321	return 0;
	322	}
	323
	324	static int uda134x_set_bias_level(struct snd_soc_codec *codec,
	325	enum snd_soc_bias_level level)
	326	{
1cad1de1 CP	327	struct uda134x_platform_data *pd = codec->control_data;
	328	int i;
	329	u8 *cache = codec->reg_cache;
	330
	331	pr_debug("%s bias level %d\n", __func__, level);
	332
	333	switch (level) {
	334	case SND_SOC_BIAS_ON:
1cad1de1 CP	335	break;
	336	case SND_SOC_BIAS_PREPARE:
	337	/* power on */
	338	if (pd->power) {
	339	pd->power(1);
	340	/* Sync reg_cache with the hardware */
	341	for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
f0fba2ad	342	codec->driver->write(codec, i, *cache++);
1cad1de1 CP	343	}
	344	break;
	345	case SND_SOC_BIAS_STANDBY:
1cad1de1 CP	346	break;
	347	case SND_SOC_BIAS_OFF:
	348	/* power off */
	349	if (pd->power)
	350	pd->power(0);
	351	break;
	352	}
1cad1de1 CP	353	return 0;
	354	}
	355
	356	static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
	357	"Minimum2", "Maximum"};
	358	static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
	359	static const char *uda134x_mixmode[] = {"Differential", "Analog1",
	360	"Analog2", "Both"};
	361
	362	static const struct soc_enum uda134x_mixer_enum[] = {
	363	SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
	364	SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
	365	SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
	366	};
	367
	368	static const struct snd_kcontrol_new uda1341_snd_controls[] = {
	369	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	370	SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
	371	SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
	372	SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
	373
	374	SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
	375	SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
	376
	377	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	378	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	379
	380	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	381	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	382	SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
	383
	384	SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
	385	SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
	386	SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
	387
	388	SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
	389	SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
	390	SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
	391	SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
	392	SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
	393	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	394	};
	395
	396	static const struct snd_kcontrol_new uda1340_snd_controls[] = {
	397	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	398
	399	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	400	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	401
	402	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	403	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	404
	405	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	406	};
	407
b28528a1 VZ	408	static const struct snd_kcontrol_new uda1345_snd_controls[] = {
	409	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	410
	411	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	412
	413	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	414	};
	415
113591e4 RK	416	/* UDA1341 has the DAC/ADC power down in STATUS1 */
	417	static const struct snd_soc_dapm_widget uda1341_dapm_widgets[] = {
	418	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_STATUS1, 0, 0),
	419	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_STATUS1, 1, 0),
	420	};
	421
	422	/* UDA1340/4/5 has the DAC/ADC pwoer down in DATA0 11 */
	423	static const struct snd_soc_dapm_widget uda1340_dapm_widgets[] = {
	424	SND_SOC_DAPM_DAC("DAC", "Playback", UDA134X_DATA011, 0, 0),
	425	SND_SOC_DAPM_ADC("ADC", "Capture", UDA134X_DATA011, 1, 0),
	426	};
	427
	428	/* Common DAPM widgets */
	429	static const struct snd_soc_dapm_widget uda134x_dapm_widgets[] = {
	430	SND_SOC_DAPM_INPUT("VINL1"),
	431	SND_SOC_DAPM_INPUT("VINR1"),
	432	SND_SOC_DAPM_INPUT("VINL2"),
	433	SND_SOC_DAPM_INPUT("VINR2"),
	434	SND_SOC_DAPM_OUTPUT("VOUTL"),
	435	SND_SOC_DAPM_OUTPUT("VOUTR"),
	436	};
	437
	438	static const struct snd_soc_dapm_route uda134x_dapm_routes[] = {
	439	{ "ADC", NULL, "VINL1" },
	440	{ "ADC", NULL, "VINR1" },
	441	{ "ADC", NULL, "VINL2" },
	442	{ "ADC", NULL, "VINR2" },
	443	{ "VOUTL", NULL, "DAC" },
	444	{ "VOUTR", NULL, "DAC" },
	445	};
	446
85e7652d	447	static const struct snd_soc_dai_ops uda134x_dai_ops = {
6335d055 EM	448	.startup = uda134x_startup,
	449	.shutdown = uda134x_shutdown,
	450	.hw_params = uda134x_hw_params,
	451	.digital_mute = uda134x_mute,
	452	.set_sysclk = uda134x_set_dai_sysclk,
	453	.set_fmt = uda134x_set_dai_fmt,
	454	};
	455
f0fba2ad LG	456	static struct snd_soc_dai_driver uda134x_dai = {
f0fba2ad LG	457	.name = "uda134x-hifi",
1cad1de1 CP	458	/* playback capabilities */
	459	.playback = {
	460	.stream_name = "Playback",
	461	.channels_min = 1,
	462	.channels_max = 2,
	463	.rates = UDA134X_RATES,
	464	.formats = UDA134X_FORMATS,
	465	},
	466	/* capture capabilities */
	467	.capture = {
	468	.stream_name = "Capture",
	469	.channels_min = 1,
	470	.channels_max = 2,
	471	.rates = UDA134X_RATES,
	472	.formats = UDA134X_FORMATS,
	473	},
	474	/* pcm operations */
6335d055	475	.ops = &uda134x_dai_ops,
1cad1de1	476	};
1cad1de1	477
f0fba2ad	478	static int uda134x_soc_probe(struct snd_soc_codec *codec)
1cad1de1	479	{
1cad1de1	480	struct uda134x_priv *uda134x;
00200107	481	struct uda134x_platform_data *pd = codec->component.card->dev->platform_data;
113591e4 RK	482	const struct snd_soc_dapm_widget *widgets;
113591e4 RK	483	unsigned num_widgets;
a110f4ef	484
f0fba2ad	485	int ret;
1cad1de1 CP	486
	487	printk(KERN_INFO "UDA134X SoC Audio Codec\n");
	488
f0fba2ad	489	if (!pd) {
1cad1de1 CP	490	printk(KERN_ERR "UDA134X SoC codec: "
	491	"missing L3 bitbang function\n");
	492	return -ENODEV;
	493	}
	494
1cad1de1 CP	495	switch (pd->model) {
	496	case UDA134X_UDA1340:
	497	case UDA134X_UDA1341:
	498	case UDA134X_UDA1344:
b28528a1	499	case UDA134X_UDA1345:
1cad1de1 CP	500	break;
	501	default:
	502	printk(KERN_ERR "UDA134X SoC codec: "
	503	"unsupported model %d\n",
	504	pd->model);
	505	return -EINVAL;
	506	}
	507
1cad1de1 CP	508	uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
1cad1de1 CP	509	if (uda134x == NULL)
f0fba2ad	510	return -ENOMEM;
b2c812e2	511	snd_soc_codec_set_drvdata(codec, uda134x);
1cad1de1	512
f0fba2ad	513	codec->control_data = pd;
1cad1de1 CP	514
	515	if (pd->power)
	516	pd->power(1);
	517
	518	uda134x_reset(codec);
	519
113591e4 RK	520	if (pd->model == UDA134X_UDA1341) {
	521	widgets = uda1341_dapm_widgets;
	522	num_widgets = ARRAY_SIZE(uda1341_dapm_widgets);
	523	} else {
	524	widgets = uda1340_dapm_widgets;
	525	num_widgets = ARRAY_SIZE(uda1340_dapm_widgets);
	526	}
	527
	528	ret = snd_soc_dapm_new_controls(&codec->dapm, widgets, num_widgets);
	529	if (ret) {
	530	printk(KERN_ERR "%s failed to register dapm controls: %d",
	531	__func__, ret);
	532	kfree(uda134x);
	533	return ret;
	534	}
	535
3e8e1952 IM	536	switch (pd->model) {
	537	case UDA134X_UDA1340:
	538	case UDA134X_UDA1344:
022658be	539	ret = snd_soc_add_codec_controls(codec, uda1340_snd_controls,
3e8e1952 IM	540	ARRAY_SIZE(uda1340_snd_controls));
	541	break;
	542	case UDA134X_UDA1341:
022658be	543	ret = snd_soc_add_codec_controls(codec, uda1341_snd_controls,
3e8e1952 IM	544	ARRAY_SIZE(uda1341_snd_controls));
3e8e1952 IM	545	break;
b28528a1	546	case UDA134X_UDA1345:
022658be	547	ret = snd_soc_add_codec_controls(codec, uda1345_snd_controls,
b28528a1 VZ	548	ARRAY_SIZE(uda1345_snd_controls));
b28528a1 VZ	549	break;
3e8e1952	550	default:
af901ca1	551	printk(KERN_ERR "%s unknown codec type: %d",
3e8e1952	552	__func__, pd->model);
f0fba2ad LG	553	kfree(uda134x);
f0fba2ad LG	554	return -EINVAL;
3e8e1952 IM	555	}
3e8e1952 IM	556
1cad1de1 CP	557	if (ret < 0) {
1cad1de1 CP	558	printk(KERN_ERR "UDA134X: failed to register controls\n");
f0fba2ad LG	559	kfree(uda134x);
f0fba2ad LG	560	return ret;
1cad1de1 CP	561	}
1cad1de1 CP	562
1cad1de1	563	return 0;
1cad1de1 CP	564	}
	565
	566	/* power down chip */
f0fba2ad	567	static int uda134x_soc_remove(struct snd_soc_codec *codec)
1cad1de1	568	{
f0fba2ad	569	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1	570
f0fba2ad	571	kfree(uda134x);
1cad1de1 CP	572	return 0;
	573	}
	574
f0fba2ad	575	static struct snd_soc_codec_driver soc_codec_dev_uda134x = {
1cad1de1 CP	576	.probe = uda134x_soc_probe,
1cad1de1 CP	577	.remove = uda134x_soc_remove,
f0fba2ad LG	578	.reg_cache_size = sizeof(uda134x_reg),
f0fba2ad LG	579	.reg_word_size = sizeof(u8),
2811fe2b	580	.reg_cache_default = uda134x_reg,
f0fba2ad LG	581	.reg_cache_step = 1,
f0fba2ad LG	582	.read = uda134x_read_reg_cache,
f0fba2ad	583	.set_bias_level = uda134x_set_bias_level,
e03b9755 LPC	584	.suspend_bias_off = true,
e03b9755 LPC	585
113591e4 RK	586	.dapm_widgets = uda134x_dapm_widgets,
	587	.num_dapm_widgets = ARRAY_SIZE(uda134x_dapm_widgets),
	588	.dapm_routes = uda134x_dapm_routes,
	589	.num_dapm_routes = ARRAY_SIZE(uda134x_dapm_routes),
f0fba2ad LG	590	};
f0fba2ad LG	591
7a79e94e	592	static int uda134x_codec_probe(struct platform_device *pdev)
f0fba2ad LG	593	{
	594	return snd_soc_register_codec(&pdev->dev,
	595	&soc_codec_dev_uda134x, &uda134x_dai, 1);
	596	}
	597
7a79e94e	598	static int uda134x_codec_remove(struct platform_device *pdev)
f0fba2ad LG	599	{
	600	snd_soc_unregister_codec(&pdev->dev);
	601	return 0;
	602	}
	603
	604	static struct platform_driver uda134x_codec_driver = {
	605	.driver = {
	606	.name = "uda134x-codec",
f0fba2ad LG	607	},
f0fba2ad LG	608	.probe = uda134x_codec_probe,
7a79e94e	609	.remove = uda134x_codec_remove,
1cad1de1	610	};
1cad1de1	611
5bbcc3c0	612	module_platform_driver(uda134x_codec_driver);
64089b84	613
1cad1de1 CP	614	MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
	615	MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
	616	MODULE_LICENSE("GPL");