[deliverable/linux.git] / sound / soc / codecs / uda134x.c

/*
 * uda134x.c  --  UDA134X ALSA SoC Codec driver
 *
 * Modifications by Christian Pellegrin <chripell@evolware.org>
 *
 * Copyright 2007 Dension Audio Systems Ltd.
 * Author: Zoltan Devai
 *
 * Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>

#include <sound/uda134x.h>
#include <sound/l3.h>

#include "uda134x.h"


#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
		SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE)

struct uda134x_priv {
	int sysclk;
	int dai_fmt;

	struct snd_pcm_substream *master_substream;
	struct snd_pcm_substream *slave_substream;
};

/* In-data addresses are hard-coded into the reg-cache values */
static const char uda134x_reg[UDA134X_REGS_NUM] = {
	/* Extended address registers */
	0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
	/* Status, data regs */
	0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
};

/*
 * The codec has no support for reading its registers except for peak level...
 */
static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
	unsigned int reg)
{
	u8 *cache = codec->reg_cache;

	if (reg >= UDA134X_REGS_NUM)
		return -1;
	return cache[reg];
}

/*
 * Write the register cache
 */
static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
	u8 reg, unsigned int value)
{
	u8 *cache = codec->reg_cache;

	if (reg >= UDA134X_REGS_NUM)
		return;
	cache[reg] = value;
}

/*
 * Write to the uda134x registers
 *
 */
static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
	unsigned int value)
{
	int ret;
	u8 addr;
	u8 data = value;
	struct uda134x_platform_data *pd = codec->control_data;

	pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);

	if (reg >= UDA134X_REGS_NUM) {
		printk(KERN_ERR "%s unknown register: reg: %u",
		       __func__, reg);
		return -EINVAL;
	}

	uda134x_write_reg_cache(codec, reg, value);

	switch (reg) {
	case UDA134X_STATUS0:
	case UDA134X_STATUS1:
		addr = UDA134X_STATUS_ADDR;
		break;
	case UDA134X_DATA000:
	case UDA134X_DATA001:
	case UDA134X_DATA010:
	case UDA134X_DATA011:
		addr = UDA134X_DATA0_ADDR;
		break;
	case UDA134X_DATA1:
		addr = UDA134X_DATA1_ADDR;
		break;
	default:
		/* It's an extended address register */
		addr =  (reg | UDA134X_EXTADDR_PREFIX);

		ret = l3_write(&pd->l3,
			       UDA134X_DATA0_ADDR, &addr, 1);
		if (ret != 1)
			return -EIO;

		addr = UDA134X_DATA0_ADDR;
		data = (value | UDA134X_EXTDATA_PREFIX);
		break;
	}

	ret = l3_write(&pd->l3,
		       addr, &data, 1);
	if (ret != 1)
		return -EIO;

	return 0;
}

static inline void uda134x_reset(struct snd_soc_codec *codec)
{
	u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	uda134x_write(codec, UDA134X_STATUS0, reset_reg | (1<<6));
	msleep(1);
	uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
}

static int uda134x_mute(struct snd_soc_dai *dai, int mute)
{
	struct snd_soc_codec *codec = dai->codec;
	u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);

	pr_debug("%s mute: %d\n", __func__, mute);

	if (mute)
		mute_reg |= (1<<2);
	else
		mute_reg &= ~(1<<2);

	uda134x_write(codec, UDA134X_DATA010, mute_reg);

	return 0;
}

static int uda134x_startup(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_device *socdev = rtd->socdev;
	struct snd_soc_codec *codec = socdev->card->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	struct snd_pcm_runtime *master_runtime;

	if (uda134x->master_substream) {
		master_runtime = uda134x->master_substream->runtime;

		pr_debug("%s constraining to %d bits at %d\n", __func__,
			 master_runtime->sample_bits,
			 master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_RATE,
					     master_runtime->rate,
					     master_runtime->rate);

		snd_pcm_hw_constraint_minmax(substream->runtime,
					     SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
					     master_runtime->sample_bits,
					     master_runtime->sample_bits);

		uda134x->slave_substream = substream;
	} else
		uda134x->master_substream = substream;

	return 0;
}

static void uda134x_shutdown(struct snd_pcm_substream *substream,
	struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_device *socdev = rtd->socdev;
	struct snd_soc_codec *codec = socdev->card->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	if (uda134x->master_substream == substream)
		uda134x->master_substream = uda134x->slave_substream;

	uda134x->slave_substream = NULL;
}

static int uda134x_hw_params(struct snd_pcm_substream *substream,
	struct snd_pcm_hw_params *params,
	struct snd_soc_dai *dai)
{
	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	struct snd_soc_device *socdev = rtd->socdev;
	struct snd_soc_codec *codec = socdev->card->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
	u8 hw_params;

	if (substream == uda134x->slave_substream) {
		pr_debug("%s ignoring hw_params for slave substream\n",
			 __func__);
		return 0;
	}

	hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	hw_params &= STATUS0_SYSCLK_MASK;
	hw_params &= STATUS0_DAIFMT_MASK;

	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
		 uda134x->sysclk, params_rate(params));

	/* set SYSCLK / fs ratio */
	switch (uda134x->sysclk / params_rate(params)) {
	case 512:
		break;
	case 384:
		hw_params |= (1<<4);
		break;
	case 256:
		hw_params |= (1<<5);
		break;
	default:
		printk(KERN_ERR "%s unsupported fs\n", __func__);
		return -EINVAL;
	}

	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
		 uda134x->dai_fmt, params_format(params));

	/* set DAI format and word length */
	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	case SND_SOC_DAIFMT_I2S:
		break;
	case SND_SOC_DAIFMT_RIGHT_J:
		switch (params_format(params)) {
		case SNDRV_PCM_FORMAT_S16_LE:
			hw_params |= (1<<1);
			break;
		case SNDRV_PCM_FORMAT_S18_3LE:
			hw_params |= (1<<2);
			break;
		case SNDRV_PCM_FORMAT_S20_3LE:
			hw_params |= ((1<<2) | (1<<1));
			break;
		default:
			printk(KERN_ERR "%s unsupported format (right)\n",
			       __func__);
			return -EINVAL;
		}
		break;
	case SND_SOC_DAIFMT_LEFT_J:
		hw_params |= (1<<3);
		break;
	default:
		printk(KERN_ERR "%s unsupported format\n", __func__);
		return -EINVAL;
	}

	uda134x_write(codec, UDA134X_STATUS0, hw_params);

	return 0;
}

static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
		 clk_id, freq, dir);

	/* Anything between 256fs*8Khz and 512fs*48Khz should be acceptable
	   because the codec is slave. Of course limitations of the clock
	   master (the IIS controller) apply.
	   We'll error out on set_hw_params if it's not OK */
	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
		uda134x->sysclk = freq;
		return 0;
	}

	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	return -EINVAL;
}

static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
			       unsigned int fmt)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);

	pr_debug("%s fmt: %08X\n", __func__, fmt);

	/* codec supports only full slave mode */
	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
		printk(KERN_ERR "%s unsupported slave mode\n", __func__);
		return -EINVAL;
	}

	/* no support for clock inversion */
	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
		printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
		return -EINVAL;
	}

	/* We can't setup DAI format here as it depends on the word bit num */
	/* so let's just store the value for later */
	uda134x->dai_fmt = fmt;

	return 0;
}

static int uda134x_set_bias_level(struct snd_soc_codec *codec,
				  enum snd_soc_bias_level level)
{
	u8 reg;
	struct uda134x_platform_data *pd = codec->control_data;
	int i;
	u8 *cache = codec->reg_cache;

	pr_debug("%s bias level %d\n", __func__, level);

	switch (level) {
	case SND_SOC_BIAS_ON:
		/* ADC, DAC on */
		switch (pd->model) {
		case UDA134X_UDA1340:
		case UDA134X_UDA1344:
		case UDA134X_UDA1345:
			reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
			uda134x_write(codec, UDA134X_DATA011, reg | 0x03);
			break;
		case UDA134X_UDA1341:
			reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
			uda134x_write(codec, UDA134X_STATUS1, reg | 0x03);
			break;
		default:
			printk(KERN_ERR "UDA134X SoC codec: "
			       "unsupported model %d\n", pd->model);
			return -EINVAL;
		}
		break;
	case SND_SOC_BIAS_PREPARE:
		/* power on */
		if (pd->power) {
			pd->power(1);
			/* Sync reg_cache with the hardware */
			for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
				codec->write(codec, i, *cache++);
		}
		break;
	case SND_SOC_BIAS_STANDBY:
		/* ADC, DAC power off */
		switch (pd->model) {
		case UDA134X_UDA1340:
		case UDA134X_UDA1344:
		case UDA134X_UDA1345:
			reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
			uda134x_write(codec, UDA134X_DATA011, reg & ~(0x03));
			break;
		case UDA134X_UDA1341:
			reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
			uda134x_write(codec, UDA134X_STATUS1, reg & ~(0x03));
			break;
		default:
			printk(KERN_ERR "UDA134X SoC codec: "
			       "unsupported model %d\n", pd->model);
			return -EINVAL;
		}
		break;
	case SND_SOC_BIAS_OFF:
		/* power off */
		if (pd->power)
			pd->power(0);
		break;
	}
	codec->bias_level = level;
	return 0;
}

static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
					    "Minimum2", "Maximum"};
static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
static const char *uda134x_mixmode[] = {"Differential", "Analog1",
					"Analog2", "Both"};

static const struct soc_enum uda134x_mixer_enum[] = {
SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
};

static const struct snd_kcontrol_new uda1341_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),

SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),

SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),

SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1340_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),

SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static const struct snd_kcontrol_new uda1345_snd_controls[] = {
SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),

SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),

SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
};

static struct snd_soc_dai_ops uda134x_dai_ops = {
	.startup	= uda134x_startup,
	.shutdown	= uda134x_shutdown,
	.hw_params	= uda134x_hw_params,
	.digital_mute	= uda134x_mute,
	.set_sysclk	= uda134x_set_dai_sysclk,
	.set_fmt	= uda134x_set_dai_fmt,
};

struct snd_soc_dai uda134x_dai = {
	.name = "UDA134X",
	/* playback capabilities */
	.playback = {
		.stream_name = "Playback",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* capture capabilities */
	.capture = {
		.stream_name = "Capture",
		.channels_min = 1,
		.channels_max = 2,
		.rates = UDA134X_RATES,
		.formats = UDA134X_FORMATS,
	},
	/* pcm operations */
	.ops = &uda134x_dai_ops,
};
EXPORT_SYMBOL(uda134x_dai);


static int uda134x_soc_probe(struct platform_device *pdev)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_codec *codec;
	struct uda134x_priv *uda134x;
	void *codec_setup_data = socdev->codec_data;
	int ret = -ENOMEM;
	struct uda134x_platform_data *pd;

	printk(KERN_INFO "UDA134X SoC Audio Codec\n");

	if (!codec_setup_data) {
		printk(KERN_ERR "UDA134X SoC codec: "
		       "missing L3 bitbang function\n");
		return -ENODEV;
	}

	pd = codec_setup_data;
	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1341:
	case UDA134X_UDA1344:
	case UDA134X_UDA1345:
		break;
	default:
		printk(KERN_ERR "UDA134X SoC codec: "
		       "unsupported model %d\n",
			pd->model);
		return -EINVAL;
	}

	socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
	if (socdev->card->codec == NULL)
		return ret;

	codec = socdev->card->codec;

	uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
	if (uda134x == NULL)
		goto priv_err;
	snd_soc_codec_set_drvdata(codec, uda134x);

	codec->reg_cache = kmemdup(uda134x_reg, sizeof(uda134x_reg),
				   GFP_KERNEL);
	if (codec->reg_cache == NULL)
		goto reg_err;

	mutex_init(&codec->mutex);

	codec->reg_cache_size = sizeof(uda134x_reg);
	codec->reg_cache_step = 1;

	codec->name = "UDA134X";
	codec->owner = THIS_MODULE;
	codec->dai = &uda134x_dai;
	codec->num_dai = 1;
	codec->read = uda134x_read_reg_cache;
	codec->write = uda134x_write;

	INIT_LIST_HEAD(&codec->dapm_widgets);
	INIT_LIST_HEAD(&codec->dapm_paths);

	codec->control_data = codec_setup_data;

	if (pd->power)
		pd->power(1);

	uda134x_reset(codec);

	if (pd->is_powered_on_standby) {
		codec->set_bias_level = NULL;
		uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	} else {
		codec->set_bias_level = uda134x_set_bias_level;
		uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	}

	/* register pcms */
	ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
	if (ret < 0) {
		printk(KERN_ERR "UDA134X: failed to register pcms\n");
		goto pcm_err;
	}

	switch (pd->model) {
	case UDA134X_UDA1340:
	case UDA134X_UDA1344:
		ret = snd_soc_add_controls(codec, uda1340_snd_controls,
					ARRAY_SIZE(uda1340_snd_controls));
	break;
	case UDA134X_UDA1341:
		ret = snd_soc_add_controls(codec, uda1341_snd_controls,
					ARRAY_SIZE(uda1341_snd_controls));
	break;
	case UDA134X_UDA1345:
		ret = snd_soc_add_controls(codec, uda1345_snd_controls,
					ARRAY_SIZE(uda1345_snd_controls));
	break;
	default:
		printk(KERN_ERR "%s unknown codec type: %d",
			__func__, pd->model);
	return -EINVAL;
	}

	if (ret < 0) {
		printk(KERN_ERR "UDA134X: failed to register controls\n");
		goto pcm_err;
	}

	return 0;

pcm_err:
	kfree(codec->reg_cache);
reg_err:
	kfree(snd_soc_codec_get_drvdata(codec));
priv_err:
	kfree(codec);
	return ret;
}

/* power down chip */
static int uda134x_soc_remove(struct platform_device *pdev)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_codec *codec = socdev->card->codec;

	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);

	snd_soc_free_pcms(socdev);
	snd_soc_dapm_free(socdev);

	kfree(snd_soc_codec_get_drvdata(codec));
	kfree(codec->reg_cache);
	kfree(codec);

	return 0;
}

#if defined(CONFIG_PM)
static int uda134x_soc_suspend(struct platform_device *pdev,
						pm_message_t state)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_codec *codec = socdev->card->codec;

	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
	return 0;
}

static int uda134x_soc_resume(struct platform_device *pdev)
{
	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	struct snd_soc_codec *codec = socdev->card->codec;

	uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
	uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	return 0;
}
#else
#define uda134x_soc_suspend NULL
#define uda134x_soc_resume NULL
#endif /* CONFIG_PM */

struct snd_soc_codec_device soc_codec_dev_uda134x = {
	.probe =        uda134x_soc_probe,
	.remove =       uda134x_soc_remove,
	.suspend =      uda134x_soc_suspend,
	.resume =       uda134x_soc_resume,
};
EXPORT_SYMBOL_GPL(soc_codec_dev_uda134x);

static int __init uda134x_init(void)
{
	return snd_soc_register_dai(&uda134x_dai);
}
module_init(uda134x_init);

static void __exit uda134x_exit(void)
{
	snd_soc_unregister_dai(&uda134x_dai);
}
module_exit(uda134x_exit);

MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
MODULE_LICENSE("GPL");
Commit	Line	Data
1cad1de1 CP	1	/*
	2	* uda134x.c -- UDA134X ALSA SoC Codec driver
	3	*
	4	* Modifications by Christian Pellegrin <chripell@evolware.org>
	5	*
	6	* Copyright 2007 Dension Audio Systems Ltd.
	7	* Author: Zoltan Devai
	8	*
	9	* Based on the WM87xx drivers by Liam Girdwood and Richard Purdie
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/delay.h>
5a0e3ad6	18	#include <linux/slab.h>
1cad1de1 CP	19	#include <sound/pcm.h>
	20	#include <sound/pcm_params.h>
	21	#include <sound/soc.h>
	22	#include <sound/soc-dapm.h>
	23	#include <sound/initval.h>
	24
	25	#include <sound/uda134x.h>
	26	#include <sound/l3.h>
	27
72f2b894	28	#include "uda134x.h"
1cad1de1 CP	29
1cad1de1 CP	30
1cad1de1 CP	31	#define UDA134X_RATES SNDRV_PCM_RATE_8000_48000
	32	#define UDA134X_FORMATS (SNDRV_PCM_FMTBIT_S8 \| SNDRV_PCM_FMTBIT_S16_LE \| \
	33	SNDRV_PCM_FMTBIT_S18_3LE \| SNDRV_PCM_FMTBIT_S20_3LE)
	34
	35	struct uda134x_priv {
	36	int sysclk;
	37	int dai_fmt;
	38
	39	struct snd_pcm_substream *master_substream;
	40	struct snd_pcm_substream *slave_substream;
	41	};
	42
	43	/* In-data addresses are hard-coded into the reg-cache values */
	44	static const char uda134x_reg[UDA134X_REGS_NUM] = {
	45	/* Extended address registers */
	46	0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
	47	/* Status, data regs */
ed632ad3	48	0x00, 0x83, 0x00, 0x40, 0x80, 0xC0, 0x00,
1cad1de1 CP	49	};
	50
	51	/*
	52	* The codec has no support for reading its registers except for peak level...
	53	*/
	54	static inline unsigned int uda134x_read_reg_cache(struct snd_soc_codec *codec,
	55	unsigned int reg)
	56	{
	57	u8 *cache = codec->reg_cache;
	58
	59	if (reg >= UDA134X_REGS_NUM)
	60	return -1;
	61	return cache[reg];
	62	}
	63
	64	/*
	65	* Write the register cache
	66	*/
	67	static inline void uda134x_write_reg_cache(struct snd_soc_codec *codec,
	68	u8 reg, unsigned int value)
	69	{
	70	u8 *cache = codec->reg_cache;
	71
	72	if (reg >= UDA134X_REGS_NUM)
	73	return;
	74	cache[reg] = value;
	75	}
	76
	77	/*
	78	* Write to the uda134x registers
	79	*
	80	*/
	81	static int uda134x_write(struct snd_soc_codec *codec, unsigned int reg,
	82	unsigned int value)
	83	{
	84	int ret;
	85	u8 addr;
	86	u8 data = value;
	87	struct uda134x_platform_data *pd = codec->control_data;
	88
	89	pr_debug("%s reg: %02X, value:%02X\n", __func__, reg, value);
	90
	91	if (reg >= UDA134X_REGS_NUM) {
af901ca1	92	printk(KERN_ERR "%s unknown register: reg: %u",
1cad1de1 CP	93	__func__, reg);
	94	return -EINVAL;
	95	}
	96
	97	uda134x_write_reg_cache(codec, reg, value);
	98
	99	switch (reg) {
	100	case UDA134X_STATUS0:
	101	case UDA134X_STATUS1:
	102	addr = UDA134X_STATUS_ADDR;
	103	break;
	104	case UDA134X_DATA000:
	105	case UDA134X_DATA001:
	106	case UDA134X_DATA010:
ed632ad3	107	case UDA134X_DATA011:
1cad1de1 CP	108	addr = UDA134X_DATA0_ADDR;
	109	break;
	110	case UDA134X_DATA1:
	111	addr = UDA134X_DATA1_ADDR;
	112	break;
	113	default:
	114	/* It's an extended address register */
	115	addr = (reg \| UDA134X_EXTADDR_PREFIX);
	116
	117	ret = l3_write(&pd->l3,
	118	UDA134X_DATA0_ADDR, &addr, 1);
	119	if (ret != 1)
	120	return -EIO;
	121
	122	addr = UDA134X_DATA0_ADDR;
	123	data = (value \| UDA134X_EXTDATA_PREFIX);
	124	break;
	125	}
	126
	127	ret = l3_write(&pd->l3,
	128	addr, &data, 1);
	129	if (ret != 1)
	130	return -EIO;
	131
	132	return 0;
	133	}
	134
	135	static inline void uda134x_reset(struct snd_soc_codec *codec)
	136	{
	137	u8 reset_reg = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	138	uda134x_write(codec, UDA134X_STATUS0, reset_reg \| (1<<6));
	139	msleep(1);
	140	uda134x_write(codec, UDA134X_STATUS0, reset_reg & ~(1<<6));
	141	}
	142
	143	static int uda134x_mute(struct snd_soc_dai *dai, int mute)
	144	{
	145	struct snd_soc_codec *codec = dai->codec;
	146	u8 mute_reg = uda134x_read_reg_cache(codec, UDA134X_DATA010);
	147
	148	pr_debug("%s mute: %d\n", __func__, mute);
	149
	150	if (mute)
	151	mute_reg \|= (1<<2);
	152	else
	153	mute_reg &= ~(1<<2);
	154
0c093fb5	155	uda134x_write(codec, UDA134X_DATA010, mute_reg);
1cad1de1 CP	156
	157	return 0;
	158	}
	159
dee89c4d MB	160	static int uda134x_startup(struct snd_pcm_substream *substream,
dee89c4d MB	161	struct snd_soc_dai *dai)
1cad1de1 CP	162	{
	163	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	164	struct snd_soc_device *socdev = rtd->socdev;
6627a653	165	struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2	166	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	167	struct snd_pcm_runtime *master_runtime;
	168
	169	if (uda134x->master_substream) {
	170	master_runtime = uda134x->master_substream->runtime;
	171
	172	pr_debug("%s constraining to %d bits at %d\n", __func__,
	173	master_runtime->sample_bits,
	174	master_runtime->rate);
	175
	176	snd_pcm_hw_constraint_minmax(substream->runtime,
	177	SNDRV_PCM_HW_PARAM_RATE,
	178	master_runtime->rate,
	179	master_runtime->rate);
	180
	181	snd_pcm_hw_constraint_minmax(substream->runtime,
	182	SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
	183	master_runtime->sample_bits,
	184	master_runtime->sample_bits);
	185
	186	uda134x->slave_substream = substream;
	187	} else
	188	uda134x->master_substream = substream;
	189
	190	return 0;
	191	}
	192
dee89c4d MB	193	static void uda134x_shutdown(struct snd_pcm_substream *substream,
dee89c4d MB	194	struct snd_soc_dai *dai)
1cad1de1 CP	195	{
	196	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	197	struct snd_soc_device *socdev = rtd->socdev;
6627a653	198	struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2	199	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	200
	201	if (uda134x->master_substream == substream)
	202	uda134x->master_substream = uda134x->slave_substream;
	203
	204	uda134x->slave_substream = NULL;
	205	}
	206
	207	static int uda134x_hw_params(struct snd_pcm_substream *substream,
dee89c4d MB	208	struct snd_pcm_hw_params *params,
dee89c4d MB	209	struct snd_soc_dai *dai)
1cad1de1 CP	210	{
	211	struct snd_soc_pcm_runtime *rtd = substream->private_data;
	212	struct snd_soc_device *socdev = rtd->socdev;
6627a653	213	struct snd_soc_codec *codec = socdev->card->codec;
b2c812e2	214	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	215	u8 hw_params;
	216
	217	if (substream == uda134x->slave_substream) {
	218	pr_debug("%s ignoring hw_params for slave substream\n",
	219	__func__);
	220	return 0;
	221	}
	222
	223	hw_params = uda134x_read_reg_cache(codec, UDA134X_STATUS0);
	224	hw_params &= STATUS0_SYSCLK_MASK;
	225	hw_params &= STATUS0_DAIFMT_MASK;
	226
	227	pr_debug("%s sysclk: %d, rate:%d\n", __func__,
	228	uda134x->sysclk, params_rate(params));
	229
	230	/* set SYSCLK / fs ratio */
	231	switch (uda134x->sysclk / params_rate(params)) {
	232	case 512:
	233	break;
	234	case 384:
	235	hw_params \|= (1<<4);
	236	break;
	237	case 256:
	238	hw_params \|= (1<<5);
	239	break;
	240	default:
	241	printk(KERN_ERR "%s unsupported fs\n", __func__);
	242	return -EINVAL;
	243	}
	244
	245	pr_debug("%s dai_fmt: %d, params_format:%d\n", __func__,
	246	uda134x->dai_fmt, params_format(params));
	247
	248	/* set DAI format and word length */
	249	switch (uda134x->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
	250	case SND_SOC_DAIFMT_I2S:
	251	break;
	252	case SND_SOC_DAIFMT_RIGHT_J:
	253	switch (params_format(params)) {
	254	case SNDRV_PCM_FORMAT_S16_LE:
	255	hw_params \|= (1<<1);
	256	break;
	257	case SNDRV_PCM_FORMAT_S18_3LE:
	258	hw_params \|= (1<<2);
	259	break;
	260	case SNDRV_PCM_FORMAT_S20_3LE:
	261	hw_params \|= ((1<<2) \| (1<<1));
	262	break;
	263	default:
	264	printk(KERN_ERR "%s unsupported format (right)\n",
	265	__func__);
	266	return -EINVAL;
	267	}
	268	break;
	269	case SND_SOC_DAIFMT_LEFT_J:
	270	hw_params \|= (1<<3);
	271	break;
	272	default:
	273	printk(KERN_ERR "%s unsupported format\n", __func__);
	274	return -EINVAL;
	275	}
	276
	277	uda134x_write(codec, UDA134X_STATUS0, hw_params);
	278
279	return 0;
280	}
281
282	static int uda134x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
283	int clk_id, unsigned int freq, int dir)
284	{
285	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	286	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1	287
449bd54d	288	pr_debug("%s clk_id: %d, freq: %u, dir: %d\n", __func__,
1cad1de1 CP	289	clk_id, freq, dir);
	290
	291	/* Anything between 256fs8Khz and 512fs48Khz should be acceptable
	292	because the codec is slave. Of course limitations of the clock
	293	master (the IIS controller) apply.
	294	We'll error out on set_hw_params if it's not OK */
	295	if ((freq >= (256 * 8000)) && (freq <= (512 * 48000))) {
	296	uda134x->sysclk = freq;
	297	return 0;
	298	}
	299
	300	printk(KERN_ERR "%s unsupported sysclk\n", __func__);
	301	return -EINVAL;
	302	}
	303
	304	static int uda134x_set_dai_fmt(struct snd_soc_dai *codec_dai,
	305	unsigned int fmt)
	306	{
	307	struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2	308	struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec);
1cad1de1 CP	309
	310	pr_debug("%s fmt: %08X\n", __func__, fmt);
	311
	312	/* codec supports only full slave mode */
	313	if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) {
	314	printk(KERN_ERR "%s unsupported slave mode\n", __func__);
	315	return -EINVAL;
	316	}
	317
	318	/* no support for clock inversion */
	319	if ((fmt & SND_SOC_DAIFMT_INV_MASK) != SND_SOC_DAIFMT_NB_NF) {
	320	printk(KERN_ERR "%s unsupported clock inversion\n", __func__);
	321	return -EINVAL;
	322	}
	323
	324	/* We can't setup DAI format here as it depends on the word bit num */
	325	/* so let's just store the value for later */
	326	uda134x->dai_fmt = fmt;
	327
	328	return 0;
	329	}
	330
	331	static int uda134x_set_bias_level(struct snd_soc_codec *codec,
	332	enum snd_soc_bias_level level)
	333	{
	334	u8 reg;
	335	struct uda134x_platform_data *pd = codec->control_data;
	336	int i;
	337	u8 *cache = codec->reg_cache;
	338
	339	pr_debug("%s bias level %d\n", __func__, level);
	340
	341	switch (level) {
	342	case SND_SOC_BIAS_ON:
	343	/* ADC, DAC on */
338de9d9 VZ	344	switch (pd->model) {
	345	case UDA134X_UDA1340:
	346	case UDA134X_UDA1344:
	347	case UDA134X_UDA1345:
	348	reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
	349	uda134x_write(codec, UDA134X_DATA011, reg \| 0x03);
	350	break;
	351	case UDA134X_UDA1341:
	352	reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
	353	uda134x_write(codec, UDA134X_STATUS1, reg \| 0x03);
	354	break;
	355	default:
	356	printk(KERN_ERR "UDA134X SoC codec: "
	357	"unsupported model %d\n", pd->model);
	358	return -EINVAL;
	359	}
1cad1de1 CP	360	break;
	361	case SND_SOC_BIAS_PREPARE:
	362	/* power on */
	363	if (pd->power) {
	364	pd->power(1);
	365	/* Sync reg_cache with the hardware */
	366	for (i = 0; i < ARRAY_SIZE(uda134x_reg); i++)
	367	codec->write(codec, i, *cache++);
	368	}
	369	break;
	370	case SND_SOC_BIAS_STANDBY:
	371	/* ADC, DAC power off */
338de9d9 VZ	372	switch (pd->model) {
	373	case UDA134X_UDA1340:
	374	case UDA134X_UDA1344:
	375	case UDA134X_UDA1345:
	376	reg = uda134x_read_reg_cache(codec, UDA134X_DATA011);
	377	uda134x_write(codec, UDA134X_DATA011, reg & ~(0x03));
	378	break;
	379	case UDA134X_UDA1341:
	380	reg = uda134x_read_reg_cache(codec, UDA134X_STATUS1);
	381	uda134x_write(codec, UDA134X_STATUS1, reg & ~(0x03));
	382	break;
	383	default:
	384	printk(KERN_ERR "UDA134X SoC codec: "
	385	"unsupported model %d\n", pd->model);
	386	return -EINVAL;
	387	}
1cad1de1 CP	388	break;
	389	case SND_SOC_BIAS_OFF:
	390	/* power off */
	391	if (pd->power)
	392	pd->power(0);
	393	break;
	394	}
	395	codec->bias_level = level;
	396	return 0;
	397	}
	398
	399	static const char *uda134x_dsp_setting[] = {"Flat", "Minimum1",
	400	"Minimum2", "Maximum"};
	401	static const char *uda134x_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
	402	static const char *uda134x_mixmode[] = {"Differential", "Analog1",
	403	"Analog2", "Both"};
	404
	405	static const struct soc_enum uda134x_mixer_enum[] = {
	406	SOC_ENUM_SINGLE(UDA134X_DATA010, 0, 0x04, uda134x_dsp_setting),
	407	SOC_ENUM_SINGLE(UDA134X_DATA010, 3, 0x04, uda134x_deemph),
	408	SOC_ENUM_SINGLE(UDA134X_EA010, 0, 0x04, uda134x_mixmode),
	409	};
	410
	411	static const struct snd_kcontrol_new uda1341_snd_controls[] = {
	412	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	413	SOC_SINGLE("Capture Volume", UDA134X_EA010, 2, 0x07, 0),
	414	SOC_SINGLE("Analog1 Volume", UDA134X_EA000, 0, 0x1F, 1),
	415	SOC_SINGLE("Analog2 Volume", UDA134X_EA001, 0, 0x1F, 1),
	416
	417	SOC_SINGLE("Mic Sensitivity", UDA134X_EA010, 2, 7, 0),
	418	SOC_SINGLE("Mic Volume", UDA134X_EA101, 0, 0x1F, 0),
	419
	420	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	421	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	422
	423	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	424	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	425	SOC_ENUM("Input Mux", uda134x_mixer_enum[2]),
	426
	427	SOC_SINGLE("AGC Switch", UDA134X_EA100, 4, 1, 0),
	428	SOC_SINGLE("AGC Target Volume", UDA134X_EA110, 0, 0x03, 1),
	429	SOC_SINGLE("AGC Timing", UDA134X_EA110, 2, 0x07, 0),
	430
	431	SOC_SINGLE("DAC +6dB Switch", UDA134X_STATUS1, 6, 1, 0),
	432	SOC_SINGLE("ADC +6dB Switch", UDA134X_STATUS1, 5, 1, 0),
	433	SOC_SINGLE("ADC Polarity Switch", UDA134X_STATUS1, 4, 1, 0),
	434	SOC_SINGLE("DAC Polarity Switch", UDA134X_STATUS1, 3, 1, 0),
	435	SOC_SINGLE("Double Speed Playback Switch", UDA134X_STATUS1, 2, 1, 0),
	436	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	437	};
	438
	439	static const struct snd_kcontrol_new uda1340_snd_controls[] = {
	440	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	441
	442	SOC_SINGLE("Tone Control - Bass", UDA134X_DATA001, 2, 0xF, 0),
	443	SOC_SINGLE("Tone Control - Treble", UDA134X_DATA001, 0, 3, 0),
	444
	445	SOC_ENUM("Sound Processing Filter", uda134x_mixer_enum[0]),
	446	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	447
	448	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	449	};
	450
b28528a1 VZ	451	static const struct snd_kcontrol_new uda1345_snd_controls[] = {
	452	SOC_SINGLE("Master Playback Volume", UDA134X_DATA000, 0, 0x3F, 1),
	453
	454	SOC_ENUM("PCM Playback De-emphasis", uda134x_mixer_enum[1]),
	455
	456	SOC_SINGLE("DC Filter Enable Switch", UDA134X_STATUS0, 0, 1, 0),
	457	};
	458
6335d055 EM	459	static struct snd_soc_dai_ops uda134x_dai_ops = {
	460	.startup = uda134x_startup,
	461	.shutdown = uda134x_shutdown,
	462	.hw_params = uda134x_hw_params,
	463	.digital_mute = uda134x_mute,
	464	.set_sysclk = uda134x_set_dai_sysclk,
	465	.set_fmt = uda134x_set_dai_fmt,
	466	};
	467
1cad1de1 CP	468	struct snd_soc_dai uda134x_dai = {
	469	.name = "UDA134X",
	470	/* playback capabilities */
	471	.playback = {
	472	.stream_name = "Playback",
	473	.channels_min = 1,
	474	.channels_max = 2,
	475	.rates = UDA134X_RATES,
	476	.formats = UDA134X_FORMATS,
	477	},
	478	/* capture capabilities */
	479	.capture = {
	480	.stream_name = "Capture",
	481	.channels_min = 1,
	482	.channels_max = 2,
	483	.rates = UDA134X_RATES,
	484	.formats = UDA134X_FORMATS,
	485	},
	486	/* pcm operations */
6335d055	487	.ops = &uda134x_dai_ops,
1cad1de1 CP	488	};
	489	EXPORT_SYMBOL(uda134x_dai);
	490
	491
	492	static int uda134x_soc_probe(struct platform_device *pdev)
	493	{
	494	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
	495	struct snd_soc_codec *codec;
	496	struct uda134x_priv *uda134x;
	497	void *codec_setup_data = socdev->codec_data;
	498	int ret = -ENOMEM;
	499	struct uda134x_platform_data *pd;
	500
	501	printk(KERN_INFO "UDA134X SoC Audio Codec\n");
	502
	503	if (!codec_setup_data) {
	504	printk(KERN_ERR "UDA134X SoC codec: "
	505	"missing L3 bitbang function\n");
	506	return -ENODEV;
	507	}
	508
	509	pd = codec_setup_data;
	510	switch (pd->model) {
	511	case UDA134X_UDA1340:
	512	case UDA134X_UDA1341:
	513	case UDA134X_UDA1344:
b28528a1	514	case UDA134X_UDA1345:
1cad1de1 CP	515	break;
	516	default:
	517	printk(KERN_ERR "UDA134X SoC codec: "
	518	"unsupported model %d\n",
	519	pd->model);
	520	return -EINVAL;
	521	}
	522
6627a653 MB	523	socdev->card->codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
6627a653 MB	524	if (socdev->card->codec == NULL)
1cad1de1 CP	525	return ret;
1cad1de1 CP	526
6627a653	527	codec = socdev->card->codec;
1cad1de1 CP	528
	529	uda134x = kzalloc(sizeof(struct uda134x_priv), GFP_KERNEL);
	530	if (uda134x == NULL)
	531	goto priv_err;
b2c812e2	532	snd_soc_codec_set_drvdata(codec, uda134x);
1cad1de1 CP	533
	534	codec->reg_cache = kmemdup(uda134x_reg, sizeof(uda134x_reg),
	535	GFP_KERNEL);
	536	if (codec->reg_cache == NULL)
	537	goto reg_err;
	538
	539	mutex_init(&codec->mutex);
	540
	541	codec->reg_cache_size = sizeof(uda134x_reg);
	542	codec->reg_cache_step = 1;
	543
	544	codec->name = "UDA134X";
	545	codec->owner = THIS_MODULE;
	546	codec->dai = &uda134x_dai;
	547	codec->num_dai = 1;
	548	codec->read = uda134x_read_reg_cache;
	549	codec->write = uda134x_write;
cc3202f5	550
1cad1de1 CP	551	INIT_LIST_HEAD(&codec->dapm_widgets);
	552	INIT_LIST_HEAD(&codec->dapm_paths);
	553
	554	codec->control_data = codec_setup_data;
	555
	556	if (pd->power)
	557	pd->power(1);
	558
	559	uda134x_reset(codec);
	560
e4295b40 VZ	561	if (pd->is_powered_on_standby) {
	562	codec->set_bias_level = NULL;
	563	uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	564	} else {
	565	codec->set_bias_level = uda134x_set_bias_level;
	566	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	567	}
	568
1cad1de1 CP	569	/* register pcms */
	570	ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
	571	if (ret < 0) {
	572	printk(KERN_ERR "UDA134X: failed to register pcms\n");
	573	goto pcm_err;
	574	}
	575
3e8e1952 IM	576	switch (pd->model) {
	577	case UDA134X_UDA1340:
	578	case UDA134X_UDA1344:
	579	ret = snd_soc_add_controls(codec, uda1340_snd_controls,
	580	ARRAY_SIZE(uda1340_snd_controls));
	581	break;
	582	case UDA134X_UDA1341:
	583	ret = snd_soc_add_controls(codec, uda1341_snd_controls,
	584	ARRAY_SIZE(uda1341_snd_controls));
	585	break;
b28528a1 VZ	586	case UDA134X_UDA1345:
	587	ret = snd_soc_add_controls(codec, uda1345_snd_controls,
	588	ARRAY_SIZE(uda1345_snd_controls));
	589	break;
3e8e1952	590	default:
af901ca1	591	printk(KERN_ERR "%s unknown codec type: %d",
3e8e1952 IM	592	__func__, pd->model);
	593	return -EINVAL;
	594	}
	595
1cad1de1 CP	596	if (ret < 0) {
	597	printk(KERN_ERR "UDA134X: failed to register controls\n");
	598	goto pcm_err;
	599	}
	600
1cad1de1 CP	601	return 0;
1cad1de1 CP	602
1cad1de1 CP	603	pcm_err:
	604	kfree(codec->reg_cache);
	605	reg_err:
b2c812e2	606	kfree(snd_soc_codec_get_drvdata(codec));
1cad1de1 CP	607	priv_err:
	608	kfree(codec);
	609	return ret;
	610	}
	611
	612	/* power down chip */
	613	static int uda134x_soc_remove(struct platform_device *pdev)
	614	{
	615	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653	616	struct snd_soc_codec *codec = socdev->card->codec;
1cad1de1 CP	617
	618	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	619	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
	620
	621	snd_soc_free_pcms(socdev);
	622	snd_soc_dapm_free(socdev);
	623
b2c812e2	624	kfree(snd_soc_codec_get_drvdata(codec));
1cad1de1 CP	625	kfree(codec->reg_cache);
	626	kfree(codec);
	627
	628	return 0;
	629	}
	630
	631	#if defined(CONFIG_PM)
	632	static int uda134x_soc_suspend(struct platform_device *pdev,
	633	pm_message_t state)
	634	{
	635	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653	636	struct snd_soc_codec *codec = socdev->card->codec;
1cad1de1 CP	637
	638	uda134x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
	639	uda134x_set_bias_level(codec, SND_SOC_BIAS_OFF);
	640	return 0;
	641	}
	642
	643	static int uda134x_soc_resume(struct platform_device *pdev)
	644	{
	645	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653	646	struct snd_soc_codec *codec = socdev->card->codec;
1cad1de1 CP	647
	648	uda134x_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
	649	uda134x_set_bias_level(codec, SND_SOC_BIAS_ON);
	650	return 0;
	651	}
	652	#else
	653	#define uda134x_soc_suspend NULL
	654	#define uda134x_soc_resume NULL
	655	#endif /* CONFIG_PM */
	656
	657	struct snd_soc_codec_device soc_codec_dev_uda134x = {
	658	.probe = uda134x_soc_probe,
	659	.remove = uda134x_soc_remove,
	660	.suspend = uda134x_soc_suspend,
	661	.resume = uda134x_soc_resume,
	662	};
	663	EXPORT_SYMBOL_GPL(soc_codec_dev_uda134x);
	664
c9b3a40f	665	static int __init uda134x_init(void)
64089b84 MB	666	{
	667	return snd_soc_register_dai(&uda134x_dai);
	668	}
	669	module_init(uda134x_init);
	670
	671	static void __exit uda134x_exit(void)
	672	{
	673	snd_soc_unregister_dai(&uda134x_dai);
	674	}
	675	module_exit(uda134x_exit);
	676
1cad1de1 CP	677	MODULE_DESCRIPTION("UDA134X ALSA soc codec driver");
	678	MODULE_AUTHOR("Zoltan Devai, Christian Pellegrin <chripell@evolware.org>");
	679	MODULE_LICENSE("GPL");