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ASoC: One more x86 typo fix
[deliverable/linux.git] / sound / soc / codecs / uda1380.c
CommitLineData
b7482f52
PZ		 1/*
2 * uda1380.c - Philips UDA1380 ALSA SoC audio driver
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
1abd9184 8 * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com>
b7482f52
PZ		 9 *
10 * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC
11 * codec model.
12 *
13 * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org>
14 * Copyright 2005 Openedhand Ltd.
15 */
16
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/types.h>
b7482f52
PZ		 20#include <linux/slab.h>
21#include <linux/errno.h>
1abd9184 22#include <linux/gpio.h>
b7482f52
PZ		 23#include <linux/delay.h>
24#include <linux/i2c.h>
ef9e5e5c 25#include <linux/workqueue.h>
b7482f52
PZ		 26#include <sound/core.h>
27#include <sound/control.h>
28#include <sound/initval.h>
b7482f52 29#include <sound/soc.h>
b7482f52 30#include <sound/tlv.h>
1abd9184 31#include <sound/uda1380.h>
b7482f52
PZ		 32
33#include "uda1380.h"
34
1abd9184
PZ		 35/* codec private data */
36struct uda1380_priv {
f0fba2ad 37 struct snd_soc_codec *codec;
1abd9184
PZ		 38 u16 reg_cache[UDA1380_CACHEREGNUM];
39 unsigned int dac_clk;
40 struct work_struct work;
8614d310 41 void *control_data;
1abd9184
PZ		 42};
43
b7482f52
PZ		 44/*
45 * uda1380 register cache
46 */
47static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = {
48 0x0502, 0x0000, 0x0000, 0x3f3f,
49 0x0202, 0x0000, 0x0000, 0x0000,
50 0x0000, 0x0000, 0x0000, 0x0000,
51 0x0000, 0x0000, 0x0000, 0x0000,
52 0x0000, 0xff00, 0x0000, 0x4800,
53 0x0000, 0x0000, 0x0000, 0x0000,
54 0x0000, 0x0000, 0x0000, 0x0000,
55 0x0000, 0x0000, 0x0000, 0x0000,
56 0x0000, 0x8000, 0x0002, 0x0000,
57};
58
ef9e5e5c
PZ		 59static unsigned long uda1380_cache_dirty;
60
b7482f52
PZ		 61/*
62 * read uda1380 register cache
63 */
64static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec,
65 unsigned int reg)
66{
67 u16 *cache = codec->reg_cache;
68 if (reg == UDA1380_RESET)
69 return 0;
70 if (reg >= UDA1380_CACHEREGNUM)
71 return -1;
72 return cache[reg];
73}
74
75/*
76 * write uda1380 register cache
77 */
78static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec,
79 u16 reg, unsigned int value)
80{
81 u16 *cache = codec->reg_cache;
ef9e5e5c 82
b7482f52
PZ		 83 if (reg >= UDA1380_CACHEREGNUM)
84 return;
ef9e5e5c
PZ		 85 if ((reg >= 0x10) && (cache[reg] != value))
86 set_bit(reg - 0x10, &uda1380_cache_dirty);
b7482f52
PZ		 87 cache[reg] = value;
88}
89
90/*
91 * write to the UDA1380 register space
92 */
93static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg,
94 unsigned int value)
95{
96 u8 data[3];
97
98 /* data is
99 * data[0] is register offset
100 * data[1] is MS byte
101 * data[2] is LS byte
102 */
103 data[0] = reg;
104 data[1] = (value & 0xff00) >> 8;
105 data[2] = value & 0x00ff;
106
107 uda1380_write_reg_cache(codec, reg, value);
108
109 /* the interpolator & decimator regs must only be written when the
110 * codec DAI is active.
111 */
112 if (!codec->active && (reg >= UDA1380_MVOL))
113 return 0;
114 pr_debug("uda1380: hw write %x val %x\n", reg, value);
115 if (codec->hw_write(codec->control_data, data, 3) == 3) {
116 unsigned int val;
117 i2c_master_send(codec->control_data, data, 1);
118 i2c_master_recv(codec->control_data, data, 2);
119 val = (data[0]<<8) | data[1];
120 if (val != value) {
121 pr_debug("uda1380: READ BACK VAL %x\n",
122 (data[0]<<8) | data[1]);
123 return -EIO;
124 }
ef9e5e5c
PZ		 125 if (reg >= 0x10)
126 clear_bit(reg - 0x10, &uda1380_cache_dirty);
b7482f52
PZ		 127 return 0;
128 } else
129 return -EIO;
130}
131
8614d310
VK		 132static void uda1380_sync_cache(struct snd_soc_codec *codec)
133{
134 int reg;
135 u8 data[3];
136 u16 *cache = codec->reg_cache;
137
138 /* Sync reg_cache with the hardware */
139 for (reg = 0; reg < UDA1380_MVOL; reg++) {
140 data[0] = reg;
141 data[1] = (cache[reg] & 0xff00) >> 8;
142 data[2] = cache[reg] & 0x00ff;
143 if (codec->hw_write(codec->control_data, data, 3) != 3)
144 dev_err(codec->dev, "%s: write to reg 0x%x failed\n",
145 __func__, reg);
146 }
147}
148
149static int uda1380_reset(struct snd_soc_codec *codec)
150{
151 struct uda1380_platform_data *pdata = codec->dev->platform_data;
152
153 if (gpio_is_valid(pdata->gpio_reset)) {
154 gpio_set_value(pdata->gpio_reset, 1);
155 mdelay(1);
156 gpio_set_value(pdata->gpio_reset, 0);
157 } else {
158 u8 data[3];
159
160 data[0] = UDA1380_RESET;
161 data[1] = 0;
162 data[2] = 0;
163
164 if (codec->hw_write(codec->control_data, data, 3) != 3) {
165 dev_err(codec->dev, "%s: failed\n", __func__);
166 return -EIO;
167 }
168 }
169
170 return 0;
171}
b7482f52 172
ef9e5e5c
PZ		 173static void uda1380_flush_work(struct work_struct *work)
174{
f0fba2ad
LG		 175 struct uda1380_priv *uda1380 = container_of(work, struct uda1380_priv, work);
176 struct snd_soc_codec *uda1380_codec = uda1380->codec;
ef9e5e5c
PZ		 177 int bit, reg;
178
984b3f57 179 for_each_set_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) {
ef9e5e5c
PZ		 180 reg = 0x10 + bit;
181 pr_debug("uda1380: flush reg %x val %x:\n", reg,
182 uda1380_read_reg_cache(uda1380_codec, reg));
183 uda1380_write(uda1380_codec, reg,
184 uda1380_read_reg_cache(uda1380_codec, reg));
185 clear_bit(bit, &uda1380_cache_dirty);
186 }
f0fba2ad 187
ef9e5e5c
PZ		 188}
189
b7482f52
PZ		 190/* declarations of ALSA reg_elem_REAL controls */
191static const char *uda1380_deemp[] = {
192 "None",
193 "32kHz",
194 "44.1kHz",
195 "48kHz",
196 "96kHz",
197};
198static const char *uda1380_input_sel[] = {
199 "Line",
200 "Mic + Line R",
201 "Line L",
202 "Mic",
203};
204static const char *uda1380_output_sel[] = {
205 "DAC",
206 "Analog Mixer",
207};
208static const char *uda1380_spf_mode[] = {
209 "Flat",
210 "Minimum1",
211 "Minimum2",
212 "Maximum"
213};
214static const char *uda1380_capture_sel[] = {
215 "ADC",
216 "Digital Mixer"
217};
218static const char *uda1380_sel_ns[] = {
219 "3rd-order",
220 "5th-order"
221};
222static const char *uda1380_mix_control[] = {
223 "off",
224 "PCM only",
225 "before sound processing",
226 "after sound processing"
227};
228static const char *uda1380_sdet_setting[] = {
229 "3200",
230 "4800",
231 "9600",
232 "19200"
233};
234static const char *uda1380_os_setting[] = {
235 "single-speed",
236 "double-speed (no mixing)",
237 "quad-speed (no mixing)"
238};
239
240static const struct soc_enum uda1380_deemp_enum[] = {
241 SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp),
242 SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp),
243};
244static const struct soc_enum uda1380_input_sel_enum =
245 SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel); /* SEL_MIC, SEL_LNA */
246static const struct soc_enum uda1380_output_sel_enum =
247 SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel); /* R02_EN_AVC */
248static const struct soc_enum uda1380_spf_enum =
249 SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode); /* M */
250static const struct soc_enum uda1380_capture_sel_enum =
251 SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel); /* SEL_SOURCE */
252static const struct soc_enum uda1380_sel_ns_enum =
253 SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns); /* SEL_NS */
254static const struct soc_enum uda1380_mix_enum =
255 SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control); /* MIX, MIX_POS */
256static const struct soc_enum uda1380_sdet_enum =
257 SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting); /* SD_VALUE */
258static const struct soc_enum uda1380_os_enum =
259 SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting); /* OS */
260
261/*
262 * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB)
263 */
264static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1);
265
266/*
267 * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored),
268 * from -66 dB in 0.5 dB steps (2 dB steps, really) and
269 * from -52 dB in 0.25 dB steps
270 */
271static const unsigned int mvol_tlv[] = {
272 TLV_DB_RANGE_HEAD(3),
273 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1),
274 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0),
275 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0),
276};
277
278/*
279 * from -72 dB in 1.5 dB steps (6 dB steps really),
280 * from -66 dB in 0.75 dB steps (3 dB steps really),
281 * from -60 dB in 0.5 dB steps (2 dB steps really) and
282 * from -46 dB in 0.25 dB steps
283 */
284static const unsigned int vc_tlv[] = {
285 TLV_DB_RANGE_HEAD(4),
286 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1),
287 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0),
288 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0),
289 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0),
290};
291
292/* from 0 to 6 dB in 2 dB steps if SPF mode != flat */
293static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0);
294
295/* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts
296 * off at 18 dB max) */
297static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0);
298
299/* from -63 to 24 dB in 0.5 dB steps (-128...48) */
300static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1);
301
302/* from 0 to 24 dB in 3 dB steps */
303static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0);
304
305/* from 0 to 30 dB in 2 dB steps */
306static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0);
307
308static const struct snd_kcontrol_new uda1380_snd_controls[] = {
309 SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */
310 SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */
311 SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */
312 SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */
313 SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */
314 SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */
315 SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */
316/**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */
317 SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */
318 SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */
319 SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */
320 SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */
321 SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */
322 SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */
323 SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */
b7482f52
PZ		 324 SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */
325 SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */
326 SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */
327 SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */
328/**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */
329 SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */
330 SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */
331 SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */
332 SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */
333 SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */
334 SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */
335 SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */
336 /* -5.5, -8, -11.5, -14 dBFS */
337 SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0),
338};
339
b7482f52
PZ		 340/* Input mux */
341static const struct snd_kcontrol_new uda1380_input_mux_control =
342 SOC_DAPM_ENUM("Route", uda1380_input_sel_enum);
343
344/* Output mux */
345static const struct snd_kcontrol_new uda1380_output_mux_control =
346 SOC_DAPM_ENUM("Route", uda1380_output_sel_enum);
347
348/* Capture mux */
349static const struct snd_kcontrol_new uda1380_capture_mux_control =
350 SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum);
351
352
353static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = {
354 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
355 &uda1380_input_mux_control),
356 SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0,
357 &uda1380_output_mux_control),
358 SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0,
359 &uda1380_capture_mux_control),
360 SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0),
361 SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0),
362 SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0),
363 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0),
364 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0),
365 SND_SOC_DAPM_INPUT("VINM"),
366 SND_SOC_DAPM_INPUT("VINL"),
367 SND_SOC_DAPM_INPUT("VINR"),
368 SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0),
369 SND_SOC_DAPM_OUTPUT("VOUTLHP"),
370 SND_SOC_DAPM_OUTPUT("VOUTRHP"),
371 SND_SOC_DAPM_OUTPUT("VOUTL"),
372 SND_SOC_DAPM_OUTPUT("VOUTR"),
373 SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0),
374 SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0),
375};
376
377static const struct snd_soc_dapm_route audio_map[] = {
378
379 /* output mux */
380 {"HeadPhone Driver", NULL, "Output Mux"},
381 {"VOUTR", NULL, "Output Mux"},
382 {"VOUTL", NULL, "Output Mux"},
383
384 {"Analog Mixer", NULL, "VINR"},
385 {"Analog Mixer", NULL, "VINL"},
386 {"Analog Mixer", NULL, "DAC"},
387
388 {"Output Mux", "DAC", "DAC"},
389 {"Output Mux", "Analog Mixer", "Analog Mixer"},
390
391 /* {"DAC", "Digital Mixer", "I2S" } */
392
393 /* headphone driver */
394 {"VOUTLHP", NULL, "HeadPhone Driver"},
395 {"VOUTRHP", NULL, "HeadPhone Driver"},
396
397 /* input mux */
398 {"Left ADC", NULL, "Input Mux"},
399 {"Input Mux", "Mic", "Mic LNA"},
400 {"Input Mux", "Mic + Line R", "Mic LNA"},
401 {"Input Mux", "Line L", "Left PGA"},
402 {"Input Mux", "Line", "Left PGA"},
403
404 /* right input */
405 {"Right ADC", "Mic + Line R", "Right PGA"},
406 {"Right ADC", "Line", "Right PGA"},
407
408 /* inputs */
409 {"Mic LNA", NULL, "VINM"},
410 {"Left PGA", NULL, "VINL"},
411 {"Right PGA", NULL, "VINR"},
412};
413
414static int uda1380_add_widgets(struct snd_soc_codec *codec)
415{
ce6120cc 416 struct snd_soc_dapm_context *dapm = &codec->dapm;
b7482f52 417
ce6120cc
LG		 418 snd_soc_dapm_new_controls(dapm, uda1380_dapm_widgets,
419 ARRAY_SIZE(uda1380_dapm_widgets));
420 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
b7482f52 421
b7482f52
PZ		 422 return 0;
423}
424
5b247442 425static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai,
b7482f52
PZ		 426 unsigned int fmt)
427{
428 struct snd_soc_codec *codec = codec_dai->codec;
429 int iface;
430
431 /* set up DAI based upon fmt */
432 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
433 iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK);
434
b7482f52
PZ		 435 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
436 case SND_SOC_DAIFMT_I2S:
437 iface |= R01_SFORI_I2S | R01_SFORO_I2S;
438 break;
439 case SND_SOC_DAIFMT_LSB:
5b247442 440 iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16;
b7482f52
PZ		 441 break;
442 case SND_SOC_DAIFMT_MSB:
5b247442
PZ		 443 iface |= R01_SFORI_MSB | R01_SFORO_MSB;
444 }
445
5f2a9384
PZ		 446 /* DATAI is slave only, so in single-link mode, this has to be slave */
447 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
448 return -EINVAL;
5b247442
PZ		 449
450 uda1380_write(codec, UDA1380_IFACE, iface);
451
452 return 0;
453}
454
455static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai,
456 unsigned int fmt)
457{
458 struct snd_soc_codec *codec = codec_dai->codec;
459 int iface;
460
461 /* set up DAI based upon fmt */
462 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
463 iface &= ~R01_SFORI_MASK;
464
465 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
466 case SND_SOC_DAIFMT_I2S:
467 iface |= R01_SFORI_I2S;
468 break;
469 case SND_SOC_DAIFMT_LSB:
470 iface |= R01_SFORI_LSB16;
471 break;
472 case SND_SOC_DAIFMT_MSB:
473 iface |= R01_SFORI_MSB;
474 }
475
5f2a9384
PZ		 476 /* DATAI is slave only, so this has to be slave */
477 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS)
478 return -EINVAL;
479
5b247442
PZ		 480 uda1380_write(codec, UDA1380_IFACE, iface);
481
482 return 0;
483}
484
485static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai,
486 unsigned int fmt)
487{
488 struct snd_soc_codec *codec = codec_dai->codec;
489 int iface;
490
491 /* set up DAI based upon fmt */
492 iface = uda1380_read_reg_cache(codec, UDA1380_IFACE);
493 iface &= ~(R01_SIM | R01_SFORO_MASK);
494
495 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
496 case SND_SOC_DAIFMT_I2S:
497 iface |= R01_SFORO_I2S;
498 break;
499 case SND_SOC_DAIFMT_LSB:
500 iface |= R01_SFORO_LSB16;
501 break;
502 case SND_SOC_DAIFMT_MSB:
503 iface |= R01_SFORO_MSB;
b7482f52
PZ		 504 }
505
506 if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM)
507 iface |= R01_SIM;
508
509 uda1380_write(codec, UDA1380_IFACE, iface);
510
511 return 0;
512}
513
ef9e5e5c
PZ		 514static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd,
515 struct snd_soc_dai *dai)
b7482f52
PZ		 516{
517 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 518 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 519 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
ef9e5e5c
PZ		 520 int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER);
521
522 switch (cmd) {
523 case SNDRV_PCM_TRIGGER_START:
524 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
525 uda1380_write_reg_cache(codec, UDA1380_MIXER,
526 mixer & ~R14_SILENCE);
1abd9184 527 schedule_work(&uda1380->work);
ef9e5e5c
PZ		 528 break;
529 case SNDRV_PCM_TRIGGER_STOP:
530 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
531 uda1380_write_reg_cache(codec, UDA1380_MIXER,
532 mixer | R14_SILENCE);
1abd9184 533 schedule_work(&uda1380->work);
ef9e5e5c 534 break;
b7482f52 535 }
b7482f52
PZ		 536 return 0;
537}
538
539static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 540 struct snd_pcm_hw_params *params,
541 struct snd_soc_dai *dai)
b7482f52
PZ		 542{
543 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 544 struct snd_soc_codec *codec = rtd->codec;
b7482f52
PZ		 545 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
546
547 /* set WSPLL power and divider if running from this clock */
548 if (clk & R00_DAC_CLK) {
549 int rate = params_rate(params);
550 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
551 clk &= ~0x3; /* clear SEL_LOOP_DIV */
552 switch (rate) {
553 case 6250 ... 12500:
554 clk |= 0x0;
555 break;
556 case 12501 ... 25000:
557 clk |= 0x1;
558 break;
559 case 25001 ... 50000:
560 clk |= 0x2;
561 break;
562 case 50001 ... 100000:
563 clk |= 0x3;
564 break;
565 }
566 uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm);
567 }
568
569 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
570 clk |= R00_EN_DAC | R00_EN_INT;
571 else
572 clk |= R00_EN_ADC | R00_EN_DEC;
573
574 uda1380_write(codec, UDA1380_CLK, clk);
575 return 0;
576}
577
dee89c4d
MB		 578static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream,
579 struct snd_soc_dai *dai)
b7482f52
PZ		 580{
581 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 582 struct snd_soc_codec *codec = rtd->codec;
b7482f52
PZ		 583 u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK);
584
585 /* shut down WSPLL power if running from this clock */
586 if (clk & R00_DAC_CLK) {
587 u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM);
588 uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm);
589 }
590
591 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
592 clk &= ~(R00_EN_DAC | R00_EN_INT);
593 else
594 clk &= ~(R00_EN_ADC | R00_EN_DEC);
595
596 uda1380_write(codec, UDA1380_CLK, clk);
597}
598
b7482f52
PZ		 599static int uda1380_set_bias_level(struct snd_soc_codec *codec,
600 enum snd_soc_bias_level level)
601{
602 int pm = uda1380_read_reg_cache(codec, UDA1380_PM);
8614d310
VK		 603 int reg;
604 struct uda1380_platform_data *pdata = codec->dev->platform_data;
605
ce6120cc 606 if (codec->dapm.bias_level == level)
8614d310 607 return 0;
b7482f52
PZ		 608
609 switch (level) {
610 case SND_SOC_BIAS_ON:
611 case SND_SOC_BIAS_PREPARE:
8614d310 612 /* ADC, DAC on */
b7482f52
PZ		 613 uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm);
614 break;
615 case SND_SOC_BIAS_STANDBY:
ce6120cc 616 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8614d310
VK		 617 if (gpio_is_valid(pdata->gpio_power)) {
618 gpio_set_value(pdata->gpio_power, 1);
8e3dce4d 619 mdelay(1);
8614d310
VK		 620 uda1380_reset(codec);
621 }
622
623 uda1380_sync_cache(codec);
624 }
b7482f52
PZ		 625 uda1380_write(codec, UDA1380_PM, 0x0);
626 break;
8614d310
VK		 627 case SND_SOC_BIAS_OFF:
628 if (!gpio_is_valid(pdata->gpio_power))
629 break;
630
631 gpio_set_value(pdata->gpio_power, 0);
632
633 /* Mark mixer regs cache dirty to sync them with
634 * codec regs on power on.
635 */
636 for (reg = UDA1380_MVOL; reg < UDA1380_CACHEREGNUM; reg++)
637 set_bit(reg - 0x10, &uda1380_cache_dirty);
b7482f52 638 }
ce6120cc 639 codec->dapm.bias_level = level;
b7482f52
PZ		 640 return 0;
641}
642
643#define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
644 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
645 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
646
6335d055
EM		 647static struct snd_soc_dai_ops uda1380_dai_ops = {
648 .hw_params = uda1380_pcm_hw_params,
649 .shutdown = uda1380_pcm_shutdown,
65ec1cd1 650 .trigger = uda1380_trigger,
6335d055
EM		 651 .set_fmt = uda1380_set_dai_fmt_both,
652};
653
654static struct snd_soc_dai_ops uda1380_dai_ops_playback = {
655 .hw_params = uda1380_pcm_hw_params,
656 .shutdown = uda1380_pcm_shutdown,
65ec1cd1 657 .trigger = uda1380_trigger,
6335d055
EM		 658 .set_fmt = uda1380_set_dai_fmt_playback,
659};
660
661static struct snd_soc_dai_ops uda1380_dai_ops_capture = {
662 .hw_params = uda1380_pcm_hw_params,
663 .shutdown = uda1380_pcm_shutdown,
65ec1cd1 664 .trigger = uda1380_trigger,
6335d055
EM		 665 .set_fmt = uda1380_set_dai_fmt_capture,
666};
667
f0fba2ad 668static struct snd_soc_dai_driver uda1380_dai[] = {
b7482f52 669{
f0fba2ad 670 .name = "uda1380-hifi",
b7482f52
PZ		 671 .playback = {
672 .stream_name = "Playback",
673 .channels_min = 1,
674 .channels_max = 2,
675 .rates = UDA1380_RATES,
676 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
677 .capture = {
678 .stream_name = "Capture",
679 .channels_min = 1,
680 .channels_max = 2,
681 .rates = UDA1380_RATES,
682 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
6335d055 683 .ops = &uda1380_dai_ops,
b7482f52
PZ		 684},
685{ /* playback only - dual interface */
f0fba2ad 686 .name = "uda1380-hifi-playback",
b7482f52
PZ		 687 .playback = {
688 .stream_name = "Playback",
689 .channels_min = 1,
690 .channels_max = 2,
691 .rates = UDA1380_RATES,
692 .formats = SNDRV_PCM_FMTBIT_S16_LE,
693 },
6335d055 694 .ops = &uda1380_dai_ops_playback,
b7482f52
PZ		 695},
696{ /* capture only - dual interface*/
f0fba2ad 697 .name = "uda1380-hifi-capture",
b7482f52
PZ		 698 .capture = {
699 .stream_name = "Capture",
700 .channels_min = 1,
701 .channels_max = 2,
702 .rates = UDA1380_RATES,
703 .formats = SNDRV_PCM_FMTBIT_S16_LE,
704 },
6335d055 705 .ops = &uda1380_dai_ops_capture,
b7482f52
PZ		 706},
707};
b7482f52 708
f0fba2ad 709static int uda1380_suspend(struct snd_soc_codec *codec, pm_message_t state)
b7482f52 710{
b7482f52
PZ		 711 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
712 return 0;
713}
714
f0fba2ad 715static int uda1380_resume(struct snd_soc_codec *codec)
b7482f52 716{
b7482f52 717 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
b7482f52
PZ		 718 return 0;
719}
720
f0fba2ad 721static int uda1380_probe(struct snd_soc_codec *codec)
88fc39d7 722{
f0fba2ad
LG		 723 struct uda1380_platform_data *pdata =codec->dev->platform_data;
724 struct uda1380_priv *uda1380 = snd_soc_codec_get_drvdata(codec);
725 int ret;
88fc39d7 726
8614d310
VK		 727 uda1380->codec = codec;
728
f0fba2ad 729 codec->hw_write = (hw_write_t)i2c_master_send;
8614d310 730 codec->control_data = uda1380->control_data;
1abd9184 731
8614d310 732 if (!pdata)
1abd9184
PZ		 733 return -EINVAL;
734
8614d310
VK		 735 if (gpio_is_valid(pdata->gpio_reset)) {
736 ret = gpio_request(pdata->gpio_reset, "uda1380 reset");
737 if (ret)
738 goto err_out;
739 ret = gpio_direction_output(pdata->gpio_reset, 0);
740 if (ret)
741 goto err_gpio_reset_conf;
742 }
1abd9184 743
8614d310
VK		 744 if (gpio_is_valid(pdata->gpio_power)) {
745 ret = gpio_request(pdata->gpio_power, "uda1380 power");
746 if (ret)
747 goto err_gpio;
748 ret = gpio_direction_output(pdata->gpio_power, 0);
749 if (ret)
750 goto err_gpio_power_conf;
751 } else {
752 ret = uda1380_reset(codec);
753 if (ret) {
754 dev_err(codec->dev, "Failed to issue reset\n");
755 goto err_reset;
756 }
88fc39d7
JD		 757 }
758
1abd9184
PZ		 759 INIT_WORK(&uda1380->work, uda1380_flush_work);
760
f0fba2ad
LG		 761 /* power on device */
762 uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
763 /* set clock input */
764 switch (pdata->dac_clk) {
765 case UDA1380_DAC_CLK_SYSCLK:
8614d310 766 uda1380_write_reg_cache(codec, UDA1380_CLK, 0);
f0fba2ad
LG		 767 break;
768 case UDA1380_DAC_CLK_WSPLL:
8614d310
VK		 769 uda1380_write_reg_cache(codec, UDA1380_CLK,
770 R00_DAC_CLK);
f0fba2ad 771 break;
88fc39d7
JD		 772 }
773
f0fba2ad
LG		 774 snd_soc_add_controls(codec, uda1380_snd_controls,
775 ARRAY_SIZE(uda1380_snd_controls));
776 uda1380_add_widgets(codec);
88fc39d7
JD		 777
778 return 0;
779
1abd9184 780err_reset:
8614d310
VK		 781err_gpio_power_conf:
782 if (gpio_is_valid(pdata->gpio_power))
783 gpio_free(pdata->gpio_power);
784
785err_gpio_reset_conf:
1abd9184 786err_gpio:
8614d310
VK		 787 if (gpio_is_valid(pdata->gpio_reset))
788 gpio_free(pdata->gpio_reset);
789err_out:
1abd9184 790 return ret;
88fc39d7 791}
b7482f52 792
f0fba2ad
LG		 793/* power down chip */
794static int uda1380_remove(struct snd_soc_codec *codec)
b7482f52 795{
f0fba2ad 796 struct uda1380_platform_data *pdata =codec->dev->platform_data;
1abd9184 797
f0fba2ad 798 uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF);
1abd9184 799
1abd9184
PZ		 800 gpio_free(pdata->gpio_reset);
801 gpio_free(pdata->gpio_power);
802
f0fba2ad 803 return 0;
1abd9184
PZ		 804}
805
f0fba2ad
LG		 806static struct snd_soc_codec_driver soc_codec_dev_uda1380 = {
807 .probe = uda1380_probe,
808 .remove = uda1380_remove,
809 .suspend = uda1380_suspend,
810 .resume = uda1380_resume,
8614d310
VK		 811 .read = uda1380_read_reg_cache,
812 .write = uda1380_write,
f0fba2ad
LG		 813 .set_bias_level = uda1380_set_bias_level,
814 .reg_cache_size = ARRAY_SIZE(uda1380_reg),
815 .reg_word_size = sizeof(u16),
816 .reg_cache_default = uda1380_reg,
817 .reg_cache_step = 1,
818};
819
1abd9184
PZ		 820#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
821static __devinit int uda1380_i2c_probe(struct i2c_client *i2c,
822 const struct i2c_device_id *id)
823{
824 struct uda1380_priv *uda1380;
b7c9d852 825 int ret;
b7482f52 826
1abd9184
PZ		 827 uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL);
828 if (uda1380 == NULL)
b7482f52
PZ		 829 return -ENOMEM;
830
1abd9184 831 i2c_set_clientdata(i2c, uda1380);
8614d310 832 uda1380->control_data = i2c;
3051e41a 833
f0fba2ad
LG		 834 ret = snd_soc_register_codec(&i2c->dev,
835 &soc_codec_dev_uda1380, uda1380_dai, ARRAY_SIZE(uda1380_dai));
836 if (ret < 0)
1abd9184 837 kfree(uda1380);
b7482f52
PZ		 838 return ret;
839}
840
1abd9184 841static int __devexit uda1380_i2c_remove(struct i2c_client *i2c)
b7482f52 842{
f0fba2ad
LG		 843 snd_soc_unregister_codec(&i2c->dev);
844 kfree(i2c_get_clientdata(i2c));
b7482f52
PZ		 845 return 0;
846}
847
1abd9184
PZ		 848static const struct i2c_device_id uda1380_i2c_id[] = {
849 { "uda1380", 0 },
850 { }
b7482f52 851};
1abd9184
PZ		 852MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id);
853
854static struct i2c_driver uda1380_i2c_driver = {
855 .driver = {
f0fba2ad 856 .name = "uda1380-codec",
1abd9184
PZ		 857 .owner = THIS_MODULE,
858 },
859 .probe = uda1380_i2c_probe,
860 .remove = __devexit_p(uda1380_i2c_remove),
861 .id_table = uda1380_i2c_id,
862};
863#endif
b7482f52 864
c9b3a40f 865static int __init uda1380_modinit(void)
64089b84 866{
1abd9184
PZ		 867 int ret;
868#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
869 ret = i2c_add_driver(&uda1380_i2c_driver);
870 if (ret != 0)
871 pr_err("Failed to register UDA1380 I2C driver: %d\n", ret);
872#endif
873 return 0;
64089b84
MB		 874}
875module_init(uda1380_modinit);
876
877static void __exit uda1380_exit(void)
878{
1abd9184
PZ		 879#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
880 i2c_del_driver(&uda1380_i2c_driver);
881#endif
64089b84
MB		 882}
883module_exit(uda1380_exit);
884
b7482f52
PZ		 885MODULE_AUTHOR("Giorgio Padrin");
886MODULE_DESCRIPTION("Audio support for codec Philips UDA1380");
887MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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