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b7482f52 PZ |
1 | /* |
2 | * uda1380.c - Philips UDA1380 ALSA SoC audio driver | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
1abd9184 | 8 | * Copyright (c) 2007-2009 Philipp Zabel <philipp.zabel@gmail.com> |
b7482f52 PZ |
9 | * |
10 | * Modified by Richard Purdie <richard@openedhand.com> to fit into SoC | |
11 | * codec model. | |
12 | * | |
13 | * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org> | |
14 | * Copyright 2005 Openedhand Ltd. | |
15 | */ | |
16 | ||
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/types.h> | |
b7482f52 PZ |
20 | #include <linux/slab.h> |
21 | #include <linux/errno.h> | |
1abd9184 | 22 | #include <linux/gpio.h> |
b7482f52 PZ |
23 | #include <linux/delay.h> |
24 | #include <linux/i2c.h> | |
ef9e5e5c | 25 | #include <linux/workqueue.h> |
b7482f52 PZ |
26 | #include <sound/core.h> |
27 | #include <sound/control.h> | |
28 | #include <sound/initval.h> | |
b7482f52 PZ |
29 | #include <sound/soc.h> |
30 | #include <sound/soc-dapm.h> | |
31 | #include <sound/tlv.h> | |
1abd9184 | 32 | #include <sound/uda1380.h> |
b7482f52 PZ |
33 | |
34 | #include "uda1380.h" | |
35 | ||
ef9e5e5c PZ |
36 | static struct snd_soc_codec *uda1380_codec; |
37 | ||
1abd9184 PZ |
38 | /* codec private data */ |
39 | struct uda1380_priv { | |
40 | struct snd_soc_codec codec; | |
41 | u16 reg_cache[UDA1380_CACHEREGNUM]; | |
42 | unsigned int dac_clk; | |
43 | struct work_struct work; | |
44 | }; | |
45 | ||
b7482f52 PZ |
46 | /* |
47 | * uda1380 register cache | |
48 | */ | |
49 | static const u16 uda1380_reg[UDA1380_CACHEREGNUM] = { | |
50 | 0x0502, 0x0000, 0x0000, 0x3f3f, | |
51 | 0x0202, 0x0000, 0x0000, 0x0000, | |
52 | 0x0000, 0x0000, 0x0000, 0x0000, | |
53 | 0x0000, 0x0000, 0x0000, 0x0000, | |
54 | 0x0000, 0xff00, 0x0000, 0x4800, | |
55 | 0x0000, 0x0000, 0x0000, 0x0000, | |
56 | 0x0000, 0x0000, 0x0000, 0x0000, | |
57 | 0x0000, 0x0000, 0x0000, 0x0000, | |
58 | 0x0000, 0x8000, 0x0002, 0x0000, | |
59 | }; | |
60 | ||
ef9e5e5c PZ |
61 | static unsigned long uda1380_cache_dirty; |
62 | ||
b7482f52 PZ |
63 | /* |
64 | * read uda1380 register cache | |
65 | */ | |
66 | static inline unsigned int uda1380_read_reg_cache(struct snd_soc_codec *codec, | |
67 | unsigned int reg) | |
68 | { | |
69 | u16 *cache = codec->reg_cache; | |
70 | if (reg == UDA1380_RESET) | |
71 | return 0; | |
72 | if (reg >= UDA1380_CACHEREGNUM) | |
73 | return -1; | |
74 | return cache[reg]; | |
75 | } | |
76 | ||
77 | /* | |
78 | * write uda1380 register cache | |
79 | */ | |
80 | static inline void uda1380_write_reg_cache(struct snd_soc_codec *codec, | |
81 | u16 reg, unsigned int value) | |
82 | { | |
83 | u16 *cache = codec->reg_cache; | |
ef9e5e5c | 84 | |
b7482f52 PZ |
85 | if (reg >= UDA1380_CACHEREGNUM) |
86 | return; | |
ef9e5e5c PZ |
87 | if ((reg >= 0x10) && (cache[reg] != value)) |
88 | set_bit(reg - 0x10, &uda1380_cache_dirty); | |
b7482f52 PZ |
89 | cache[reg] = value; |
90 | } | |
91 | ||
92 | /* | |
93 | * write to the UDA1380 register space | |
94 | */ | |
95 | static int uda1380_write(struct snd_soc_codec *codec, unsigned int reg, | |
96 | unsigned int value) | |
97 | { | |
98 | u8 data[3]; | |
99 | ||
100 | /* data is | |
101 | * data[0] is register offset | |
102 | * data[1] is MS byte | |
103 | * data[2] is LS byte | |
104 | */ | |
105 | data[0] = reg; | |
106 | data[1] = (value & 0xff00) >> 8; | |
107 | data[2] = value & 0x00ff; | |
108 | ||
109 | uda1380_write_reg_cache(codec, reg, value); | |
110 | ||
111 | /* the interpolator & decimator regs must only be written when the | |
112 | * codec DAI is active. | |
113 | */ | |
114 | if (!codec->active && (reg >= UDA1380_MVOL)) | |
115 | return 0; | |
116 | pr_debug("uda1380: hw write %x val %x\n", reg, value); | |
117 | if (codec->hw_write(codec->control_data, data, 3) == 3) { | |
118 | unsigned int val; | |
119 | i2c_master_send(codec->control_data, data, 1); | |
120 | i2c_master_recv(codec->control_data, data, 2); | |
121 | val = (data[0]<<8) | data[1]; | |
122 | if (val != value) { | |
123 | pr_debug("uda1380: READ BACK VAL %x\n", | |
124 | (data[0]<<8) | data[1]); | |
125 | return -EIO; | |
126 | } | |
ef9e5e5c PZ |
127 | if (reg >= 0x10) |
128 | clear_bit(reg - 0x10, &uda1380_cache_dirty); | |
b7482f52 PZ |
129 | return 0; |
130 | } else | |
131 | return -EIO; | |
132 | } | |
133 | ||
134 | #define uda1380_reset(c) uda1380_write(c, UDA1380_RESET, 0) | |
135 | ||
ef9e5e5c PZ |
136 | static void uda1380_flush_work(struct work_struct *work) |
137 | { | |
138 | int bit, reg; | |
139 | ||
140 | for_each_bit(bit, &uda1380_cache_dirty, UDA1380_CACHEREGNUM - 0x10) { | |
141 | reg = 0x10 + bit; | |
142 | pr_debug("uda1380: flush reg %x val %x:\n", reg, | |
143 | uda1380_read_reg_cache(uda1380_codec, reg)); | |
144 | uda1380_write(uda1380_codec, reg, | |
145 | uda1380_read_reg_cache(uda1380_codec, reg)); | |
146 | clear_bit(bit, &uda1380_cache_dirty); | |
147 | } | |
148 | } | |
149 | ||
b7482f52 PZ |
150 | /* declarations of ALSA reg_elem_REAL controls */ |
151 | static const char *uda1380_deemp[] = { | |
152 | "None", | |
153 | "32kHz", | |
154 | "44.1kHz", | |
155 | "48kHz", | |
156 | "96kHz", | |
157 | }; | |
158 | static const char *uda1380_input_sel[] = { | |
159 | "Line", | |
160 | "Mic + Line R", | |
161 | "Line L", | |
162 | "Mic", | |
163 | }; | |
164 | static const char *uda1380_output_sel[] = { | |
165 | "DAC", | |
166 | "Analog Mixer", | |
167 | }; | |
168 | static const char *uda1380_spf_mode[] = { | |
169 | "Flat", | |
170 | "Minimum1", | |
171 | "Minimum2", | |
172 | "Maximum" | |
173 | }; | |
174 | static const char *uda1380_capture_sel[] = { | |
175 | "ADC", | |
176 | "Digital Mixer" | |
177 | }; | |
178 | static const char *uda1380_sel_ns[] = { | |
179 | "3rd-order", | |
180 | "5th-order" | |
181 | }; | |
182 | static const char *uda1380_mix_control[] = { | |
183 | "off", | |
184 | "PCM only", | |
185 | "before sound processing", | |
186 | "after sound processing" | |
187 | }; | |
188 | static const char *uda1380_sdet_setting[] = { | |
189 | "3200", | |
190 | "4800", | |
191 | "9600", | |
192 | "19200" | |
193 | }; | |
194 | static const char *uda1380_os_setting[] = { | |
195 | "single-speed", | |
196 | "double-speed (no mixing)", | |
197 | "quad-speed (no mixing)" | |
198 | }; | |
199 | ||
200 | static const struct soc_enum uda1380_deemp_enum[] = { | |
201 | SOC_ENUM_SINGLE(UDA1380_DEEMP, 8, 5, uda1380_deemp), | |
202 | SOC_ENUM_SINGLE(UDA1380_DEEMP, 0, 5, uda1380_deemp), | |
203 | }; | |
204 | static const struct soc_enum uda1380_input_sel_enum = | |
205 | SOC_ENUM_SINGLE(UDA1380_ADC, 2, 4, uda1380_input_sel); /* SEL_MIC, SEL_LNA */ | |
206 | static const struct soc_enum uda1380_output_sel_enum = | |
207 | SOC_ENUM_SINGLE(UDA1380_PM, 7, 2, uda1380_output_sel); /* R02_EN_AVC */ | |
208 | static const struct soc_enum uda1380_spf_enum = | |
209 | SOC_ENUM_SINGLE(UDA1380_MODE, 14, 4, uda1380_spf_mode); /* M */ | |
210 | static const struct soc_enum uda1380_capture_sel_enum = | |
211 | SOC_ENUM_SINGLE(UDA1380_IFACE, 6, 2, uda1380_capture_sel); /* SEL_SOURCE */ | |
212 | static const struct soc_enum uda1380_sel_ns_enum = | |
213 | SOC_ENUM_SINGLE(UDA1380_MIXER, 14, 2, uda1380_sel_ns); /* SEL_NS */ | |
214 | static const struct soc_enum uda1380_mix_enum = | |
215 | SOC_ENUM_SINGLE(UDA1380_MIXER, 12, 4, uda1380_mix_control); /* MIX, MIX_POS */ | |
216 | static const struct soc_enum uda1380_sdet_enum = | |
217 | SOC_ENUM_SINGLE(UDA1380_MIXER, 4, 4, uda1380_sdet_setting); /* SD_VALUE */ | |
218 | static const struct soc_enum uda1380_os_enum = | |
219 | SOC_ENUM_SINGLE(UDA1380_MIXER, 0, 3, uda1380_os_setting); /* OS */ | |
220 | ||
221 | /* | |
222 | * from -48 dB in 1.5 dB steps (mute instead of -49.5 dB) | |
223 | */ | |
224 | static DECLARE_TLV_DB_SCALE(amix_tlv, -4950, 150, 1); | |
225 | ||
226 | /* | |
227 | * from -78 dB in 1 dB steps (3 dB steps, really. LSB are ignored), | |
228 | * from -66 dB in 0.5 dB steps (2 dB steps, really) and | |
229 | * from -52 dB in 0.25 dB steps | |
230 | */ | |
231 | static const unsigned int mvol_tlv[] = { | |
232 | TLV_DB_RANGE_HEAD(3), | |
233 | 0, 15, TLV_DB_SCALE_ITEM(-8200, 100, 1), | |
234 | 16, 43, TLV_DB_SCALE_ITEM(-6600, 50, 0), | |
235 | 44, 252, TLV_DB_SCALE_ITEM(-5200, 25, 0), | |
236 | }; | |
237 | ||
238 | /* | |
239 | * from -72 dB in 1.5 dB steps (6 dB steps really), | |
240 | * from -66 dB in 0.75 dB steps (3 dB steps really), | |
241 | * from -60 dB in 0.5 dB steps (2 dB steps really) and | |
242 | * from -46 dB in 0.25 dB steps | |
243 | */ | |
244 | static const unsigned int vc_tlv[] = { | |
245 | TLV_DB_RANGE_HEAD(4), | |
246 | 0, 7, TLV_DB_SCALE_ITEM(-7800, 150, 1), | |
247 | 8, 15, TLV_DB_SCALE_ITEM(-6600, 75, 0), | |
248 | 16, 43, TLV_DB_SCALE_ITEM(-6000, 50, 0), | |
249 | 44, 228, TLV_DB_SCALE_ITEM(-4600, 25, 0), | |
250 | }; | |
251 | ||
252 | /* from 0 to 6 dB in 2 dB steps if SPF mode != flat */ | |
253 | static DECLARE_TLV_DB_SCALE(tr_tlv, 0, 200, 0); | |
254 | ||
255 | /* from 0 to 24 dB in 2 dB steps, if SPF mode == maximum, otherwise cuts | |
256 | * off at 18 dB max) */ | |
257 | static DECLARE_TLV_DB_SCALE(bb_tlv, 0, 200, 0); | |
258 | ||
259 | /* from -63 to 24 dB in 0.5 dB steps (-128...48) */ | |
260 | static DECLARE_TLV_DB_SCALE(dec_tlv, -6400, 50, 1); | |
261 | ||
262 | /* from 0 to 24 dB in 3 dB steps */ | |
263 | static DECLARE_TLV_DB_SCALE(pga_tlv, 0, 300, 0); | |
264 | ||
265 | /* from 0 to 30 dB in 2 dB steps */ | |
266 | static DECLARE_TLV_DB_SCALE(vga_tlv, 0, 200, 0); | |
267 | ||
268 | static const struct snd_kcontrol_new uda1380_snd_controls[] = { | |
269 | SOC_DOUBLE_TLV("Analog Mixer Volume", UDA1380_AMIX, 0, 8, 44, 1, amix_tlv), /* AVCR, AVCL */ | |
270 | SOC_DOUBLE_TLV("Master Playback Volume", UDA1380_MVOL, 0, 8, 252, 1, mvol_tlv), /* MVCL, MVCR */ | |
271 | SOC_SINGLE_TLV("ADC Playback Volume", UDA1380_MIXVOL, 8, 228, 1, vc_tlv), /* VC2 */ | |
272 | SOC_SINGLE_TLV("PCM Playback Volume", UDA1380_MIXVOL, 0, 228, 1, vc_tlv), /* VC1 */ | |
273 | SOC_ENUM("Sound Processing Filter", uda1380_spf_enum), /* M */ | |
274 | SOC_DOUBLE_TLV("Tone Control - Treble", UDA1380_MODE, 4, 12, 3, 0, tr_tlv), /* TRL, TRR */ | |
275 | SOC_DOUBLE_TLV("Tone Control - Bass", UDA1380_MODE, 0, 8, 15, 0, bb_tlv), /* BBL, BBR */ | |
276 | /**/ SOC_SINGLE("Master Playback Switch", UDA1380_DEEMP, 14, 1, 1), /* MTM */ | |
277 | SOC_SINGLE("ADC Playback Switch", UDA1380_DEEMP, 11, 1, 1), /* MT2 from decimation filter */ | |
278 | SOC_ENUM("ADC Playback De-emphasis", uda1380_deemp_enum[0]), /* DE2 */ | |
279 | SOC_SINGLE("PCM Playback Switch", UDA1380_DEEMP, 3, 1, 1), /* MT1, from digital data input */ | |
280 | SOC_ENUM("PCM Playback De-emphasis", uda1380_deemp_enum[1]), /* DE1 */ | |
281 | SOC_SINGLE("DAC Polarity inverting Switch", UDA1380_MIXER, 15, 1, 0), /* DA_POL_INV */ | |
282 | SOC_ENUM("Noise Shaper", uda1380_sel_ns_enum), /* SEL_NS */ | |
283 | SOC_ENUM("Digital Mixer Signal Control", uda1380_mix_enum), /* MIX_POS, MIX */ | |
b7482f52 PZ |
284 | SOC_SINGLE("Silence Detector Switch", UDA1380_MIXER, 6, 1, 0), /* SDET_ON */ |
285 | SOC_ENUM("Silence Detector Setting", uda1380_sdet_enum), /* SD_VALUE */ | |
286 | SOC_ENUM("Oversampling Input", uda1380_os_enum), /* OS */ | |
287 | SOC_DOUBLE_S8_TLV("ADC Capture Volume", UDA1380_DEC, -128, 48, dec_tlv), /* ML_DEC, MR_DEC */ | |
288 | /**/ SOC_SINGLE("ADC Capture Switch", UDA1380_PGA, 15, 1, 1), /* MT_ADC */ | |
289 | SOC_DOUBLE_TLV("Line Capture Volume", UDA1380_PGA, 0, 8, 8, 0, pga_tlv), /* PGA_GAINCTRLL, PGA_GAINCTRLR */ | |
290 | SOC_SINGLE("ADC Polarity inverting Switch", UDA1380_ADC, 12, 1, 0), /* ADCPOL_INV */ | |
291 | SOC_SINGLE_TLV("Mic Capture Volume", UDA1380_ADC, 8, 15, 0, vga_tlv), /* VGA_CTRL */ | |
292 | SOC_SINGLE("DC Filter Bypass Switch", UDA1380_ADC, 1, 1, 0), /* SKIP_DCFIL (before decimator) */ | |
293 | SOC_SINGLE("DC Filter Enable Switch", UDA1380_ADC, 0, 1, 0), /* EN_DCFIL (at output of decimator) */ | |
294 | SOC_SINGLE("AGC Timing", UDA1380_AGC, 8, 7, 0), /* TODO: enum, see table 62 */ | |
295 | SOC_SINGLE("AGC Target level", UDA1380_AGC, 2, 3, 1), /* AGC_LEVEL */ | |
296 | /* -5.5, -8, -11.5, -14 dBFS */ | |
297 | SOC_SINGLE("AGC Switch", UDA1380_AGC, 0, 1, 0), | |
298 | }; | |
299 | ||
b7482f52 PZ |
300 | /* Input mux */ |
301 | static const struct snd_kcontrol_new uda1380_input_mux_control = | |
302 | SOC_DAPM_ENUM("Route", uda1380_input_sel_enum); | |
303 | ||
304 | /* Output mux */ | |
305 | static const struct snd_kcontrol_new uda1380_output_mux_control = | |
306 | SOC_DAPM_ENUM("Route", uda1380_output_sel_enum); | |
307 | ||
308 | /* Capture mux */ | |
309 | static const struct snd_kcontrol_new uda1380_capture_mux_control = | |
310 | SOC_DAPM_ENUM("Route", uda1380_capture_sel_enum); | |
311 | ||
312 | ||
313 | static const struct snd_soc_dapm_widget uda1380_dapm_widgets[] = { | |
314 | SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0, | |
315 | &uda1380_input_mux_control), | |
316 | SND_SOC_DAPM_MUX("Output Mux", SND_SOC_NOPM, 0, 0, | |
317 | &uda1380_output_mux_control), | |
318 | SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, | |
319 | &uda1380_capture_mux_control), | |
320 | SND_SOC_DAPM_PGA("Left PGA", UDA1380_PM, 3, 0, NULL, 0), | |
321 | SND_SOC_DAPM_PGA("Right PGA", UDA1380_PM, 1, 0, NULL, 0), | |
322 | SND_SOC_DAPM_PGA("Mic LNA", UDA1380_PM, 4, 0, NULL, 0), | |
323 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", UDA1380_PM, 2, 0), | |
324 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", UDA1380_PM, 0, 0), | |
325 | SND_SOC_DAPM_INPUT("VINM"), | |
326 | SND_SOC_DAPM_INPUT("VINL"), | |
327 | SND_SOC_DAPM_INPUT("VINR"), | |
328 | SND_SOC_DAPM_MIXER("Analog Mixer", UDA1380_PM, 6, 0, NULL, 0), | |
329 | SND_SOC_DAPM_OUTPUT("VOUTLHP"), | |
330 | SND_SOC_DAPM_OUTPUT("VOUTRHP"), | |
331 | SND_SOC_DAPM_OUTPUT("VOUTL"), | |
332 | SND_SOC_DAPM_OUTPUT("VOUTR"), | |
333 | SND_SOC_DAPM_DAC("DAC", "Playback", UDA1380_PM, 10, 0), | |
334 | SND_SOC_DAPM_PGA("HeadPhone Driver", UDA1380_PM, 13, 0, NULL, 0), | |
335 | }; | |
336 | ||
337 | static const struct snd_soc_dapm_route audio_map[] = { | |
338 | ||
339 | /* output mux */ | |
340 | {"HeadPhone Driver", NULL, "Output Mux"}, | |
341 | {"VOUTR", NULL, "Output Mux"}, | |
342 | {"VOUTL", NULL, "Output Mux"}, | |
343 | ||
344 | {"Analog Mixer", NULL, "VINR"}, | |
345 | {"Analog Mixer", NULL, "VINL"}, | |
346 | {"Analog Mixer", NULL, "DAC"}, | |
347 | ||
348 | {"Output Mux", "DAC", "DAC"}, | |
349 | {"Output Mux", "Analog Mixer", "Analog Mixer"}, | |
350 | ||
351 | /* {"DAC", "Digital Mixer", "I2S" } */ | |
352 | ||
353 | /* headphone driver */ | |
354 | {"VOUTLHP", NULL, "HeadPhone Driver"}, | |
355 | {"VOUTRHP", NULL, "HeadPhone Driver"}, | |
356 | ||
357 | /* input mux */ | |
358 | {"Left ADC", NULL, "Input Mux"}, | |
359 | {"Input Mux", "Mic", "Mic LNA"}, | |
360 | {"Input Mux", "Mic + Line R", "Mic LNA"}, | |
361 | {"Input Mux", "Line L", "Left PGA"}, | |
362 | {"Input Mux", "Line", "Left PGA"}, | |
363 | ||
364 | /* right input */ | |
365 | {"Right ADC", "Mic + Line R", "Right PGA"}, | |
366 | {"Right ADC", "Line", "Right PGA"}, | |
367 | ||
368 | /* inputs */ | |
369 | {"Mic LNA", NULL, "VINM"}, | |
370 | {"Left PGA", NULL, "VINL"}, | |
371 | {"Right PGA", NULL, "VINR"}, | |
372 | }; | |
373 | ||
374 | static int uda1380_add_widgets(struct snd_soc_codec *codec) | |
375 | { | |
376 | snd_soc_dapm_new_controls(codec, uda1380_dapm_widgets, | |
377 | ARRAY_SIZE(uda1380_dapm_widgets)); | |
378 | ||
379 | snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); | |
380 | ||
381 | snd_soc_dapm_new_widgets(codec); | |
382 | return 0; | |
383 | } | |
384 | ||
5b247442 | 385 | static int uda1380_set_dai_fmt_both(struct snd_soc_dai *codec_dai, |
b7482f52 PZ |
386 | unsigned int fmt) |
387 | { | |
388 | struct snd_soc_codec *codec = codec_dai->codec; | |
389 | int iface; | |
390 | ||
391 | /* set up DAI based upon fmt */ | |
392 | iface = uda1380_read_reg_cache(codec, UDA1380_IFACE); | |
393 | iface &= ~(R01_SFORI_MASK | R01_SIM | R01_SFORO_MASK); | |
394 | ||
b7482f52 PZ |
395 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { |
396 | case SND_SOC_DAIFMT_I2S: | |
397 | iface |= R01_SFORI_I2S | R01_SFORO_I2S; | |
398 | break; | |
399 | case SND_SOC_DAIFMT_LSB: | |
5b247442 | 400 | iface |= R01_SFORI_LSB16 | R01_SFORO_LSB16; |
b7482f52 PZ |
401 | break; |
402 | case SND_SOC_DAIFMT_MSB: | |
5b247442 PZ |
403 | iface |= R01_SFORI_MSB | R01_SFORO_MSB; |
404 | } | |
405 | ||
5f2a9384 PZ |
406 | /* DATAI is slave only, so in single-link mode, this has to be slave */ |
407 | if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) | |
408 | return -EINVAL; | |
5b247442 PZ |
409 | |
410 | uda1380_write(codec, UDA1380_IFACE, iface); | |
411 | ||
412 | return 0; | |
413 | } | |
414 | ||
415 | static int uda1380_set_dai_fmt_playback(struct snd_soc_dai *codec_dai, | |
416 | unsigned int fmt) | |
417 | { | |
418 | struct snd_soc_codec *codec = codec_dai->codec; | |
419 | int iface; | |
420 | ||
421 | /* set up DAI based upon fmt */ | |
422 | iface = uda1380_read_reg_cache(codec, UDA1380_IFACE); | |
423 | iface &= ~R01_SFORI_MASK; | |
424 | ||
425 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
426 | case SND_SOC_DAIFMT_I2S: | |
427 | iface |= R01_SFORI_I2S; | |
428 | break; | |
429 | case SND_SOC_DAIFMT_LSB: | |
430 | iface |= R01_SFORI_LSB16; | |
431 | break; | |
432 | case SND_SOC_DAIFMT_MSB: | |
433 | iface |= R01_SFORI_MSB; | |
434 | } | |
435 | ||
5f2a9384 PZ |
436 | /* DATAI is slave only, so this has to be slave */ |
437 | if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) != SND_SOC_DAIFMT_CBS_CFS) | |
438 | return -EINVAL; | |
439 | ||
5b247442 PZ |
440 | uda1380_write(codec, UDA1380_IFACE, iface); |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
445 | static int uda1380_set_dai_fmt_capture(struct snd_soc_dai *codec_dai, | |
446 | unsigned int fmt) | |
447 | { | |
448 | struct snd_soc_codec *codec = codec_dai->codec; | |
449 | int iface; | |
450 | ||
451 | /* set up DAI based upon fmt */ | |
452 | iface = uda1380_read_reg_cache(codec, UDA1380_IFACE); | |
453 | iface &= ~(R01_SIM | R01_SFORO_MASK); | |
454 | ||
455 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
456 | case SND_SOC_DAIFMT_I2S: | |
457 | iface |= R01_SFORO_I2S; | |
458 | break; | |
459 | case SND_SOC_DAIFMT_LSB: | |
460 | iface |= R01_SFORO_LSB16; | |
461 | break; | |
462 | case SND_SOC_DAIFMT_MSB: | |
463 | iface |= R01_SFORO_MSB; | |
b7482f52 PZ |
464 | } |
465 | ||
466 | if ((fmt & SND_SOC_DAIFMT_MASTER_MASK) == SND_SOC_DAIFMT_CBM_CFM) | |
467 | iface |= R01_SIM; | |
468 | ||
469 | uda1380_write(codec, UDA1380_IFACE, iface); | |
470 | ||
471 | return 0; | |
472 | } | |
473 | ||
ef9e5e5c PZ |
474 | static int uda1380_trigger(struct snd_pcm_substream *substream, int cmd, |
475 | struct snd_soc_dai *dai) | |
b7482f52 PZ |
476 | { |
477 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
478 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 479 | struct snd_soc_codec *codec = socdev->card->codec; |
1abd9184 | 480 | struct uda1380_priv *uda1380 = codec->private_data; |
ef9e5e5c PZ |
481 | int mixer = uda1380_read_reg_cache(codec, UDA1380_MIXER); |
482 | ||
483 | switch (cmd) { | |
484 | case SNDRV_PCM_TRIGGER_START: | |
485 | case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: | |
486 | uda1380_write_reg_cache(codec, UDA1380_MIXER, | |
487 | mixer & ~R14_SILENCE); | |
1abd9184 | 488 | schedule_work(&uda1380->work); |
ef9e5e5c PZ |
489 | break; |
490 | case SNDRV_PCM_TRIGGER_STOP: | |
491 | case SNDRV_PCM_TRIGGER_PAUSE_PUSH: | |
492 | uda1380_write_reg_cache(codec, UDA1380_MIXER, | |
493 | mixer | R14_SILENCE); | |
1abd9184 | 494 | schedule_work(&uda1380->work); |
ef9e5e5c | 495 | break; |
b7482f52 | 496 | } |
b7482f52 PZ |
497 | return 0; |
498 | } | |
499 | ||
500 | static int uda1380_pcm_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
501 | struct snd_pcm_hw_params *params, |
502 | struct snd_soc_dai *dai) | |
b7482f52 PZ |
503 | { |
504 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
505 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 506 | struct snd_soc_codec *codec = socdev->card->codec; |
b7482f52 PZ |
507 | u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK); |
508 | ||
509 | /* set WSPLL power and divider if running from this clock */ | |
510 | if (clk & R00_DAC_CLK) { | |
511 | int rate = params_rate(params); | |
512 | u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM); | |
513 | clk &= ~0x3; /* clear SEL_LOOP_DIV */ | |
514 | switch (rate) { | |
515 | case 6250 ... 12500: | |
516 | clk |= 0x0; | |
517 | break; | |
518 | case 12501 ... 25000: | |
519 | clk |= 0x1; | |
520 | break; | |
521 | case 25001 ... 50000: | |
522 | clk |= 0x2; | |
523 | break; | |
524 | case 50001 ... 100000: | |
525 | clk |= 0x3; | |
526 | break; | |
527 | } | |
528 | uda1380_write(codec, UDA1380_PM, R02_PON_PLL | pm); | |
529 | } | |
530 | ||
531 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
532 | clk |= R00_EN_DAC | R00_EN_INT; | |
533 | else | |
534 | clk |= R00_EN_ADC | R00_EN_DEC; | |
535 | ||
536 | uda1380_write(codec, UDA1380_CLK, clk); | |
537 | return 0; | |
538 | } | |
539 | ||
dee89c4d MB |
540 | static void uda1380_pcm_shutdown(struct snd_pcm_substream *substream, |
541 | struct snd_soc_dai *dai) | |
b7482f52 PZ |
542 | { |
543 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
544 | struct snd_soc_device *socdev = rtd->socdev; | |
6627a653 | 545 | struct snd_soc_codec *codec = socdev->card->codec; |
b7482f52 PZ |
546 | u16 clk = uda1380_read_reg_cache(codec, UDA1380_CLK); |
547 | ||
548 | /* shut down WSPLL power if running from this clock */ | |
549 | if (clk & R00_DAC_CLK) { | |
550 | u16 pm = uda1380_read_reg_cache(codec, UDA1380_PM); | |
551 | uda1380_write(codec, UDA1380_PM, ~R02_PON_PLL & pm); | |
552 | } | |
553 | ||
554 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) | |
555 | clk &= ~(R00_EN_DAC | R00_EN_INT); | |
556 | else | |
557 | clk &= ~(R00_EN_ADC | R00_EN_DEC); | |
558 | ||
559 | uda1380_write(codec, UDA1380_CLK, clk); | |
560 | } | |
561 | ||
b7482f52 PZ |
562 | static int uda1380_set_bias_level(struct snd_soc_codec *codec, |
563 | enum snd_soc_bias_level level) | |
564 | { | |
565 | int pm = uda1380_read_reg_cache(codec, UDA1380_PM); | |
566 | ||
567 | switch (level) { | |
568 | case SND_SOC_BIAS_ON: | |
569 | case SND_SOC_BIAS_PREPARE: | |
570 | uda1380_write(codec, UDA1380_PM, R02_PON_BIAS | pm); | |
571 | break; | |
572 | case SND_SOC_BIAS_STANDBY: | |
573 | uda1380_write(codec, UDA1380_PM, R02_PON_BIAS); | |
574 | break; | |
575 | case SND_SOC_BIAS_OFF: | |
576 | uda1380_write(codec, UDA1380_PM, 0x0); | |
577 | break; | |
578 | } | |
579 | codec->bias_level = level; | |
580 | return 0; | |
581 | } | |
582 | ||
583 | #define UDA1380_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ | |
584 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\ | |
585 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000) | |
586 | ||
6335d055 EM |
587 | static struct snd_soc_dai_ops uda1380_dai_ops = { |
588 | .hw_params = uda1380_pcm_hw_params, | |
589 | .shutdown = uda1380_pcm_shutdown, | |
65ec1cd1 | 590 | .trigger = uda1380_trigger, |
6335d055 EM |
591 | .set_fmt = uda1380_set_dai_fmt_both, |
592 | }; | |
593 | ||
594 | static struct snd_soc_dai_ops uda1380_dai_ops_playback = { | |
595 | .hw_params = uda1380_pcm_hw_params, | |
596 | .shutdown = uda1380_pcm_shutdown, | |
65ec1cd1 | 597 | .trigger = uda1380_trigger, |
6335d055 EM |
598 | .set_fmt = uda1380_set_dai_fmt_playback, |
599 | }; | |
600 | ||
601 | static struct snd_soc_dai_ops uda1380_dai_ops_capture = { | |
602 | .hw_params = uda1380_pcm_hw_params, | |
603 | .shutdown = uda1380_pcm_shutdown, | |
65ec1cd1 | 604 | .trigger = uda1380_trigger, |
6335d055 EM |
605 | .set_fmt = uda1380_set_dai_fmt_capture, |
606 | }; | |
607 | ||
e550e17f | 608 | struct snd_soc_dai uda1380_dai[] = { |
b7482f52 PZ |
609 | { |
610 | .name = "UDA1380", | |
611 | .playback = { | |
612 | .stream_name = "Playback", | |
613 | .channels_min = 1, | |
614 | .channels_max = 2, | |
615 | .rates = UDA1380_RATES, | |
616 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
617 | .capture = { | |
618 | .stream_name = "Capture", | |
619 | .channels_min = 1, | |
620 | .channels_max = 2, | |
621 | .rates = UDA1380_RATES, | |
622 | .formats = SNDRV_PCM_FMTBIT_S16_LE,}, | |
6335d055 | 623 | .ops = &uda1380_dai_ops, |
b7482f52 PZ |
624 | }, |
625 | { /* playback only - dual interface */ | |
626 | .name = "UDA1380", | |
627 | .playback = { | |
628 | .stream_name = "Playback", | |
629 | .channels_min = 1, | |
630 | .channels_max = 2, | |
631 | .rates = UDA1380_RATES, | |
632 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
633 | }, | |
6335d055 | 634 | .ops = &uda1380_dai_ops_playback, |
b7482f52 PZ |
635 | }, |
636 | { /* capture only - dual interface*/ | |
637 | .name = "UDA1380", | |
638 | .capture = { | |
639 | .stream_name = "Capture", | |
640 | .channels_min = 1, | |
641 | .channels_max = 2, | |
642 | .rates = UDA1380_RATES, | |
643 | .formats = SNDRV_PCM_FMTBIT_S16_LE, | |
644 | }, | |
6335d055 | 645 | .ops = &uda1380_dai_ops_capture, |
b7482f52 PZ |
646 | }, |
647 | }; | |
648 | EXPORT_SYMBOL_GPL(uda1380_dai); | |
649 | ||
650 | static int uda1380_suspend(struct platform_device *pdev, pm_message_t state) | |
651 | { | |
652 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 653 | struct snd_soc_codec *codec = socdev->card->codec; |
b7482f52 PZ |
654 | |
655 | uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
656 | return 0; | |
657 | } | |
658 | ||
659 | static int uda1380_resume(struct platform_device *pdev) | |
660 | { | |
661 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 662 | struct snd_soc_codec *codec = socdev->card->codec; |
b7482f52 PZ |
663 | int i; |
664 | u8 data[2]; | |
665 | u16 *cache = codec->reg_cache; | |
666 | ||
667 | /* Sync reg_cache with the hardware */ | |
668 | for (i = 0; i < ARRAY_SIZE(uda1380_reg); i++) { | |
669 | data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001); | |
670 | data[1] = cache[i] & 0x00ff; | |
671 | codec->hw_write(codec->control_data, data, 2); | |
672 | } | |
673 | uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
674 | uda1380_set_bias_level(codec, codec->suspend_bias_level); | |
675 | return 0; | |
676 | } | |
677 | ||
1abd9184 | 678 | static int uda1380_probe(struct platform_device *pdev) |
b7482f52 | 679 | { |
1abd9184 PZ |
680 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
681 | struct snd_soc_codec *codec; | |
682 | struct uda1380_platform_data *pdata; | |
b7482f52 PZ |
683 | int ret = 0; |
684 | ||
1abd9184 PZ |
685 | if (uda1380_codec == NULL) { |
686 | dev_err(&pdev->dev, "Codec device not registered\n"); | |
687 | return -ENODEV; | |
688 | } | |
b7482f52 | 689 | |
1abd9184 PZ |
690 | socdev->card->codec = uda1380_codec; |
691 | codec = uda1380_codec; | |
692 | pdata = codec->dev->platform_data; | |
ef9e5e5c | 693 | |
b7482f52 PZ |
694 | /* register pcms */ |
695 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); | |
696 | if (ret < 0) { | |
1abd9184 | 697 | dev_err(codec->dev, "failed to create pcms: %d\n", ret); |
b7482f52 PZ |
698 | goto pcm_err; |
699 | } | |
700 | ||
701 | /* power on device */ | |
702 | uda1380_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
703 | /* set clock input */ | |
1abd9184 | 704 | switch (pdata->dac_clk) { |
b7482f52 PZ |
705 | case UDA1380_DAC_CLK_SYSCLK: |
706 | uda1380_write(codec, UDA1380_CLK, 0); | |
707 | break; | |
708 | case UDA1380_DAC_CLK_WSPLL: | |
709 | uda1380_write(codec, UDA1380_CLK, R00_DAC_CLK); | |
710 | break; | |
711 | } | |
712 | ||
3e8e1952 IM |
713 | snd_soc_add_controls(codec, uda1380_snd_controls, |
714 | ARRAY_SIZE(uda1380_snd_controls)); | |
b7482f52 | 715 | uda1380_add_widgets(codec); |
968a6025 | 716 | ret = snd_soc_init_card(socdev); |
b7482f52 | 717 | if (ret < 0) { |
1abd9184 | 718 | dev_err(codec->dev, "failed to register card: %d\n", ret); |
b7482f52 PZ |
719 | goto card_err; |
720 | } | |
721 | ||
722 | return ret; | |
723 | ||
724 | card_err: | |
725 | snd_soc_free_pcms(socdev); | |
726 | snd_soc_dapm_free(socdev); | |
727 | pcm_err: | |
b7482f52 PZ |
728 | return ret; |
729 | } | |
730 | ||
1abd9184 PZ |
731 | /* power down chip */ |
732 | static int uda1380_remove(struct platform_device *pdev) | |
b7482f52 | 733 | { |
1abd9184 | 734 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); |
6627a653 | 735 | struct snd_soc_codec *codec = socdev->card->codec; |
b7482f52 | 736 | |
1abd9184 PZ |
737 | if (codec->control_data) |
738 | uda1380_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
b7482f52 | 739 | |
1abd9184 PZ |
740 | snd_soc_free_pcms(socdev); |
741 | snd_soc_dapm_free(socdev); | |
b7482f52 | 742 | |
b7482f52 PZ |
743 | return 0; |
744 | } | |
745 | ||
1abd9184 PZ |
746 | struct snd_soc_codec_device soc_codec_dev_uda1380 = { |
747 | .probe = uda1380_probe, | |
748 | .remove = uda1380_remove, | |
749 | .suspend = uda1380_suspend, | |
750 | .resume = uda1380_resume, | |
b7482f52 | 751 | }; |
1abd9184 | 752 | EXPORT_SYMBOL_GPL(soc_codec_dev_uda1380); |
b7482f52 | 753 | |
1abd9184 | 754 | static int uda1380_register(struct uda1380_priv *uda1380) |
88fc39d7 | 755 | { |
1abd9184 PZ |
756 | int ret, i; |
757 | struct snd_soc_codec *codec = &uda1380->codec; | |
758 | struct uda1380_platform_data *pdata = codec->dev->platform_data; | |
88fc39d7 | 759 | |
1abd9184 PZ |
760 | if (uda1380_codec) { |
761 | dev_err(codec->dev, "Another UDA1380 is registered\n"); | |
762 | return -EINVAL; | |
763 | } | |
764 | ||
765 | if (!pdata || !pdata->gpio_power || !pdata->gpio_reset) | |
766 | return -EINVAL; | |
767 | ||
768 | ret = gpio_request(pdata->gpio_power, "uda1380 power"); | |
769 | if (ret) | |
770 | goto err_out; | |
771 | ret = gpio_request(pdata->gpio_reset, "uda1380 reset"); | |
772 | if (ret) | |
773 | goto err_gpio; | |
774 | ||
775 | gpio_direction_output(pdata->gpio_power, 1); | |
776 | ||
777 | /* we may need to have the clock running here - pH5 */ | |
778 | gpio_direction_output(pdata->gpio_reset, 1); | |
779 | udelay(5); | |
780 | gpio_set_value(pdata->gpio_reset, 0); | |
781 | ||
782 | mutex_init(&codec->mutex); | |
783 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
784 | INIT_LIST_HEAD(&codec->dapm_paths); | |
785 | ||
786 | codec->private_data = uda1380; | |
787 | codec->name = "UDA1380"; | |
788 | codec->owner = THIS_MODULE; | |
789 | codec->read = uda1380_read_reg_cache; | |
790 | codec->write = uda1380_write; | |
791 | codec->bias_level = SND_SOC_BIAS_OFF; | |
792 | codec->set_bias_level = uda1380_set_bias_level; | |
793 | codec->dai = uda1380_dai; | |
794 | codec->num_dai = ARRAY_SIZE(uda1380_dai); | |
795 | codec->reg_cache_size = ARRAY_SIZE(uda1380_reg); | |
796 | codec->reg_cache = &uda1380->reg_cache; | |
797 | codec->reg_cache_step = 1; | |
798 | ||
799 | memcpy(codec->reg_cache, uda1380_reg, sizeof(uda1380_reg)); | |
800 | ||
801 | ret = uda1380_reset(codec); | |
802 | if (ret < 0) { | |
803 | dev_err(codec->dev, "Failed to issue reset\n"); | |
804 | goto err_reset; | |
88fc39d7 JD |
805 | } |
806 | ||
1abd9184 PZ |
807 | INIT_WORK(&uda1380->work, uda1380_flush_work); |
808 | ||
809 | for (i = 0; i < ARRAY_SIZE(uda1380_dai); i++) | |
810 | uda1380_dai[i].dev = codec->dev; | |
88fc39d7 | 811 | |
1abd9184 PZ |
812 | uda1380_codec = codec; |
813 | ||
814 | ret = snd_soc_register_codec(codec); | |
815 | if (ret != 0) { | |
816 | dev_err(codec->dev, "Failed to register codec: %d\n", ret); | |
817 | goto err_reset; | |
88fc39d7 JD |
818 | } |
819 | ||
1abd9184 PZ |
820 | ret = snd_soc_register_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai)); |
821 | if (ret != 0) { | |
822 | dev_err(codec->dev, "Failed to register DAIs: %d\n", ret); | |
823 | goto err_dai; | |
88fc39d7 JD |
824 | } |
825 | ||
826 | return 0; | |
827 | ||
1abd9184 PZ |
828 | err_dai: |
829 | snd_soc_unregister_codec(codec); | |
830 | err_reset: | |
831 | gpio_set_value(pdata->gpio_power, 0); | |
832 | gpio_free(pdata->gpio_reset); | |
833 | err_gpio: | |
834 | gpio_free(pdata->gpio_power); | |
835 | err_out: | |
836 | return ret; | |
88fc39d7 | 837 | } |
b7482f52 | 838 | |
1abd9184 | 839 | static void uda1380_unregister(struct uda1380_priv *uda1380) |
b7482f52 | 840 | { |
1abd9184 PZ |
841 | struct snd_soc_codec *codec = &uda1380->codec; |
842 | struct uda1380_platform_data *pdata = codec->dev->platform_data; | |
843 | ||
844 | snd_soc_unregister_dais(uda1380_dai, ARRAY_SIZE(uda1380_dai)); | |
845 | snd_soc_unregister_codec(&uda1380->codec); | |
846 | ||
847 | gpio_set_value(pdata->gpio_power, 0); | |
848 | gpio_free(pdata->gpio_reset); | |
849 | gpio_free(pdata->gpio_power); | |
850 | ||
851 | kfree(uda1380); | |
852 | uda1380_codec = NULL; | |
853 | } | |
854 | ||
855 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
856 | static __devinit int uda1380_i2c_probe(struct i2c_client *i2c, | |
857 | const struct i2c_device_id *id) | |
858 | { | |
859 | struct uda1380_priv *uda1380; | |
b7482f52 | 860 | struct snd_soc_codec *codec; |
b7c9d852 | 861 | int ret; |
b7482f52 | 862 | |
1abd9184 PZ |
863 | uda1380 = kzalloc(sizeof(struct uda1380_priv), GFP_KERNEL); |
864 | if (uda1380 == NULL) | |
b7482f52 PZ |
865 | return -ENOMEM; |
866 | ||
1abd9184 PZ |
867 | codec = &uda1380->codec; |
868 | codec->hw_write = (hw_write_t)i2c_master_send; | |
b7482f52 | 869 | |
1abd9184 PZ |
870 | i2c_set_clientdata(i2c, uda1380); |
871 | codec->control_data = i2c; | |
b7c9d852 | 872 | |
1abd9184 | 873 | codec->dev = &i2c->dev; |
3051e41a | 874 | |
1abd9184 | 875 | ret = uda1380_register(uda1380); |
3051e41a | 876 | if (ret != 0) |
1abd9184 PZ |
877 | kfree(uda1380); |
878 | ||
b7482f52 PZ |
879 | return ret; |
880 | } | |
881 | ||
1abd9184 | 882 | static int __devexit uda1380_i2c_remove(struct i2c_client *i2c) |
b7482f52 | 883 | { |
1abd9184 PZ |
884 | struct uda1380_priv *uda1380 = i2c_get_clientdata(i2c); |
885 | uda1380_unregister(uda1380); | |
b7482f52 PZ |
886 | return 0; |
887 | } | |
888 | ||
1abd9184 PZ |
889 | static const struct i2c_device_id uda1380_i2c_id[] = { |
890 | { "uda1380", 0 }, | |
891 | { } | |
b7482f52 | 892 | }; |
1abd9184 PZ |
893 | MODULE_DEVICE_TABLE(i2c, uda1380_i2c_id); |
894 | ||
895 | static struct i2c_driver uda1380_i2c_driver = { | |
896 | .driver = { | |
897 | .name = "UDA1380 I2C Codec", | |
898 | .owner = THIS_MODULE, | |
899 | }, | |
900 | .probe = uda1380_i2c_probe, | |
901 | .remove = __devexit_p(uda1380_i2c_remove), | |
902 | .id_table = uda1380_i2c_id, | |
903 | }; | |
904 | #endif | |
b7482f52 | 905 | |
c9b3a40f | 906 | static int __init uda1380_modinit(void) |
64089b84 | 907 | { |
1abd9184 PZ |
908 | int ret; |
909 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) | |
910 | ret = i2c_add_driver(&uda1380_i2c_driver); | |
911 | if (ret != 0) | |
912 | pr_err("Failed to register UDA1380 I2C driver: %d\n", ret); | |
913 | #endif | |
914 | return 0; | |
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915 | } |
916 | module_init(uda1380_modinit); | |
917 | ||
918 | static void __exit uda1380_exit(void) | |
919 | { | |
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920 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
921 | i2c_del_driver(&uda1380_i2c_driver); | |
922 | #endif | |
64089b84 MB |
923 | } |
924 | module_exit(uda1380_exit); | |
925 | ||
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926 | MODULE_AUTHOR("Giorgio Padrin"); |
927 | MODULE_DESCRIPTION("Audio support for codec Philips UDA1380"); | |
928 | MODULE_LICENSE("GPL"); |