Commit | Line | Data |
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b7482f52 PZ |
1 | /* |
2 | * Audio support for Philips UDA1380 | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Copyright (c) 2005 Giorgio Padrin <giorgio@mandarinlogiq.org> | |
9 | */ | |
10 | ||
11 | #ifndef _UDA1380_H | |
12 | #define _UDA1380_H | |
13 | ||
14 | #define UDA1380_CLK 0x00 | |
15 | #define UDA1380_IFACE 0x01 | |
16 | #define UDA1380_PM 0x02 | |
17 | #define UDA1380_AMIX 0x03 | |
18 | #define UDA1380_HP 0x04 | |
19 | #define UDA1380_MVOL 0x10 | |
20 | #define UDA1380_MIXVOL 0x11 | |
21 | #define UDA1380_MODE 0x12 | |
22 | #define UDA1380_DEEMP 0x13 | |
23 | #define UDA1380_MIXER 0x14 | |
24 | #define UDA1380_INTSTAT 0x18 | |
25 | #define UDA1380_DEC 0x20 | |
26 | #define UDA1380_PGA 0x21 | |
27 | #define UDA1380_ADC 0x22 | |
28 | #define UDA1380_AGC 0x23 | |
29 | #define UDA1380_DECSTAT 0x28 | |
30 | #define UDA1380_RESET 0x7f | |
31 | ||
32 | #define UDA1380_CACHEREGNUM 0x24 | |
33 | ||
34 | /* Register flags */ | |
35 | #define R00_EN_ADC 0x0800 | |
36 | #define R00_EN_DEC 0x0400 | |
37 | #define R00_EN_DAC 0x0200 | |
38 | #define R00_EN_INT 0x0100 | |
39 | #define R00_DAC_CLK 0x0010 | |
40 | #define R01_SFORI_I2S 0x0000 | |
41 | #define R01_SFORI_LSB16 0x0100 | |
42 | #define R01_SFORI_LSB18 0x0200 | |
43 | #define R01_SFORI_LSB20 0x0300 | |
44 | #define R01_SFORI_MSB 0x0500 | |
45 | #define R01_SFORI_MASK 0x0700 | |
46 | #define R01_SFORO_I2S 0x0000 | |
47 | #define R01_SFORO_LSB16 0x0001 | |
48 | #define R01_SFORO_LSB18 0x0002 | |
49 | #define R01_SFORO_LSB20 0x0003 | |
50 | #define R01_SFORO_LSB24 0x0004 | |
51 | #define R01_SFORO_MSB 0x0005 | |
52 | #define R01_SFORO_MASK 0x0007 | |
53 | #define R01_SEL_SOURCE 0x0040 | |
54 | #define R01_SIM 0x0010 | |
55 | #define R02_PON_PLL 0x8000 | |
56 | #define R02_PON_HP 0x2000 | |
57 | #define R02_PON_DAC 0x0400 | |
58 | #define R02_PON_BIAS 0x0100 | |
59 | #define R02_EN_AVC 0x0080 | |
60 | #define R02_PON_AVC 0x0040 | |
61 | #define R02_PON_LNA 0x0010 | |
62 | #define R02_PON_PGAL 0x0008 | |
63 | #define R02_PON_ADCL 0x0004 | |
64 | #define R02_PON_PGAR 0x0002 | |
65 | #define R02_PON_ADCR 0x0001 | |
66 | #define R13_MTM 0x4000 | |
67 | #define R14_SILENCE 0x0080 | |
68 | #define R14_SDET_ON 0x0040 | |
69 | #define R21_MT_ADC 0x8000 | |
70 | #define R22_SEL_LNA 0x0008 | |
71 | #define R22_SEL_MIC 0x0004 | |
72 | #define R22_SKIP_DCFIL 0x0002 | |
73 | #define R23_AGC_EN 0x0001 | |
74 | ||
75 | struct uda1380_setup_data { | |
88fc39d7 | 76 | int i2c_bus; |
b7482f52 PZ |
77 | unsigned short i2c_address; |
78 | int dac_clk; | |
79 | #define UDA1380_DAC_CLK_SYSCLK 0 | |
80 | #define UDA1380_DAC_CLK_WSPLL 1 | |
81 | }; | |
82 | ||
83 | #define UDA1380_DAI_DUPLEX 0 /* playback and capture on single DAI */ | |
84 | #define UDA1380_DAI_PLAYBACK 1 /* playback DAI */ | |
85 | #define UDA1380_DAI_CAPTURE 2 /* capture DAI */ | |
86 | ||
e550e17f | 87 | extern struct snd_soc_dai uda1380_dai[3]; |
b7482f52 PZ |
88 | extern struct snd_soc_codec_device soc_codec_dev_uda1380; |
89 | ||
90 | #endif /* _UDA1380_H */ |