projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: wm0010: Up the completion timeout to 20ms instead of 10ms
[deliverable/linux.git] / sound / soc / codecs / wm0010.c
CommitLineData
e3523e01
DP		 1/*
2 * wm0010.c -- WM0010 DSP Driver
3 *
4 * Copyright 2012 Wolfson Microelectronics PLC.
5 *
6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * Scott Ling <sl@opensource.wolfsonmicro.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/irqreturn.h>
18#include <linux/init.h>
19#include <linux/spi/spi.h>
20#include <linux/firmware.h>
21#include <linux/delay.h>
22#include <linux/fs.h>
23#include <linux/miscdevice.h>
24#include <linux/gpio.h>
25#include <linux/regulator/consumer.h>
26#include <linux/mutex.h>
27#include <linux/workqueue.h>
28
29#include <sound/soc.h>
30#include <sound/wm0010.h>
31
32#define DEVICE_ID_WM0010 10
33
34enum dfw_cmd {
35 DFW_CMD_FUSE = 0x01,
36 DFW_CMD_CODE_HDR,
37 DFW_CMD_CODE_DATA,
38 DFW_CMD_PLL,
39 DFW_CMD_INFO = 0xff
40};
41
42struct dfw_binrec {
43 u8 command;
44 u32 length:24;
45 u32 address;
46 uint8_t data[0];
47} __packed;
48
49struct dfw_pllrec {
50 u8 command;
51 u32 length:24;
52 u32 address;
53 u32 clkctrl1;
54 u32 clkctrl2;
55 u32 clkctrl3;
56 u32 ldetctrl;
57 u32 uart_div;
58 u32 spi_div;
59} __packed;
60
61static struct pll_clock_map {
62 int max_sysclk;
63 int max_pll_spi_speed;
64 u32 pll_clkctrl1;
65} pll_clock_map[] = { /* Dividers */
66 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
67 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
68 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
69 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
70 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
71 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
72};
73
74enum wm0010_state {
75 WM0010_POWER_OFF,
76 WM0010_OUT_OF_RESET,
77 WM0010_BOOTROM,
78 WM0010_STAGE2,
79 WM0010_FIRMWARE,
80};
81
82struct wm0010_priv {
83 struct snd_soc_codec *codec;
84
85 struct mutex lock;
86 struct device *dev;
87
88 struct wm0010_pdata pdata;
89
90 int gpio_reset;
91 int gpio_reset_value;
92
93 struct regulator_bulk_data core_supplies[2];
94 struct regulator *dbvdd;
95
96 int sysclk;
97
98 enum wm0010_state state;
99 bool boot_failed;
e3523e01
DP		 100 bool ready;
101 bool pll_running;
102 int max_spi_freq;
103 int board_max_spi_speed;
104 u32 pll_clkctrl1;
105
106 spinlock_t irq_lock;
107 int irq;
108
109 struct completion boot_completion;
110};
111
112struct wm0010_spi_msg {
113 struct spi_message m;
114 struct spi_transfer t;
115 u8 *tx_buf;
116 u8 *rx_buf;
117 size_t len;
118};
119
1470bfac
MB		 120static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
121SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
122};
123
e3523e01 124static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
1549c34b
MB		 125 { "SDI2 Capture", NULL, "SDI1 Playback" },
126 { "SDI1 Capture", NULL, "SDI2 Playback" },
1470bfac
MB		 127
128 { "SDI1 Capture", NULL, "CLKIN" },
129 { "SDI2 Capture", NULL, "CLKIN" },
130 { "SDI1 Playback", NULL, "CLKIN" },
131 { "SDI2 Playback", NULL, "CLKIN" },
e3523e01
DP		 132};
133
134static const char *wm0010_state_to_str(enum wm0010_state state)
135{
136 const char *state_to_str[] = {
137 "Power off",
138 "Out of reset",
bf9d3237 139 "Boot ROM",
e3523e01
DP		 140 "Stage2",
141 "Firmware"
142 };
143
144 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
145 return "null";
146 return state_to_str[state];
147}
148
149/* Called with wm0010->lock held */
150static void wm0010_halt(struct snd_soc_codec *codec)
151{
152 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
153 unsigned long flags;
154 enum wm0010_state state;
155
156 /* Fetch the wm0010 state */
157 spin_lock_irqsave(&wm0010->irq_lock, flags);
158 state = wm0010->state;
159 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
160
161 switch (state) {
162 case WM0010_POWER_OFF:
163 /* If there's nothing to do, bail out */
164 return;
165 case WM0010_OUT_OF_RESET:
166 case WM0010_BOOTROM:
167 case WM0010_STAGE2:
168 case WM0010_FIRMWARE:
169 /* Remember to put chip back into reset */
fff00cbc
MB		 170 gpio_set_value_cansleep(wm0010->gpio_reset,
171 wm0010->gpio_reset_value);
e3523e01
DP		 172 /* Disable the regulators */
173 regulator_disable(wm0010->dbvdd);
174 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
175 wm0010->core_supplies);
176 break;
177 }
178
179 spin_lock_irqsave(&wm0010->irq_lock, flags);
180 wm0010->state = WM0010_POWER_OFF;
181 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
182}
183
184struct wm0010_boot_xfer {
185 struct list_head list;
186 struct snd_soc_codec *codec;
187 struct completion *done;
188 struct spi_message m;
189 struct spi_transfer t;
190};
191
192/* Called with wm0010->lock held */
193static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
194{
195 enum wm0010_state state;
196 unsigned long flags;
197
198 spin_lock_irqsave(&wm0010->irq_lock, flags);
199 state = wm0010->state;
200 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
201
202 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
203 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
204
205 wm0010->boot_failed = true;
206}
207
208static void wm0010_boot_xfer_complete(void *data)
209{
210 struct wm0010_boot_xfer *xfer = data;
211 struct snd_soc_codec *codec = xfer->codec;
212 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
213 u32 *out32 = xfer->t.rx_buf;
214 int i;
215
216 if (xfer->m.status != 0) {
217 dev_err(codec->dev, "SPI transfer failed: %d\n",
218 xfer->m.status);
219 wm0010_mark_boot_failure(wm0010);
220 if (xfer->done)
221 complete(xfer->done);
222 return;
223 }
224
225 for (i = 0; i < xfer->t.len / 4; i++) {
226 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]);
227
228 switch (be32_to_cpu(out32[i])) {
229 case 0xe0e0e0e0:
230 dev_err(codec->dev,
231 "%d: ROM error reported in stage 2\n", i);
232 wm0010_mark_boot_failure(wm0010);
233 break;
234
235 case 0x55555555:
f9baa0cc 236 if (wm0010->state < WM0010_STAGE2)
e3523e01
DP		 237 break;
238 dev_err(codec->dev,
239 "%d: ROM bootloader running in stage 2\n", i);
240 wm0010_mark_boot_failure(wm0010);
241 break;
242
243 case 0x0fed0000:
244 dev_dbg(codec->dev, "Stage2 loader running\n");
245 break;
246
247 case 0x0fed0007:
248 dev_dbg(codec->dev, "CODE_HDR packet received\n");
249 break;
250
251 case 0x0fed0008:
252 dev_dbg(codec->dev, "CODE_DATA packet received\n");
253 break;
254
255 case 0x0fed0009:
256 dev_dbg(codec->dev, "Download complete\n");
257 break;
258
259 case 0x0fed000c:
260 dev_dbg(codec->dev, "Application start\n");
261 break;
262
263 case 0x0fed000e:
264 dev_dbg(codec->dev, "PLL packet received\n");
265 wm0010->pll_running = true;
266 break;
267
268 case 0x0fed0025:
269 dev_err(codec->dev, "Device reports image too long\n");
270 wm0010_mark_boot_failure(wm0010);
271 break;
272
273 case 0x0fed002c:
274 dev_err(codec->dev, "Device reports bad SPI packet\n");
275 wm0010_mark_boot_failure(wm0010);
276 break;
277
278 case 0x0fed0031:
279 dev_err(codec->dev, "Device reports SPI read overflow\n");
280 wm0010_mark_boot_failure(wm0010);
281 break;
282
283 case 0x0fed0032:
284 dev_err(codec->dev, "Device reports SPI underclock\n");
285 wm0010_mark_boot_failure(wm0010);
286 break;
287
288 case 0x0fed0033:
289 dev_err(codec->dev, "Device reports bad header packet\n");
290 wm0010_mark_boot_failure(wm0010);
291 break;
292
293 case 0x0fed0034:
294 dev_err(codec->dev, "Device reports invalid packet type\n");
295 wm0010_mark_boot_failure(wm0010);
296 break;
297
298 case 0x0fed0035:
299 dev_err(codec->dev, "Device reports data before header error\n");
300 wm0010_mark_boot_failure(wm0010);
301 break;
302
303 case 0x0fed0038:
304 dev_err(codec->dev, "Device reports invalid PLL packet\n");
305 break;
306
307 case 0x0fed003a:
308 dev_err(codec->dev, "Device reports packet alignment error\n");
309 wm0010_mark_boot_failure(wm0010);
310 break;
311
312 default:
313 dev_err(codec->dev, "Unrecognised return 0x%x\n",
314 be32_to_cpu(out32[i]));
315 wm0010_mark_boot_failure(wm0010);
316 break;
317 }
318
319 if (wm0010->boot_failed)
320 break;
321 }
322
e3523e01
DP		 323 if (xfer->done)
324 complete(xfer->done);
325}
326
327static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
328{
329 int i;
330
331 for (i = 0; i < len / 8; i++)
332 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
333}
334
8f7d52af 335static int wm0010_firmware_load(char *name, struct snd_soc_codec *codec)
e3523e01
DP		 336{
337 struct spi_device *spi = to_spi_device(codec->dev);
338 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
e3523e01
DP		 339 struct list_head xfer_list;
340 struct wm0010_boot_xfer *xfer;
341 int ret;
342 struct completion done;
343 const struct firmware *fw;
344 const struct dfw_binrec *rec;
8f7d52af
SL		 345 u64 *img;
346 u8 *out, dsp;
347 u32 len, offset;
348
349 INIT_LIST_HEAD(&xfer_list);
350
351 ret = request_firmware(&fw, name, codec->dev);
352 if (ret != 0) {
353 dev_err(codec->dev, "Failed to request application: %d\n",
354 ret);
355 return ret;
356 }
357
358 rec = (const struct dfw_binrec *)fw->data;
359 offset = 0;
360 dsp = rec->data[0];
361 wm0010->boot_failed = false;
362 BUG_ON(!list_empty(&xfer_list));
363 init_completion(&done);
364
365 /* First record should be INFO */
366 if (rec->command != DFW_CMD_INFO) {
367 dev_err(codec->dev, "First record not INFO\r\n");
368 ret = -EINVAL;
369 goto abort;
370 }
371
372 /* Check it's a DSP file */
373 if (dsp != DEVICE_ID_WM0010) {
374 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n");
375 ret = -EINVAL;
376 goto abort;
377 }
378
379 /* Skip the info record as we don't need to send it */
380 offset += ((rec->length) + 8);
381 rec = (void *)&rec->data[rec->length];
382
383 while (offset < fw->size) {
384 dev_dbg(codec->dev,
385 "Packet: command %d, data length = 0x%x\r\n",
386 rec->command, rec->length);
387 len = rec->length + 8;
388
389 out = kzalloc(len, GFP_KERNEL);
390 if (!out) {
391 dev_err(codec->dev,
392 "Failed to allocate RX buffer\n");
393 ret = -ENOMEM;
394 goto abort1;
395 }
396
397 img = kzalloc(len, GFP_KERNEL);
398 if (!img) {
399 dev_err(codec->dev,
400 "Failed to allocate image buffer\n");
401 ret = -ENOMEM;
402 goto abort1;
403 }
404
405 byte_swap_64((u64 *)&rec->command, img, len);
406
407 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
408 if (!xfer) {
409 dev_err(codec->dev, "Failed to allocate xfer\n");
410 ret = -ENOMEM;
411 goto abort1;
412 }
413
414 xfer->codec = codec;
415 list_add_tail(&xfer->list, &xfer_list);
416
417 spi_message_init(&xfer->m);
418 xfer->m.complete = wm0010_boot_xfer_complete;
419 xfer->m.context = xfer;
420 xfer->t.tx_buf = img;
421 xfer->t.rx_buf = out;
422 xfer->t.len = len;
423 xfer->t.bits_per_word = 8;
424
425 if (!wm0010->pll_running) {
426 xfer->t.speed_hz = wm0010->sysclk / 6;
427 } else {
428 xfer->t.speed_hz = wm0010->max_spi_freq;
429
430 if (wm0010->board_max_spi_speed &&
431 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
432 xfer->t.speed_hz = wm0010->board_max_spi_speed;
433 }
434
435 /* Store max usable spi frequency for later use */
436 wm0010->max_spi_freq = xfer->t.speed_hz;
437
438 spi_message_add_tail(&xfer->t, &xfer->m);
439
440 offset += ((rec->length) + 8);
441 rec = (void *)&rec->data[rec->length];
442
443 if (offset >= fw->size) {
444 dev_dbg(codec->dev, "All transfers scheduled\n");
445 xfer->done = &done;
446 }
447
448 ret = spi_async(spi, &xfer->m);
449 if (ret != 0) {
450 dev_err(codec->dev, "Write failed: %d\n", ret);
451 goto abort1;
452 }
453
454 if (wm0010->boot_failed) {
455 dev_dbg(codec->dev, "Boot fail!\n");
456 ret = -EINVAL;
457 goto abort1;
458 }
459 }
460
461 wait_for_completion(&done);
462
463 ret = 0;
464
465abort1:
466 while (!list_empty(&xfer_list)) {
467 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
468 list);
469 kfree(xfer->t.rx_buf);
470 kfree(xfer->t.tx_buf);
471 list_del(&xfer->list);
472 kfree(xfer);
473 }
474
475abort:
476 release_firmware(fw);
477 return ret;
478}
479
3f5475df
SL		 480static int wm0010_stage2_load(struct snd_soc_codec *codec)
481{
482 struct spi_device *spi = to_spi_device(codec->dev);
483 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
484 const struct firmware *fw;
485 struct spi_message m;
486 struct spi_transfer t;
487 u32 *img;
488 u8 *out;
489 int i;
490 int ret = 0;
491
492 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
493 if (ret != 0) {
494 dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
495 ret);
496 return ret;
497 }
498
499 dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
500
501 /* Copy to local buffer first as vmalloc causes problems for dma */
502 img = kzalloc(fw->size, GFP_KERNEL);
503 if (!img) {
504 dev_err(codec->dev, "Failed to allocate image buffer\n");
505 ret = -ENOMEM;
506 goto abort2;
507 }
508
509 out = kzalloc(fw->size, GFP_KERNEL);
510 if (!out) {
511 dev_err(codec->dev, "Failed to allocate output buffer\n");
512 ret = -ENOMEM;
513 goto abort1;
514 }
515
516 memcpy(img, &fw->data[0], fw->size);
517
518 spi_message_init(&m);
519 memset(&t, 0, sizeof(t));
520 t.rx_buf = out;
521 t.tx_buf = img;
522 t.len = fw->size;
523 t.bits_per_word = 8;
524 t.speed_hz = wm0010->sysclk / 10;
525 spi_message_add_tail(&t, &m);
526
527 dev_dbg(codec->dev, "Starting initial download at %dHz\n",
528 t.speed_hz);
529
530 ret = spi_sync(spi, &m);
531 if (ret != 0) {
532 dev_err(codec->dev, "Initial download failed: %d\n", ret);
533 goto abort;
534 }
535
536 /* Look for errors from the boot ROM */
537 for (i = 0; i < fw->size; i++) {
538 if (out[i] != 0x55) {
539 dev_err(codec->dev, "Boot ROM error: %x in %d\n",
540 out[i], i);
541 wm0010_mark_boot_failure(wm0010);
542 ret = -EBUSY;
543 goto abort;
544 }
545 }
546abort:
547 kfree(out);
548abort1:
549 kfree(img);
550abort2:
551 release_firmware(fw);
552
553 return ret;
554}
555
8f7d52af
SL		 556static int wm0010_boot(struct snd_soc_codec *codec)
557{
558 struct spi_device *spi = to_spi_device(codec->dev);
559 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
560 unsigned long flags;
561 int ret;
562 const struct firmware *fw;
e3523e01
DP		 563 struct spi_message m;
564 struct spi_transfer t;
565 struct dfw_pllrec pll_rec;
3f5475df 566 u32 *p, len;
e3523e01
DP		 567 u64 *img_swap;
568 u8 *out;
e3523e01
DP		 569 int i;
570
571 spin_lock_irqsave(&wm0010->irq_lock, flags);
572 if (wm0010->state != WM0010_POWER_OFF)
573 dev_warn(wm0010->dev, "DSP already powered up!\n");
574 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
575
576 if (wm0010->sysclk > 26000000) {
577 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n");
578 ret = -ECANCELED;
579 goto err;
580 }
581
e3523e01
DP		 582 mutex_lock(&wm0010->lock);
583 wm0010->pll_running = false;
584
585 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
586
587 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
588 wm0010->core_supplies);
589 if (ret != 0) {
590 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
591 ret);
592 mutex_unlock(&wm0010->lock);
593 goto err;
594 }
595
596 ret = regulator_enable(wm0010->dbvdd);
597 if (ret != 0) {
598 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
599 goto err_core;
600 }
601
602 /* Release reset */
fff00cbc 603 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
e3523e01
DP		 604 spin_lock_irqsave(&wm0010->irq_lock, flags);
605 wm0010->state = WM0010_OUT_OF_RESET;
606 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
607
608 /* First the bootloader */
609 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
610 if (ret != 0) {
611 dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
612 ret);
613 goto abort;
614 }
615
616 if (!wait_for_completion_timeout(&wm0010->boot_completion,
631fcab2 617 msecs_to_jiffies(20)))
e3523e01
DP		 618 dev_err(codec->dev, "Failed to get interrupt from DSP\n");
619
620 spin_lock_irqsave(&wm0010->irq_lock, flags);
621 wm0010->state = WM0010_BOOTROM;
622 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
623
3f5475df
SL		 624 ret = wm0010_stage2_load(codec);
625 if (ret)
e3523e01 626 goto abort;
e3523e01
DP		 627
628 if (!wait_for_completion_timeout(&wm0010->boot_completion,
631fcab2 629 msecs_to_jiffies(20)))
e3523e01
DP		 630 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n");
631
632 spin_lock_irqsave(&wm0010->irq_lock, flags);
633 wm0010->state = WM0010_STAGE2;
634 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
635
636 /* Only initialise PLL if max_spi_freq initialised */
637 if (wm0010->max_spi_freq) {
638
639 /* Initialise a PLL record */
640 memset(&pll_rec, 0, sizeof(pll_rec));
641 pll_rec.command = DFW_CMD_PLL;
642 pll_rec.length = (sizeof(pll_rec) - 8);
643
644 /* On wm0010 only the CLKCTRL1 value is used */
645 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
646
647 len = pll_rec.length + 8;
648 out = kzalloc(len, GFP_KERNEL);
649 if (!out) {
650 dev_err(codec->dev,
651 "Failed to allocate RX buffer\n");
652 goto abort;
653 }
654
655 img_swap = kzalloc(len, GFP_KERNEL);
656 if (!img_swap) {
657 dev_err(codec->dev,
658 "Failed to allocate image buffer\n");
659 goto abort;
660 }
661
662 /* We need to re-order for 0010 */
663 byte_swap_64((u64 *)&pll_rec, img_swap, len);
664
665 spi_message_init(&m);
666 memset(&t, 0, sizeof(t));
667 t.rx_buf = out;
668 t.tx_buf = img_swap;
669 t.len = len;
670 t.bits_per_word = 8;
671 t.speed_hz = wm0010->sysclk / 6;
672 spi_message_add_tail(&t, &m);
673
674 ret = spi_sync(spi, &m);
675 if (ret != 0) {
676 dev_err(codec->dev, "First PLL write failed: %d\n", ret);
677 goto abort;
678 }
679
680 /* Use a second send of the message to get the return status */
681 ret = spi_sync(spi, &m);
682 if (ret != 0) {
683 dev_err(codec->dev, "Second PLL write failed: %d\n", ret);
684 goto abort;
685 }
686
687 p = (u32 *)out;
688
689 /* Look for PLL active code from the DSP */
690 for (i = 0; i < len / 4; i++) {
691 if (*p == 0x0e00ed0f) {
692 dev_dbg(codec->dev, "PLL packet received\n");
693 wm0010->pll_running = true;
694 break;
695 }
696 p++;
697 }
698
699 kfree(img_swap);
700 kfree(out);
701 } else
702 dev_dbg(codec->dev, "Not enabling DSP PLL.");
703
8f7d52af 704 ret = wm0010_firmware_load("wm0010.dfw", codec);
e3523e01 705
8f7d52af 706 if (ret != 0)
e3523e01 707 goto abort;
e3523e01
DP		 708
709 spin_lock_irqsave(&wm0010->irq_lock, flags);
710 wm0010->state = WM0010_FIRMWARE;
711 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
712
713 mutex_unlock(&wm0010->lock);
714
e3523e01
DP		 715 return 0;
716
717abort:
718 /* Put the chip back into reset */
719 wm0010_halt(codec);
720 mutex_unlock(&wm0010->lock);
721 return ret;
4f3ad795 722
e3523e01 723err_core:
4f3ad795 724 mutex_unlock(&wm0010->lock);
e3523e01
DP		 725 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
726 wm0010->core_supplies);
727err:
728 return ret;
729}
730
731static int wm0010_set_bias_level(struct snd_soc_codec *codec,
732 enum snd_soc_bias_level level)
733{
734 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
735
736 switch (level) {
737 case SND_SOC_BIAS_ON:
738 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
739 wm0010_boot(codec);
740 break;
741 case SND_SOC_BIAS_PREPARE:
742 break;
743 case SND_SOC_BIAS_STANDBY:
744 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
745 mutex_lock(&wm0010->lock);
746 wm0010_halt(codec);
747 mutex_unlock(&wm0010->lock);
748 }
749 break;
750 case SND_SOC_BIAS_OFF:
751 break;
752 }
753
754 codec->dapm.bias_level = level;
755
756 return 0;
757}
758
759static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source,
760 int clk_id, unsigned int freq, int dir)
761{
762 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
763 unsigned int i;
764
765 wm0010->sysclk = freq;
766
767 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
768 wm0010->max_spi_freq = 0;
769 } else {
770 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
771 if (freq >= pll_clock_map[i].max_sysclk)
772 break;
773
774 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
775 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
776 }
777
778 return 0;
779}
780
781static int wm0010_probe(struct snd_soc_codec *codec);
782
783static struct snd_soc_codec_driver soc_codec_dev_wm0010 = {
784 .probe = wm0010_probe,
785 .set_bias_level = wm0010_set_bias_level,
786 .set_sysclk = wm0010_set_sysclk,
d3fd716e 787 .idle_bias_off = true,
e3523e01 788
1470bfac
MB		 789 .dapm_widgets = wm0010_dapm_widgets,
790 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
e3523e01
DP		 791 .dapm_routes = wm0010_dapm_routes,
792 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
793};
794
6df31986 795#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
e3523e01
DP		 796#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
797 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
798 SNDRV_PCM_FMTBIT_S32_LE)
799
800static struct snd_soc_dai_driver wm0010_dai[] = {
801 {
802 .name = "wm0010-sdi1",
803 .playback = {
804 .stream_name = "SDI1 Playback",
805 .channels_min = 1,
806 .channels_max = 2,
807 .rates = WM0010_RATES,
808 .formats = WM0010_FORMATS,
809 },
810 .capture = {
811 .stream_name = "SDI1 Capture",
812 .channels_min = 1,
813 .channels_max = 2,
814 .rates = WM0010_RATES,
815 .formats = WM0010_FORMATS,
816 },
817 },
818 {
819 .name = "wm0010-sdi2",
820 .playback = {
821 .stream_name = "SDI2 Playback",
822 .channels_min = 1,
823 .channels_max = 2,
824 .rates = WM0010_RATES,
825 .formats = WM0010_FORMATS,
826 },
827 .capture = {
828 .stream_name = "SDI2 Capture",
829 .channels_min = 1,
830 .channels_max = 2,
831 .rates = WM0010_RATES,
832 .formats = WM0010_FORMATS,
833 },
834 },
835};
836
837static irqreturn_t wm0010_irq(int irq, void *data)
838{
839 struct wm0010_priv *wm0010 = data;
840
841 switch (wm0010->state) {
842 case WM0010_POWER_OFF:
843 case WM0010_OUT_OF_RESET:
844 case WM0010_BOOTROM:
845 case WM0010_STAGE2:
846 spin_lock(&wm0010->irq_lock);
847 complete(&wm0010->boot_completion);
848 spin_unlock(&wm0010->irq_lock);
849 return IRQ_HANDLED;
850 default:
851 return IRQ_NONE;
852 }
853
854 return IRQ_NONE;
855}
856
857static int wm0010_probe(struct snd_soc_codec *codec)
858{
859 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
32c50a31
MB		 860
861 wm0010->codec = codec;
862
863 return 0;
864}
865
866static int __devinit wm0010_spi_probe(struct spi_device *spi)
867{
e3523e01
DP		 868 unsigned long gpio_flags;
869 int ret;
870 int trigger;
871 int irq;
32c50a31 872 struct wm0010_priv *wm0010;
e3523e01 873
32c50a31
MB		 874 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
875 GFP_KERNEL);
876 if (!wm0010)
877 return -ENOMEM;
878
879 mutex_init(&wm0010->lock);
880 spin_lock_init(&wm0010->irq_lock);
881
882 spi_set_drvdata(spi, wm0010);
883 wm0010->dev = &spi->dev;
884
885 if (dev_get_platdata(&spi->dev))
886 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
887 sizeof(wm0010->pdata));
e3523e01
DP		 888
889 init_completion(&wm0010->boot_completion);
890
891 wm0010->core_supplies[0].supply = "AVDD";
892 wm0010->core_supplies[1].supply = "DCVDD";
893 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
894 wm0010->core_supplies);
895 if (ret != 0) {
896 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
897 ret);
898 return ret;
899 }
900
901 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
902 if (IS_ERR(wm0010->dbvdd)) {
903 ret = PTR_ERR(wm0010->dbvdd);
904 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
905 return ret;
906 }
907
908 if (wm0010->pdata.gpio_reset) {
909 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
910
911 if (wm0010->pdata.reset_active_high)
912 wm0010->gpio_reset_value = 1;
913 else
914 wm0010->gpio_reset_value = 0;
915
916 if (wm0010->gpio_reset_value)
917 gpio_flags = GPIOF_OUT_INIT_HIGH;
918 else
919 gpio_flags = GPIOF_OUT_INIT_LOW;
920
921 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
922 gpio_flags, "wm0010 reset");
923 if (ret < 0) {
924 dev_err(wm0010->dev,
925 "Failed to request GPIO for DSP reset: %d\n",
926 ret);
927 return ret;
928 }
929 } else {
930 dev_err(wm0010->dev, "No reset GPIO configured\n");
32c50a31 931 return -EINVAL;
e3523e01
DP		 932 }
933
9bb68444
MB		 934 wm0010->state = WM0010_POWER_OFF;
935
e3523e01
DP		 936 irq = spi->irq;
937 if (wm0010->pdata.irq_flags)
938 trigger = wm0010->pdata.irq_flags;
939 else
940 trigger = IRQF_TRIGGER_FALLING;
941 trigger |= IRQF_ONESHOT;
942
58d46832 943 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger | IRQF_ONESHOT,
e3523e01 944 "wm0010", wm0010);
32c50a31 945 if (ret) {
e3523e01
DP		 946 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
947 irq, ret);
32c50a31
MB		 948 return ret;
949 }
e3523e01
DP		 950 wm0010->irq = irq;
951
952 if (spi->max_speed_hz)
953 wm0010->board_max_spi_speed = spi->max_speed_hz;
954 else
955 wm0010->board_max_spi_speed = 0;
956
e3523e01
DP		 957 ret = snd_soc_register_codec(&spi->dev,
958 &soc_codec_dev_wm0010, wm0010_dai,
959 ARRAY_SIZE(wm0010_dai));
960 if (ret < 0)
961 return ret;
962
963 return 0;
964}
965
966static int __devexit wm0010_spi_remove(struct spi_device *spi)
967{
968 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
969
970 snd_soc_unregister_codec(&spi->dev);
971
5afe5bfe
MB		 972 gpio_set_value_cansleep(wm0010->gpio_reset,
973 wm0010->gpio_reset_value);
e3523e01
DP		 974
975 if (wm0010->irq)
976 free_irq(wm0010->irq, wm0010);
977
978 return 0;
979}
980
981static struct spi_driver wm0010_spi_driver = {
982 .driver = {
983 .name = "wm0010",
984 .bus = &spi_bus_type,
985 .owner = THIS_MODULE,
986 },
987 .probe = wm0010_spi_probe,
988 .remove = __devexit_p(wm0010_spi_remove),
989};
990
991module_spi_driver(wm0010_spi_driver);
992
993MODULE_DESCRIPTION("ASoC WM0010 driver");
994MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
995MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.091411 seconds and 5 git commands to generate.