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Linux 3.7-rc2
[deliverable/linux.git] / sound / soc / codecs / wm0010.c
CommitLineData
e3523e01
DP		 1/*
2 * wm0010.c -- WM0010 DSP Driver
3 *
4 * Copyright 2012 Wolfson Microelectronics PLC.
5 *
6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * Scott Ling <sl@opensource.wolfsonmicro.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/irqreturn.h>
18#include <linux/init.h>
19#include <linux/spi/spi.h>
20#include <linux/firmware.h>
21#include <linux/delay.h>
22#include <linux/fs.h>
23#include <linux/miscdevice.h>
24#include <linux/gpio.h>
25#include <linux/regulator/consumer.h>
26#include <linux/mutex.h>
27#include <linux/workqueue.h>
28
29#include <sound/soc.h>
30#include <sound/wm0010.h>
31
32#define DEVICE_ID_WM0010 10
33
34enum dfw_cmd {
35 DFW_CMD_FUSE = 0x01,
36 DFW_CMD_CODE_HDR,
37 DFW_CMD_CODE_DATA,
38 DFW_CMD_PLL,
39 DFW_CMD_INFO = 0xff
40};
41
42struct dfw_binrec {
43 u8 command;
44 u32 length:24;
45 u32 address;
46 uint8_t data[0];
47} __packed;
48
49struct dfw_pllrec {
50 u8 command;
51 u32 length:24;
52 u32 address;
53 u32 clkctrl1;
54 u32 clkctrl2;
55 u32 clkctrl3;
56 u32 ldetctrl;
57 u32 uart_div;
58 u32 spi_div;
59} __packed;
60
61static struct pll_clock_map {
62 int max_sysclk;
63 int max_pll_spi_speed;
64 u32 pll_clkctrl1;
65} pll_clock_map[] = { /* Dividers */
66 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
67 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
68 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
69 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
70 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
71 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
72};
73
74enum wm0010_state {
75 WM0010_POWER_OFF,
76 WM0010_OUT_OF_RESET,
77 WM0010_BOOTROM,
78 WM0010_STAGE2,
79 WM0010_FIRMWARE,
80};
81
82struct wm0010_priv {
83 struct snd_soc_codec *codec;
84
85 struct mutex lock;
86 struct device *dev;
87
88 struct wm0010_pdata pdata;
89
90 int gpio_reset;
91 int gpio_reset_value;
92
93 struct regulator_bulk_data core_supplies[2];
94 struct regulator *dbvdd;
95
96 int sysclk;
97
98 enum wm0010_state state;
99 bool boot_failed;
100 int boot_done;
101 bool ready;
102 bool pll_running;
103 int max_spi_freq;
104 int board_max_spi_speed;
105 u32 pll_clkctrl1;
106
107 spinlock_t irq_lock;
108 int irq;
109
110 struct completion boot_completion;
111};
112
113struct wm0010_spi_msg {
114 struct spi_message m;
115 struct spi_transfer t;
116 u8 *tx_buf;
117 u8 *rx_buf;
118 size_t len;
119};
120
1470bfac
MB		 121static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
122SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
123};
124
e3523e01 125static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
1549c34b
MB		 126 { "SDI2 Capture", NULL, "SDI1 Playback" },
127 { "SDI1 Capture", NULL, "SDI2 Playback" },
1470bfac
MB		 128
129 { "SDI1 Capture", NULL, "CLKIN" },
130 { "SDI2 Capture", NULL, "CLKIN" },
131 { "SDI1 Playback", NULL, "CLKIN" },
132 { "SDI2 Playback", NULL, "CLKIN" },
e3523e01
DP		 133};
134
135static const char *wm0010_state_to_str(enum wm0010_state state)
136{
137 const char *state_to_str[] = {
138 "Power off",
139 "Out of reset",
bf9d3237 140 "Boot ROM",
e3523e01
DP		 141 "Stage2",
142 "Firmware"
143 };
144
145 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
146 return "null";
147 return state_to_str[state];
148}
149
150/* Called with wm0010->lock held */
151static void wm0010_halt(struct snd_soc_codec *codec)
152{
153 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
154 unsigned long flags;
155 enum wm0010_state state;
156
157 /* Fetch the wm0010 state */
158 spin_lock_irqsave(&wm0010->irq_lock, flags);
159 state = wm0010->state;
160 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
161
162 switch (state) {
163 case WM0010_POWER_OFF:
164 /* If there's nothing to do, bail out */
165 return;
166 case WM0010_OUT_OF_RESET:
167 case WM0010_BOOTROM:
168 case WM0010_STAGE2:
169 case WM0010_FIRMWARE:
170 /* Remember to put chip back into reset */
fff00cbc
MB		 171 gpio_set_value_cansleep(wm0010->gpio_reset,
172 wm0010->gpio_reset_value);
e3523e01
DP		 173 /* Disable the regulators */
174 regulator_disable(wm0010->dbvdd);
175 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
176 wm0010->core_supplies);
177 break;
178 }
179
180 spin_lock_irqsave(&wm0010->irq_lock, flags);
181 wm0010->state = WM0010_POWER_OFF;
182 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
183}
184
185struct wm0010_boot_xfer {
186 struct list_head list;
187 struct snd_soc_codec *codec;
188 struct completion *done;
189 struct spi_message m;
190 struct spi_transfer t;
191};
192
193/* Called with wm0010->lock held */
194static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
195{
196 enum wm0010_state state;
197 unsigned long flags;
198
199 spin_lock_irqsave(&wm0010->irq_lock, flags);
200 state = wm0010->state;
201 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
202
203 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
204 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
205
206 wm0010->boot_failed = true;
207}
208
209static void wm0010_boot_xfer_complete(void *data)
210{
211 struct wm0010_boot_xfer *xfer = data;
212 struct snd_soc_codec *codec = xfer->codec;
213 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
214 u32 *out32 = xfer->t.rx_buf;
215 int i;
216
217 if (xfer->m.status != 0) {
218 dev_err(codec->dev, "SPI transfer failed: %d\n",
219 xfer->m.status);
220 wm0010_mark_boot_failure(wm0010);
221 if (xfer->done)
222 complete(xfer->done);
223 return;
224 }
225
226 for (i = 0; i < xfer->t.len / 4; i++) {
227 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]);
228
229 switch (be32_to_cpu(out32[i])) {
230 case 0xe0e0e0e0:
231 dev_err(codec->dev,
232 "%d: ROM error reported in stage 2\n", i);
233 wm0010_mark_boot_failure(wm0010);
234 break;
235
236 case 0x55555555:
237 if (wm0010->boot_done == 0)
238 break;
239 dev_err(codec->dev,
240 "%d: ROM bootloader running in stage 2\n", i);
241 wm0010_mark_boot_failure(wm0010);
242 break;
243
244 case 0x0fed0000:
245 dev_dbg(codec->dev, "Stage2 loader running\n");
246 break;
247
248 case 0x0fed0007:
249 dev_dbg(codec->dev, "CODE_HDR packet received\n");
250 break;
251
252 case 0x0fed0008:
253 dev_dbg(codec->dev, "CODE_DATA packet received\n");
254 break;
255
256 case 0x0fed0009:
257 dev_dbg(codec->dev, "Download complete\n");
258 break;
259
260 case 0x0fed000c:
261 dev_dbg(codec->dev, "Application start\n");
262 break;
263
264 case 0x0fed000e:
265 dev_dbg(codec->dev, "PLL packet received\n");
266 wm0010->pll_running = true;
267 break;
268
269 case 0x0fed0025:
270 dev_err(codec->dev, "Device reports image too long\n");
271 wm0010_mark_boot_failure(wm0010);
272 break;
273
274 case 0x0fed002c:
275 dev_err(codec->dev, "Device reports bad SPI packet\n");
276 wm0010_mark_boot_failure(wm0010);
277 break;
278
279 case 0x0fed0031:
280 dev_err(codec->dev, "Device reports SPI read overflow\n");
281 wm0010_mark_boot_failure(wm0010);
282 break;
283
284 case 0x0fed0032:
285 dev_err(codec->dev, "Device reports SPI underclock\n");
286 wm0010_mark_boot_failure(wm0010);
287 break;
288
289 case 0x0fed0033:
290 dev_err(codec->dev, "Device reports bad header packet\n");
291 wm0010_mark_boot_failure(wm0010);
292 break;
293
294 case 0x0fed0034:
295 dev_err(codec->dev, "Device reports invalid packet type\n");
296 wm0010_mark_boot_failure(wm0010);
297 break;
298
299 case 0x0fed0035:
300 dev_err(codec->dev, "Device reports data before header error\n");
301 wm0010_mark_boot_failure(wm0010);
302 break;
303
304 case 0x0fed0038:
305 dev_err(codec->dev, "Device reports invalid PLL packet\n");
306 break;
307
308 case 0x0fed003a:
309 dev_err(codec->dev, "Device reports packet alignment error\n");
310 wm0010_mark_boot_failure(wm0010);
311 break;
312
313 default:
314 dev_err(codec->dev, "Unrecognised return 0x%x\n",
315 be32_to_cpu(out32[i]));
316 wm0010_mark_boot_failure(wm0010);
317 break;
318 }
319
320 if (wm0010->boot_failed)
321 break;
322 }
323
324 wm0010->boot_done++;
325 if (xfer->done)
326 complete(xfer->done);
327}
328
329static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
330{
331 int i;
332
333 for (i = 0; i < len / 8; i++)
334 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
335}
336
337static int wm0010_boot(struct snd_soc_codec *codec)
338{
339 struct spi_device *spi = to_spi_device(codec->dev);
340 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
341 unsigned long flags;
342 struct list_head xfer_list;
343 struct wm0010_boot_xfer *xfer;
344 int ret;
345 struct completion done;
346 const struct firmware *fw;
347 const struct dfw_binrec *rec;
348 struct spi_message m;
349 struct spi_transfer t;
350 struct dfw_pllrec pll_rec;
351 u32 *img, *p;
352 u64 *img_swap;
353 u8 *out;
354 u32 len, offset;
355 int i;
356
357 spin_lock_irqsave(&wm0010->irq_lock, flags);
358 if (wm0010->state != WM0010_POWER_OFF)
359 dev_warn(wm0010->dev, "DSP already powered up!\n");
360 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
361
362 if (wm0010->sysclk > 26000000) {
363 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n");
364 ret = -ECANCELED;
365 goto err;
366 }
367
368 INIT_LIST_HEAD(&xfer_list);
369
370 mutex_lock(&wm0010->lock);
371 wm0010->pll_running = false;
372
373 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
374
375 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
376 wm0010->core_supplies);
377 if (ret != 0) {
378 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
379 ret);
380 mutex_unlock(&wm0010->lock);
381 goto err;
382 }
383
384 ret = regulator_enable(wm0010->dbvdd);
385 if (ret != 0) {
386 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
387 goto err_core;
388 }
389
390 /* Release reset */
fff00cbc 391 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
e3523e01
DP		 392 spin_lock_irqsave(&wm0010->irq_lock, flags);
393 wm0010->state = WM0010_OUT_OF_RESET;
394 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
395
396 /* First the bootloader */
397 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
398 if (ret != 0) {
399 dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
400 ret);
401 goto abort;
402 }
403
404 if (!wait_for_completion_timeout(&wm0010->boot_completion,
405 msecs_to_jiffies(10)))
406 dev_err(codec->dev, "Failed to get interrupt from DSP\n");
407
408 spin_lock_irqsave(&wm0010->irq_lock, flags);
409 wm0010->state = WM0010_BOOTROM;
410 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
411
5d86e25c 412 dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
e3523e01
DP		 413
414 /* Copy to local buffer first as vmalloc causes problems for dma */
415 img = kzalloc(fw->size, GFP_KERNEL);
416 if (!img) {
417 dev_err(codec->dev, "Failed to allocate image buffer\n");
418 goto abort;
419 }
420
421 out = kzalloc(fw->size, GFP_KERNEL);
422 if (!out) {
423 dev_err(codec->dev, "Failed to allocate output buffer\n");
424 goto abort;
425 }
426
427 memcpy(img, &fw->data[0], fw->size);
428
429 spi_message_init(&m);
430 memset(&t, 0, sizeof(t));
431 t.rx_buf = out;
432 t.tx_buf = img;
433 t.len = fw->size;
434 t.bits_per_word = 8;
435 t.speed_hz = wm0010->sysclk / 10;
436 spi_message_add_tail(&t, &m);
437
438 dev_dbg(codec->dev, "Starting initial download at %dHz\n",
439 t.speed_hz);
440
441 ret = spi_sync(spi, &m);
442 if (ret != 0) {
443 dev_err(codec->dev, "Initial download failed: %d\n", ret);
444 goto abort;
445 }
446
447 /* Look for errors from the boot ROM */
448 for (i = 0; i < fw->size; i++) {
449 if (out[i] != 0x55) {
450 ret = -EBUSY;
451 dev_err(codec->dev, "Boot ROM error: %x in %d\n",
452 out[i], i);
453 wm0010_mark_boot_failure(wm0010);
454 goto abort;
455 }
456 }
457
458 release_firmware(fw);
459 kfree(img);
460 kfree(out);
461
462 if (!wait_for_completion_timeout(&wm0010->boot_completion,
463 msecs_to_jiffies(10)))
464 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n");
465
466 spin_lock_irqsave(&wm0010->irq_lock, flags);
467 wm0010->state = WM0010_STAGE2;
468 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
469
470 /* Only initialise PLL if max_spi_freq initialised */
471 if (wm0010->max_spi_freq) {
472
473 /* Initialise a PLL record */
474 memset(&pll_rec, 0, sizeof(pll_rec));
475 pll_rec.command = DFW_CMD_PLL;
476 pll_rec.length = (sizeof(pll_rec) - 8);
477
478 /* On wm0010 only the CLKCTRL1 value is used */
479 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
480
481 len = pll_rec.length + 8;
482 out = kzalloc(len, GFP_KERNEL);
483 if (!out) {
484 dev_err(codec->dev,
485 "Failed to allocate RX buffer\n");
486 goto abort;
487 }
488
489 img_swap = kzalloc(len, GFP_KERNEL);
490 if (!img_swap) {
491 dev_err(codec->dev,
492 "Failed to allocate image buffer\n");
493 goto abort;
494 }
495
496 /* We need to re-order for 0010 */
497 byte_swap_64((u64 *)&pll_rec, img_swap, len);
498
499 spi_message_init(&m);
500 memset(&t, 0, sizeof(t));
501 t.rx_buf = out;
502 t.tx_buf = img_swap;
503 t.len = len;
504 t.bits_per_word = 8;
505 t.speed_hz = wm0010->sysclk / 6;
506 spi_message_add_tail(&t, &m);
507
508 ret = spi_sync(spi, &m);
509 if (ret != 0) {
510 dev_err(codec->dev, "First PLL write failed: %d\n", ret);
511 goto abort;
512 }
513
514 /* Use a second send of the message to get the return status */
515 ret = spi_sync(spi, &m);
516 if (ret != 0) {
517 dev_err(codec->dev, "Second PLL write failed: %d\n", ret);
518 goto abort;
519 }
520
521 p = (u32 *)out;
522
523 /* Look for PLL active code from the DSP */
524 for (i = 0; i < len / 4; i++) {
525 if (*p == 0x0e00ed0f) {
526 dev_dbg(codec->dev, "PLL packet received\n");
527 wm0010->pll_running = true;
528 break;
529 }
530 p++;
531 }
532
533 kfree(img_swap);
534 kfree(out);
535 } else
536 dev_dbg(codec->dev, "Not enabling DSP PLL.");
537
538 ret = request_firmware(&fw, "wm0010.dfw", codec->dev);
539 if (ret != 0) {
540 dev_err(codec->dev, "Failed to request application: %d\n",
541 ret);
542 goto abort;
543 }
544
545 rec = (const struct dfw_binrec *)fw->data;
546 offset = 0;
547 wm0010->boot_done = 0;
548 wm0010->boot_failed = false;
549 BUG_ON(!list_empty(&xfer_list));
550 init_completion(&done);
551
552 /* First record should be INFO */
553 if (rec->command != DFW_CMD_INFO) {
554 dev_err(codec->dev, "First record not INFO\r\n");
555 goto abort;
556 }
557
558 /* Check it's a 0010 file */
559 if (rec->data[0] != DEVICE_ID_WM0010) {
560 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n");
561 goto abort;
562 }
563
564 /* Skip the info record as we don't need to send it */
565 offset += ((rec->length) + 8);
566 rec = (void *)&rec->data[rec->length];
567
568 while (offset < fw->size) {
569 dev_dbg(codec->dev,
570 "Packet: command %d, data length = 0x%x\r\n",
571 rec->command, rec->length);
572 len = rec->length + 8;
573
574 out = kzalloc(len, GFP_KERNEL);
575 if (!out) {
576 dev_err(codec->dev,
577 "Failed to allocate RX buffer\n");
578 goto abort;
579 }
580
581 img_swap = kzalloc(len, GFP_KERNEL);
582 if (!img_swap) {
583 dev_err(codec->dev,
584 "Failed to allocate image buffer\n");
585 goto abort;
586 }
587
588 /* We need to re-order for 0010 */
589 byte_swap_64((u64 *)&rec->command, img_swap, len);
590
591 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
592 if (!xfer) {
593 dev_err(codec->dev, "Failed to allocate xfer\n");
594 goto abort;
595 }
596
597 xfer->codec = codec;
598 list_add_tail(&xfer->list, &xfer_list);
599
600 spi_message_init(&xfer->m);
601 xfer->m.complete = wm0010_boot_xfer_complete;
602 xfer->m.context = xfer;
603 xfer->t.tx_buf = img_swap;
604 xfer->t.rx_buf = out;
605 xfer->t.len = len;
606 xfer->t.bits_per_word = 8;
607
608 if (!wm0010->pll_running) {
609 xfer->t.speed_hz = wm0010->sysclk / 6;
610 } else {
611 xfer->t.speed_hz = wm0010->max_spi_freq;
612
613 if (wm0010->board_max_spi_speed &&
614 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
615 xfer->t.speed_hz = wm0010->board_max_spi_speed;
616 }
617
618 /* Store max usable spi frequency for later use */
619 wm0010->max_spi_freq = xfer->t.speed_hz;
620
621 spi_message_add_tail(&xfer->t, &xfer->m);
622
623 offset += ((rec->length) + 8);
624 rec = (void *)&rec->data[rec->length];
625
626 if (offset >= fw->size) {
627 dev_dbg(codec->dev, "All transfers scheduled\n");
628 xfer->done = &done;
629 }
630
631 ret = spi_async(spi, &xfer->m);
632 if (ret != 0) {
633 dev_err(codec->dev, "Write failed: %d\n", ret);
634 goto abort;
635 }
636
637 if (wm0010->boot_failed)
638 goto abort;
639 }
640
641 wait_for_completion(&done);
642
643 spin_lock_irqsave(&wm0010->irq_lock, flags);
644 wm0010->state = WM0010_FIRMWARE;
645 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
646
647 mutex_unlock(&wm0010->lock);
648
649 release_firmware(fw);
650
651 while (!list_empty(&xfer_list)) {
652 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
653 list);
654 kfree(xfer->t.rx_buf);
655 kfree(xfer->t.tx_buf);
656 list_del(&xfer->list);
657 kfree(xfer);
658 }
659
660 return 0;
661
662abort:
663 /* Put the chip back into reset */
664 wm0010_halt(codec);
665 mutex_unlock(&wm0010->lock);
666 return ret;
4f3ad795 667
e3523e01 668err_core:
4f3ad795 669 mutex_unlock(&wm0010->lock);
e3523e01
DP		 670 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
671 wm0010->core_supplies);
672err:
673 return ret;
674}
675
676static int wm0010_set_bias_level(struct snd_soc_codec *codec,
677 enum snd_soc_bias_level level)
678{
679 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
680
681 switch (level) {
682 case SND_SOC_BIAS_ON:
683 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
684 wm0010_boot(codec);
685 break;
686 case SND_SOC_BIAS_PREPARE:
687 break;
688 case SND_SOC_BIAS_STANDBY:
689 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
690 mutex_lock(&wm0010->lock);
691 wm0010_halt(codec);
692 mutex_unlock(&wm0010->lock);
693 }
694 break;
695 case SND_SOC_BIAS_OFF:
696 break;
697 }
698
699 codec->dapm.bias_level = level;
700
701 return 0;
702}
703
704static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source,
705 int clk_id, unsigned int freq, int dir)
706{
707 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
708 unsigned int i;
709
710 wm0010->sysclk = freq;
711
712 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
713 wm0010->max_spi_freq = 0;
714 } else {
715 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
716 if (freq >= pll_clock_map[i].max_sysclk)
717 break;
718
719 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
720 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
721 }
722
723 return 0;
724}
725
726static int wm0010_probe(struct snd_soc_codec *codec);
727
728static struct snd_soc_codec_driver soc_codec_dev_wm0010 = {
729 .probe = wm0010_probe,
730 .set_bias_level = wm0010_set_bias_level,
731 .set_sysclk = wm0010_set_sysclk,
d3fd716e 732 .idle_bias_off = true,
e3523e01 733
1470bfac
MB		 734 .dapm_widgets = wm0010_dapm_widgets,
735 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
e3523e01
DP		 736 .dapm_routes = wm0010_dapm_routes,
737 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
738};
739
6df31986 740#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
e3523e01
DP		 741#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
742 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
743 SNDRV_PCM_FMTBIT_S32_LE)
744
745static struct snd_soc_dai_driver wm0010_dai[] = {
746 {
747 .name = "wm0010-sdi1",
748 .playback = {
749 .stream_name = "SDI1 Playback",
750 .channels_min = 1,
751 .channels_max = 2,
752 .rates = WM0010_RATES,
753 .formats = WM0010_FORMATS,
754 },
755 .capture = {
756 .stream_name = "SDI1 Capture",
757 .channels_min = 1,
758 .channels_max = 2,
759 .rates = WM0010_RATES,
760 .formats = WM0010_FORMATS,
761 },
762 },
763 {
764 .name = "wm0010-sdi2",
765 .playback = {
766 .stream_name = "SDI2 Playback",
767 .channels_min = 1,
768 .channels_max = 2,
769 .rates = WM0010_RATES,
770 .formats = WM0010_FORMATS,
771 },
772 .capture = {
773 .stream_name = "SDI2 Capture",
774 .channels_min = 1,
775 .channels_max = 2,
776 .rates = WM0010_RATES,
777 .formats = WM0010_FORMATS,
778 },
779 },
780};
781
782static irqreturn_t wm0010_irq(int irq, void *data)
783{
784 struct wm0010_priv *wm0010 = data;
785
786 switch (wm0010->state) {
787 case WM0010_POWER_OFF:
788 case WM0010_OUT_OF_RESET:
789 case WM0010_BOOTROM:
790 case WM0010_STAGE2:
791 spin_lock(&wm0010->irq_lock);
792 complete(&wm0010->boot_completion);
793 spin_unlock(&wm0010->irq_lock);
794 return IRQ_HANDLED;
795 default:
796 return IRQ_NONE;
797 }
798
799 return IRQ_NONE;
800}
801
802static int wm0010_probe(struct snd_soc_codec *codec)
803{
804 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
32c50a31
MB		 805
806 wm0010->codec = codec;
807
808 return 0;
809}
810
811static int __devinit wm0010_spi_probe(struct spi_device *spi)
812{
e3523e01
DP		 813 unsigned long gpio_flags;
814 int ret;
815 int trigger;
816 int irq;
32c50a31 817 struct wm0010_priv *wm0010;
e3523e01 818
32c50a31
MB		 819 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
820 GFP_KERNEL);
821 if (!wm0010)
822 return -ENOMEM;
823
824 mutex_init(&wm0010->lock);
825 spin_lock_init(&wm0010->irq_lock);
826
827 spi_set_drvdata(spi, wm0010);
828 wm0010->dev = &spi->dev;
829
830 if (dev_get_platdata(&spi->dev))
831 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
832 sizeof(wm0010->pdata));
e3523e01
DP		 833
834 init_completion(&wm0010->boot_completion);
835
836 wm0010->core_supplies[0].supply = "AVDD";
837 wm0010->core_supplies[1].supply = "DCVDD";
838 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
839 wm0010->core_supplies);
840 if (ret != 0) {
841 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
842 ret);
843 return ret;
844 }
845
846 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
847 if (IS_ERR(wm0010->dbvdd)) {
848 ret = PTR_ERR(wm0010->dbvdd);
849 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
850 return ret;
851 }
852
853 if (wm0010->pdata.gpio_reset) {
854 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
855
856 if (wm0010->pdata.reset_active_high)
857 wm0010->gpio_reset_value = 1;
858 else
859 wm0010->gpio_reset_value = 0;
860
861 if (wm0010->gpio_reset_value)
862 gpio_flags = GPIOF_OUT_INIT_HIGH;
863 else
864 gpio_flags = GPIOF_OUT_INIT_LOW;
865
866 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
867 gpio_flags, "wm0010 reset");
868 if (ret < 0) {
869 dev_err(wm0010->dev,
870 "Failed to request GPIO for DSP reset: %d\n",
871 ret);
872 return ret;
873 }
874 } else {
875 dev_err(wm0010->dev, "No reset GPIO configured\n");
32c50a31 876 return -EINVAL;
e3523e01
DP		 877 }
878
9bb68444
MB		 879 wm0010->state = WM0010_POWER_OFF;
880
e3523e01
DP		 881 irq = spi->irq;
882 if (wm0010->pdata.irq_flags)
883 trigger = wm0010->pdata.irq_flags;
884 else
885 trigger = IRQF_TRIGGER_FALLING;
886 trigger |= IRQF_ONESHOT;
887
58d46832 888 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger | IRQF_ONESHOT,
e3523e01 889 "wm0010", wm0010);
32c50a31 890 if (ret) {
e3523e01
DP		 891 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
892 irq, ret);
32c50a31
MB		 893 return ret;
894 }
e3523e01
DP		 895 wm0010->irq = irq;
896
897 if (spi->max_speed_hz)
898 wm0010->board_max_spi_speed = spi->max_speed_hz;
899 else
900 wm0010->board_max_spi_speed = 0;
901
e3523e01
DP		 902 ret = snd_soc_register_codec(&spi->dev,
903 &soc_codec_dev_wm0010, wm0010_dai,
904 ARRAY_SIZE(wm0010_dai));
905 if (ret < 0)
906 return ret;
907
908 return 0;
909}
910
911static int __devexit wm0010_spi_remove(struct spi_device *spi)
912{
913 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
914
915 snd_soc_unregister_codec(&spi->dev);
916
5afe5bfe
MB		 917 gpio_set_value_cansleep(wm0010->gpio_reset,
918 wm0010->gpio_reset_value);
e3523e01
DP		 919
920 if (wm0010->irq)
921 free_irq(wm0010->irq, wm0010);
922
923 return 0;
924}
925
926static struct spi_driver wm0010_spi_driver = {
927 .driver = {
928 .name = "wm0010",
929 .bus = &spi_bus_type,
930 .owner = THIS_MODULE,
931 },
932 .probe = wm0010_spi_probe,
933 .remove = __devexit_p(wm0010_spi_remove),
934};
935
936module_spi_driver(wm0010_spi_driver);
937
938MODULE_DESCRIPTION("ASoC WM0010 driver");
939MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
940MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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