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Linux 3.16-rc1
[deliverable/linux.git] / sound / soc / codecs / wm0010.c
CommitLineData
e3523e01
DP		 1/*
2 * wm0010.c -- WM0010 DSP Driver
3 *
4 * Copyright 2012 Wolfson Microelectronics PLC.
5 *
6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * Scott Ling <sl@opensource.wolfsonmicro.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
fd8b9657 17#include <linux/interrupt.h>
e3523e01
DP		 18#include <linux/irqreturn.h>
19#include <linux/init.h>
20#include <linux/spi/spi.h>
21#include <linux/firmware.h>
22#include <linux/delay.h>
23#include <linux/fs.h>
24#include <linux/miscdevice.h>
25#include <linux/gpio.h>
26#include <linux/regulator/consumer.h>
27#include <linux/mutex.h>
28#include <linux/workqueue.h>
29
30#include <sound/soc.h>
31#include <sound/wm0010.h>
32
33#define DEVICE_ID_WM0010 10
34
68e1969e
SL		 35/* We only support v1 of the .dfw INFO record */
36#define INFO_VERSION 1
37
e3523e01
DP		 38enum dfw_cmd {
39 DFW_CMD_FUSE = 0x01,
40 DFW_CMD_CODE_HDR,
41 DFW_CMD_CODE_DATA,
42 DFW_CMD_PLL,
43 DFW_CMD_INFO = 0xff
44};
45
46struct dfw_binrec {
47 u8 command;
48 u32 length:24;
49 u32 address;
50 uint8_t data[0];
51} __packed;
52
68e1969e
SL		 53struct dfw_inforec {
54 u8 info_version;
55 u8 tool_major_version;
56 u8 tool_minor_version;
57 u8 dsp_target;
58};
59
e3523e01
DP		 60struct dfw_pllrec {
61 u8 command;
62 u32 length:24;
63 u32 address;
64 u32 clkctrl1;
65 u32 clkctrl2;
66 u32 clkctrl3;
67 u32 ldetctrl;
68 u32 uart_div;
69 u32 spi_div;
70} __packed;
71
72static struct pll_clock_map {
73 int max_sysclk;
74 int max_pll_spi_speed;
75 u32 pll_clkctrl1;
76} pll_clock_map[] = { /* Dividers */
77 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
78 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
79 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
80 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
81 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
82 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
83};
84
85enum wm0010_state {
86 WM0010_POWER_OFF,
87 WM0010_OUT_OF_RESET,
88 WM0010_BOOTROM,
89 WM0010_STAGE2,
90 WM0010_FIRMWARE,
91};
92
93struct wm0010_priv {
94 struct snd_soc_codec *codec;
95
96 struct mutex lock;
97 struct device *dev;
98
99 struct wm0010_pdata pdata;
100
101 int gpio_reset;
102 int gpio_reset_value;
103
104 struct regulator_bulk_data core_supplies[2];
105 struct regulator *dbvdd;
106
107 int sysclk;
108
109 enum wm0010_state state;
110 bool boot_failed;
e3523e01
DP		 111 bool ready;
112 bool pll_running;
113 int max_spi_freq;
114 int board_max_spi_speed;
115 u32 pll_clkctrl1;
116
117 spinlock_t irq_lock;
118 int irq;
119
120 struct completion boot_completion;
121};
122
123struct wm0010_spi_msg {
124 struct spi_message m;
125 struct spi_transfer t;
126 u8 *tx_buf;
127 u8 *rx_buf;
128 size_t len;
129};
130
1470bfac
MB		 131static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
132SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
133};
134
e3523e01 135static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
1549c34b
MB		 136 { "SDI2 Capture", NULL, "SDI1 Playback" },
137 { "SDI1 Capture", NULL, "SDI2 Playback" },
1470bfac
MB		 138
139 { "SDI1 Capture", NULL, "CLKIN" },
140 { "SDI2 Capture", NULL, "CLKIN" },
141 { "SDI1 Playback", NULL, "CLKIN" },
142 { "SDI2 Playback", NULL, "CLKIN" },
e3523e01
DP		 143};
144
145static const char *wm0010_state_to_str(enum wm0010_state state)
146{
147 const char *state_to_str[] = {
148 "Power off",
149 "Out of reset",
bf9d3237 150 "Boot ROM",
e3523e01
DP		 151 "Stage2",
152 "Firmware"
153 };
154
155 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
156 return "null";
157 return state_to_str[state];
158}
159
160/* Called with wm0010->lock held */
161static void wm0010_halt(struct snd_soc_codec *codec)
162{
163 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
164 unsigned long flags;
165 enum wm0010_state state;
166
167 /* Fetch the wm0010 state */
168 spin_lock_irqsave(&wm0010->irq_lock, flags);
169 state = wm0010->state;
170 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
171
172 switch (state) {
173 case WM0010_POWER_OFF:
174 /* If there's nothing to do, bail out */
175 return;
176 case WM0010_OUT_OF_RESET:
177 case WM0010_BOOTROM:
178 case WM0010_STAGE2:
179 case WM0010_FIRMWARE:
180 /* Remember to put chip back into reset */
fff00cbc
MB		 181 gpio_set_value_cansleep(wm0010->gpio_reset,
182 wm0010->gpio_reset_value);
e3523e01
DP		 183 /* Disable the regulators */
184 regulator_disable(wm0010->dbvdd);
185 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
186 wm0010->core_supplies);
187 break;
188 }
189
190 spin_lock_irqsave(&wm0010->irq_lock, flags);
191 wm0010->state = WM0010_POWER_OFF;
192 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
193}
194
195struct wm0010_boot_xfer {
196 struct list_head list;
197 struct snd_soc_codec *codec;
198 struct completion *done;
199 struct spi_message m;
200 struct spi_transfer t;
201};
202
203/* Called with wm0010->lock held */
204static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
205{
206 enum wm0010_state state;
207 unsigned long flags;
208
209 spin_lock_irqsave(&wm0010->irq_lock, flags);
210 state = wm0010->state;
211 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
212
213 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
214 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
215
216 wm0010->boot_failed = true;
217}
218
219static void wm0010_boot_xfer_complete(void *data)
220{
221 struct wm0010_boot_xfer *xfer = data;
222 struct snd_soc_codec *codec = xfer->codec;
223 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
224 u32 *out32 = xfer->t.rx_buf;
225 int i;
226
227 if (xfer->m.status != 0) {
228 dev_err(codec->dev, "SPI transfer failed: %d\n",
229 xfer->m.status);
230 wm0010_mark_boot_failure(wm0010);
231 if (xfer->done)
232 complete(xfer->done);
233 return;
234 }
235
236 for (i = 0; i < xfer->t.len / 4; i++) {
237 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]);
238
239 switch (be32_to_cpu(out32[i])) {
240 case 0xe0e0e0e0:
241 dev_err(codec->dev,
242 "%d: ROM error reported in stage 2\n", i);
243 wm0010_mark_boot_failure(wm0010);
244 break;
245
246 case 0x55555555:
f9baa0cc 247 if (wm0010->state < WM0010_STAGE2)
e3523e01
DP		 248 break;
249 dev_err(codec->dev,
250 "%d: ROM bootloader running in stage 2\n", i);
251 wm0010_mark_boot_failure(wm0010);
252 break;
253
254 case 0x0fed0000:
255 dev_dbg(codec->dev, "Stage2 loader running\n");
256 break;
257
258 case 0x0fed0007:
259 dev_dbg(codec->dev, "CODE_HDR packet received\n");
260 break;
261
262 case 0x0fed0008:
263 dev_dbg(codec->dev, "CODE_DATA packet received\n");
264 break;
265
266 case 0x0fed0009:
267 dev_dbg(codec->dev, "Download complete\n");
268 break;
269
270 case 0x0fed000c:
271 dev_dbg(codec->dev, "Application start\n");
272 break;
273
274 case 0x0fed000e:
275 dev_dbg(codec->dev, "PLL packet received\n");
276 wm0010->pll_running = true;
277 break;
278
279 case 0x0fed0025:
280 dev_err(codec->dev, "Device reports image too long\n");
281 wm0010_mark_boot_failure(wm0010);
282 break;
283
284 case 0x0fed002c:
285 dev_err(codec->dev, "Device reports bad SPI packet\n");
286 wm0010_mark_boot_failure(wm0010);
287 break;
288
289 case 0x0fed0031:
290 dev_err(codec->dev, "Device reports SPI read overflow\n");
291 wm0010_mark_boot_failure(wm0010);
292 break;
293
294 case 0x0fed0032:
295 dev_err(codec->dev, "Device reports SPI underclock\n");
296 wm0010_mark_boot_failure(wm0010);
297 break;
298
299 case 0x0fed0033:
300 dev_err(codec->dev, "Device reports bad header packet\n");
301 wm0010_mark_boot_failure(wm0010);
302 break;
303
304 case 0x0fed0034:
305 dev_err(codec->dev, "Device reports invalid packet type\n");
306 wm0010_mark_boot_failure(wm0010);
307 break;
308
309 case 0x0fed0035:
310 dev_err(codec->dev, "Device reports data before header error\n");
311 wm0010_mark_boot_failure(wm0010);
312 break;
313
314 case 0x0fed0038:
315 dev_err(codec->dev, "Device reports invalid PLL packet\n");
316 break;
317
318 case 0x0fed003a:
319 dev_err(codec->dev, "Device reports packet alignment error\n");
320 wm0010_mark_boot_failure(wm0010);
321 break;
322
323 default:
324 dev_err(codec->dev, "Unrecognised return 0x%x\n",
325 be32_to_cpu(out32[i]));
326 wm0010_mark_boot_failure(wm0010);
327 break;
328 }
329
330 if (wm0010->boot_failed)
331 break;
332 }
333
e3523e01
DP		 334 if (xfer->done)
335 complete(xfer->done);
336}
337
338static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
339{
340 int i;
341
342 for (i = 0; i < len / 8; i++)
343 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
344}
345
961b0fc8 346static int wm0010_firmware_load(const char *name, struct snd_soc_codec *codec)
e3523e01
DP		 347{
348 struct spi_device *spi = to_spi_device(codec->dev);
349 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
e3523e01
DP		 350 struct list_head xfer_list;
351 struct wm0010_boot_xfer *xfer;
352 int ret;
353 struct completion done;
354 const struct firmware *fw;
355 const struct dfw_binrec *rec;
68e1969e 356 const struct dfw_inforec *inforec;
8f7d52af
SL		 357 u64 *img;
358 u8 *out, dsp;
359 u32 len, offset;
360
361 INIT_LIST_HEAD(&xfer_list);
362
363 ret = request_firmware(&fw, name, codec->dev);
364 if (ret != 0) {
3e112af5
CK		 365 dev_err(codec->dev, "Failed to request application(%s): %d\n",
366 name, ret);
8f7d52af
SL		 367 return ret;
368 }
369
370 rec = (const struct dfw_binrec *)fw->data;
68e1969e 371 inforec = (const struct dfw_inforec *)rec->data;
8f7d52af 372 offset = 0;
68e1969e 373 dsp = inforec->dsp_target;
8f7d52af 374 wm0010->boot_failed = false;
f5b3a563
TI		 375 if (WARN_ON(!list_empty(&xfer_list)))
376 return -EINVAL;
8f7d52af
SL		 377 init_completion(&done);
378
379 /* First record should be INFO */
380 if (rec->command != DFW_CMD_INFO) {
381 dev_err(codec->dev, "First record not INFO\r\n");
382 ret = -EINVAL;
383 goto abort;
384 }
385
68e1969e
SL		 386 if (inforec->info_version != INFO_VERSION) {
387 dev_err(codec->dev,
388 "Unsupported version (%02d) of INFO record\r\n",
389 inforec->info_version);
390 ret = -EINVAL;
391 goto abort;
392 }
393
394 dev_dbg(codec->dev, "Version v%02d INFO record found\r\n",
395 inforec->info_version);
396
8f7d52af
SL		 397 /* Check it's a DSP file */
398 if (dsp != DEVICE_ID_WM0010) {
399 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n");
400 ret = -EINVAL;
401 goto abort;
402 }
403
404 /* Skip the info record as we don't need to send it */
405 offset += ((rec->length) + 8);
406 rec = (void *)&rec->data[rec->length];
407
408 while (offset < fw->size) {
409 dev_dbg(codec->dev,
410 "Packet: command %d, data length = 0x%x\r\n",
411 rec->command, rec->length);
412 len = rec->length + 8;
413
4f8b1914
DP		 414 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
415 if (!xfer) {
416 dev_err(codec->dev, "Failed to allocate xfer\n");
417 ret = -ENOMEM;
418 goto abort;
419 }
420
421 xfer->codec = codec;
422 list_add_tail(&xfer->list, &xfer_list);
423
d4780eec 424 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
8f7d52af
SL		 425 if (!out) {
426 dev_err(codec->dev,
427 "Failed to allocate RX buffer\n");
428 ret = -ENOMEM;
429 goto abort1;
430 }
4f8b1914 431 xfer->t.rx_buf = out;
8f7d52af 432
d4780eec 433 img = kzalloc(len, GFP_KERNEL | GFP_DMA);
8f7d52af
SL		 434 if (!img) {
435 dev_err(codec->dev,
436 "Failed to allocate image buffer\n");
437 ret = -ENOMEM;
438 goto abort1;
439 }
4f8b1914 440 xfer->t.tx_buf = img;
8f7d52af
SL		 441
442 byte_swap_64((u64 *)&rec->command, img, len);
443
8f7d52af
SL		 444 spi_message_init(&xfer->m);
445 xfer->m.complete = wm0010_boot_xfer_complete;
446 xfer->m.context = xfer;
8f7d52af
SL		 447 xfer->t.len = len;
448 xfer->t.bits_per_word = 8;
449
450 if (!wm0010->pll_running) {
451 xfer->t.speed_hz = wm0010->sysclk / 6;
452 } else {
453 xfer->t.speed_hz = wm0010->max_spi_freq;
454
455 if (wm0010->board_max_spi_speed &&
456 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
457 xfer->t.speed_hz = wm0010->board_max_spi_speed;
458 }
459
460 /* Store max usable spi frequency for later use */
461 wm0010->max_spi_freq = xfer->t.speed_hz;
462
463 spi_message_add_tail(&xfer->t, &xfer->m);
464
465 offset += ((rec->length) + 8);
466 rec = (void *)&rec->data[rec->length];
467
468 if (offset >= fw->size) {
469 dev_dbg(codec->dev, "All transfers scheduled\n");
470 xfer->done = &done;
471 }
472
473 ret = spi_async(spi, &xfer->m);
474 if (ret != 0) {
475 dev_err(codec->dev, "Write failed: %d\n", ret);
476 goto abort1;
477 }
478
479 if (wm0010->boot_failed) {
480 dev_dbg(codec->dev, "Boot fail!\n");
481 ret = -EINVAL;
482 goto abort1;
483 }
484 }
485
486 wait_for_completion(&done);
487
488 ret = 0;
489
490abort1:
491 while (!list_empty(&xfer_list)) {
492 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
493 list);
494 kfree(xfer->t.rx_buf);
495 kfree(xfer->t.tx_buf);
496 list_del(&xfer->list);
497 kfree(xfer);
498 }
499
500abort:
501 release_firmware(fw);
502 return ret;
503}
504
3f5475df
SL		 505static int wm0010_stage2_load(struct snd_soc_codec *codec)
506{
507 struct spi_device *spi = to_spi_device(codec->dev);
508 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
509 const struct firmware *fw;
510 struct spi_message m;
511 struct spi_transfer t;
512 u32 *img;
513 u8 *out;
514 int i;
515 int ret = 0;
516
517 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
518 if (ret != 0) {
519 dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
520 ret);
521 return ret;
522 }
523
524 dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
525
526 /* Copy to local buffer first as vmalloc causes problems for dma */
d4780eec 527 img = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
3f5475df
SL		 528 if (!img) {
529 dev_err(codec->dev, "Failed to allocate image buffer\n");
530 ret = -ENOMEM;
531 goto abort2;
532 }
533
d4780eec 534 out = kzalloc(fw->size, GFP_KERNEL | GFP_DMA);
3f5475df
SL		 535 if (!out) {
536 dev_err(codec->dev, "Failed to allocate output buffer\n");
537 ret = -ENOMEM;
538 goto abort1;
539 }
540
541 memcpy(img, &fw->data[0], fw->size);
542
543 spi_message_init(&m);
544 memset(&t, 0, sizeof(t));
545 t.rx_buf = out;
546 t.tx_buf = img;
547 t.len = fw->size;
548 t.bits_per_word = 8;
549 t.speed_hz = wm0010->sysclk / 10;
550 spi_message_add_tail(&t, &m);
551
552 dev_dbg(codec->dev, "Starting initial download at %dHz\n",
553 t.speed_hz);
554
555 ret = spi_sync(spi, &m);
556 if (ret != 0) {
557 dev_err(codec->dev, "Initial download failed: %d\n", ret);
558 goto abort;
559 }
560
561 /* Look for errors from the boot ROM */
562 for (i = 0; i < fw->size; i++) {
563 if (out[i] != 0x55) {
564 dev_err(codec->dev, "Boot ROM error: %x in %d\n",
565 out[i], i);
566 wm0010_mark_boot_failure(wm0010);
567 ret = -EBUSY;
568 goto abort;
569 }
570 }
571abort:
572 kfree(out);
573abort1:
574 kfree(img);
575abort2:
576 release_firmware(fw);
577
578 return ret;
579}
580
8f7d52af
SL		 581static int wm0010_boot(struct snd_soc_codec *codec)
582{
583 struct spi_device *spi = to_spi_device(codec->dev);
584 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
585 unsigned long flags;
586 int ret;
587 const struct firmware *fw;
e3523e01
DP		 588 struct spi_message m;
589 struct spi_transfer t;
590 struct dfw_pllrec pll_rec;
3f5475df 591 u32 *p, len;
e3523e01
DP		 592 u64 *img_swap;
593 u8 *out;
e3523e01
DP		 594 int i;
595
596 spin_lock_irqsave(&wm0010->irq_lock, flags);
597 if (wm0010->state != WM0010_POWER_OFF)
598 dev_warn(wm0010->dev, "DSP already powered up!\n");
599 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
600
601 if (wm0010->sysclk > 26000000) {
602 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n");
603 ret = -ECANCELED;
604 goto err;
605 }
606
e3523e01
DP		 607 mutex_lock(&wm0010->lock);
608 wm0010->pll_running = false;
609
610 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
611
612 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
613 wm0010->core_supplies);
614 if (ret != 0) {
615 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
616 ret);
617 mutex_unlock(&wm0010->lock);
618 goto err;
619 }
620
621 ret = regulator_enable(wm0010->dbvdd);
622 if (ret != 0) {
623 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
624 goto err_core;
625 }
626
627 /* Release reset */
fff00cbc 628 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
e3523e01
DP		 629 spin_lock_irqsave(&wm0010->irq_lock, flags);
630 wm0010->state = WM0010_OUT_OF_RESET;
631 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
632
633 /* First the bootloader */
634 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
635 if (ret != 0) {
636 dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
637 ret);
638 goto abort;
639 }
640
641 if (!wait_for_completion_timeout(&wm0010->boot_completion,
631fcab2 642 msecs_to_jiffies(20)))
e3523e01
DP		 643 dev_err(codec->dev, "Failed to get interrupt from DSP\n");
644
645 spin_lock_irqsave(&wm0010->irq_lock, flags);
646 wm0010->state = WM0010_BOOTROM;
647 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
648
3f5475df
SL		 649 ret = wm0010_stage2_load(codec);
650 if (ret)
e3523e01 651 goto abort;
e3523e01
DP		 652
653 if (!wait_for_completion_timeout(&wm0010->boot_completion,
631fcab2 654 msecs_to_jiffies(20)))
e3523e01
DP		 655 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n");
656
657 spin_lock_irqsave(&wm0010->irq_lock, flags);
658 wm0010->state = WM0010_STAGE2;
659 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
660
661 /* Only initialise PLL if max_spi_freq initialised */
662 if (wm0010->max_spi_freq) {
663
664 /* Initialise a PLL record */
665 memset(&pll_rec, 0, sizeof(pll_rec));
666 pll_rec.command = DFW_CMD_PLL;
667 pll_rec.length = (sizeof(pll_rec) - 8);
668
669 /* On wm0010 only the CLKCTRL1 value is used */
670 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
671
2e0192f1 672 ret = -ENOMEM;
e3523e01 673 len = pll_rec.length + 8;
d4780eec 674 out = kzalloc(len, GFP_KERNEL | GFP_DMA);
e3523e01
DP		 675 if (!out) {
676 dev_err(codec->dev,
677 "Failed to allocate RX buffer\n");
678 goto abort;
679 }
680
d4780eec 681 img_swap = kzalloc(len, GFP_KERNEL | GFP_DMA);
e3523e01
DP		 682 if (!img_swap) {
683 dev_err(codec->dev,
684 "Failed to allocate image buffer\n");
685 goto abort;
686 }
687
688 /* We need to re-order for 0010 */
689 byte_swap_64((u64 *)&pll_rec, img_swap, len);
690
691 spi_message_init(&m);
692 memset(&t, 0, sizeof(t));
693 t.rx_buf = out;
694 t.tx_buf = img_swap;
695 t.len = len;
696 t.bits_per_word = 8;
697 t.speed_hz = wm0010->sysclk / 6;
698 spi_message_add_tail(&t, &m);
699
700 ret = spi_sync(spi, &m);
701 if (ret != 0) {
702 dev_err(codec->dev, "First PLL write failed: %d\n", ret);
703 goto abort;
704 }
705
706 /* Use a second send of the message to get the return status */
707 ret = spi_sync(spi, &m);
708 if (ret != 0) {
709 dev_err(codec->dev, "Second PLL write failed: %d\n", ret);
710 goto abort;
711 }
712
713 p = (u32 *)out;
714
715 /* Look for PLL active code from the DSP */
716 for (i = 0; i < len / 4; i++) {
717 if (*p == 0x0e00ed0f) {
718 dev_dbg(codec->dev, "PLL packet received\n");
719 wm0010->pll_running = true;
720 break;
721 }
722 p++;
723 }
724
725 kfree(img_swap);
726 kfree(out);
727 } else
728 dev_dbg(codec->dev, "Not enabling DSP PLL.");
729
8f7d52af 730 ret = wm0010_firmware_load("wm0010.dfw", codec);
e3523e01 731
8f7d52af 732 if (ret != 0)
e3523e01 733 goto abort;
e3523e01
DP		 734
735 spin_lock_irqsave(&wm0010->irq_lock, flags);
736 wm0010->state = WM0010_FIRMWARE;
737 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
738
739 mutex_unlock(&wm0010->lock);
740
e3523e01
DP		 741 return 0;
742
743abort:
744 /* Put the chip back into reset */
745 wm0010_halt(codec);
746 mutex_unlock(&wm0010->lock);
747 return ret;
4f3ad795 748
e3523e01 749err_core:
4f3ad795 750 mutex_unlock(&wm0010->lock);
e3523e01
DP		 751 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
752 wm0010->core_supplies);
753err:
754 return ret;
755}
756
757static int wm0010_set_bias_level(struct snd_soc_codec *codec,
758 enum snd_soc_bias_level level)
759{
760 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
761
762 switch (level) {
763 case SND_SOC_BIAS_ON:
764 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
765 wm0010_boot(codec);
766 break;
767 case SND_SOC_BIAS_PREPARE:
768 break;
769 case SND_SOC_BIAS_STANDBY:
770 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
771 mutex_lock(&wm0010->lock);
772 wm0010_halt(codec);
773 mutex_unlock(&wm0010->lock);
774 }
775 break;
776 case SND_SOC_BIAS_OFF:
777 break;
778 }
779
780 codec->dapm.bias_level = level;
781
782 return 0;
783}
784
785static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source,
786 int clk_id, unsigned int freq, int dir)
787{
788 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
789 unsigned int i;
790
791 wm0010->sysclk = freq;
792
793 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
794 wm0010->max_spi_freq = 0;
795 } else {
796 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
c36c8909
TI		 797 if (freq >= pll_clock_map[i].max_sysclk) {
798 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
799 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
e3523e01 800 break;
c36c8909 801 }
e3523e01
DP		 802 }
803
804 return 0;
805}
806
807static int wm0010_probe(struct snd_soc_codec *codec);
808
809static struct snd_soc_codec_driver soc_codec_dev_wm0010 = {
810 .probe = wm0010_probe,
811 .set_bias_level = wm0010_set_bias_level,
812 .set_sysclk = wm0010_set_sysclk,
d3fd716e 813 .idle_bias_off = true,
e3523e01 814
1470bfac
MB		 815 .dapm_widgets = wm0010_dapm_widgets,
816 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
e3523e01
DP		 817 .dapm_routes = wm0010_dapm_routes,
818 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
819};
820
6df31986 821#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
e3523e01
DP		 822#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
823 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
824 SNDRV_PCM_FMTBIT_S32_LE)
825
826static struct snd_soc_dai_driver wm0010_dai[] = {
827 {
828 .name = "wm0010-sdi1",
829 .playback = {
830 .stream_name = "SDI1 Playback",
831 .channels_min = 1,
832 .channels_max = 2,
833 .rates = WM0010_RATES,
834 .formats = WM0010_FORMATS,
835 },
836 .capture = {
837 .stream_name = "SDI1 Capture",
838 .channels_min = 1,
839 .channels_max = 2,
840 .rates = WM0010_RATES,
841 .formats = WM0010_FORMATS,
842 },
843 },
844 {
845 .name = "wm0010-sdi2",
846 .playback = {
847 .stream_name = "SDI2 Playback",
848 .channels_min = 1,
849 .channels_max = 2,
850 .rates = WM0010_RATES,
851 .formats = WM0010_FORMATS,
852 },
853 .capture = {
854 .stream_name = "SDI2 Capture",
855 .channels_min = 1,
856 .channels_max = 2,
857 .rates = WM0010_RATES,
858 .formats = WM0010_FORMATS,
859 },
860 },
861};
862
863static irqreturn_t wm0010_irq(int irq, void *data)
864{
865 struct wm0010_priv *wm0010 = data;
866
867 switch (wm0010->state) {
e3523e01
DP		 868 case WM0010_OUT_OF_RESET:
869 case WM0010_BOOTROM:
870 case WM0010_STAGE2:
871 spin_lock(&wm0010->irq_lock);
872 complete(&wm0010->boot_completion);
873 spin_unlock(&wm0010->irq_lock);
874 return IRQ_HANDLED;
875 default:
876 return IRQ_NONE;
877 }
878
879 return IRQ_NONE;
880}
881
882static int wm0010_probe(struct snd_soc_codec *codec)
883{
884 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
32c50a31
MB		 885
886 wm0010->codec = codec;
887
888 return 0;
889}
890
7a79e94e 891static int wm0010_spi_probe(struct spi_device *spi)
32c50a31 892{
e3523e01
DP		 893 unsigned long gpio_flags;
894 int ret;
895 int trigger;
896 int irq;
32c50a31 897 struct wm0010_priv *wm0010;
e3523e01 898
32c50a31
MB		 899 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
900 GFP_KERNEL);
901 if (!wm0010)
902 return -ENOMEM;
903
904 mutex_init(&wm0010->lock);
905 spin_lock_init(&wm0010->irq_lock);
906
907 spi_set_drvdata(spi, wm0010);
908 wm0010->dev = &spi->dev;
909
910 if (dev_get_platdata(&spi->dev))
911 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
912 sizeof(wm0010->pdata));
e3523e01
DP		 913
914 init_completion(&wm0010->boot_completion);
915
916 wm0010->core_supplies[0].supply = "AVDD";
917 wm0010->core_supplies[1].supply = "DCVDD";
918 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
919 wm0010->core_supplies);
920 if (ret != 0) {
921 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
922 ret);
923 return ret;
924 }
925
926 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
927 if (IS_ERR(wm0010->dbvdd)) {
928 ret = PTR_ERR(wm0010->dbvdd);
929 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
930 return ret;
931 }
932
933 if (wm0010->pdata.gpio_reset) {
934 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
935
936 if (wm0010->pdata.reset_active_high)
937 wm0010->gpio_reset_value = 1;
938 else
939 wm0010->gpio_reset_value = 0;
940
941 if (wm0010->gpio_reset_value)
942 gpio_flags = GPIOF_OUT_INIT_HIGH;
943 else
944 gpio_flags = GPIOF_OUT_INIT_LOW;
945
946 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
947 gpio_flags, "wm0010 reset");
948 if (ret < 0) {
949 dev_err(wm0010->dev,
950 "Failed to request GPIO for DSP reset: %d\n",
951 ret);
952 return ret;
953 }
954 } else {
955 dev_err(wm0010->dev, "No reset GPIO configured\n");
32c50a31 956 return -EINVAL;
e3523e01
DP		 957 }
958
9bb68444
MB		 959 wm0010->state = WM0010_POWER_OFF;
960
e3523e01
DP		 961 irq = spi->irq;
962 if (wm0010->pdata.irq_flags)
963 trigger = wm0010->pdata.irq_flags;
964 else
965 trigger = IRQF_TRIGGER_FALLING;
966 trigger |= IRQF_ONESHOT;
967
58d46832 968 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger | IRQF_ONESHOT,
e3523e01 969 "wm0010", wm0010);
32c50a31 970 if (ret) {
e3523e01
DP		 971 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
972 irq, ret);
32c50a31
MB		 973 return ret;
974 }
e3523e01
DP		 975 wm0010->irq = irq;
976
e684533b
CK		 977 ret = irq_set_irq_wake(irq, 1);
978 if (ret) {
979 dev_err(wm0010->dev, "Failed to set IRQ %d as wake source: %d\n",
980 irq, ret);
981 return ret;
982 }
983
e3523e01
DP		 984 if (spi->max_speed_hz)
985 wm0010->board_max_spi_speed = spi->max_speed_hz;
986 else
987 wm0010->board_max_spi_speed = 0;
988
e3523e01
DP		 989 ret = snd_soc_register_codec(&spi->dev,
990 &soc_codec_dev_wm0010, wm0010_dai,
991 ARRAY_SIZE(wm0010_dai));
992 if (ret < 0)
993 return ret;
994
995 return 0;
996}
997
7a79e94e 998static int wm0010_spi_remove(struct spi_device *spi)
e3523e01
DP		 999{
1000 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
1001
1002 snd_soc_unregister_codec(&spi->dev);
1003
5afe5bfe
MB		 1004 gpio_set_value_cansleep(wm0010->gpio_reset,
1005 wm0010->gpio_reset_value);
e3523e01 1006
fd8b9657
CK		 1007 irq_set_irq_wake(wm0010->irq, 0);
1008
e3523e01
DP		 1009 if (wm0010->irq)
1010 free_irq(wm0010->irq, wm0010);
1011
1012 return 0;
1013}
1014
1015static struct spi_driver wm0010_spi_driver = {
1016 .driver = {
1017 .name = "wm0010",
1018 .bus = &spi_bus_type,
1019 .owner = THIS_MODULE,
1020 },
1021 .probe = wm0010_spi_probe,
7a79e94e 1022 .remove = wm0010_spi_remove,
e3523e01
DP		 1023};
1024
1025module_spi_driver(wm0010_spi_driver);
1026
1027MODULE_DESCRIPTION("ASoC WM0010 driver");
1028MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1029MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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