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ASoC: wm0010: Split out the firmware file parsing from the boot
[deliverable/linux.git] / sound / soc / codecs / wm0010.c
CommitLineData
e3523e01
DP		 1/*
2 * wm0010.c -- WM0010 DSP Driver
3 *
4 * Copyright 2012 Wolfson Microelectronics PLC.
5 *
6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * Scott Ling <sl@opensource.wolfsonmicro.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/irqreturn.h>
18#include <linux/init.h>
19#include <linux/spi/spi.h>
20#include <linux/firmware.h>
21#include <linux/delay.h>
22#include <linux/fs.h>
23#include <linux/miscdevice.h>
24#include <linux/gpio.h>
25#include <linux/regulator/consumer.h>
26#include <linux/mutex.h>
27#include <linux/workqueue.h>
28
29#include <sound/soc.h>
30#include <sound/wm0010.h>
31
32#define DEVICE_ID_WM0010 10
33
34enum dfw_cmd {
35 DFW_CMD_FUSE = 0x01,
36 DFW_CMD_CODE_HDR,
37 DFW_CMD_CODE_DATA,
38 DFW_CMD_PLL,
39 DFW_CMD_INFO = 0xff
40};
41
42struct dfw_binrec {
43 u8 command;
44 u32 length:24;
45 u32 address;
46 uint8_t data[0];
47} __packed;
48
49struct dfw_pllrec {
50 u8 command;
51 u32 length:24;
52 u32 address;
53 u32 clkctrl1;
54 u32 clkctrl2;
55 u32 clkctrl3;
56 u32 ldetctrl;
57 u32 uart_div;
58 u32 spi_div;
59} __packed;
60
61static struct pll_clock_map {
62 int max_sysclk;
63 int max_pll_spi_speed;
64 u32 pll_clkctrl1;
65} pll_clock_map[] = { /* Dividers */
66 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
67 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
68 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
69 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
70 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
71 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
72};
73
74enum wm0010_state {
75 WM0010_POWER_OFF,
76 WM0010_OUT_OF_RESET,
77 WM0010_BOOTROM,
78 WM0010_STAGE2,
79 WM0010_FIRMWARE,
80};
81
82struct wm0010_priv {
83 struct snd_soc_codec *codec;
84
85 struct mutex lock;
86 struct device *dev;
87
88 struct wm0010_pdata pdata;
89
90 int gpio_reset;
91 int gpio_reset_value;
92
93 struct regulator_bulk_data core_supplies[2];
94 struct regulator *dbvdd;
95
96 int sysclk;
97
98 enum wm0010_state state;
99 bool boot_failed;
e3523e01
DP		 100 bool ready;
101 bool pll_running;
102 int max_spi_freq;
103 int board_max_spi_speed;
104 u32 pll_clkctrl1;
105
106 spinlock_t irq_lock;
107 int irq;
108
109 struct completion boot_completion;
110};
111
112struct wm0010_spi_msg {
113 struct spi_message m;
114 struct spi_transfer t;
115 u8 *tx_buf;
116 u8 *rx_buf;
117 size_t len;
118};
119
1470bfac
MB		 120static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
121SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
122};
123
e3523e01 124static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
1549c34b
MB		 125 { "SDI2 Capture", NULL, "SDI1 Playback" },
126 { "SDI1 Capture", NULL, "SDI2 Playback" },
1470bfac
MB		 127
128 { "SDI1 Capture", NULL, "CLKIN" },
129 { "SDI2 Capture", NULL, "CLKIN" },
130 { "SDI1 Playback", NULL, "CLKIN" },
131 { "SDI2 Playback", NULL, "CLKIN" },
e3523e01
DP		 132};
133
134static const char *wm0010_state_to_str(enum wm0010_state state)
135{
136 const char *state_to_str[] = {
137 "Power off",
138 "Out of reset",
bf9d3237 139 "Boot ROM",
e3523e01
DP		 140 "Stage2",
141 "Firmware"
142 };
143
144 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
145 return "null";
146 return state_to_str[state];
147}
148
149/* Called with wm0010->lock held */
150static void wm0010_halt(struct snd_soc_codec *codec)
151{
152 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
153 unsigned long flags;
154 enum wm0010_state state;
155
156 /* Fetch the wm0010 state */
157 spin_lock_irqsave(&wm0010->irq_lock, flags);
158 state = wm0010->state;
159 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
160
161 switch (state) {
162 case WM0010_POWER_OFF:
163 /* If there's nothing to do, bail out */
164 return;
165 case WM0010_OUT_OF_RESET:
166 case WM0010_BOOTROM:
167 case WM0010_STAGE2:
168 case WM0010_FIRMWARE:
169 /* Remember to put chip back into reset */
fff00cbc
MB		 170 gpio_set_value_cansleep(wm0010->gpio_reset,
171 wm0010->gpio_reset_value);
e3523e01
DP		 172 /* Disable the regulators */
173 regulator_disable(wm0010->dbvdd);
174 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
175 wm0010->core_supplies);
176 break;
177 }
178
179 spin_lock_irqsave(&wm0010->irq_lock, flags);
180 wm0010->state = WM0010_POWER_OFF;
181 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
182}
183
184struct wm0010_boot_xfer {
185 struct list_head list;
186 struct snd_soc_codec *codec;
187 struct completion *done;
188 struct spi_message m;
189 struct spi_transfer t;
190};
191
192/* Called with wm0010->lock held */
193static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
194{
195 enum wm0010_state state;
196 unsigned long flags;
197
198 spin_lock_irqsave(&wm0010->irq_lock, flags);
199 state = wm0010->state;
200 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
201
202 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
203 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
204
205 wm0010->boot_failed = true;
206}
207
208static void wm0010_boot_xfer_complete(void *data)
209{
210 struct wm0010_boot_xfer *xfer = data;
211 struct snd_soc_codec *codec = xfer->codec;
212 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
213 u32 *out32 = xfer->t.rx_buf;
214 int i;
215
216 if (xfer->m.status != 0) {
217 dev_err(codec->dev, "SPI transfer failed: %d\n",
218 xfer->m.status);
219 wm0010_mark_boot_failure(wm0010);
220 if (xfer->done)
221 complete(xfer->done);
222 return;
223 }
224
225 for (i = 0; i < xfer->t.len / 4; i++) {
226 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]);
227
228 switch (be32_to_cpu(out32[i])) {
229 case 0xe0e0e0e0:
230 dev_err(codec->dev,
231 "%d: ROM error reported in stage 2\n", i);
232 wm0010_mark_boot_failure(wm0010);
233 break;
234
235 case 0x55555555:
f9baa0cc 236 if (wm0010->state < WM0010_STAGE2)
e3523e01
DP		 237 break;
238 dev_err(codec->dev,
239 "%d: ROM bootloader running in stage 2\n", i);
240 wm0010_mark_boot_failure(wm0010);
241 break;
242
243 case 0x0fed0000:
244 dev_dbg(codec->dev, "Stage2 loader running\n");
245 break;
246
247 case 0x0fed0007:
248 dev_dbg(codec->dev, "CODE_HDR packet received\n");
249 break;
250
251 case 0x0fed0008:
252 dev_dbg(codec->dev, "CODE_DATA packet received\n");
253 break;
254
255 case 0x0fed0009:
256 dev_dbg(codec->dev, "Download complete\n");
257 break;
258
259 case 0x0fed000c:
260 dev_dbg(codec->dev, "Application start\n");
261 break;
262
263 case 0x0fed000e:
264 dev_dbg(codec->dev, "PLL packet received\n");
265 wm0010->pll_running = true;
266 break;
267
268 case 0x0fed0025:
269 dev_err(codec->dev, "Device reports image too long\n");
270 wm0010_mark_boot_failure(wm0010);
271 break;
272
273 case 0x0fed002c:
274 dev_err(codec->dev, "Device reports bad SPI packet\n");
275 wm0010_mark_boot_failure(wm0010);
276 break;
277
278 case 0x0fed0031:
279 dev_err(codec->dev, "Device reports SPI read overflow\n");
280 wm0010_mark_boot_failure(wm0010);
281 break;
282
283 case 0x0fed0032:
284 dev_err(codec->dev, "Device reports SPI underclock\n");
285 wm0010_mark_boot_failure(wm0010);
286 break;
287
288 case 0x0fed0033:
289 dev_err(codec->dev, "Device reports bad header packet\n");
290 wm0010_mark_boot_failure(wm0010);
291 break;
292
293 case 0x0fed0034:
294 dev_err(codec->dev, "Device reports invalid packet type\n");
295 wm0010_mark_boot_failure(wm0010);
296 break;
297
298 case 0x0fed0035:
299 dev_err(codec->dev, "Device reports data before header error\n");
300 wm0010_mark_boot_failure(wm0010);
301 break;
302
303 case 0x0fed0038:
304 dev_err(codec->dev, "Device reports invalid PLL packet\n");
305 break;
306
307 case 0x0fed003a:
308 dev_err(codec->dev, "Device reports packet alignment error\n");
309 wm0010_mark_boot_failure(wm0010);
310 break;
311
312 default:
313 dev_err(codec->dev, "Unrecognised return 0x%x\n",
314 be32_to_cpu(out32[i]));
315 wm0010_mark_boot_failure(wm0010);
316 break;
317 }
318
319 if (wm0010->boot_failed)
320 break;
321 }
322
e3523e01
DP		 323 if (xfer->done)
324 complete(xfer->done);
325}
326
327static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
328{
329 int i;
330
331 for (i = 0; i < len / 8; i++)
332 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
333}
334
8f7d52af 335static int wm0010_firmware_load(char *name, struct snd_soc_codec *codec)
e3523e01
DP		 336{
337 struct spi_device *spi = to_spi_device(codec->dev);
338 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
e3523e01
DP		 339 struct list_head xfer_list;
340 struct wm0010_boot_xfer *xfer;
341 int ret;
342 struct completion done;
343 const struct firmware *fw;
344 const struct dfw_binrec *rec;
8f7d52af
SL		 345 u64 *img;
346 u8 *out, dsp;
347 u32 len, offset;
348
349 INIT_LIST_HEAD(&xfer_list);
350
351 ret = request_firmware(&fw, name, codec->dev);
352 if (ret != 0) {
353 dev_err(codec->dev, "Failed to request application: %d\n",
354 ret);
355 return ret;
356 }
357
358 rec = (const struct dfw_binrec *)fw->data;
359 offset = 0;
360 dsp = rec->data[0];
361 wm0010->boot_failed = false;
362 BUG_ON(!list_empty(&xfer_list));
363 init_completion(&done);
364
365 /* First record should be INFO */
366 if (rec->command != DFW_CMD_INFO) {
367 dev_err(codec->dev, "First record not INFO\r\n");
368 ret = -EINVAL;
369 goto abort;
370 }
371
372 /* Check it's a DSP file */
373 if (dsp != DEVICE_ID_WM0010) {
374 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n");
375 ret = -EINVAL;
376 goto abort;
377 }
378
379 /* Skip the info record as we don't need to send it */
380 offset += ((rec->length) + 8);
381 rec = (void *)&rec->data[rec->length];
382
383 while (offset < fw->size) {
384 dev_dbg(codec->dev,
385 "Packet: command %d, data length = 0x%x\r\n",
386 rec->command, rec->length);
387 len = rec->length + 8;
388
389 out = kzalloc(len, GFP_KERNEL);
390 if (!out) {
391 dev_err(codec->dev,
392 "Failed to allocate RX buffer\n");
393 ret = -ENOMEM;
394 goto abort1;
395 }
396
397 img = kzalloc(len, GFP_KERNEL);
398 if (!img) {
399 dev_err(codec->dev,
400 "Failed to allocate image buffer\n");
401 ret = -ENOMEM;
402 goto abort1;
403 }
404
405 byte_swap_64((u64 *)&rec->command, img, len);
406
407 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
408 if (!xfer) {
409 dev_err(codec->dev, "Failed to allocate xfer\n");
410 ret = -ENOMEM;
411 goto abort1;
412 }
413
414 xfer->codec = codec;
415 list_add_tail(&xfer->list, &xfer_list);
416
417 spi_message_init(&xfer->m);
418 xfer->m.complete = wm0010_boot_xfer_complete;
419 xfer->m.context = xfer;
420 xfer->t.tx_buf = img;
421 xfer->t.rx_buf = out;
422 xfer->t.len = len;
423 xfer->t.bits_per_word = 8;
424
425 if (!wm0010->pll_running) {
426 xfer->t.speed_hz = wm0010->sysclk / 6;
427 } else {
428 xfer->t.speed_hz = wm0010->max_spi_freq;
429
430 if (wm0010->board_max_spi_speed &&
431 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
432 xfer->t.speed_hz = wm0010->board_max_spi_speed;
433 }
434
435 /* Store max usable spi frequency for later use */
436 wm0010->max_spi_freq = xfer->t.speed_hz;
437
438 spi_message_add_tail(&xfer->t, &xfer->m);
439
440 offset += ((rec->length) + 8);
441 rec = (void *)&rec->data[rec->length];
442
443 if (offset >= fw->size) {
444 dev_dbg(codec->dev, "All transfers scheduled\n");
445 xfer->done = &done;
446 }
447
448 ret = spi_async(spi, &xfer->m);
449 if (ret != 0) {
450 dev_err(codec->dev, "Write failed: %d\n", ret);
451 goto abort1;
452 }
453
454 if (wm0010->boot_failed) {
455 dev_dbg(codec->dev, "Boot fail!\n");
456 ret = -EINVAL;
457 goto abort1;
458 }
459 }
460
461 wait_for_completion(&done);
462
463 ret = 0;
464
465abort1:
466 while (!list_empty(&xfer_list)) {
467 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
468 list);
469 kfree(xfer->t.rx_buf);
470 kfree(xfer->t.tx_buf);
471 list_del(&xfer->list);
472 kfree(xfer);
473 }
474
475abort:
476 release_firmware(fw);
477 return ret;
478}
479
480static int wm0010_boot(struct snd_soc_codec *codec)
481{
482 struct spi_device *spi = to_spi_device(codec->dev);
483 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
484 unsigned long flags;
485 int ret;
486 const struct firmware *fw;
e3523e01
DP		 487 struct spi_message m;
488 struct spi_transfer t;
489 struct dfw_pllrec pll_rec;
490 u32 *img, *p;
491 u64 *img_swap;
492 u8 *out;
8f7d52af 493 u32 len;
e3523e01
DP		 494 int i;
495
496 spin_lock_irqsave(&wm0010->irq_lock, flags);
497 if (wm0010->state != WM0010_POWER_OFF)
498 dev_warn(wm0010->dev, "DSP already powered up!\n");
499 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
500
501 if (wm0010->sysclk > 26000000) {
502 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n");
503 ret = -ECANCELED;
504 goto err;
505 }
506
e3523e01
DP		 507 mutex_lock(&wm0010->lock);
508 wm0010->pll_running = false;
509
510 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
511
512 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
513 wm0010->core_supplies);
514 if (ret != 0) {
515 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
516 ret);
517 mutex_unlock(&wm0010->lock);
518 goto err;
519 }
520
521 ret = regulator_enable(wm0010->dbvdd);
522 if (ret != 0) {
523 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
524 goto err_core;
525 }
526
527 /* Release reset */
fff00cbc 528 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
e3523e01
DP		 529 spin_lock_irqsave(&wm0010->irq_lock, flags);
530 wm0010->state = WM0010_OUT_OF_RESET;
531 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
532
533 /* First the bootloader */
534 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
535 if (ret != 0) {
536 dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
537 ret);
538 goto abort;
539 }
540
541 if (!wait_for_completion_timeout(&wm0010->boot_completion,
542 msecs_to_jiffies(10)))
543 dev_err(codec->dev, "Failed to get interrupt from DSP\n");
544
545 spin_lock_irqsave(&wm0010->irq_lock, flags);
546 wm0010->state = WM0010_BOOTROM;
547 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
548
5d86e25c 549 dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
e3523e01
DP		 550
551 /* Copy to local buffer first as vmalloc causes problems for dma */
552 img = kzalloc(fw->size, GFP_KERNEL);
553 if (!img) {
554 dev_err(codec->dev, "Failed to allocate image buffer\n");
555 goto abort;
556 }
557
558 out = kzalloc(fw->size, GFP_KERNEL);
559 if (!out) {
560 dev_err(codec->dev, "Failed to allocate output buffer\n");
561 goto abort;
562 }
563
564 memcpy(img, &fw->data[0], fw->size);
565
566 spi_message_init(&m);
567 memset(&t, 0, sizeof(t));
568 t.rx_buf = out;
569 t.tx_buf = img;
570 t.len = fw->size;
571 t.bits_per_word = 8;
572 t.speed_hz = wm0010->sysclk / 10;
573 spi_message_add_tail(&t, &m);
574
575 dev_dbg(codec->dev, "Starting initial download at %dHz\n",
576 t.speed_hz);
577
578 ret = spi_sync(spi, &m);
579 if (ret != 0) {
580 dev_err(codec->dev, "Initial download failed: %d\n", ret);
581 goto abort;
582 }
583
584 /* Look for errors from the boot ROM */
585 for (i = 0; i < fw->size; i++) {
586 if (out[i] != 0x55) {
587 ret = -EBUSY;
588 dev_err(codec->dev, "Boot ROM error: %x in %d\n",
589 out[i], i);
590 wm0010_mark_boot_failure(wm0010);
591 goto abort;
592 }
593 }
594
595 release_firmware(fw);
596 kfree(img);
597 kfree(out);
598
599 if (!wait_for_completion_timeout(&wm0010->boot_completion,
600 msecs_to_jiffies(10)))
601 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n");
602
603 spin_lock_irqsave(&wm0010->irq_lock, flags);
604 wm0010->state = WM0010_STAGE2;
605 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
606
607 /* Only initialise PLL if max_spi_freq initialised */
608 if (wm0010->max_spi_freq) {
609
610 /* Initialise a PLL record */
611 memset(&pll_rec, 0, sizeof(pll_rec));
612 pll_rec.command = DFW_CMD_PLL;
613 pll_rec.length = (sizeof(pll_rec) - 8);
614
615 /* On wm0010 only the CLKCTRL1 value is used */
616 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
617
618 len = pll_rec.length + 8;
619 out = kzalloc(len, GFP_KERNEL);
620 if (!out) {
621 dev_err(codec->dev,
622 "Failed to allocate RX buffer\n");
623 goto abort;
624 }
625
626 img_swap = kzalloc(len, GFP_KERNEL);
627 if (!img_swap) {
628 dev_err(codec->dev,
629 "Failed to allocate image buffer\n");
630 goto abort;
631 }
632
633 /* We need to re-order for 0010 */
634 byte_swap_64((u64 *)&pll_rec, img_swap, len);
635
636 spi_message_init(&m);
637 memset(&t, 0, sizeof(t));
638 t.rx_buf = out;
639 t.tx_buf = img_swap;
640 t.len = len;
641 t.bits_per_word = 8;
642 t.speed_hz = wm0010->sysclk / 6;
643 spi_message_add_tail(&t, &m);
644
645 ret = spi_sync(spi, &m);
646 if (ret != 0) {
647 dev_err(codec->dev, "First PLL write failed: %d\n", ret);
648 goto abort;
649 }
650
651 /* Use a second send of the message to get the return status */
652 ret = spi_sync(spi, &m);
653 if (ret != 0) {
654 dev_err(codec->dev, "Second PLL write failed: %d\n", ret);
655 goto abort;
656 }
657
658 p = (u32 *)out;
659
660 /* Look for PLL active code from the DSP */
661 for (i = 0; i < len / 4; i++) {
662 if (*p == 0x0e00ed0f) {
663 dev_dbg(codec->dev, "PLL packet received\n");
664 wm0010->pll_running = true;
665 break;
666 }
667 p++;
668 }
669
670 kfree(img_swap);
671 kfree(out);
672 } else
673 dev_dbg(codec->dev, "Not enabling DSP PLL.");
674
8f7d52af 675 ret = wm0010_firmware_load("wm0010.dfw", codec);
e3523e01 676
8f7d52af 677 if (ret != 0)
e3523e01 678 goto abort;
e3523e01
DP		 679
680 spin_lock_irqsave(&wm0010->irq_lock, flags);
681 wm0010->state = WM0010_FIRMWARE;
682 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
683
684 mutex_unlock(&wm0010->lock);
685
e3523e01
DP		 686 return 0;
687
688abort:
689 /* Put the chip back into reset */
690 wm0010_halt(codec);
691 mutex_unlock(&wm0010->lock);
692 return ret;
4f3ad795 693
e3523e01 694err_core:
4f3ad795 695 mutex_unlock(&wm0010->lock);
e3523e01
DP		 696 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
697 wm0010->core_supplies);
698err:
699 return ret;
700}
701
702static int wm0010_set_bias_level(struct snd_soc_codec *codec,
703 enum snd_soc_bias_level level)
704{
705 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
706
707 switch (level) {
708 case SND_SOC_BIAS_ON:
709 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
710 wm0010_boot(codec);
711 break;
712 case SND_SOC_BIAS_PREPARE:
713 break;
714 case SND_SOC_BIAS_STANDBY:
715 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
716 mutex_lock(&wm0010->lock);
717 wm0010_halt(codec);
718 mutex_unlock(&wm0010->lock);
719 }
720 break;
721 case SND_SOC_BIAS_OFF:
722 break;
723 }
724
725 codec->dapm.bias_level = level;
726
727 return 0;
728}
729
730static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source,
731 int clk_id, unsigned int freq, int dir)
732{
733 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
734 unsigned int i;
735
736 wm0010->sysclk = freq;
737
738 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
739 wm0010->max_spi_freq = 0;
740 } else {
741 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
742 if (freq >= pll_clock_map[i].max_sysclk)
743 break;
744
745 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
746 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
747 }
748
749 return 0;
750}
751
752static int wm0010_probe(struct snd_soc_codec *codec);
753
754static struct snd_soc_codec_driver soc_codec_dev_wm0010 = {
755 .probe = wm0010_probe,
756 .set_bias_level = wm0010_set_bias_level,
757 .set_sysclk = wm0010_set_sysclk,
d3fd716e 758 .idle_bias_off = true,
e3523e01 759
1470bfac
MB		 760 .dapm_widgets = wm0010_dapm_widgets,
761 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
e3523e01
DP		 762 .dapm_routes = wm0010_dapm_routes,
763 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
764};
765
6df31986 766#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
e3523e01
DP		 767#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
768 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
769 SNDRV_PCM_FMTBIT_S32_LE)
770
771static struct snd_soc_dai_driver wm0010_dai[] = {
772 {
773 .name = "wm0010-sdi1",
774 .playback = {
775 .stream_name = "SDI1 Playback",
776 .channels_min = 1,
777 .channels_max = 2,
778 .rates = WM0010_RATES,
779 .formats = WM0010_FORMATS,
780 },
781 .capture = {
782 .stream_name = "SDI1 Capture",
783 .channels_min = 1,
784 .channels_max = 2,
785 .rates = WM0010_RATES,
786 .formats = WM0010_FORMATS,
787 },
788 },
789 {
790 .name = "wm0010-sdi2",
791 .playback = {
792 .stream_name = "SDI2 Playback",
793 .channels_min = 1,
794 .channels_max = 2,
795 .rates = WM0010_RATES,
796 .formats = WM0010_FORMATS,
797 },
798 .capture = {
799 .stream_name = "SDI2 Capture",
800 .channels_min = 1,
801 .channels_max = 2,
802 .rates = WM0010_RATES,
803 .formats = WM0010_FORMATS,
804 },
805 },
806};
807
808static irqreturn_t wm0010_irq(int irq, void *data)
809{
810 struct wm0010_priv *wm0010 = data;
811
812 switch (wm0010->state) {
813 case WM0010_POWER_OFF:
814 case WM0010_OUT_OF_RESET:
815 case WM0010_BOOTROM:
816 case WM0010_STAGE2:
817 spin_lock(&wm0010->irq_lock);
818 complete(&wm0010->boot_completion);
819 spin_unlock(&wm0010->irq_lock);
820 return IRQ_HANDLED;
821 default:
822 return IRQ_NONE;
823 }
824
825 return IRQ_NONE;
826}
827
828static int wm0010_probe(struct snd_soc_codec *codec)
829{
830 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
32c50a31
MB		 831
832 wm0010->codec = codec;
833
834 return 0;
835}
836
837static int __devinit wm0010_spi_probe(struct spi_device *spi)
838{
e3523e01
DP		 839 unsigned long gpio_flags;
840 int ret;
841 int trigger;
842 int irq;
32c50a31 843 struct wm0010_priv *wm0010;
e3523e01 844
32c50a31
MB		 845 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
846 GFP_KERNEL);
847 if (!wm0010)
848 return -ENOMEM;
849
850 mutex_init(&wm0010->lock);
851 spin_lock_init(&wm0010->irq_lock);
852
853 spi_set_drvdata(spi, wm0010);
854 wm0010->dev = &spi->dev;
855
856 if (dev_get_platdata(&spi->dev))
857 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
858 sizeof(wm0010->pdata));
e3523e01
DP		 859
860 init_completion(&wm0010->boot_completion);
861
862 wm0010->core_supplies[0].supply = "AVDD";
863 wm0010->core_supplies[1].supply = "DCVDD";
864 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
865 wm0010->core_supplies);
866 if (ret != 0) {
867 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
868 ret);
869 return ret;
870 }
871
872 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
873 if (IS_ERR(wm0010->dbvdd)) {
874 ret = PTR_ERR(wm0010->dbvdd);
875 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
876 return ret;
877 }
878
879 if (wm0010->pdata.gpio_reset) {
880 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
881
882 if (wm0010->pdata.reset_active_high)
883 wm0010->gpio_reset_value = 1;
884 else
885 wm0010->gpio_reset_value = 0;
886
887 if (wm0010->gpio_reset_value)
888 gpio_flags = GPIOF_OUT_INIT_HIGH;
889 else
890 gpio_flags = GPIOF_OUT_INIT_LOW;
891
892 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
893 gpio_flags, "wm0010 reset");
894 if (ret < 0) {
895 dev_err(wm0010->dev,
896 "Failed to request GPIO for DSP reset: %d\n",
897 ret);
898 return ret;
899 }
900 } else {
901 dev_err(wm0010->dev, "No reset GPIO configured\n");
32c50a31 902 return -EINVAL;
e3523e01
DP		 903 }
904
9bb68444
MB		 905 wm0010->state = WM0010_POWER_OFF;
906
e3523e01
DP		 907 irq = spi->irq;
908 if (wm0010->pdata.irq_flags)
909 trigger = wm0010->pdata.irq_flags;
910 else
911 trigger = IRQF_TRIGGER_FALLING;
912 trigger |= IRQF_ONESHOT;
913
58d46832 914 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger | IRQF_ONESHOT,
e3523e01 915 "wm0010", wm0010);
32c50a31 916 if (ret) {
e3523e01
DP		 917 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
918 irq, ret);
32c50a31
MB		 919 return ret;
920 }
e3523e01
DP		 921 wm0010->irq = irq;
922
923 if (spi->max_speed_hz)
924 wm0010->board_max_spi_speed = spi->max_speed_hz;
925 else
926 wm0010->board_max_spi_speed = 0;
927
e3523e01
DP		 928 ret = snd_soc_register_codec(&spi->dev,
929 &soc_codec_dev_wm0010, wm0010_dai,
930 ARRAY_SIZE(wm0010_dai));
931 if (ret < 0)
932 return ret;
933
934 return 0;
935}
936
937static int __devexit wm0010_spi_remove(struct spi_device *spi)
938{
939 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
940
941 snd_soc_unregister_codec(&spi->dev);
942
5afe5bfe
MB		 943 gpio_set_value_cansleep(wm0010->gpio_reset,
944 wm0010->gpio_reset_value);
e3523e01
DP		 945
946 if (wm0010->irq)
947 free_irq(wm0010->irq, wm0010);
948
949 return 0;
950}
951
952static struct spi_driver wm0010_spi_driver = {
953 .driver = {
954 .name = "wm0010",
955 .bus = &spi_bus_type,
956 .owner = THIS_MODULE,
957 },
958 .probe = wm0010_spi_probe,
959 .remove = __devexit_p(wm0010_spi_remove),
960};
961
962module_spi_driver(wm0010_spi_driver);
963
964MODULE_DESCRIPTION("ASoC WM0010 driver");
965MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
966MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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