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ASoC: samsung: Add hookup of WM0010 on Speyside
[deliverable/linux.git] / sound / soc / codecs / wm0010.c
CommitLineData
e3523e01
DP		 1/*
2 * wm0010.c -- WM0010 DSP Driver
3 *
4 * Copyright 2012 Wolfson Microelectronics PLC.
5 *
6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * Scott Ling <sl@opensource.wolfsonmicro.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/irqreturn.h>
18#include <linux/init.h>
19#include <linux/spi/spi.h>
20#include <linux/firmware.h>
21#include <linux/delay.h>
22#include <linux/fs.h>
23#include <linux/miscdevice.h>
24#include <linux/gpio.h>
25#include <linux/regulator/consumer.h>
26#include <linux/mutex.h>
27#include <linux/workqueue.h>
28
29#include <sound/soc.h>
30#include <sound/wm0010.h>
31
32#define DEVICE_ID_WM0010 10
33
34enum dfw_cmd {
35 DFW_CMD_FUSE = 0x01,
36 DFW_CMD_CODE_HDR,
37 DFW_CMD_CODE_DATA,
38 DFW_CMD_PLL,
39 DFW_CMD_INFO = 0xff
40};
41
42struct dfw_binrec {
43 u8 command;
44 u32 length:24;
45 u32 address;
46 uint8_t data[0];
47} __packed;
48
49struct dfw_pllrec {
50 u8 command;
51 u32 length:24;
52 u32 address;
53 u32 clkctrl1;
54 u32 clkctrl2;
55 u32 clkctrl3;
56 u32 ldetctrl;
57 u32 uart_div;
58 u32 spi_div;
59} __packed;
60
61static struct pll_clock_map {
62 int max_sysclk;
63 int max_pll_spi_speed;
64 u32 pll_clkctrl1;
65} pll_clock_map[] = { /* Dividers */
66 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
67 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
68 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
69 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
70 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
71 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
72};
73
74enum wm0010_state {
75 WM0010_POWER_OFF,
76 WM0010_OUT_OF_RESET,
77 WM0010_BOOTROM,
78 WM0010_STAGE2,
79 WM0010_FIRMWARE,
80};
81
82struct wm0010_priv {
83 struct snd_soc_codec *codec;
84
85 struct mutex lock;
86 struct device *dev;
87
88 struct wm0010_pdata pdata;
89
90 int gpio_reset;
91 int gpio_reset_value;
92
93 struct regulator_bulk_data core_supplies[2];
94 struct regulator *dbvdd;
95
96 int sysclk;
97
98 enum wm0010_state state;
99 bool boot_failed;
100 int boot_done;
101 bool ready;
102 bool pll_running;
103 int max_spi_freq;
104 int board_max_spi_speed;
105 u32 pll_clkctrl1;
106
107 spinlock_t irq_lock;
108 int irq;
109
110 struct completion boot_completion;
111};
112
113struct wm0010_spi_msg {
114 struct spi_message m;
115 struct spi_transfer t;
116 u8 *tx_buf;
117 u8 *rx_buf;
118 size_t len;
119};
120
121static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
1549c34b
MB		 122 { "SDI2 Capture", NULL, "SDI1 Playback" },
123 { "SDI1 Capture", NULL, "SDI2 Playback" },
e3523e01
DP		 124};
125
126static const char *wm0010_state_to_str(enum wm0010_state state)
127{
128 const char *state_to_str[] = {
129 "Power off",
130 "Out of reset",
131 "Bootrom",
132 "Stage2",
133 "Firmware"
134 };
135
136 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
137 return "null";
138 return state_to_str[state];
139}
140
141/* Called with wm0010->lock held */
142static void wm0010_halt(struct snd_soc_codec *codec)
143{
144 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
145 unsigned long flags;
146 enum wm0010_state state;
147
148 /* Fetch the wm0010 state */
149 spin_lock_irqsave(&wm0010->irq_lock, flags);
150 state = wm0010->state;
151 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
152
153 switch (state) {
154 case WM0010_POWER_OFF:
155 /* If there's nothing to do, bail out */
156 return;
157 case WM0010_OUT_OF_RESET:
158 case WM0010_BOOTROM:
159 case WM0010_STAGE2:
160 case WM0010_FIRMWARE:
161 /* Remember to put chip back into reset */
162 gpio_set_value(wm0010->gpio_reset, wm0010->gpio_reset_value);
163 /* Disable the regulators */
164 regulator_disable(wm0010->dbvdd);
165 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
166 wm0010->core_supplies);
167 break;
168 }
169
170 spin_lock_irqsave(&wm0010->irq_lock, flags);
171 wm0010->state = WM0010_POWER_OFF;
172 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
173}
174
175struct wm0010_boot_xfer {
176 struct list_head list;
177 struct snd_soc_codec *codec;
178 struct completion *done;
179 struct spi_message m;
180 struct spi_transfer t;
181};
182
183/* Called with wm0010->lock held */
184static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
185{
186 enum wm0010_state state;
187 unsigned long flags;
188
189 spin_lock_irqsave(&wm0010->irq_lock, flags);
190 state = wm0010->state;
191 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
192
193 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
194 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
195
196 wm0010->boot_failed = true;
197}
198
199static void wm0010_boot_xfer_complete(void *data)
200{
201 struct wm0010_boot_xfer *xfer = data;
202 struct snd_soc_codec *codec = xfer->codec;
203 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
204 u32 *out32 = xfer->t.rx_buf;
205 int i;
206
207 if (xfer->m.status != 0) {
208 dev_err(codec->dev, "SPI transfer failed: %d\n",
209 xfer->m.status);
210 wm0010_mark_boot_failure(wm0010);
211 if (xfer->done)
212 complete(xfer->done);
213 return;
214 }
215
216 for (i = 0; i < xfer->t.len / 4; i++) {
217 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]);
218
219 switch (be32_to_cpu(out32[i])) {
220 case 0xe0e0e0e0:
221 dev_err(codec->dev,
222 "%d: ROM error reported in stage 2\n", i);
223 wm0010_mark_boot_failure(wm0010);
224 break;
225
226 case 0x55555555:
227 if (wm0010->boot_done == 0)
228 break;
229 dev_err(codec->dev,
230 "%d: ROM bootloader running in stage 2\n", i);
231 wm0010_mark_boot_failure(wm0010);
232 break;
233
234 case 0x0fed0000:
235 dev_dbg(codec->dev, "Stage2 loader running\n");
236 break;
237
238 case 0x0fed0007:
239 dev_dbg(codec->dev, "CODE_HDR packet received\n");
240 break;
241
242 case 0x0fed0008:
243 dev_dbg(codec->dev, "CODE_DATA packet received\n");
244 break;
245
246 case 0x0fed0009:
247 dev_dbg(codec->dev, "Download complete\n");
248 break;
249
250 case 0x0fed000c:
251 dev_dbg(codec->dev, "Application start\n");
252 break;
253
254 case 0x0fed000e:
255 dev_dbg(codec->dev, "PLL packet received\n");
256 wm0010->pll_running = true;
257 break;
258
259 case 0x0fed0025:
260 dev_err(codec->dev, "Device reports image too long\n");
261 wm0010_mark_boot_failure(wm0010);
262 break;
263
264 case 0x0fed002c:
265 dev_err(codec->dev, "Device reports bad SPI packet\n");
266 wm0010_mark_boot_failure(wm0010);
267 break;
268
269 case 0x0fed0031:
270 dev_err(codec->dev, "Device reports SPI read overflow\n");
271 wm0010_mark_boot_failure(wm0010);
272 break;
273
274 case 0x0fed0032:
275 dev_err(codec->dev, "Device reports SPI underclock\n");
276 wm0010_mark_boot_failure(wm0010);
277 break;
278
279 case 0x0fed0033:
280 dev_err(codec->dev, "Device reports bad header packet\n");
281 wm0010_mark_boot_failure(wm0010);
282 break;
283
284 case 0x0fed0034:
285 dev_err(codec->dev, "Device reports invalid packet type\n");
286 wm0010_mark_boot_failure(wm0010);
287 break;
288
289 case 0x0fed0035:
290 dev_err(codec->dev, "Device reports data before header error\n");
291 wm0010_mark_boot_failure(wm0010);
292 break;
293
294 case 0x0fed0038:
295 dev_err(codec->dev, "Device reports invalid PLL packet\n");
296 break;
297
298 case 0x0fed003a:
299 dev_err(codec->dev, "Device reports packet alignment error\n");
300 wm0010_mark_boot_failure(wm0010);
301 break;
302
303 default:
304 dev_err(codec->dev, "Unrecognised return 0x%x\n",
305 be32_to_cpu(out32[i]));
306 wm0010_mark_boot_failure(wm0010);
307 break;
308 }
309
310 if (wm0010->boot_failed)
311 break;
312 }
313
314 wm0010->boot_done++;
315 if (xfer->done)
316 complete(xfer->done);
317}
318
319static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
320{
321 int i;
322
323 for (i = 0; i < len / 8; i++)
324 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
325}
326
327static int wm0010_boot(struct snd_soc_codec *codec)
328{
329 struct spi_device *spi = to_spi_device(codec->dev);
330 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
331 unsigned long flags;
332 struct list_head xfer_list;
333 struct wm0010_boot_xfer *xfer;
334 int ret;
335 struct completion done;
336 const struct firmware *fw;
337 const struct dfw_binrec *rec;
338 struct spi_message m;
339 struct spi_transfer t;
340 struct dfw_pllrec pll_rec;
341 u32 *img, *p;
342 u64 *img_swap;
343 u8 *out;
344 u32 len, offset;
345 int i;
346
347 spin_lock_irqsave(&wm0010->irq_lock, flags);
348 if (wm0010->state != WM0010_POWER_OFF)
349 dev_warn(wm0010->dev, "DSP already powered up!\n");
350 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
351
352 if (wm0010->sysclk > 26000000) {
353 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n");
354 ret = -ECANCELED;
355 goto err;
356 }
357
358 INIT_LIST_HEAD(&xfer_list);
359
360 mutex_lock(&wm0010->lock);
361 wm0010->pll_running = false;
362
363 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
364
365 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
366 wm0010->core_supplies);
367 if (ret != 0) {
368 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
369 ret);
370 mutex_unlock(&wm0010->lock);
371 goto err;
372 }
373
374 ret = regulator_enable(wm0010->dbvdd);
375 if (ret != 0) {
376 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
377 goto err_core;
378 }
379
380 /* Release reset */
381 gpio_set_value(wm0010->gpio_reset, !wm0010->gpio_reset_value);
382 spin_lock_irqsave(&wm0010->irq_lock, flags);
383 wm0010->state = WM0010_OUT_OF_RESET;
384 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
385
386 /* First the bootloader */
387 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
388 if (ret != 0) {
389 dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
390 ret);
391 goto abort;
392 }
393
394 if (!wait_for_completion_timeout(&wm0010->boot_completion,
395 msecs_to_jiffies(10)))
396 dev_err(codec->dev, "Failed to get interrupt from DSP\n");
397
398 spin_lock_irqsave(&wm0010->irq_lock, flags);
399 wm0010->state = WM0010_BOOTROM;
400 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
401
402 dev_dbg(codec->dev, "Downloading %d byte stage 2 loader\n", fw->size);
403
404 /* Copy to local buffer first as vmalloc causes problems for dma */
405 img = kzalloc(fw->size, GFP_KERNEL);
406 if (!img) {
407 dev_err(codec->dev, "Failed to allocate image buffer\n");
408 goto abort;
409 }
410
411 out = kzalloc(fw->size, GFP_KERNEL);
412 if (!out) {
413 dev_err(codec->dev, "Failed to allocate output buffer\n");
414 goto abort;
415 }
416
417 memcpy(img, &fw->data[0], fw->size);
418
419 spi_message_init(&m);
420 memset(&t, 0, sizeof(t));
421 t.rx_buf = out;
422 t.tx_buf = img;
423 t.len = fw->size;
424 t.bits_per_word = 8;
425 t.speed_hz = wm0010->sysclk / 10;
426 spi_message_add_tail(&t, &m);
427
428 dev_dbg(codec->dev, "Starting initial download at %dHz\n",
429 t.speed_hz);
430
431 ret = spi_sync(spi, &m);
432 if (ret != 0) {
433 dev_err(codec->dev, "Initial download failed: %d\n", ret);
434 goto abort;
435 }
436
437 /* Look for errors from the boot ROM */
438 for (i = 0; i < fw->size; i++) {
439 if (out[i] != 0x55) {
440 ret = -EBUSY;
441 dev_err(codec->dev, "Boot ROM error: %x in %d\n",
442 out[i], i);
443 wm0010_mark_boot_failure(wm0010);
444 goto abort;
445 }
446 }
447
448 release_firmware(fw);
449 kfree(img);
450 kfree(out);
451
452 if (!wait_for_completion_timeout(&wm0010->boot_completion,
453 msecs_to_jiffies(10)))
454 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n");
455
456 spin_lock_irqsave(&wm0010->irq_lock, flags);
457 wm0010->state = WM0010_STAGE2;
458 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
459
460 /* Only initialise PLL if max_spi_freq initialised */
461 if (wm0010->max_spi_freq) {
462
463 /* Initialise a PLL record */
464 memset(&pll_rec, 0, sizeof(pll_rec));
465 pll_rec.command = DFW_CMD_PLL;
466 pll_rec.length = (sizeof(pll_rec) - 8);
467
468 /* On wm0010 only the CLKCTRL1 value is used */
469 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
470
471 len = pll_rec.length + 8;
472 out = kzalloc(len, GFP_KERNEL);
473 if (!out) {
474 dev_err(codec->dev,
475 "Failed to allocate RX buffer\n");
476 goto abort;
477 }
478
479 img_swap = kzalloc(len, GFP_KERNEL);
480 if (!img_swap) {
481 dev_err(codec->dev,
482 "Failed to allocate image buffer\n");
483 goto abort;
484 }
485
486 /* We need to re-order for 0010 */
487 byte_swap_64((u64 *)&pll_rec, img_swap, len);
488
489 spi_message_init(&m);
490 memset(&t, 0, sizeof(t));
491 t.rx_buf = out;
492 t.tx_buf = img_swap;
493 t.len = len;
494 t.bits_per_word = 8;
495 t.speed_hz = wm0010->sysclk / 6;
496 spi_message_add_tail(&t, &m);
497
498 ret = spi_sync(spi, &m);
499 if (ret != 0) {
500 dev_err(codec->dev, "First PLL write failed: %d\n", ret);
501 goto abort;
502 }
503
504 /* Use a second send of the message to get the return status */
505 ret = spi_sync(spi, &m);
506 if (ret != 0) {
507 dev_err(codec->dev, "Second PLL write failed: %d\n", ret);
508 goto abort;
509 }
510
511 p = (u32 *)out;
512
513 /* Look for PLL active code from the DSP */
514 for (i = 0; i < len / 4; i++) {
515 if (*p == 0x0e00ed0f) {
516 dev_dbg(codec->dev, "PLL packet received\n");
517 wm0010->pll_running = true;
518 break;
519 }
520 p++;
521 }
522
523 kfree(img_swap);
524 kfree(out);
525 } else
526 dev_dbg(codec->dev, "Not enabling DSP PLL.");
527
528 ret = request_firmware(&fw, "wm0010.dfw", codec->dev);
529 if (ret != 0) {
530 dev_err(codec->dev, "Failed to request application: %d\n",
531 ret);
532 goto abort;
533 }
534
535 rec = (const struct dfw_binrec *)fw->data;
536 offset = 0;
537 wm0010->boot_done = 0;
538 wm0010->boot_failed = false;
539 BUG_ON(!list_empty(&xfer_list));
540 init_completion(&done);
541
542 /* First record should be INFO */
543 if (rec->command != DFW_CMD_INFO) {
544 dev_err(codec->dev, "First record not INFO\r\n");
545 goto abort;
546 }
547
548 /* Check it's a 0010 file */
549 if (rec->data[0] != DEVICE_ID_WM0010) {
550 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n");
551 goto abort;
552 }
553
554 /* Skip the info record as we don't need to send it */
555 offset += ((rec->length) + 8);
556 rec = (void *)&rec->data[rec->length];
557
558 while (offset < fw->size) {
559 dev_dbg(codec->dev,
560 "Packet: command %d, data length = 0x%x\r\n",
561 rec->command, rec->length);
562 len = rec->length + 8;
563
564 out = kzalloc(len, GFP_KERNEL);
565 if (!out) {
566 dev_err(codec->dev,
567 "Failed to allocate RX buffer\n");
568 goto abort;
569 }
570
571 img_swap = kzalloc(len, GFP_KERNEL);
572 if (!img_swap) {
573 dev_err(codec->dev,
574 "Failed to allocate image buffer\n");
575 goto abort;
576 }
577
578 /* We need to re-order for 0010 */
579 byte_swap_64((u64 *)&rec->command, img_swap, len);
580
581 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
582 if (!xfer) {
583 dev_err(codec->dev, "Failed to allocate xfer\n");
584 goto abort;
585 }
586
587 xfer->codec = codec;
588 list_add_tail(&xfer->list, &xfer_list);
589
590 spi_message_init(&xfer->m);
591 xfer->m.complete = wm0010_boot_xfer_complete;
592 xfer->m.context = xfer;
593 xfer->t.tx_buf = img_swap;
594 xfer->t.rx_buf = out;
595 xfer->t.len = len;
596 xfer->t.bits_per_word = 8;
597
598 if (!wm0010->pll_running) {
599 xfer->t.speed_hz = wm0010->sysclk / 6;
600 } else {
601 xfer->t.speed_hz = wm0010->max_spi_freq;
602
603 if (wm0010->board_max_spi_speed &&
604 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
605 xfer->t.speed_hz = wm0010->board_max_spi_speed;
606 }
607
608 /* Store max usable spi frequency for later use */
609 wm0010->max_spi_freq = xfer->t.speed_hz;
610
611 spi_message_add_tail(&xfer->t, &xfer->m);
612
613 offset += ((rec->length) + 8);
614 rec = (void *)&rec->data[rec->length];
615
616 if (offset >= fw->size) {
617 dev_dbg(codec->dev, "All transfers scheduled\n");
618 xfer->done = &done;
619 }
620
621 ret = spi_async(spi, &xfer->m);
622 if (ret != 0) {
623 dev_err(codec->dev, "Write failed: %d\n", ret);
624 goto abort;
625 }
626
627 if (wm0010->boot_failed)
628 goto abort;
629 }
630
631 wait_for_completion(&done);
632
633 spin_lock_irqsave(&wm0010->irq_lock, flags);
634 wm0010->state = WM0010_FIRMWARE;
635 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
636
637 mutex_unlock(&wm0010->lock);
638
639 release_firmware(fw);
640
641 while (!list_empty(&xfer_list)) {
642 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
643 list);
644 kfree(xfer->t.rx_buf);
645 kfree(xfer->t.tx_buf);
646 list_del(&xfer->list);
647 kfree(xfer);
648 }
649
650 return 0;
651
652abort:
653 /* Put the chip back into reset */
654 wm0010_halt(codec);
655 mutex_unlock(&wm0010->lock);
656 return ret;
657err_core:
658 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
659 wm0010->core_supplies);
660err:
661 return ret;
662}
663
664static int wm0010_set_bias_level(struct snd_soc_codec *codec,
665 enum snd_soc_bias_level level)
666{
667 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
668
669 switch (level) {
670 case SND_SOC_BIAS_ON:
671 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
672 wm0010_boot(codec);
673 break;
674 case SND_SOC_BIAS_PREPARE:
675 break;
676 case SND_SOC_BIAS_STANDBY:
677 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
678 mutex_lock(&wm0010->lock);
679 wm0010_halt(codec);
680 mutex_unlock(&wm0010->lock);
681 }
682 break;
683 case SND_SOC_BIAS_OFF:
684 break;
685 }
686
687 codec->dapm.bias_level = level;
688
689 return 0;
690}
691
692static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source,
693 int clk_id, unsigned int freq, int dir)
694{
695 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
696 unsigned int i;
697
698 wm0010->sysclk = freq;
699
700 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
701 wm0010->max_spi_freq = 0;
702 } else {
703 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
704 if (freq >= pll_clock_map[i].max_sysclk)
705 break;
706
707 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
708 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
709 }
710
711 return 0;
712}
713
714static int wm0010_probe(struct snd_soc_codec *codec);
715
716static struct snd_soc_codec_driver soc_codec_dev_wm0010 = {
717 .probe = wm0010_probe,
718 .set_bias_level = wm0010_set_bias_level,
719 .set_sysclk = wm0010_set_sysclk,
720
721 .dapm_routes = wm0010_dapm_routes,
722 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
723};
724
725#define WM0010_RATES (SNDRV_PCM_RATE_48000)
726#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
727 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
728 SNDRV_PCM_FMTBIT_S32_LE)
729
730static struct snd_soc_dai_driver wm0010_dai[] = {
731 {
732 .name = "wm0010-sdi1",
733 .playback = {
734 .stream_name = "SDI1 Playback",
735 .channels_min = 1,
736 .channels_max = 2,
737 .rates = WM0010_RATES,
738 .formats = WM0010_FORMATS,
739 },
740 .capture = {
741 .stream_name = "SDI1 Capture",
742 .channels_min = 1,
743 .channels_max = 2,
744 .rates = WM0010_RATES,
745 .formats = WM0010_FORMATS,
746 },
747 },
748 {
749 .name = "wm0010-sdi2",
750 .playback = {
751 .stream_name = "SDI2 Playback",
752 .channels_min = 1,
753 .channels_max = 2,
754 .rates = WM0010_RATES,
755 .formats = WM0010_FORMATS,
756 },
757 .capture = {
758 .stream_name = "SDI2 Capture",
759 .channels_min = 1,
760 .channels_max = 2,
761 .rates = WM0010_RATES,
762 .formats = WM0010_FORMATS,
763 },
764 },
765};
766
767static irqreturn_t wm0010_irq(int irq, void *data)
768{
769 struct wm0010_priv *wm0010 = data;
770
771 switch (wm0010->state) {
772 case WM0010_POWER_OFF:
773 case WM0010_OUT_OF_RESET:
774 case WM0010_BOOTROM:
775 case WM0010_STAGE2:
776 spin_lock(&wm0010->irq_lock);
777 complete(&wm0010->boot_completion);
778 spin_unlock(&wm0010->irq_lock);
779 return IRQ_HANDLED;
780 default:
781 return IRQ_NONE;
782 }
783
784 return IRQ_NONE;
785}
786
787static int wm0010_probe(struct snd_soc_codec *codec)
788{
789 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
790 struct spi_device *spi = to_spi_device(wm0010->dev);
791 unsigned long flags;
792 unsigned long gpio_flags;
793 int ret;
794 int trigger;
795 int irq;
796
797 wm0010->codec = codec;
798
799 init_completion(&wm0010->boot_completion);
800
801 wm0010->core_supplies[0].supply = "AVDD";
802 wm0010->core_supplies[1].supply = "DCVDD";
803 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
804 wm0010->core_supplies);
805 if (ret != 0) {
806 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
807 ret);
808 return ret;
809 }
810
811 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
812 if (IS_ERR(wm0010->dbvdd)) {
813 ret = PTR_ERR(wm0010->dbvdd);
814 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
815 return ret;
816 }
817
818 if (wm0010->pdata.gpio_reset) {
819 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
820
821 if (wm0010->pdata.reset_active_high)
822 wm0010->gpio_reset_value = 1;
823 else
824 wm0010->gpio_reset_value = 0;
825
826 if (wm0010->gpio_reset_value)
827 gpio_flags = GPIOF_OUT_INIT_HIGH;
828 else
829 gpio_flags = GPIOF_OUT_INIT_LOW;
830
831 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
832 gpio_flags, "wm0010 reset");
833 if (ret < 0) {
834 dev_err(wm0010->dev,
835 "Failed to request GPIO for DSP reset: %d\n",
836 ret);
837 return ret;
838 }
839 } else {
840 dev_err(wm0010->dev, "No reset GPIO configured\n");
841 return ret;
842 }
843
844 irq = spi->irq;
845 if (wm0010->pdata.irq_flags)
846 trigger = wm0010->pdata.irq_flags;
847 else
848 trigger = IRQF_TRIGGER_FALLING;
849 trigger |= IRQF_ONESHOT;
850
851 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger,
852 "wm0010", wm0010);
853 if (ret)
854 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
855 irq, ret);
856 wm0010->irq = irq;
857
858 if (spi->max_speed_hz)
859 wm0010->board_max_spi_speed = spi->max_speed_hz;
860 else
861 wm0010->board_max_spi_speed = 0;
862
863 spin_lock_irqsave(&wm0010->irq_lock, flags);
864 wm0010->state = WM0010_POWER_OFF;
865 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
866
867 return 0;
868}
869
870static int __devinit wm0010_spi_probe(struct spi_device *spi)
871{
872 struct wm0010_priv *wm0010;
873 int ret;
874
875 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
876 GFP_KERNEL);
877 if (!wm0010)
878 return -ENOMEM;
879
880 mutex_init(&wm0010->lock);
881 spin_lock_init(&wm0010->irq_lock);
882
883 spi_set_drvdata(spi, wm0010);
884 wm0010->dev = &spi->dev;
885
886 if (dev_get_platdata(&spi->dev))
887 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
888 sizeof(wm0010->pdata));
889
890 ret = snd_soc_register_codec(&spi->dev,
891 &soc_codec_dev_wm0010, wm0010_dai,
892 ARRAY_SIZE(wm0010_dai));
893 if (ret < 0)
894 return ret;
895
896 return 0;
897}
898
899static int __devexit wm0010_spi_remove(struct spi_device *spi)
900{
901 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
902
903 snd_soc_unregister_codec(&spi->dev);
904
905 if (wm0010->gpio_reset) {
906 /* Remember to put chip back into reset */
907 gpio_set_value(wm0010->gpio_reset, wm0010->gpio_reset_value);
908 gpio_free(wm0010->gpio_reset);
909 }
910
911 if (wm0010->irq)
912 free_irq(wm0010->irq, wm0010);
913
914 return 0;
915}
916
917static struct spi_driver wm0010_spi_driver = {
918 .driver = {
919 .name = "wm0010",
920 .bus = &spi_bus_type,
921 .owner = THIS_MODULE,
922 },
923 .probe = wm0010_spi_probe,
924 .remove = __devexit_p(wm0010_spi_remove),
925};
926
927module_spi_driver(wm0010_spi_driver);
928
929MODULE_DESCRIPTION("ASoC WM0010 driver");
930MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
931MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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