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ASoC: wm0010: Remove boot_done variable as no longer required.
[deliverable/linux.git] / sound / soc / codecs / wm0010.c
CommitLineData
e3523e01
DP		 1/*
2 * wm0010.c -- WM0010 DSP Driver
3 *
4 * Copyright 2012 Wolfson Microelectronics PLC.
5 *
6 * Authors: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 * Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
8 * Scott Ling <sl@opensource.wolfsonmicro.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/irqreturn.h>
18#include <linux/init.h>
19#include <linux/spi/spi.h>
20#include <linux/firmware.h>
21#include <linux/delay.h>
22#include <linux/fs.h>
23#include <linux/miscdevice.h>
24#include <linux/gpio.h>
25#include <linux/regulator/consumer.h>
26#include <linux/mutex.h>
27#include <linux/workqueue.h>
28
29#include <sound/soc.h>
30#include <sound/wm0010.h>
31
32#define DEVICE_ID_WM0010 10
33
34enum dfw_cmd {
35 DFW_CMD_FUSE = 0x01,
36 DFW_CMD_CODE_HDR,
37 DFW_CMD_CODE_DATA,
38 DFW_CMD_PLL,
39 DFW_CMD_INFO = 0xff
40};
41
42struct dfw_binrec {
43 u8 command;
44 u32 length:24;
45 u32 address;
46 uint8_t data[0];
47} __packed;
48
49struct dfw_pllrec {
50 u8 command;
51 u32 length:24;
52 u32 address;
53 u32 clkctrl1;
54 u32 clkctrl2;
55 u32 clkctrl3;
56 u32 ldetctrl;
57 u32 uart_div;
58 u32 spi_div;
59} __packed;
60
61static struct pll_clock_map {
62 int max_sysclk;
63 int max_pll_spi_speed;
64 u32 pll_clkctrl1;
65} pll_clock_map[] = { /* Dividers */
66 { 22000000, 26000000, 0x00201f11 }, /* 2,32,2 */
67 { 18000000, 26000000, 0x00203f21 }, /* 2,64,4 */
68 { 14000000, 26000000, 0x00202620 }, /* 1,39,4 */
69 { 10000000, 22000000, 0x00203120 }, /* 1,50,4 */
70 { 6500000, 22000000, 0x00204520 }, /* 1,70,4 */
71 { 5500000, 22000000, 0x00103f10 }, /* 1,64,2 */
72};
73
74enum wm0010_state {
75 WM0010_POWER_OFF,
76 WM0010_OUT_OF_RESET,
77 WM0010_BOOTROM,
78 WM0010_STAGE2,
79 WM0010_FIRMWARE,
80};
81
82struct wm0010_priv {
83 struct snd_soc_codec *codec;
84
85 struct mutex lock;
86 struct device *dev;
87
88 struct wm0010_pdata pdata;
89
90 int gpio_reset;
91 int gpio_reset_value;
92
93 struct regulator_bulk_data core_supplies[2];
94 struct regulator *dbvdd;
95
96 int sysclk;
97
98 enum wm0010_state state;
99 bool boot_failed;
e3523e01
DP		 100 bool ready;
101 bool pll_running;
102 int max_spi_freq;
103 int board_max_spi_speed;
104 u32 pll_clkctrl1;
105
106 spinlock_t irq_lock;
107 int irq;
108
109 struct completion boot_completion;
110};
111
112struct wm0010_spi_msg {
113 struct spi_message m;
114 struct spi_transfer t;
115 u8 *tx_buf;
116 u8 *rx_buf;
117 size_t len;
118};
119
1470bfac
MB		 120static const struct snd_soc_dapm_widget wm0010_dapm_widgets[] = {
121SND_SOC_DAPM_SUPPLY("CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
122};
123
e3523e01 124static const struct snd_soc_dapm_route wm0010_dapm_routes[] = {
1549c34b
MB		 125 { "SDI2 Capture", NULL, "SDI1 Playback" },
126 { "SDI1 Capture", NULL, "SDI2 Playback" },
1470bfac
MB		 127
128 { "SDI1 Capture", NULL, "CLKIN" },
129 { "SDI2 Capture", NULL, "CLKIN" },
130 { "SDI1 Playback", NULL, "CLKIN" },
131 { "SDI2 Playback", NULL, "CLKIN" },
e3523e01
DP		 132};
133
134static const char *wm0010_state_to_str(enum wm0010_state state)
135{
136 const char *state_to_str[] = {
137 "Power off",
138 "Out of reset",
bf9d3237 139 "Boot ROM",
e3523e01
DP		 140 "Stage2",
141 "Firmware"
142 };
143
144 if (state < 0 || state >= ARRAY_SIZE(state_to_str))
145 return "null";
146 return state_to_str[state];
147}
148
149/* Called with wm0010->lock held */
150static void wm0010_halt(struct snd_soc_codec *codec)
151{
152 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
153 unsigned long flags;
154 enum wm0010_state state;
155
156 /* Fetch the wm0010 state */
157 spin_lock_irqsave(&wm0010->irq_lock, flags);
158 state = wm0010->state;
159 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
160
161 switch (state) {
162 case WM0010_POWER_OFF:
163 /* If there's nothing to do, bail out */
164 return;
165 case WM0010_OUT_OF_RESET:
166 case WM0010_BOOTROM:
167 case WM0010_STAGE2:
168 case WM0010_FIRMWARE:
169 /* Remember to put chip back into reset */
fff00cbc
MB		 170 gpio_set_value_cansleep(wm0010->gpio_reset,
171 wm0010->gpio_reset_value);
e3523e01
DP		 172 /* Disable the regulators */
173 regulator_disable(wm0010->dbvdd);
174 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
175 wm0010->core_supplies);
176 break;
177 }
178
179 spin_lock_irqsave(&wm0010->irq_lock, flags);
180 wm0010->state = WM0010_POWER_OFF;
181 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
182}
183
184struct wm0010_boot_xfer {
185 struct list_head list;
186 struct snd_soc_codec *codec;
187 struct completion *done;
188 struct spi_message m;
189 struct spi_transfer t;
190};
191
192/* Called with wm0010->lock held */
193static void wm0010_mark_boot_failure(struct wm0010_priv *wm0010)
194{
195 enum wm0010_state state;
196 unsigned long flags;
197
198 spin_lock_irqsave(&wm0010->irq_lock, flags);
199 state = wm0010->state;
200 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
201
202 dev_err(wm0010->dev, "Failed to transition from `%s' state to `%s' state\n",
203 wm0010_state_to_str(state), wm0010_state_to_str(state + 1));
204
205 wm0010->boot_failed = true;
206}
207
208static void wm0010_boot_xfer_complete(void *data)
209{
210 struct wm0010_boot_xfer *xfer = data;
211 struct snd_soc_codec *codec = xfer->codec;
212 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
213 u32 *out32 = xfer->t.rx_buf;
214 int i;
215
216 if (xfer->m.status != 0) {
217 dev_err(codec->dev, "SPI transfer failed: %d\n",
218 xfer->m.status);
219 wm0010_mark_boot_failure(wm0010);
220 if (xfer->done)
221 complete(xfer->done);
222 return;
223 }
224
225 for (i = 0; i < xfer->t.len / 4; i++) {
226 dev_dbg(codec->dev, "%d: %04x\n", i, out32[i]);
227
228 switch (be32_to_cpu(out32[i])) {
229 case 0xe0e0e0e0:
230 dev_err(codec->dev,
231 "%d: ROM error reported in stage 2\n", i);
232 wm0010_mark_boot_failure(wm0010);
233 break;
234
235 case 0x55555555:
f9baa0cc 236 if (wm0010->state < WM0010_STAGE2)
e3523e01
DP		 237 break;
238 dev_err(codec->dev,
239 "%d: ROM bootloader running in stage 2\n", i);
240 wm0010_mark_boot_failure(wm0010);
241 break;
242
243 case 0x0fed0000:
244 dev_dbg(codec->dev, "Stage2 loader running\n");
245 break;
246
247 case 0x0fed0007:
248 dev_dbg(codec->dev, "CODE_HDR packet received\n");
249 break;
250
251 case 0x0fed0008:
252 dev_dbg(codec->dev, "CODE_DATA packet received\n");
253 break;
254
255 case 0x0fed0009:
256 dev_dbg(codec->dev, "Download complete\n");
257 break;
258
259 case 0x0fed000c:
260 dev_dbg(codec->dev, "Application start\n");
261 break;
262
263 case 0x0fed000e:
264 dev_dbg(codec->dev, "PLL packet received\n");
265 wm0010->pll_running = true;
266 break;
267
268 case 0x0fed0025:
269 dev_err(codec->dev, "Device reports image too long\n");
270 wm0010_mark_boot_failure(wm0010);
271 break;
272
273 case 0x0fed002c:
274 dev_err(codec->dev, "Device reports bad SPI packet\n");
275 wm0010_mark_boot_failure(wm0010);
276 break;
277
278 case 0x0fed0031:
279 dev_err(codec->dev, "Device reports SPI read overflow\n");
280 wm0010_mark_boot_failure(wm0010);
281 break;
282
283 case 0x0fed0032:
284 dev_err(codec->dev, "Device reports SPI underclock\n");
285 wm0010_mark_boot_failure(wm0010);
286 break;
287
288 case 0x0fed0033:
289 dev_err(codec->dev, "Device reports bad header packet\n");
290 wm0010_mark_boot_failure(wm0010);
291 break;
292
293 case 0x0fed0034:
294 dev_err(codec->dev, "Device reports invalid packet type\n");
295 wm0010_mark_boot_failure(wm0010);
296 break;
297
298 case 0x0fed0035:
299 dev_err(codec->dev, "Device reports data before header error\n");
300 wm0010_mark_boot_failure(wm0010);
301 break;
302
303 case 0x0fed0038:
304 dev_err(codec->dev, "Device reports invalid PLL packet\n");
305 break;
306
307 case 0x0fed003a:
308 dev_err(codec->dev, "Device reports packet alignment error\n");
309 wm0010_mark_boot_failure(wm0010);
310 break;
311
312 default:
313 dev_err(codec->dev, "Unrecognised return 0x%x\n",
314 be32_to_cpu(out32[i]));
315 wm0010_mark_boot_failure(wm0010);
316 break;
317 }
318
319 if (wm0010->boot_failed)
320 break;
321 }
322
e3523e01
DP		 323 if (xfer->done)
324 complete(xfer->done);
325}
326
327static void byte_swap_64(u64 *data_in, u64 *data_out, u32 len)
328{
329 int i;
330
331 for (i = 0; i < len / 8; i++)
332 data_out[i] = cpu_to_be64(le64_to_cpu(data_in[i]));
333}
334
335static int wm0010_boot(struct snd_soc_codec *codec)
336{
337 struct spi_device *spi = to_spi_device(codec->dev);
338 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
339 unsigned long flags;
340 struct list_head xfer_list;
341 struct wm0010_boot_xfer *xfer;
342 int ret;
343 struct completion done;
344 const struct firmware *fw;
345 const struct dfw_binrec *rec;
346 struct spi_message m;
347 struct spi_transfer t;
348 struct dfw_pllrec pll_rec;
349 u32 *img, *p;
350 u64 *img_swap;
351 u8 *out;
352 u32 len, offset;
353 int i;
354
355 spin_lock_irqsave(&wm0010->irq_lock, flags);
356 if (wm0010->state != WM0010_POWER_OFF)
357 dev_warn(wm0010->dev, "DSP already powered up!\n");
358 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
359
360 if (wm0010->sysclk > 26000000) {
361 dev_err(codec->dev, "Max DSP clock frequency is 26MHz\n");
362 ret = -ECANCELED;
363 goto err;
364 }
365
366 INIT_LIST_HEAD(&xfer_list);
367
368 mutex_lock(&wm0010->lock);
369 wm0010->pll_running = false;
370
371 dev_dbg(codec->dev, "max_spi_freq: %d\n", wm0010->max_spi_freq);
372
373 ret = regulator_bulk_enable(ARRAY_SIZE(wm0010->core_supplies),
374 wm0010->core_supplies);
375 if (ret != 0) {
376 dev_err(&spi->dev, "Failed to enable core supplies: %d\n",
377 ret);
378 mutex_unlock(&wm0010->lock);
379 goto err;
380 }
381
382 ret = regulator_enable(wm0010->dbvdd);
383 if (ret != 0) {
384 dev_err(&spi->dev, "Failed to enable DBVDD: %d\n", ret);
385 goto err_core;
386 }
387
388 /* Release reset */
fff00cbc 389 gpio_set_value_cansleep(wm0010->gpio_reset, !wm0010->gpio_reset_value);
e3523e01
DP		 390 spin_lock_irqsave(&wm0010->irq_lock, flags);
391 wm0010->state = WM0010_OUT_OF_RESET;
392 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
393
394 /* First the bootloader */
395 ret = request_firmware(&fw, "wm0010_stage2.bin", codec->dev);
396 if (ret != 0) {
397 dev_err(codec->dev, "Failed to request stage2 loader: %d\n",
398 ret);
399 goto abort;
400 }
401
402 if (!wait_for_completion_timeout(&wm0010->boot_completion,
403 msecs_to_jiffies(10)))
404 dev_err(codec->dev, "Failed to get interrupt from DSP\n");
405
406 spin_lock_irqsave(&wm0010->irq_lock, flags);
407 wm0010->state = WM0010_BOOTROM;
408 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
409
5d86e25c 410 dev_dbg(codec->dev, "Downloading %zu byte stage 2 loader\n", fw->size);
e3523e01
DP		 411
412 /* Copy to local buffer first as vmalloc causes problems for dma */
413 img = kzalloc(fw->size, GFP_KERNEL);
414 if (!img) {
415 dev_err(codec->dev, "Failed to allocate image buffer\n");
416 goto abort;
417 }
418
419 out = kzalloc(fw->size, GFP_KERNEL);
420 if (!out) {
421 dev_err(codec->dev, "Failed to allocate output buffer\n");
422 goto abort;
423 }
424
425 memcpy(img, &fw->data[0], fw->size);
426
427 spi_message_init(&m);
428 memset(&t, 0, sizeof(t));
429 t.rx_buf = out;
430 t.tx_buf = img;
431 t.len = fw->size;
432 t.bits_per_word = 8;
433 t.speed_hz = wm0010->sysclk / 10;
434 spi_message_add_tail(&t, &m);
435
436 dev_dbg(codec->dev, "Starting initial download at %dHz\n",
437 t.speed_hz);
438
439 ret = spi_sync(spi, &m);
440 if (ret != 0) {
441 dev_err(codec->dev, "Initial download failed: %d\n", ret);
442 goto abort;
443 }
444
445 /* Look for errors from the boot ROM */
446 for (i = 0; i < fw->size; i++) {
447 if (out[i] != 0x55) {
448 ret = -EBUSY;
449 dev_err(codec->dev, "Boot ROM error: %x in %d\n",
450 out[i], i);
451 wm0010_mark_boot_failure(wm0010);
452 goto abort;
453 }
454 }
455
456 release_firmware(fw);
457 kfree(img);
458 kfree(out);
459
460 if (!wait_for_completion_timeout(&wm0010->boot_completion,
461 msecs_to_jiffies(10)))
462 dev_err(codec->dev, "Failed to get interrupt from DSP loader.\n");
463
464 spin_lock_irqsave(&wm0010->irq_lock, flags);
465 wm0010->state = WM0010_STAGE2;
466 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
467
468 /* Only initialise PLL if max_spi_freq initialised */
469 if (wm0010->max_spi_freq) {
470
471 /* Initialise a PLL record */
472 memset(&pll_rec, 0, sizeof(pll_rec));
473 pll_rec.command = DFW_CMD_PLL;
474 pll_rec.length = (sizeof(pll_rec) - 8);
475
476 /* On wm0010 only the CLKCTRL1 value is used */
477 pll_rec.clkctrl1 = wm0010->pll_clkctrl1;
478
479 len = pll_rec.length + 8;
480 out = kzalloc(len, GFP_KERNEL);
481 if (!out) {
482 dev_err(codec->dev,
483 "Failed to allocate RX buffer\n");
484 goto abort;
485 }
486
487 img_swap = kzalloc(len, GFP_KERNEL);
488 if (!img_swap) {
489 dev_err(codec->dev,
490 "Failed to allocate image buffer\n");
491 goto abort;
492 }
493
494 /* We need to re-order for 0010 */
495 byte_swap_64((u64 *)&pll_rec, img_swap, len);
496
497 spi_message_init(&m);
498 memset(&t, 0, sizeof(t));
499 t.rx_buf = out;
500 t.tx_buf = img_swap;
501 t.len = len;
502 t.bits_per_word = 8;
503 t.speed_hz = wm0010->sysclk / 6;
504 spi_message_add_tail(&t, &m);
505
506 ret = spi_sync(spi, &m);
507 if (ret != 0) {
508 dev_err(codec->dev, "First PLL write failed: %d\n", ret);
509 goto abort;
510 }
511
512 /* Use a second send of the message to get the return status */
513 ret = spi_sync(spi, &m);
514 if (ret != 0) {
515 dev_err(codec->dev, "Second PLL write failed: %d\n", ret);
516 goto abort;
517 }
518
519 p = (u32 *)out;
520
521 /* Look for PLL active code from the DSP */
522 for (i = 0; i < len / 4; i++) {
523 if (*p == 0x0e00ed0f) {
524 dev_dbg(codec->dev, "PLL packet received\n");
525 wm0010->pll_running = true;
526 break;
527 }
528 p++;
529 }
530
531 kfree(img_swap);
532 kfree(out);
533 } else
534 dev_dbg(codec->dev, "Not enabling DSP PLL.");
535
536 ret = request_firmware(&fw, "wm0010.dfw", codec->dev);
537 if (ret != 0) {
538 dev_err(codec->dev, "Failed to request application: %d\n",
539 ret);
540 goto abort;
541 }
542
543 rec = (const struct dfw_binrec *)fw->data;
544 offset = 0;
e3523e01
DP		 545 wm0010->boot_failed = false;
546 BUG_ON(!list_empty(&xfer_list));
547 init_completion(&done);
548
549 /* First record should be INFO */
550 if (rec->command != DFW_CMD_INFO) {
551 dev_err(codec->dev, "First record not INFO\r\n");
552 goto abort;
553 }
554
555 /* Check it's a 0010 file */
556 if (rec->data[0] != DEVICE_ID_WM0010) {
557 dev_err(codec->dev, "Not a WM0010 firmware file.\r\n");
558 goto abort;
559 }
560
561 /* Skip the info record as we don't need to send it */
562 offset += ((rec->length) + 8);
563 rec = (void *)&rec->data[rec->length];
564
565 while (offset < fw->size) {
566 dev_dbg(codec->dev,
567 "Packet: command %d, data length = 0x%x\r\n",
568 rec->command, rec->length);
569 len = rec->length + 8;
570
571 out = kzalloc(len, GFP_KERNEL);
572 if (!out) {
573 dev_err(codec->dev,
574 "Failed to allocate RX buffer\n");
575 goto abort;
576 }
577
578 img_swap = kzalloc(len, GFP_KERNEL);
579 if (!img_swap) {
580 dev_err(codec->dev,
581 "Failed to allocate image buffer\n");
582 goto abort;
583 }
584
585 /* We need to re-order for 0010 */
586 byte_swap_64((u64 *)&rec->command, img_swap, len);
587
588 xfer = kzalloc(sizeof(*xfer), GFP_KERNEL);
589 if (!xfer) {
590 dev_err(codec->dev, "Failed to allocate xfer\n");
591 goto abort;
592 }
593
594 xfer->codec = codec;
595 list_add_tail(&xfer->list, &xfer_list);
596
597 spi_message_init(&xfer->m);
598 xfer->m.complete = wm0010_boot_xfer_complete;
599 xfer->m.context = xfer;
600 xfer->t.tx_buf = img_swap;
601 xfer->t.rx_buf = out;
602 xfer->t.len = len;
603 xfer->t.bits_per_word = 8;
604
605 if (!wm0010->pll_running) {
606 xfer->t.speed_hz = wm0010->sysclk / 6;
607 } else {
608 xfer->t.speed_hz = wm0010->max_spi_freq;
609
610 if (wm0010->board_max_spi_speed &&
611 (wm0010->board_max_spi_speed < wm0010->max_spi_freq))
612 xfer->t.speed_hz = wm0010->board_max_spi_speed;
613 }
614
615 /* Store max usable spi frequency for later use */
616 wm0010->max_spi_freq = xfer->t.speed_hz;
617
618 spi_message_add_tail(&xfer->t, &xfer->m);
619
620 offset += ((rec->length) + 8);
621 rec = (void *)&rec->data[rec->length];
622
623 if (offset >= fw->size) {
624 dev_dbg(codec->dev, "All transfers scheduled\n");
625 xfer->done = &done;
626 }
627
628 ret = spi_async(spi, &xfer->m);
629 if (ret != 0) {
630 dev_err(codec->dev, "Write failed: %d\n", ret);
631 goto abort;
632 }
633
634 if (wm0010->boot_failed)
635 goto abort;
636 }
637
638 wait_for_completion(&done);
639
640 spin_lock_irqsave(&wm0010->irq_lock, flags);
641 wm0010->state = WM0010_FIRMWARE;
642 spin_unlock_irqrestore(&wm0010->irq_lock, flags);
643
644 mutex_unlock(&wm0010->lock);
645
646 release_firmware(fw);
647
648 while (!list_empty(&xfer_list)) {
649 xfer = list_first_entry(&xfer_list, struct wm0010_boot_xfer,
650 list);
651 kfree(xfer->t.rx_buf);
652 kfree(xfer->t.tx_buf);
653 list_del(&xfer->list);
654 kfree(xfer);
655 }
656
657 return 0;
658
659abort:
660 /* Put the chip back into reset */
661 wm0010_halt(codec);
662 mutex_unlock(&wm0010->lock);
663 return ret;
4f3ad795 664
e3523e01 665err_core:
4f3ad795 666 mutex_unlock(&wm0010->lock);
e3523e01
DP		 667 regulator_bulk_disable(ARRAY_SIZE(wm0010->core_supplies),
668 wm0010->core_supplies);
669err:
670 return ret;
671}
672
673static int wm0010_set_bias_level(struct snd_soc_codec *codec,
674 enum snd_soc_bias_level level)
675{
676 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
677
678 switch (level) {
679 case SND_SOC_BIAS_ON:
680 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE)
681 wm0010_boot(codec);
682 break;
683 case SND_SOC_BIAS_PREPARE:
684 break;
685 case SND_SOC_BIAS_STANDBY:
686 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE) {
687 mutex_lock(&wm0010->lock);
688 wm0010_halt(codec);
689 mutex_unlock(&wm0010->lock);
690 }
691 break;
692 case SND_SOC_BIAS_OFF:
693 break;
694 }
695
696 codec->dapm.bias_level = level;
697
698 return 0;
699}
700
701static int wm0010_set_sysclk(struct snd_soc_codec *codec, int source,
702 int clk_id, unsigned int freq, int dir)
703{
704 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
705 unsigned int i;
706
707 wm0010->sysclk = freq;
708
709 if (freq < pll_clock_map[ARRAY_SIZE(pll_clock_map)-1].max_sysclk) {
710 wm0010->max_spi_freq = 0;
711 } else {
712 for (i = 0; i < ARRAY_SIZE(pll_clock_map); i++)
713 if (freq >= pll_clock_map[i].max_sysclk)
714 break;
715
716 wm0010->max_spi_freq = pll_clock_map[i].max_pll_spi_speed;
717 wm0010->pll_clkctrl1 = pll_clock_map[i].pll_clkctrl1;
718 }
719
720 return 0;
721}
722
723static int wm0010_probe(struct snd_soc_codec *codec);
724
725static struct snd_soc_codec_driver soc_codec_dev_wm0010 = {
726 .probe = wm0010_probe,
727 .set_bias_level = wm0010_set_bias_level,
728 .set_sysclk = wm0010_set_sysclk,
d3fd716e 729 .idle_bias_off = true,
e3523e01 730
1470bfac
MB		 731 .dapm_widgets = wm0010_dapm_widgets,
732 .num_dapm_widgets = ARRAY_SIZE(wm0010_dapm_widgets),
e3523e01
DP		 733 .dapm_routes = wm0010_dapm_routes,
734 .num_dapm_routes = ARRAY_SIZE(wm0010_dapm_routes),
735};
736
6df31986 737#define WM0010_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
e3523e01
DP		 738#define WM0010_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
739 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
740 SNDRV_PCM_FMTBIT_S32_LE)
741
742static struct snd_soc_dai_driver wm0010_dai[] = {
743 {
744 .name = "wm0010-sdi1",
745 .playback = {
746 .stream_name = "SDI1 Playback",
747 .channels_min = 1,
748 .channels_max = 2,
749 .rates = WM0010_RATES,
750 .formats = WM0010_FORMATS,
751 },
752 .capture = {
753 .stream_name = "SDI1 Capture",
754 .channels_min = 1,
755 .channels_max = 2,
756 .rates = WM0010_RATES,
757 .formats = WM0010_FORMATS,
758 },
759 },
760 {
761 .name = "wm0010-sdi2",
762 .playback = {
763 .stream_name = "SDI2 Playback",
764 .channels_min = 1,
765 .channels_max = 2,
766 .rates = WM0010_RATES,
767 .formats = WM0010_FORMATS,
768 },
769 .capture = {
770 .stream_name = "SDI2 Capture",
771 .channels_min = 1,
772 .channels_max = 2,
773 .rates = WM0010_RATES,
774 .formats = WM0010_FORMATS,
775 },
776 },
777};
778
779static irqreturn_t wm0010_irq(int irq, void *data)
780{
781 struct wm0010_priv *wm0010 = data;
782
783 switch (wm0010->state) {
784 case WM0010_POWER_OFF:
785 case WM0010_OUT_OF_RESET:
786 case WM0010_BOOTROM:
787 case WM0010_STAGE2:
788 spin_lock(&wm0010->irq_lock);
789 complete(&wm0010->boot_completion);
790 spin_unlock(&wm0010->irq_lock);
791 return IRQ_HANDLED;
792 default:
793 return IRQ_NONE;
794 }
795
796 return IRQ_NONE;
797}
798
799static int wm0010_probe(struct snd_soc_codec *codec)
800{
801 struct wm0010_priv *wm0010 = snd_soc_codec_get_drvdata(codec);
32c50a31
MB		 802
803 wm0010->codec = codec;
804
805 return 0;
806}
807
808static int __devinit wm0010_spi_probe(struct spi_device *spi)
809{
e3523e01
DP		 810 unsigned long gpio_flags;
811 int ret;
812 int trigger;
813 int irq;
32c50a31 814 struct wm0010_priv *wm0010;
e3523e01 815
32c50a31
MB		 816 wm0010 = devm_kzalloc(&spi->dev, sizeof(*wm0010),
817 GFP_KERNEL);
818 if (!wm0010)
819 return -ENOMEM;
820
821 mutex_init(&wm0010->lock);
822 spin_lock_init(&wm0010->irq_lock);
823
824 spi_set_drvdata(spi, wm0010);
825 wm0010->dev = &spi->dev;
826
827 if (dev_get_platdata(&spi->dev))
828 memcpy(&wm0010->pdata, dev_get_platdata(&spi->dev),
829 sizeof(wm0010->pdata));
e3523e01
DP		 830
831 init_completion(&wm0010->boot_completion);
832
833 wm0010->core_supplies[0].supply = "AVDD";
834 wm0010->core_supplies[1].supply = "DCVDD";
835 ret = devm_regulator_bulk_get(wm0010->dev, ARRAY_SIZE(wm0010->core_supplies),
836 wm0010->core_supplies);
837 if (ret != 0) {
838 dev_err(wm0010->dev, "Failed to obtain core supplies: %d\n",
839 ret);
840 return ret;
841 }
842
843 wm0010->dbvdd = devm_regulator_get(wm0010->dev, "DBVDD");
844 if (IS_ERR(wm0010->dbvdd)) {
845 ret = PTR_ERR(wm0010->dbvdd);
846 dev_err(wm0010->dev, "Failed to obtain DBVDD: %d\n", ret);
847 return ret;
848 }
849
850 if (wm0010->pdata.gpio_reset) {
851 wm0010->gpio_reset = wm0010->pdata.gpio_reset;
852
853 if (wm0010->pdata.reset_active_high)
854 wm0010->gpio_reset_value = 1;
855 else
856 wm0010->gpio_reset_value = 0;
857
858 if (wm0010->gpio_reset_value)
859 gpio_flags = GPIOF_OUT_INIT_HIGH;
860 else
861 gpio_flags = GPIOF_OUT_INIT_LOW;
862
863 ret = devm_gpio_request_one(wm0010->dev, wm0010->gpio_reset,
864 gpio_flags, "wm0010 reset");
865 if (ret < 0) {
866 dev_err(wm0010->dev,
867 "Failed to request GPIO for DSP reset: %d\n",
868 ret);
869 return ret;
870 }
871 } else {
872 dev_err(wm0010->dev, "No reset GPIO configured\n");
32c50a31 873 return -EINVAL;
e3523e01
DP		 874 }
875
9bb68444
MB		 876 wm0010->state = WM0010_POWER_OFF;
877
e3523e01
DP		 878 irq = spi->irq;
879 if (wm0010->pdata.irq_flags)
880 trigger = wm0010->pdata.irq_flags;
881 else
882 trigger = IRQF_TRIGGER_FALLING;
883 trigger |= IRQF_ONESHOT;
884
58d46832 885 ret = request_threaded_irq(irq, NULL, wm0010_irq, trigger | IRQF_ONESHOT,
e3523e01 886 "wm0010", wm0010);
32c50a31 887 if (ret) {
e3523e01
DP		 888 dev_err(wm0010->dev, "Failed to request IRQ %d: %d\n",
889 irq, ret);
32c50a31
MB		 890 return ret;
891 }
e3523e01
DP		 892 wm0010->irq = irq;
893
894 if (spi->max_speed_hz)
895 wm0010->board_max_spi_speed = spi->max_speed_hz;
896 else
897 wm0010->board_max_spi_speed = 0;
898
e3523e01
DP		 899 ret = snd_soc_register_codec(&spi->dev,
900 &soc_codec_dev_wm0010, wm0010_dai,
901 ARRAY_SIZE(wm0010_dai));
902 if (ret < 0)
903 return ret;
904
905 return 0;
906}
907
908static int __devexit wm0010_spi_remove(struct spi_device *spi)
909{
910 struct wm0010_priv *wm0010 = spi_get_drvdata(spi);
911
912 snd_soc_unregister_codec(&spi->dev);
913
5afe5bfe
MB		 914 gpio_set_value_cansleep(wm0010->gpio_reset,
915 wm0010->gpio_reset_value);
e3523e01
DP		 916
917 if (wm0010->irq)
918 free_irq(wm0010->irq, wm0010);
919
920 return 0;
921}
922
923static struct spi_driver wm0010_spi_driver = {
924 .driver = {
925 .name = "wm0010",
926 .bus = &spi_bus_type,
927 .owner = THIS_MODULE,
928 },
929 .probe = wm0010_spi_probe,
930 .remove = __devexit_p(wm0010_spi_remove),
931};
932
933module_spi_driver(wm0010_spi_driver);
934
935MODULE_DESCRIPTION("ASoC WM0010 driver");
936MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
937MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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