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Merge branch 'for-3.3/drivers' of git://git.kernel.dk/linux-block
[deliverable/linux.git] / sound / soc / codecs / wm5100.c
CommitLineData
6d4baf08
MB		 1/*
2 * wm5100.c -- WM5100 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/gcd.h>
19#include <linux/gpio.h>
20#include <linux/i2c.h>
6d4baf08
MB		 21#include <linux/regulator/consumer.h>
22#include <linux/regulator/fixed.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
ba896ede 28#include <sound/jack.h>
6d4baf08
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <sound/wm5100.h>
32
33#include "wm5100.h"
34
35#define WM5100_NUM_CORE_SUPPLIES 2
36static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
37 "DBVDD1",
38 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
39};
40
41#define WM5100_AIFS 3
42#define WM5100_SYNC_SRS 3
43
44struct wm5100_fll {
45 int fref;
46 int fout;
47 int src;
48 struct completion lock;
49};
50
51/* codec private data */
52struct wm5100_priv {
bd132ec5 53 struct regmap *regmap;
6d4baf08
MB		 54 struct snd_soc_codec *codec;
55
56 struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
57 struct regulator *cpvdd;
7aefb086
MB		 58 struct regulator *dbvdd2;
59 struct regulator *dbvdd3;
6d4baf08
MB		 60
61 int rev;
62
63 int sysclk;
64 int asyncclk;
65
66 bool aif_async[WM5100_AIFS];
67 bool aif_symmetric[WM5100_AIFS];
68 int sr_ref[WM5100_SYNC_SRS];
69
70 bool out_ena[2];
71
ba896ede
MB		 72 struct snd_soc_jack *jack;
73 bool jack_detecting;
74 bool jack_mic;
75 int jack_mode;
76
6d4baf08
MB		 77 struct wm5100_fll fll[2];
78
79 struct wm5100_pdata pdata;
80
81#ifdef CONFIG_GPIOLIB
82 struct gpio_chip gpio_chip;
83#endif
84};
85
86static int wm5100_sr_code[] = {
87 0,
88 12000,
89 24000,
90 48000,
91 96000,
92 192000,
93 384000,
94 768000,
95 0,
96 11025,
97 22050,
98 44100,
99 88200,
100 176400,
101 352800,
102 705600,
103 4000,
104 8000,
105 16000,
106 32000,
107 64000,
108 128000,
109 256000,
110 512000,
111};
112
113static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
114 WM5100_CLOCKING_4,
115 WM5100_CLOCKING_5,
116 WM5100_CLOCKING_6,
117};
118
119static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
120{
121 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
122 int sr_code, sr_free, i;
123
124 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
125 if (wm5100_sr_code[i] == rate)
126 break;
127 if (i == ARRAY_SIZE(wm5100_sr_code)) {
128 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
129 return -EINVAL;
130 }
131 sr_code = i;
132
133 if ((wm5100->sysclk % rate) == 0) {
134 /* Is this rate already in use? */
135 sr_free = -1;
136 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
137 if (!wm5100->sr_ref[i] && sr_free == -1) {
138 sr_free = i;
139 continue;
140 }
141 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
142 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
143 break;
144 }
145
146 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
147 wm5100->sr_ref[i]++;
148 dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
149 rate, i, wm5100->sr_ref[i]);
150 return i;
151 }
152
153 if (sr_free == -1) {
154 dev_err(codec->dev, "All SR slots already in use\n");
155 return -EBUSY;
156 }
157
158 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
159 sr_free, rate);
160 wm5100->sr_ref[sr_free]++;
161 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
162 WM5100_SAMPLE_RATE_1_MASK,
163 sr_code);
164
165 return sr_free;
166
167 } else {
168 dev_err(codec->dev,
169 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
170 rate, wm5100->sysclk, wm5100->asyncclk);
171 return -EINVAL;
172 }
173}
174
175static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
176{
177 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
178 int i, sr_code;
179
180 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
181 if (wm5100_sr_code[i] == rate)
182 break;
183 if (i == ARRAY_SIZE(wm5100_sr_code)) {
184 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
185 return;
186 }
187 sr_code = wm5100_sr_code[i];
188
189 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
190 if (!wm5100->sr_ref[i])
191 continue;
192
193 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
194 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
195 break;
196 }
197 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
198 wm5100->sr_ref[i]--;
199 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
200 rate, wm5100->sr_ref[i]);
201 } else {
202 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
203 rate);
204 }
205}
206
588ac5e0 207static int wm5100_reset(struct wm5100_priv *wm5100)
6d4baf08 208{
6d4baf08
MB		 209 if (wm5100->pdata.reset) {
210 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
211 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
212
213 return 0;
214 } else {
588ac5e0 215 return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
6d4baf08
MB		 216 }
217}
218
219static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
220static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
221static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
222static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
223static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
224
225static const char *wm5100_mixer_texts[] = {
226 "None",
227 "Tone Generator 1",
228 "Tone Generator 2",
229 "AEC loopback",
230 "IN1L",
231 "IN1R",
232 "IN2L",
233 "IN2R",
234 "IN3L",
235 "IN3R",
236 "IN4L",
237 "IN4R",
238 "AIF1RX1",
239 "AIF1RX2",
240 "AIF1RX3",
241 "AIF1RX4",
242 "AIF1RX5",
243 "AIF1RX6",
244 "AIF1RX7",
245 "AIF1RX8",
246 "AIF2RX1",
247 "AIF2RX2",
248 "AIF3RX1",
249 "AIF3RX2",
250 "EQ1",
251 "EQ2",
252 "EQ3",
253 "EQ4",
254 "DRC1L",
255 "DRC1R",
256 "LHPF1",
257 "LHPF2",
258 "LHPF3",
259 "LHPF4",
260 "DSP1.1",
261 "DSP1.2",
262 "DSP1.3",
263 "DSP1.4",
264 "DSP1.5",
265 "DSP1.6",
266 "DSP2.1",
267 "DSP2.2",
268 "DSP2.3",
269 "DSP2.4",
270 "DSP2.5",
271 "DSP2.6",
272 "DSP3.1",
273 "DSP3.2",
274 "DSP3.3",
275 "DSP3.4",
276 "DSP3.5",
277 "DSP3.6",
278 "ASRC1L",
279 "ASRC1R",
280 "ASRC2L",
281 "ASRC2R",
282 "ISRC1INT1",
283 "ISRC1INT2",
284 "ISRC1INT3",
285 "ISRC1INT4",
286 "ISRC2INT1",
287 "ISRC2INT2",
288 "ISRC2INT3",
289 "ISRC2INT4",
290 "ISRC1DEC1",
291 "ISRC1DEC2",
292 "ISRC1DEC3",
293 "ISRC1DEC4",
294 "ISRC2DEC1",
295 "ISRC2DEC2",
296 "ISRC2DEC3",
297 "ISRC2DEC4",
298};
299
300static int wm5100_mixer_values[] = {
301 0x00,
302 0x04, /* Tone */
303 0x05,
304 0x08, /* AEC */
305 0x10, /* Input */
306 0x11,
307 0x12,
308 0x13,
309 0x14,
310 0x15,
311 0x16,
312 0x17,
313 0x20, /* AIF */
314 0x21,
315 0x22,
316 0x23,
317 0x24,
318 0x25,
319 0x26,
320 0x27,
321 0x28,
322 0x29,
323 0x30, /* AIF3 - check */
324 0x31,
325 0x50, /* EQ */
326 0x51,
327 0x52,
328 0x53,
329 0x54,
330 0x58, /* DRC */
331 0x59,
332 0x60, /* LHPF1 */
333 0x61, /* LHPF2 */
334 0x62, /* LHPF3 */
335 0x63, /* LHPF4 */
336 0x68, /* DSP1 */
337 0x69,
338 0x6a,
339 0x6b,
340 0x6c,
341 0x6d,
342 0x70, /* DSP2 */
343 0x71,
344 0x72,
345 0x73,
346 0x74,
347 0x75,
348 0x78, /* DSP3 */
349 0x79,
350 0x7a,
351 0x7b,
352 0x7c,
353 0x7d,
354 0x90, /* ASRC1 */
355 0x91,
356 0x92, /* ASRC2 */
357 0x93,
358 0xa0, /* ISRC1DEC1 */
359 0xa1,
360 0xa2,
361 0xa3,
362 0xa4, /* ISRC1INT1 */
363 0xa5,
364 0xa6,
365 0xa7,
366 0xa8, /* ISRC2DEC1 */
367 0xa9,
368 0xaa,
369 0xab,
370 0xac, /* ISRC2INT1 */
371 0xad,
372 0xae,
373 0xaf,
374};
375
376#define WM5100_MIXER_CONTROLS(name, base) \
377 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
378 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
379 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
380 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
381 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
382 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
383 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
384 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
385
386#define WM5100_MUX_ENUM_DECL(name, reg) \
387 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
388 wm5100_mixer_texts, wm5100_mixer_values)
389
390#define WM5100_MUX_CTL_DECL(name) \
391 const struct snd_kcontrol_new name##_mux = \
392 SOC_DAPM_VALUE_ENUM("Route", name##_enum)
393
394#define WM5100_MIXER_ENUMS(name, base_reg) \
395 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
396 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
397 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
398 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
399 static WM5100_MUX_CTL_DECL(name##_in1); \
400 static WM5100_MUX_CTL_DECL(name##_in2); \
401 static WM5100_MUX_CTL_DECL(name##_in3); \
402 static WM5100_MUX_CTL_DECL(name##_in4)
403
404WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
405WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
406WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
407WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
408WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
409WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
410
411WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
412WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
413WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
414WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
415WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
416WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
417
418WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
419WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
420
421WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
422WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
423WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
424WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
425WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
426WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
427WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
428WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
429
430WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
431WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
432
433WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
434WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
435
436WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
437WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
438WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
439WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
440
441WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
442WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
443
444WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
445WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
446WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
447WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
448
449#define WM5100_MUX(name, ctrl) \
450 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
451
452#define WM5100_MIXER_WIDGETS(name, name_str) \
453 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
454 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
455 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
456 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
457 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
458
459#define WM5100_MIXER_INPUT_ROUTES(name) \
460 { name, "Tone Generator 1", "Tone Generator 1" }, \
461 { name, "Tone Generator 2", "Tone Generator 2" }, \
462 { name, "IN1L", "IN1L PGA" }, \
463 { name, "IN1R", "IN1R PGA" }, \
464 { name, "IN2L", "IN2L PGA" }, \
465 { name, "IN2R", "IN2R PGA" }, \
466 { name, "IN3L", "IN3L PGA" }, \
467 { name, "IN3R", "IN3R PGA" }, \
468 { name, "IN4L", "IN4L PGA" }, \
469 { name, "IN4R", "IN4R PGA" }, \
470 { name, "AIF1RX1", "AIF1RX1" }, \
471 { name, "AIF1RX2", "AIF1RX2" }, \
472 { name, "AIF1RX3", "AIF1RX3" }, \
473 { name, "AIF1RX4", "AIF1RX4" }, \
474 { name, "AIF1RX5", "AIF1RX5" }, \
475 { name, "AIF1RX6", "AIF1RX6" }, \
476 { name, "AIF1RX7", "AIF1RX7" }, \
477 { name, "AIF1RX8", "AIF1RX8" }, \
478 { name, "AIF2RX1", "AIF2RX1" }, \
479 { name, "AIF2RX2", "AIF2RX2" }, \
480 { name, "AIF3RX1", "AIF3RX1" }, \
481 { name, "AIF3RX2", "AIF3RX2" }, \
482 { name, "EQ1", "EQ1" }, \
483 { name, "EQ2", "EQ2" }, \
484 { name, "EQ3", "EQ3" }, \
485 { name, "EQ4", "EQ4" }, \
486 { name, "DRC1L", "DRC1L" }, \
487 { name, "DRC1R", "DRC1R" }, \
488 { name, "LHPF1", "LHPF1" }, \
489 { name, "LHPF2", "LHPF2" }, \
490 { name, "LHPF3", "LHPF3" }, \
491 { name, "LHPF4", "LHPF4" }
492
493#define WM5100_MIXER_ROUTES(widget, name) \
494 { widget, NULL, name " Mixer" }, \
495 { name " Mixer", NULL, name " Input 1" }, \
496 { name " Mixer", NULL, name " Input 2" }, \
497 { name " Mixer", NULL, name " Input 3" }, \
498 { name " Mixer", NULL, name " Input 4" }, \
499 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
500 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
501 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
502 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
503
504static const char *wm5100_lhpf_mode_text[] = {
505 "Low-pass", "High-pass"
506};
507
508static const struct soc_enum wm5100_lhpf1_mode =
509 SOC_ENUM_SINGLE(WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT, 2,
510 wm5100_lhpf_mode_text);
511
512static const struct soc_enum wm5100_lhpf2_mode =
513 SOC_ENUM_SINGLE(WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT, 2,
514 wm5100_lhpf_mode_text);
515
516static const struct soc_enum wm5100_lhpf3_mode =
517 SOC_ENUM_SINGLE(WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT, 2,
518 wm5100_lhpf_mode_text);
519
520static const struct soc_enum wm5100_lhpf4_mode =
521 SOC_ENUM_SINGLE(WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT, 2,
522 wm5100_lhpf_mode_text);
523
524static const struct snd_kcontrol_new wm5100_snd_controls[] = {
525SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
526 WM5100_IN1_OSR_SHIFT, 1, 0),
527SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
528 WM5100_IN2_OSR_SHIFT, 1, 0),
529SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
530 WM5100_IN3_OSR_SHIFT, 1, 0),
531SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
532 WM5100_IN4_OSR_SHIFT, 1, 0),
533
534/* Only applicable for analogue inputs */
535SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
536 WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
537SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
538 WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
539SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
540 WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
541SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
542 WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
543
544SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
545 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
546 0, digital_tlv),
547SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
548 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
549 0, digital_tlv),
550SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
551 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
552 0, digital_tlv),
553SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
554 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
555 0, digital_tlv),
556
557SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
558 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
559SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
560 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
561SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
562 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
563SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
564 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
565
566SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
567 WM5100_OUT1_OSR_SHIFT, 1, 0),
568SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
569 WM5100_OUT2_OSR_SHIFT, 1, 0),
570SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
571 WM5100_OUT3_OSR_SHIFT, 1, 0),
572SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
573 WM5100_OUT4_OSR_SHIFT, 1, 0),
574SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
575 WM5100_OUT5_OSR_SHIFT, 1, 0),
576SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
577 WM5100_OUT6_OSR_SHIFT, 1, 0),
578
579SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
580 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
581 digital_tlv),
582SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
583 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
584 digital_tlv),
585SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
586 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
587 digital_tlv),
588SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
589 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
590 digital_tlv),
591SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
592 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
593 digital_tlv),
594SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
595 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
596 digital_tlv),
597
598SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
599 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
600SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
601 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
602SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
603 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
604SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
605 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
606SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
607 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
608SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
609 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
610
611/* FIXME: Only valid from -12dB to 0dB (52-64) */
612SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
613 WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
614SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
615 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
616SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
617 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
618
619SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
620 WM5100_SPK1R_MUTE_SHIFT, 1, 1),
621SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
622 WM5100_SPK2R_MUTE_SHIFT, 1, 1),
623
624SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
625 24, 0, eq_tlv),
626SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
627 24, 0, eq_tlv),
628SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
629 24, 0, eq_tlv),
630SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
631 24, 0, eq_tlv),
632SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
633 24, 0, eq_tlv),
634
635SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
636 24, 0, eq_tlv),
637SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
638 24, 0, eq_tlv),
639SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
640 24, 0, eq_tlv),
641SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
642 24, 0, eq_tlv),
643SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
644 24, 0, eq_tlv),
645
646SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
647 24, 0, eq_tlv),
648SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
649 24, 0, eq_tlv),
650SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
651 24, 0, eq_tlv),
652SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
653 24, 0, eq_tlv),
654SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
655 24, 0, eq_tlv),
656
657SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
658 24, 0, eq_tlv),
659SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
660 24, 0, eq_tlv),
661SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
662 24, 0, eq_tlv),
663SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
664 24, 0, eq_tlv),
665SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
666 24, 0, eq_tlv),
667
668SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
669SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
670SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
671SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
672
673WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
674WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
675WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
676WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
677WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
678WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
679
680WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
681WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
682WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
683WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
684WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
685WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
686
687WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
688WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
689
690WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
691WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
692WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
693WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
694WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
695WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
696WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
697WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
698
699WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
700WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
701
702WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
703WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
704
705WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
706WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
707WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
708WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
709
710WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
711WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
712
713WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
714WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
715WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
716WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
717};
718
719static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
720 enum snd_soc_dapm_type event, int subseq)
721{
722 struct snd_soc_codec *codec = container_of(dapm,
723 struct snd_soc_codec, dapm);
724 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
725 u16 val, expect, i;
726
727 /* Wait for the outputs to flag themselves as enabled */
728 if (wm5100->out_ena[0]) {
729 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
730 for (i = 0; i < 200; i++) {
731 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
732 if (val == expect) {
733 wm5100->out_ena[0] = false;
734 break;
735 }
736 }
737 if (i == 200) {
738 dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
739 expect);
740 }
741 }
742
743 if (wm5100->out_ena[1]) {
744 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
745 for (i = 0; i < 200; i++) {
746 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
747 if (val == expect) {
748 wm5100->out_ena[1] = false;
749 break;
750 }
751 }
752 if (i == 200) {
753 dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
754 expect);
755 }
756 }
757}
758
759static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
760 struct snd_kcontrol *kcontrol,
761 int event)
762{
763 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec);
764
765 switch (w->reg) {
766 case WM5100_CHANNEL_ENABLES_1:
767 wm5100->out_ena[0] = true;
768 break;
769 case WM5100_OUTPUT_ENABLES_2:
770 wm5100->out_ena[0] = true;
771 break;
772 default:
773 break;
774 }
775
776 return 0;
777}
778
779static int wm5100_cp_ev(struct snd_soc_dapm_widget *w,
780 struct snd_kcontrol *kcontrol,
781 int event)
782{
783 struct snd_soc_codec *codec = w->codec;
784 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
785 int ret;
786
787 switch (event) {
788 case SND_SOC_DAPM_PRE_PMU:
789 ret = regulator_enable(wm5100->cpvdd);
790 if (ret != 0) {
791 dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
792 ret);
793 return ret;
794 }
795 return ret;
796
797 case SND_SOC_DAPM_POST_PMD:
798 ret = regulator_disable_deferred(wm5100->cpvdd, 20);
799 if (ret != 0) {
800 dev_err(codec->dev, "Failed to disable CPVDD: %d\n",
801 ret);
802 return ret;
803 }
804 return ret;
805
806 default:
807 BUG();
808 return 0;
809 }
810}
811
7aefb086
MB		 812static int wm5100_dbvdd_ev(struct snd_soc_dapm_widget *w,
813 struct snd_kcontrol *kcontrol,
814 int event)
815{
816 struct snd_soc_codec *codec = w->codec;
817 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
818 struct regulator *regulator;
819 int ret;
820
821 switch (w->shift) {
822 case 2:
823 regulator = wm5100->dbvdd2;
824 break;
825 case 3:
826 regulator = wm5100->dbvdd3;
827 break;
828 default:
829 BUG();
830 return 0;
831 }
832
833 switch (event) {
834 case SND_SOC_DAPM_PRE_PMU:
835 ret = regulator_enable(regulator);
836 if (ret != 0) {
837 dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
838 w->shift, ret);
839 return ret;
840 }
841 return ret;
842
843 case SND_SOC_DAPM_POST_PMD:
844 ret = regulator_disable(regulator);
845 if (ret != 0) {
846 dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
847 w->shift, ret);
848 return ret;
849 }
850 return ret;
851
852 default:
853 BUG();
854 return 0;
855 }
856}
857
6d4baf08
MB		 858static void wm5100_log_status3(struct snd_soc_codec *codec, int val)
859{
860 if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
861 dev_crit(codec->dev, "Speaker shutdown warning\n");
862 if (val & WM5100_SPK_SHUTDOWN_EINT)
863 dev_crit(codec->dev, "Speaker shutdown\n");
864 if (val & WM5100_CLKGEN_ERR_EINT)
865 dev_crit(codec->dev, "SYSCLK underclocked\n");
866 if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
867 dev_crit(codec->dev, "ASYNCCLK underclocked\n");
868}
869
870static void wm5100_log_status4(struct snd_soc_codec *codec, int val)
871{
872 if (val & WM5100_AIF3_ERR_EINT)
873 dev_err(codec->dev, "AIF3 configuration error\n");
874 if (val & WM5100_AIF2_ERR_EINT)
875 dev_err(codec->dev, "AIF2 configuration error\n");
876 if (val & WM5100_AIF1_ERR_EINT)
877 dev_err(codec->dev, "AIF1 configuration error\n");
878 if (val & WM5100_CTRLIF_ERR_EINT)
879 dev_err(codec->dev, "Control interface error\n");
880 if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
881 dev_err(codec->dev, "ISRC2 underclocked\n");
882 if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
883 dev_err(codec->dev, "ISRC1 underclocked\n");
884 if (val & WM5100_FX_UNDERCLOCKED_EINT)
885 dev_err(codec->dev, "FX underclocked\n");
886 if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
887 dev_err(codec->dev, "AIF3 underclocked\n");
888 if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
889 dev_err(codec->dev, "AIF2 underclocked\n");
890 if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
891 dev_err(codec->dev, "AIF1 underclocked\n");
892 if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
893 dev_err(codec->dev, "ASRC underclocked\n");
894 if (val & WM5100_DAC_UNDERCLOCKED_EINT)
895 dev_err(codec->dev, "DAC underclocked\n");
896 if (val & WM5100_ADC_UNDERCLOCKED_EINT)
897 dev_err(codec->dev, "ADC underclocked\n");
898 if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
899 dev_err(codec->dev, "Mixer underclocked\n");
900}
901
902static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
903 struct snd_kcontrol *kcontrol,
904 int event)
905{
906 struct snd_soc_codec *codec = w->codec;
907 int ret;
908
909 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
910 ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
911 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
912 WM5100_CLKGEN_ERR_ASYNC_STS;
913 wm5100_log_status3(codec, ret);
914
915 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
916 wm5100_log_status4(codec, ret);
917
918 return 0;
919}
920
921static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
922SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
923 NULL, 0),
924SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
925 0, NULL, 0),
926
927SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
928 wm5100_cp_ev,
929 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
930SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
931 NULL, 0),
932SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
933 WM5100_CP2_BYPASS_SHIFT, 1, wm5100_cp_ev,
934 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
7aefb086
MB		 935SND_SOC_DAPM_SUPPLY("DBVDD2", SND_SOC_NOPM, 2, 0, wm5100_dbvdd_ev,
936 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
937SND_SOC_DAPM_SUPPLY("DBVDD3", SND_SOC_NOPM, 3, 0, wm5100_dbvdd_ev,
938 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
6d4baf08
MB		 939
940SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
941 0, NULL, 0),
942SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
943 0, NULL, 0),
944SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
945 0, NULL, 0),
946
947SND_SOC_DAPM_INPUT("IN1L"),
948SND_SOC_DAPM_INPUT("IN1R"),
949SND_SOC_DAPM_INPUT("IN2L"),
950SND_SOC_DAPM_INPUT("IN2R"),
951SND_SOC_DAPM_INPUT("IN3L"),
952SND_SOC_DAPM_INPUT("IN3R"),
953SND_SOC_DAPM_INPUT("IN4L"),
954SND_SOC_DAPM_INPUT("IN4R"),
dea8e237 955SND_SOC_DAPM_SIGGEN("TONE"),
6d4baf08
MB		 956
957SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
958 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
959SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
960 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
961SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
962 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
963SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
964 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
965SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
966 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
967SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
968 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
969SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
970 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
971SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
972 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
973
974SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
975 WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
976SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
977 WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
978
979SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
980 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
981SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
982 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
983SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
984 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
985SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
986 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
987SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
988 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
989SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
990 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
991SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
992 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
993SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
994 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
995
996SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
997 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
998SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
999 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
1000
1001SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
1002 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
1003SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
1004 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
1005
1006SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
1007 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
1008SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
1009 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
1010SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
1011 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
1012SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
1013 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
1014SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
1015 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
1016SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
1017 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
1018SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
1019 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
1020SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
1021 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
1022
1023SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
1024 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
1025SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
1026 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
1027
1028SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
1029 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
1030SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
1031 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
1032
1033SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
1034 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1035SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
1036 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1037SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
1038 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1039SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
1040 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1041SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
1042 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1043SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
1044 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1045SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
1046 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1047SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
1048 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1049SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
1050 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1051SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
1052 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1053SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
1054 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1055SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
1056 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1057SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
1058 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1059SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
1060 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1061
1062SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
1063SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
1064SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1065SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1066
1067SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1068 NULL, 0),
1069SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1070 NULL, 0),
1071
1072SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1073 NULL, 0),
1074SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1075 NULL, 0),
1076SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1077 NULL, 0),
1078SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1079 NULL, 0),
1080
1081WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1082WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1083WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1084WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1085
1086WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1087WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1088
1089WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1090WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1091WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1092WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1093
1094WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1095WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1096WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1097WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1098WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1099WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1100WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1101WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1102
1103WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1104WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1105
1106WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1107WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1108
1109WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1110WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1111WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1112WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1113WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1114WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1115
1116WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1117WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1118WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1119WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1120WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1121WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1122
1123WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1124WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1125
1126SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1127SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1128SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1129SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1130SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1131SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1132SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1133SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1134SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1135SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1136SND_SOC_DAPM_OUTPUT("PWM1"),
1137SND_SOC_DAPM_OUTPUT("PWM2"),
1138};
1139
1140/* We register a _POST event if we don't have IRQ support so we can
1141 * look at the error status from the CODEC - if we've got the IRQ
1142 * hooked up then we will get prompted to look by an interrupt.
1143 */
1144static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1145SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1146};
1147
1148static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1149 { "IN1L", NULL, "SYSCLK" },
1150 { "IN1R", NULL, "SYSCLK" },
1151 { "IN2L", NULL, "SYSCLK" },
1152 { "IN2R", NULL, "SYSCLK" },
1153 { "IN3L", NULL, "SYSCLK" },
1154 { "IN3R", NULL, "SYSCLK" },
1155 { "IN4L", NULL, "SYSCLK" },
1156 { "IN4R", NULL, "SYSCLK" },
1157
1158 { "OUT1L", NULL, "SYSCLK" },
1159 { "OUT1R", NULL, "SYSCLK" },
1160 { "OUT2L", NULL, "SYSCLK" },
1161 { "OUT2R", NULL, "SYSCLK" },
1162 { "OUT3L", NULL, "SYSCLK" },
1163 { "OUT3R", NULL, "SYSCLK" },
1164 { "OUT4L", NULL, "SYSCLK" },
1165 { "OUT4R", NULL, "SYSCLK" },
1166 { "OUT5L", NULL, "SYSCLK" },
1167 { "OUT5R", NULL, "SYSCLK" },
1168 { "OUT6L", NULL, "SYSCLK" },
1169 { "OUT6R", NULL, "SYSCLK" },
1170
1171 { "AIF1RX1", NULL, "SYSCLK" },
1172 { "AIF1RX2", NULL, "SYSCLK" },
1173 { "AIF1RX3", NULL, "SYSCLK" },
1174 { "AIF1RX4", NULL, "SYSCLK" },
1175 { "AIF1RX5", NULL, "SYSCLK" },
1176 { "AIF1RX6", NULL, "SYSCLK" },
1177 { "AIF1RX7", NULL, "SYSCLK" },
1178 { "AIF1RX8", NULL, "SYSCLK" },
1179
1180 { "AIF2RX1", NULL, "SYSCLK" },
7aefb086 1181 { "AIF2RX1", NULL, "DBVDD2" },
6d4baf08 1182 { "AIF2RX2", NULL, "SYSCLK" },
7aefb086 1183 { "AIF2RX2", NULL, "DBVDD2" },
6d4baf08
MB		 1184
1185 { "AIF3RX1", NULL, "SYSCLK" },
7aefb086 1186 { "AIF3RX1", NULL, "DBVDD3" },
6d4baf08 1187 { "AIF3RX2", NULL, "SYSCLK" },
7aefb086 1188 { "AIF3RX2", NULL, "DBVDD3" },
6d4baf08
MB		 1189
1190 { "AIF1TX1", NULL, "SYSCLK" },
1191 { "AIF1TX2", NULL, "SYSCLK" },
1192 { "AIF1TX3", NULL, "SYSCLK" },
1193 { "AIF1TX4", NULL, "SYSCLK" },
1194 { "AIF1TX5", NULL, "SYSCLK" },
1195 { "AIF1TX6", NULL, "SYSCLK" },
1196 { "AIF1TX7", NULL, "SYSCLK" },
1197 { "AIF1TX8", NULL, "SYSCLK" },
1198
1199 { "AIF2TX1", NULL, "SYSCLK" },
7aefb086 1200 { "AIF2TX1", NULL, "DBVDD2" },
6d4baf08 1201 { "AIF2TX2", NULL, "SYSCLK" },
7aefb086 1202 { "AIF2TX2", NULL, "DBVDD2" },
6d4baf08
MB		 1203
1204 { "AIF3TX1", NULL, "SYSCLK" },
7aefb086 1205 { "AIF3TX1", NULL, "DBVDD3" },
6d4baf08 1206 { "AIF3TX2", NULL, "SYSCLK" },
7aefb086 1207 { "AIF3TX2", NULL, "DBVDD3" },
6d4baf08
MB		 1208
1209 { "MICBIAS1", NULL, "CP2" },
1210 { "MICBIAS2", NULL, "CP2" },
1211 { "MICBIAS3", NULL, "CP2" },
1212
1213 { "IN1L PGA", NULL, "CP2" },
1214 { "IN1R PGA", NULL, "CP2" },
1215 { "IN2L PGA", NULL, "CP2" },
1216 { "IN2R PGA", NULL, "CP2" },
1217 { "IN3L PGA", NULL, "CP2" },
1218 { "IN3R PGA", NULL, "CP2" },
1219 { "IN4L PGA", NULL, "CP2" },
1220 { "IN4R PGA", NULL, "CP2" },
1221
1222 { "IN1L PGA", NULL, "CP2 Active" },
1223 { "IN1R PGA", NULL, "CP2 Active" },
1224 { "IN2L PGA", NULL, "CP2 Active" },
1225 { "IN2R PGA", NULL, "CP2 Active" },
1226 { "IN3L PGA", NULL, "CP2 Active" },
1227 { "IN3R PGA", NULL, "CP2 Active" },
1228 { "IN4L PGA", NULL, "CP2 Active" },
1229 { "IN4R PGA", NULL, "CP2 Active" },
1230
1231 { "OUT1L", NULL, "CP1" },
1232 { "OUT1R", NULL, "CP1" },
1233 { "OUT2L", NULL, "CP1" },
1234 { "OUT2R", NULL, "CP1" },
1235 { "OUT3L", NULL, "CP1" },
1236 { "OUT3R", NULL, "CP1" },
1237
1238 { "Tone Generator 1", NULL, "TONE" },
1239 { "Tone Generator 2", NULL, "TONE" },
1240
1241 { "IN1L PGA", NULL, "IN1L" },
1242 { "IN1R PGA", NULL, "IN1R" },
1243 { "IN2L PGA", NULL, "IN2L" },
1244 { "IN2R PGA", NULL, "IN2R" },
1245 { "IN3L PGA", NULL, "IN3L" },
1246 { "IN3R PGA", NULL, "IN3R" },
1247 { "IN4L PGA", NULL, "IN4L" },
1248 { "IN4R PGA", NULL, "IN4R" },
1249
1250 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1251 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1252 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1253 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1254 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1255 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1256
1257 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1258 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1259 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1260 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1261 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1262 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1263
1264 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1265 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1266
1267 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1268 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1269 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1270 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1271 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1272 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1273 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1274 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1275
1276 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1277 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1278
1279 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1280 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1281
1282 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1283 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1284 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1285 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1286
1287 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1288 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1289
1290 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1291 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1292 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1293 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1294
1295 { "HPOUT1L", NULL, "OUT1L" },
1296 { "HPOUT1R", NULL, "OUT1R" },
1297 { "HPOUT2L", NULL, "OUT2L" },
1298 { "HPOUT2R", NULL, "OUT2R" },
1299 { "HPOUT3L", NULL, "OUT3L" },
1300 { "HPOUT3R", NULL, "OUT3R" },
1301 { "SPKOUTL", NULL, "OUT4L" },
1302 { "SPKOUTR", NULL, "OUT4R" },
1303 { "SPKDAT1", NULL, "OUT5L" },
1304 { "SPKDAT1", NULL, "OUT5R" },
1305 { "SPKDAT2", NULL, "OUT6L" },
1306 { "SPKDAT2", NULL, "OUT6R" },
1307 { "PWM1", NULL, "PWM1 Driver" },
1308 { "PWM2", NULL, "PWM2 Driver" },
1309};
1310
1311static struct {
1312 int reg;
1313 int val;
1314} wm5100_reva_patches[] = {
1315 { WM5100_AUDIO_IF_1_10, 0 },
1316 { WM5100_AUDIO_IF_1_11, 1 },
1317 { WM5100_AUDIO_IF_1_12, 2 },
1318 { WM5100_AUDIO_IF_1_13, 3 },
1319 { WM5100_AUDIO_IF_1_14, 4 },
1320 { WM5100_AUDIO_IF_1_15, 5 },
1321 { WM5100_AUDIO_IF_1_16, 6 },
1322 { WM5100_AUDIO_IF_1_17, 7 },
1323
1324 { WM5100_AUDIO_IF_1_18, 0 },
1325 { WM5100_AUDIO_IF_1_19, 1 },
1326 { WM5100_AUDIO_IF_1_20, 2 },
1327 { WM5100_AUDIO_IF_1_21, 3 },
1328 { WM5100_AUDIO_IF_1_22, 4 },
1329 { WM5100_AUDIO_IF_1_23, 5 },
1330 { WM5100_AUDIO_IF_1_24, 6 },
1331 { WM5100_AUDIO_IF_1_25, 7 },
1332
1333 { WM5100_AUDIO_IF_2_10, 0 },
1334 { WM5100_AUDIO_IF_2_11, 1 },
1335
1336 { WM5100_AUDIO_IF_2_18, 0 },
1337 { WM5100_AUDIO_IF_2_19, 1 },
1338
1339 { WM5100_AUDIO_IF_3_10, 0 },
1340 { WM5100_AUDIO_IF_3_11, 1 },
1341
1342 { WM5100_AUDIO_IF_3_18, 0 },
1343 { WM5100_AUDIO_IF_3_19, 1 },
1344};
1345
1346static int wm5100_set_bias_level(struct snd_soc_codec *codec,
1347 enum snd_soc_bias_level level)
1348{
1349 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1350 int ret, i;
1351
1352 switch (level) {
1353 case SND_SOC_BIAS_ON:
1354 break;
1355
1356 case SND_SOC_BIAS_PREPARE:
1357 break;
1358
1359 case SND_SOC_BIAS_STANDBY:
1360 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1361 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
1362 wm5100->core_supplies);
1363 if (ret != 0) {
1364 dev_err(codec->dev,
1365 "Failed to enable supplies: %d\n",
1366 ret);
1367 return ret;
1368 }
1369
1370 if (wm5100->pdata.ldo_ena) {
1371 gpio_set_value_cansleep(wm5100->pdata.ldo_ena,
1372 1);
1373 msleep(2);
1374 }
1375
bd132ec5 1376 regcache_cache_only(wm5100->regmap, false);
6d4baf08
MB		 1377
1378 switch (wm5100->rev) {
1379 case 0:
1380 snd_soc_write(codec, 0x11, 0x3);
1381 snd_soc_write(codec, 0x203, 0xc);
1382 snd_soc_write(codec, 0x206, 0);
1383 snd_soc_write(codec, 0x207, 0xf0);
1384 snd_soc_write(codec, 0x208, 0x3c);
1385 snd_soc_write(codec, 0x209, 0);
1386 snd_soc_write(codec, 0x211, 0x20d8);
1387 snd_soc_write(codec, 0x11, 0);
1388
1389 for (i = 0;
1390 i < ARRAY_SIZE(wm5100_reva_patches);
1391 i++)
1392 snd_soc_write(codec,
1393 wm5100_reva_patches[i].reg,
1394 wm5100_reva_patches[i].val);
1395 break;
1396 default:
1397 break;
1398 }
1399
60bf5b07 1400 regcache_sync(wm5100->regmap);
6d4baf08
MB		 1401 }
1402 break;
1403
1404 case SND_SOC_BIAS_OFF:
1405 if (wm5100->pdata.ldo_ena)
1406 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
1407 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
1408 wm5100->core_supplies);
1409 break;
1410 }
1411 codec->dapm.bias_level = level;
1412
1413 return 0;
1414}
1415
1416static int wm5100_dai_to_base(struct snd_soc_dai *dai)
1417{
1418 switch (dai->id) {
1419 case 0:
1420 return WM5100_AUDIO_IF_1_1 - 1;
1421 case 1:
1422 return WM5100_AUDIO_IF_2_1 - 1;
1423 case 2:
1424 return WM5100_AUDIO_IF_3_1 - 1;
1425 default:
1426 BUG();
1427 return -EINVAL;
1428 }
1429}
1430
1431static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1432{
1433 struct snd_soc_codec *codec = dai->codec;
1434 int lrclk, bclk, mask, base;
1435
1436 base = wm5100_dai_to_base(dai);
1437 if (base < 0)
1438 return base;
1439
1440 lrclk = 0;
1441 bclk = 0;
1442
1443 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1444 case SND_SOC_DAIFMT_DSP_A:
1445 mask = 0;
1446 break;
1447 case SND_SOC_DAIFMT_DSP_B:
1448 mask = 1;
1449 break;
1450 case SND_SOC_DAIFMT_I2S:
1451 mask = 2;
1452 break;
1453 case SND_SOC_DAIFMT_LEFT_J:
1454 mask = 3;
1455 break;
1456 default:
1457 dev_err(codec->dev, "Unsupported DAI format %d\n",
1458 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1459 return -EINVAL;
1460 }
1461
1462 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1463 case SND_SOC_DAIFMT_CBS_CFS:
1464 break;
1465 case SND_SOC_DAIFMT_CBS_CFM:
1466 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1467 break;
1468 case SND_SOC_DAIFMT_CBM_CFS:
1469 bclk |= WM5100_AIF1_BCLK_MSTR;
1470 break;
1471 case SND_SOC_DAIFMT_CBM_CFM:
1472 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1473 bclk |= WM5100_AIF1_BCLK_MSTR;
1474 break;
1475 default:
1476 dev_err(codec->dev, "Unsupported master mode %d\n",
1477 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1478 return -EINVAL;
1479 }
1480
1481 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1482 case SND_SOC_DAIFMT_NB_NF:
1483 break;
1484 case SND_SOC_DAIFMT_IB_IF:
1485 bclk |= WM5100_AIF1_BCLK_INV;
1486 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1487 break;
1488 case SND_SOC_DAIFMT_IB_NF:
1489 bclk |= WM5100_AIF1_BCLK_INV;
1490 break;
1491 case SND_SOC_DAIFMT_NB_IF:
1492 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1493 break;
1494 default:
1495 return -EINVAL;
1496 }
1497
1498 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1499 WM5100_AIF1_BCLK_INV, bclk);
1500 snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1501 WM5100_AIF1TX_LRCLK_INV, lrclk);
1502 snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1503 WM5100_AIF1TX_LRCLK_INV, lrclk);
1504 snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1505
1506 return 0;
1507}
1508
1509#define WM5100_NUM_BCLK_RATES 19
1510
1511static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1512 32000,
1513 48000,
1514 64000,
1515 96000,
1516 128000,
1517 192000,
d73ec75c 1518 256000,
6d4baf08
MB		 1519 384000,
1520 512000,
1521 768000,
1522 1024000,
1523 1536000,
1524 2048000,
1525 3072000,
1526 4096000,
1527 6144000,
1528 8192000,
1529 12288000,
1530 24576000,
1531};
1532
1533static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1534 29400,
1535 44100,
1536 58800,
1537 88200,
1538 117600,
1539 176400,
1540 235200,
1541 352800,
1542 470400,
1543 705600,
1544 940800,
1545 1411200,
1546 1881600,
1547 2882400,
1548 3763200,
1549 5644800,
1550 7526400,
1551 11289600,
1552 22579600,
1553};
1554
1555static int wm5100_hw_params(struct snd_pcm_substream *substream,
1556 struct snd_pcm_hw_params *params,
1557 struct snd_soc_dai *dai)
1558{
1559 struct snd_soc_codec *codec = dai->codec;
1560 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1561 bool async = wm5100->aif_async[dai->id];
1562 int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1563 int *bclk_rates;
1564
1565 base = wm5100_dai_to_base(dai);
1566 if (base < 0)
1567 return base;
1568
1569 /* Data sizes if not using TDM */
1570 wl = snd_pcm_format_width(params_format(params));
1571 if (wl < 0)
1572 return wl;
1573 fl = snd_soc_params_to_frame_size(params);
1574 if (fl < 0)
1575 return fl;
1576
1577 dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1578 wl, fl);
1579
1580 /* Target BCLK rate */
1581 bclk = snd_soc_params_to_bclk(params);
1582 if (bclk < 0)
1583 return bclk;
1584
1585 /* Root for BCLK depends on SYS/ASYNCCLK */
1586 if (!async) {
1587 aif_rate = wm5100->sysclk;
1588 sr = wm5100_alloc_sr(codec, params_rate(params));
1589 if (sr < 0)
1590 return sr;
1591 } else {
1592 /* If we're in ASYNCCLK set the ASYNC sample rate */
1593 aif_rate = wm5100->asyncclk;
1594 sr = 3;
1595
1596 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1597 if (params_rate(params) == wm5100_sr_code[i])
1598 break;
1599 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1600 dev_err(codec->dev, "Invalid rate %dHzn",
1601 params_rate(params));
1602 return -EINVAL;
1603 }
1604
1605 /* TODO: We should really check for symmetry */
1606 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1607 WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1608 }
1609
1610 if (!aif_rate) {
1611 dev_err(codec->dev, "%s has no rate set\n",
1612 async ? "ASYNCCLK" : "SYSCLK");
1613 return -EINVAL;
1614 }
1615
1616 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1617 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1618
1619 if (aif_rate % 4000)
1620 bclk_rates = wm5100_bclk_rates_cd;
1621 else
1622 bclk_rates = wm5100_bclk_rates_dat;
1623
1624 for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1625 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1626 break;
1627 if (i == WM5100_NUM_BCLK_RATES) {
1628 dev_err(codec->dev,
1629 "No valid BCLK for %dHz found from %dHz %s\n",
1630 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1631 return -EINVAL;
1632 }
1633
1634 bclk = i;
1635 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1636 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1637
1638 lrclk = bclk_rates[bclk] / params_rate(params);
1639 dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1640 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1641 wm5100->aif_symmetric[dai->id])
1642 snd_soc_update_bits(codec, base + 7,
1643 WM5100_AIF1RX_BCPF_MASK, lrclk);
1644 else
1645 snd_soc_update_bits(codec, base + 6,
1646 WM5100_AIF1TX_BCPF_MASK, lrclk);
1647
1648 i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1649 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1650 snd_soc_update_bits(codec, base + 9,
1651 WM5100_AIF1RX_WL_MASK |
1652 WM5100_AIF1RX_SLOT_LEN_MASK, i);
1653 else
1654 snd_soc_update_bits(codec, base + 8,
1655 WM5100_AIF1TX_WL_MASK |
1656 WM5100_AIF1TX_SLOT_LEN_MASK, i);
1657
1658 snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1659
1660 return 0;
1661}
1662
85e7652d 1663static const struct snd_soc_dai_ops wm5100_dai_ops = {
6d4baf08
MB		 1664 .set_fmt = wm5100_set_fmt,
1665 .hw_params = wm5100_hw_params,
1666};
1667
1668static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1669 int source, unsigned int freq, int dir)
1670{
1671 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1672 int *rate_store;
1673 int fval, audio_rate, ret, reg;
1674
1675 switch (clk_id) {
1676 case WM5100_CLK_SYSCLK:
1677 reg = WM5100_CLOCKING_3;
1678 rate_store = &wm5100->sysclk;
1679 break;
1680 case WM5100_CLK_ASYNCCLK:
1681 reg = WM5100_CLOCKING_7;
1682 rate_store = &wm5100->asyncclk;
1683 break;
1684 case WM5100_CLK_32KHZ:
1685 /* The 32kHz clock is slightly different to the others */
1686 switch (source) {
1687 case WM5100_CLKSRC_MCLK1:
1688 case WM5100_CLKSRC_MCLK2:
1689 case WM5100_CLKSRC_SYSCLK:
1690 snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1691 WM5100_CLK_32K_SRC_MASK,
1692 source);
1693 break;
1694 default:
1695 return -EINVAL;
1696 }
1697 return 0;
1698
1699 case WM5100_CLK_AIF1:
1700 case WM5100_CLK_AIF2:
1701 case WM5100_CLK_AIF3:
1702 /* Not real clocks, record which clock domain they're in */
1703 switch (source) {
1704 case WM5100_CLKSRC_SYSCLK:
1705 wm5100->aif_async[clk_id - 1] = false;
1706 break;
1707 case WM5100_CLKSRC_ASYNCCLK:
1708 wm5100->aif_async[clk_id - 1] = true;
1709 break;
1710 default:
1711 dev_err(codec->dev, "Invalid source %d\n", source);
1712 return -EINVAL;
1713 }
1714 return 0;
1715
1716 case WM5100_CLK_OPCLK:
1717 switch (freq) {
1718 case 5644800:
1719 case 6144000:
1720 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1721 WM5100_OPCLK_SEL_MASK, 0);
1722 break;
1723 case 11289600:
1724 case 12288000:
1725 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1726 WM5100_OPCLK_SEL_MASK, 0);
1727 break;
1728 case 22579200:
1729 case 24576000:
1730 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1731 WM5100_OPCLK_SEL_MASK, 0);
1732 break;
1733 default:
1734 dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1735 freq);
1736 return -EINVAL;
1737 }
1738 return 0;
1739
1740 default:
1741 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1742 return -EINVAL;
1743 }
1744
1745 switch (source) {
1746 case WM5100_CLKSRC_SYSCLK:
1747 case WM5100_CLKSRC_ASYNCCLK:
1748 dev_err(codec->dev, "Invalid source %d\n", source);
1749 return -EINVAL;
1750 }
1751
1752 switch (freq) {
1753 case 5644800:
1754 case 6144000:
1755 fval = 0;
1756 break;
1757 case 11289600:
1758 case 12288000:
1759 fval = 1;
1760 break;
1761 case 22579200:
11c2b5f2 1762 case 24576000:
6d4baf08
MB		 1763 fval = 2;
1764 break;
1765 default:
1766 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1767 return -EINVAL;
1768 }
1769
1770 switch (freq) {
1771 case 5644800:
1772 case 11289600:
1773 case 22579200:
1774 audio_rate = 44100;
1775 break;
1776
1777 case 6144000:
1778 case 12288000:
11c2b5f2 1779 case 24576000:
6d4baf08
MB		 1780 audio_rate = 48000;
1781 break;
1782
1783 default:
1784 BUG();
1785 audio_rate = 0;
1786 break;
1787 }
1788
1789 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1790 * match.
1791 */
1792
1793 snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1794 WM5100_SYSCLK_SRC_MASK,
1795 fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1796
1797 /* If this is SYSCLK then configure the clock rate for the
1798 * internal audio functions to the natural sample rate for
1799 * this clock rate.
1800 */
1801 if (clk_id == WM5100_CLK_SYSCLK) {
1802 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1803 audio_rate);
1804 if (0 && *rate_store)
1805 wm5100_free_sr(codec, audio_rate);
1806 ret = wm5100_alloc_sr(codec, audio_rate);
1807 if (ret != 0)
1808 dev_warn(codec->dev, "Primary audio slot is %d\n",
1809 ret);
1810 }
1811
1812 *rate_store = freq;
1813
1814 return 0;
1815}
1816
1817struct _fll_div {
1818 u16 fll_fratio;
1819 u16 fll_outdiv;
1820 u16 fll_refclk_div;
1821 u16 n;
1822 u16 theta;
1823 u16 lambda;
1824};
1825
1826static struct {
1827 unsigned int min;
1828 unsigned int max;
1829 u16 fll_fratio;
1830 int ratio;
1831} fll_fratios[] = {
1832 { 0, 64000, 4, 16 },
1833 { 64000, 128000, 3, 8 },
1834 { 128000, 256000, 2, 4 },
1835 { 256000, 1000000, 1, 2 },
1836 { 1000000, 13500000, 0, 1 },
1837};
1838
1839static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1840 unsigned int Fout)
1841{
1842 unsigned int target;
1843 unsigned int div;
1844 unsigned int fratio, gcd_fll;
1845 int i;
1846
1847 /* Fref must be <=13.5MHz */
1848 div = 1;
1849 fll_div->fll_refclk_div = 0;
1850 while ((Fref / div) > 13500000) {
1851 div *= 2;
1852 fll_div->fll_refclk_div++;
1853
1854 if (div > 8) {
1855 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1856 Fref);
1857 return -EINVAL;
1858 }
1859 }
1860
1861 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1862
1863 /* Apply the division for our remaining calculations */
1864 Fref /= div;
1865
1866 /* Fvco should be 90-100MHz; don't check the upper bound */
1867 div = 2;
1868 while (Fout * div < 90000000) {
1869 div++;
1870 if (div > 64) {
1871 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1872 Fout);
1873 return -EINVAL;
1874 }
1875 }
1876 target = Fout * div;
1877 fll_div->fll_outdiv = div - 1;
1878
1879 pr_debug("FLL Fvco=%dHz\n", target);
1880
1881 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1882 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1883 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1884 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1885 fratio = fll_fratios[i].ratio;
1886 break;
1887 }
1888 }
1889 if (i == ARRAY_SIZE(fll_fratios)) {
1890 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1891 return -EINVAL;
1892 }
1893
1894 fll_div->n = target / (fratio * Fref);
1895
1896 if (target % Fref == 0) {
1897 fll_div->theta = 0;
1898 fll_div->lambda = 0;
1899 } else {
1900 gcd_fll = gcd(target, fratio * Fref);
1901
1902 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1903 / gcd_fll;
1904 fll_div->lambda = (fratio * Fref) / gcd_fll;
1905 }
1906
1907 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1908 fll_div->n, fll_div->theta, fll_div->lambda);
1909 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1910 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1911 fll_div->fll_refclk_div);
1912
1913 return 0;
1914}
1915
1916static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1917 unsigned int Fref, unsigned int Fout)
1918{
1919 struct i2c_client *i2c = to_i2c_client(codec->dev);
1920 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1921 struct _fll_div factors;
1922 struct wm5100_fll *fll;
1923 int ret, base, lock, i, timeout;
1924
1925 switch (fll_id) {
1926 case WM5100_FLL1:
1927 fll = &wm5100->fll[0];
1928 base = WM5100_FLL1_CONTROL_1 - 1;
1929 lock = WM5100_FLL1_LOCK_STS;
1930 break;
1931 case WM5100_FLL2:
1932 fll = &wm5100->fll[1];
1933 base = WM5100_FLL2_CONTROL_2 - 1;
1934 lock = WM5100_FLL2_LOCK_STS;
1935 break;
1936 default:
1937 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1938 return -EINVAL;
1939 }
1940
1941 if (!Fout) {
1942 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1943 fll->fout = 0;
1944 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1945 return 0;
1946 }
1947
1948 switch (source) {
1949 case WM5100_FLL_SRC_MCLK1:
1950 case WM5100_FLL_SRC_MCLK2:
1951 case WM5100_FLL_SRC_FLL1:
1952 case WM5100_FLL_SRC_FLL2:
1953 case WM5100_FLL_SRC_AIF1BCLK:
1954 case WM5100_FLL_SRC_AIF2BCLK:
1955 case WM5100_FLL_SRC_AIF3BCLK:
1956 break;
1957 default:
1958 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1959 return -EINVAL;
1960 }
1961
1962 ret = fll_factors(&factors, Fref, Fout);
1963 if (ret < 0)
1964 return ret;
1965
1966 /* Disable the FLL while we reconfigure */
1967 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1968
1969 snd_soc_update_bits(codec, base + 2,
1970 WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1971 (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1972 factors.fll_fratio);
1973 snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1974 factors.theta);
1975 snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1976 snd_soc_update_bits(codec, base + 6,
1977 WM5100_FLL1_REFCLK_DIV_MASK |
1978 WM5100_FLL1_REFCLK_SRC_MASK,
1979 (factors.fll_refclk_div
1980 << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1981 snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1982 factors.lambda);
1983
1984 /* Clear any pending completions */
1985 try_wait_for_completion(&fll->lock);
1986
1987 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1988
1989 if (i2c->irq)
1990 timeout = 2;
1991 else
1992 timeout = 50;
1993
bd132ec5
MB		 1994 snd_soc_update_bits(codec, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
1995 WM5100_SYSCLK_ENA);
1996
6d4baf08
MB		 1997 /* Poll for the lock; will use interrupt when we can test */
1998 for (i = 0; i < timeout; i++) {
1999 if (i2c->irq) {
2000 ret = wait_for_completion_timeout(&fll->lock,
2001 msecs_to_jiffies(25));
2002 if (ret > 0)
2003 break;
2004 } else {
2005 msleep(1);
2006 }
2007
2008 ret = snd_soc_read(codec,
2009 WM5100_INTERRUPT_RAW_STATUS_3);
2010 if (ret < 0) {
2011 dev_err(codec->dev,
2012 "Failed to read FLL status: %d\n",
2013 ret);
2014 continue;
2015 }
2016 if (ret & lock)
2017 break;
2018 }
2019 if (i == timeout) {
2020 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
2021 return -ETIMEDOUT;
2022 }
2023
2024 fll->src = source;
2025 fll->fref = Fref;
2026 fll->fout = Fout;
2027
2028 dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
2029 Fref, Fout);
2030
2031 return 0;
2032}
2033
2034/* Actually go much higher */
2035#define WM5100_RATES SNDRV_PCM_RATE_8000_192000
2036
2037#define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2038 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2039
2040static struct snd_soc_dai_driver wm5100_dai[] = {
2041 {
2042 .name = "wm5100-aif1",
2043 .playback = {
2044 .stream_name = "AIF1 Playback",
2045 .channels_min = 2,
2046 .channels_max = 2,
2047 .rates = WM5100_RATES,
2048 .formats = WM5100_FORMATS,
2049 },
2050 .capture = {
2051 .stream_name = "AIF1 Capture",
2052 .channels_min = 2,
2053 .channels_max = 2,
2054 .rates = WM5100_RATES,
2055 .formats = WM5100_FORMATS,
2056 },
2057 .ops = &wm5100_dai_ops,
2058 },
2059 {
2060 .name = "wm5100-aif2",
2061 .id = 1,
2062 .playback = {
2063 .stream_name = "AIF2 Playback",
2064 .channels_min = 2,
2065 .channels_max = 2,
2066 .rates = WM5100_RATES,
2067 .formats = WM5100_FORMATS,
2068 },
2069 .capture = {
2070 .stream_name = "AIF2 Capture",
2071 .channels_min = 2,
2072 .channels_max = 2,
2073 .rates = WM5100_RATES,
2074 .formats = WM5100_FORMATS,
2075 },
2076 .ops = &wm5100_dai_ops,
2077 },
2078 {
2079 .name = "wm5100-aif3",
2080 .id = 2,
2081 .playback = {
2082 .stream_name = "AIF3 Playback",
2083 .channels_min = 2,
2084 .channels_max = 2,
2085 .rates = WM5100_RATES,
2086 .formats = WM5100_FORMATS,
2087 },
2088 .capture = {
2089 .stream_name = "AIF3 Capture",
2090 .channels_min = 2,
2091 .channels_max = 2,
2092 .rates = WM5100_RATES,
2093 .formats = WM5100_FORMATS,
2094 },
2095 .ops = &wm5100_dai_ops,
2096 },
2097};
2098
2099static int wm5100_dig_vu[] = {
2100 WM5100_ADC_DIGITAL_VOLUME_1L,
2101 WM5100_ADC_DIGITAL_VOLUME_1R,
2102 WM5100_ADC_DIGITAL_VOLUME_2L,
2103 WM5100_ADC_DIGITAL_VOLUME_2R,
2104 WM5100_ADC_DIGITAL_VOLUME_3L,
2105 WM5100_ADC_DIGITAL_VOLUME_3R,
2106 WM5100_ADC_DIGITAL_VOLUME_4L,
2107 WM5100_ADC_DIGITAL_VOLUME_4R,
2108
2109 WM5100_DAC_DIGITAL_VOLUME_1L,
2110 WM5100_DAC_DIGITAL_VOLUME_1R,
2111 WM5100_DAC_DIGITAL_VOLUME_2L,
2112 WM5100_DAC_DIGITAL_VOLUME_2R,
2113 WM5100_DAC_DIGITAL_VOLUME_3L,
2114 WM5100_DAC_DIGITAL_VOLUME_3R,
2115 WM5100_DAC_DIGITAL_VOLUME_4L,
2116 WM5100_DAC_DIGITAL_VOLUME_4R,
2117 WM5100_DAC_DIGITAL_VOLUME_5L,
2118 WM5100_DAC_DIGITAL_VOLUME_5R,
2119 WM5100_DAC_DIGITAL_VOLUME_6L,
2120 WM5100_DAC_DIGITAL_VOLUME_6R,
2121};
2122
ba896ede
MB		 2123static void wm5100_set_detect_mode(struct snd_soc_codec *codec, int the_mode)
2124{
2125 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2126 struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
2127
2128 BUG_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes));
2129
2130 gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
2131 snd_soc_update_bits(codec, WM5100_ACCESSORY_DETECT_MODE_1,
2132 WM5100_ACCDET_BIAS_SRC_MASK |
2133 WM5100_ACCDET_SRC,
2134 (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
2135 mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
1cba77c1
MB		 2136 snd_soc_update_bits(codec, WM5100_MISC_CONTROL,
2137 WM5100_HPCOM_SRC,
2138 mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
ba896ede
MB		 2139
2140 wm5100->jack_mode = the_mode;
2141
2142 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2143 wm5100->jack_mode);
2144}
2145
2146static void wm5100_micd_irq(struct snd_soc_codec *codec)
2147{
2148 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2149 int val;
2150
2151 val = snd_soc_read(codec, WM5100_MIC_DETECT_3);
2152
2153 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2154
2155 if (!(val & WM5100_ACCDET_VALID)) {
2156 dev_warn(codec->dev, "Microphone detection state invalid\n");
2157 return;
2158 }
2159
2160 /* No accessory, reset everything and report removal */
2161 if (!(val & WM5100_ACCDET_STS)) {
2162 dev_dbg(codec->dev, "Jack removal detected\n");
2163 wm5100->jack_mic = false;
2164 wm5100->jack_detecting = true;
2165 snd_soc_jack_report(wm5100->jack, 0,
2166 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2167 SND_JACK_BTN_0);
2168
2169 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2170 WM5100_ACCDET_RATE_MASK,
2171 WM5100_ACCDET_RATE_MASK);
2172 return;
2173 }
2174
2175 /* If the measurement is very high we've got a microphone,
2176 * either we just detected one or if we already reported then
2177 * we've got a button release event.
2178 */
2179 if (val & 0x400) {
2180 if (wm5100->jack_detecting) {
2181 dev_dbg(codec->dev, "Microphone detected\n");
2182 wm5100->jack_mic = true;
2183 snd_soc_jack_report(wm5100->jack,
2184 SND_JACK_HEADSET,
2185 SND_JACK_HEADSET | SND_JACK_BTN_0);
2186
2187 /* Increase poll rate to give better responsiveness
2188 * for buttons */
2189 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2190 WM5100_ACCDET_RATE_MASK,
2191 5 << WM5100_ACCDET_RATE_SHIFT);
2192 } else {
2193 dev_dbg(codec->dev, "Mic button up\n");
2194 snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2195 }
2196
2197 return;
2198 }
2199
2200 /* If we detected a lower impedence during initial startup
2201 * then we probably have the wrong polarity, flip it. Don't
2202 * do this for the lowest impedences to speed up detection of
2203 * plain headphones.
2204 */
2205 if (wm5100->jack_detecting && (val & 0x3f8)) {
2206 wm5100_set_detect_mode(codec, !wm5100->jack_mode);
2207
2208 return;
2209 }
2210
2211 /* Don't distinguish between buttons, just report any low
2212 * impedence as BTN_0.
2213 */
2214 if (val & 0x3fc) {
2215 if (wm5100->jack_mic) {
2216 dev_dbg(codec->dev, "Mic button detected\n");
2217 snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2218 SND_JACK_BTN_0);
2219 } else if (wm5100->jack_detecting) {
2220 dev_dbg(codec->dev, "Headphone detected\n");
2221 snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
2222 SND_JACK_HEADPHONE);
2223
2224 /* Increase the detection rate a bit for
2225 * responsiveness.
2226 */
2227 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2228 WM5100_ACCDET_RATE_MASK,
2229 7 << WM5100_ACCDET_RATE_SHIFT);
2230 }
2231 }
2232}
2233
2234int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2235{
2236 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2237
2238 if (jack) {
2239 wm5100->jack = jack;
2240 wm5100->jack_detecting = true;
2241
2242 wm5100_set_detect_mode(codec, 0);
2243
2244 /* Slowest detection rate, gives debounce for initial
2245 * detection */
2246 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2247 WM5100_ACCDET_BIAS_STARTTIME_MASK |
2248 WM5100_ACCDET_RATE_MASK,
2249 (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2250 WM5100_ACCDET_RATE_MASK);
2251
2252 /* We need the charge pump to power MICBIAS */
2253 snd_soc_dapm_force_enable_pin(&codec->dapm, "CP2");
2254 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2255 snd_soc_dapm_sync(&codec->dapm);
2256
2257 /* We start off just enabling microphone detection - even a
2258 * plain headphone will trigger detection.
2259 */
2260 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2261 WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2262
2263 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2264 WM5100_IM_ACCDET_EINT, 0);
2265 } else {
2266 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2267 WM5100_IM_HPDET_EINT |
2268 WM5100_IM_ACCDET_EINT,
2269 WM5100_IM_HPDET_EINT |
2270 WM5100_IM_ACCDET_EINT);
2271 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2272 WM5100_ACCDET_ENA, 0);
2273 wm5100->jack = NULL;
2274 }
2275
2276 return 0;
2277}
2278
6d4baf08
MB		 2279static irqreturn_t wm5100_irq(int irq, void *data)
2280{
2281 struct snd_soc_codec *codec = data;
2282 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2283 irqreturn_t status = IRQ_NONE;
2284 int irq_val;
2285
2286 irq_val = snd_soc_read(codec, WM5100_INTERRUPT_STATUS_3);
2287 if (irq_val < 0) {
2288 dev_err(codec->dev, "Failed to read IRQ status 3: %d\n",
2289 irq_val);
2290 irq_val = 0;
2291 }
2292 irq_val &= ~snd_soc_read(codec, WM5100_INTERRUPT_STATUS_3_MASK);
2293
2294 snd_soc_write(codec, WM5100_INTERRUPT_STATUS_3, irq_val);
2295
2296 if (irq_val)
2297 status = IRQ_HANDLED;
2298
2299 wm5100_log_status3(codec, irq_val);
2300
2301 if (irq_val & WM5100_FLL1_LOCK_EINT) {
2302 dev_dbg(codec->dev, "FLL1 locked\n");
2303 complete(&wm5100->fll[0].lock);
2304 }
2305 if (irq_val & WM5100_FLL2_LOCK_EINT) {
2306 dev_dbg(codec->dev, "FLL2 locked\n");
2307 complete(&wm5100->fll[1].lock);
2308 }
2309
ba896ede
MB		 2310 if (irq_val & WM5100_ACCDET_EINT)
2311 wm5100_micd_irq(codec);
2312
6d4baf08
MB		 2313 irq_val = snd_soc_read(codec, WM5100_INTERRUPT_STATUS_4);
2314 if (irq_val < 0) {
2315 dev_err(codec->dev, "Failed to read IRQ status 4: %d\n",
2316 irq_val);
2317 irq_val = 0;
2318 }
2319 irq_val &= ~snd_soc_read(codec, WM5100_INTERRUPT_STATUS_4_MASK);
2320
2321 if (irq_val)
2322 status = IRQ_HANDLED;
2323
2324 snd_soc_write(codec, WM5100_INTERRUPT_STATUS_4, irq_val);
2325
2326 wm5100_log_status4(codec, irq_val);
2327
2328 return status;
2329}
2330
2331static irqreturn_t wm5100_edge_irq(int irq, void *data)
2332{
2333 irqreturn_t ret = IRQ_NONE;
2334 irqreturn_t val;
2335
2336 do {
2337 val = wm5100_irq(irq, data);
2338 if (val != IRQ_NONE)
2339 ret = val;
2340 } while (val != IRQ_NONE);
2341
2342 return ret;
2343}
2344
2345#ifdef CONFIG_GPIOLIB
2346static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2347{
2348 return container_of(chip, struct wm5100_priv, gpio_chip);
2349}
2350
2351static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2352{
2353 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
6d4baf08 2354
9db16e4c
MB		 2355 regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2356 WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
6d4baf08
MB		 2357}
2358
2359static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2360 unsigned offset, int value)
2361{
2362 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
64964e82 2363 int val, ret;
6d4baf08
MB		 2364
2365 val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2366
9db16e4c
MB		 2367 ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2368 WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2369 WM5100_GP1_LVL, val);
64964e82
MB		 2370 if (ret < 0)
2371 return ret;
2372 else
2373 return 0;
6d4baf08
MB		 2374}
2375
2376static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2377{
2378 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
9db16e4c 2379 unsigned int reg;
6d4baf08
MB		 2380 int ret;
2381
9db16e4c 2382 ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, &reg);
6d4baf08
MB		 2383 if (ret < 0)
2384 return ret;
2385
9db16e4c 2386 return (reg & WM5100_GP1_LVL) != 0;
6d4baf08
MB		 2387}
2388
2389static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2390{
2391 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
6d4baf08 2392
9db16e4c
MB		 2393 return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2394 WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2395 (1 << WM5100_GP1_FN_SHIFT) |
2396 (1 << WM5100_GP1_DIR_SHIFT));
6d4baf08
MB		 2397}
2398
2399static struct gpio_chip wm5100_template_chip = {
2400 .label = "wm5100",
2401 .owner = THIS_MODULE,
2402 .direction_output = wm5100_gpio_direction_out,
2403 .set = wm5100_gpio_set,
2404 .direction_input = wm5100_gpio_direction_in,
2405 .get = wm5100_gpio_get,
2406 .can_sleep = 1,
2407};
2408
9db16e4c 2409static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08 2410{
9db16e4c 2411 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08
MB		 2412 int ret;
2413
2414 wm5100->gpio_chip = wm5100_template_chip;
2415 wm5100->gpio_chip.ngpio = 6;
9db16e4c 2416 wm5100->gpio_chip.dev = &i2c->dev;
6d4baf08
MB		 2417
2418 if (wm5100->pdata.gpio_base)
2419 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2420 else
2421 wm5100->gpio_chip.base = -1;
2422
2423 ret = gpiochip_add(&wm5100->gpio_chip);
2424 if (ret != 0)
9db16e4c 2425 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
6d4baf08
MB		 2426}
2427
9db16e4c 2428static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08 2429{
9db16e4c 2430 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08
MB		 2431 int ret;
2432
2433 ret = gpiochip_remove(&wm5100->gpio_chip);
2434 if (ret != 0)
9db16e4c 2435 dev_err(&i2c->dev, "Failed to remove GPIOs: %d\n", ret);
6d4baf08
MB		 2436}
2437#else
9db16e4c 2438static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2439{
2440}
2441
9db16e4c 2442static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2443{
2444}
2445#endif
2446
2447static int wm5100_probe(struct snd_soc_codec *codec)
2448{
2449 struct i2c_client *i2c = to_i2c_client(codec->dev);
2450 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2451 int ret, i, irq_flags;
2452
2453 wm5100->codec = codec;
bd132ec5 2454 codec->control_data = wm5100->regmap;
6d4baf08 2455
bd132ec5 2456 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
6d4baf08
MB		 2457 if (ret != 0) {
2458 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2459 return ret;
2460 }
2461
bd132ec5 2462 regcache_cache_only(wm5100->regmap, true);
6d4baf08 2463
6d4baf08
MB		 2464
2465 for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2466 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2467 WM5100_OUT_VU);
2468
6d4baf08
MB		 2469 /* Don't debounce interrupts to support use of SYSCLK only */
2470 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2471 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2472
2473 /* TODO: check if we're symmetric */
2474
2475 if (i2c->irq) {
2476 if (wm5100->pdata.irq_flags)
2477 irq_flags = wm5100->pdata.irq_flags;
2478 else
2479 irq_flags = IRQF_TRIGGER_LOW;
2480
2481 irq_flags |= IRQF_ONESHOT;
2482
2483 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2484 ret = request_threaded_irq(i2c->irq, NULL,
2485 wm5100_edge_irq,
2486 irq_flags, "wm5100", codec);
2487 else
2488 ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2489 irq_flags, "wm5100", codec);
2490
2491 if (ret != 0) {
2492 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
2493 i2c->irq, ret);
2494 } else {
2495 /* Enable default interrupts */
2496 snd_soc_update_bits(codec,
2497 WM5100_INTERRUPT_STATUS_3_MASK,
2498 WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2499 WM5100_IM_SPK_SHUTDOWN_EINT |
2500 WM5100_IM_ASRC2_LOCK_EINT |
2501 WM5100_IM_ASRC1_LOCK_EINT |
2502 WM5100_IM_FLL2_LOCK_EINT |
2503 WM5100_IM_FLL1_LOCK_EINT |
2504 WM5100_CLKGEN_ERR_EINT |
2505 WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2506
2507 snd_soc_update_bits(codec,
2508 WM5100_INTERRUPT_STATUS_4_MASK,
2509 WM5100_AIF3_ERR_EINT |
2510 WM5100_AIF2_ERR_EINT |
2511 WM5100_AIF1_ERR_EINT |
2512 WM5100_CTRLIF_ERR_EINT |
2513 WM5100_ISRC2_UNDERCLOCKED_EINT |
2514 WM5100_ISRC1_UNDERCLOCKED_EINT |
2515 WM5100_FX_UNDERCLOCKED_EINT |
2516 WM5100_AIF3_UNDERCLOCKED_EINT |
2517 WM5100_AIF2_UNDERCLOCKED_EINT |
2518 WM5100_AIF1_UNDERCLOCKED_EINT |
2519 WM5100_ASRC_UNDERCLOCKED_EINT |
2520 WM5100_DAC_UNDERCLOCKED_EINT |
2521 WM5100_ADC_UNDERCLOCKED_EINT |
2522 WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2523 }
2524 } else {
2525 snd_soc_dapm_new_controls(&codec->dapm,
2526 wm5100_dapm_widgets_noirq,
2527 ARRAY_SIZE(wm5100_dapm_widgets_noirq));
2528 }
2529
2530 if (wm5100->pdata.hp_pol) {
2531 ret = gpio_request_one(wm5100->pdata.hp_pol,
2532 GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2533 if (ret < 0) {
2534 dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2535 wm5100->pdata.hp_pol, ret);
2536 goto err_gpio;
2537 }
2538 }
2539
2540 /* We'll get woken up again when the system has something useful
2541 * for us to do.
2542 */
2543 if (wm5100->pdata.ldo_ena)
2544 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2545 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2546 wm5100->core_supplies);
2547
2548 return 0;
2549
2550err_gpio:
0a742681
AL		 2551 if (i2c->irq)
2552 free_irq(i2c->irq, codec);
6d4baf08
MB		 2553
2554 return ret;
2555}
2556
2557static int wm5100_remove(struct snd_soc_codec *codec)
2558{
2559 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
0a742681 2560 struct i2c_client *i2c = to_i2c_client(codec->dev);
6d4baf08
MB		 2561
2562 wm5100_set_bias_level(codec, SND_SOC_BIAS_OFF);
2563 if (wm5100->pdata.hp_pol) {
2564 gpio_free(wm5100->pdata.hp_pol);
2565 }
0a742681
AL		 2566 if (i2c->irq)
2567 free_irq(i2c->irq, codec);
6d4baf08
MB		 2568 return 0;
2569}
2570
1b39bf34
MB		 2571static int wm5100_soc_volatile(struct snd_soc_codec *codec,
2572 unsigned int reg)
2573{
2574 return true;
2575}
2576
2577
6d4baf08
MB		 2578static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2579 .probe = wm5100_probe,
2580 .remove = wm5100_remove,
2581
2582 .set_sysclk = wm5100_set_sysclk,
2583 .set_pll = wm5100_set_fll,
2584 .set_bias_level = wm5100_set_bias_level,
2585 .idle_bias_off = 1,
1b39bf34
MB		 2586 .reg_cache_size = WM5100_MAX_REGISTER,
2587 .volatile_register = wm5100_soc_volatile,
6d4baf08
MB		 2588
2589 .seq_notifier = wm5100_seq_notifier,
2590 .controls = wm5100_snd_controls,
2591 .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2592 .dapm_widgets = wm5100_dapm_widgets,
2593 .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2594 .dapm_routes = wm5100_dapm_routes,
2595 .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
bd132ec5 2596};
6d4baf08 2597
bd132ec5
MB		 2598static const struct regmap_config wm5100_regmap = {
2599 .reg_bits = 16,
2600 .val_bits = 16,
6d4baf08 2601
bd132ec5
MB		 2602 .max_register = WM5100_MAX_REGISTER,
2603 .reg_defaults = wm5100_reg_defaults,
2604 .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2605 .volatile_reg = wm5100_volatile_register,
2606 .readable_reg = wm5100_readable_register,
2607 .cache_type = REGCACHE_RBTREE,
6d4baf08
MB		 2608};
2609
2610static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2611 const struct i2c_device_id *id)
2612{
2613 struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2614 struct wm5100_priv *wm5100;
588ac5e0 2615 unsigned int reg;
6d4baf08
MB		 2616 int ret, i;
2617
a81b82c0
MB		 2618 wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2619 GFP_KERNEL);
6d4baf08
MB		 2620 if (wm5100 == NULL)
2621 return -ENOMEM;
2622
bd132ec5
MB		 2623 wm5100->regmap = regmap_init_i2c(i2c, &wm5100_regmap);
2624 if (IS_ERR(wm5100->regmap)) {
2625 ret = PTR_ERR(wm5100->regmap);
2626 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2627 ret);
a81b82c0 2628 goto err;
bd132ec5
MB		 2629 }
2630
6d4baf08
MB		 2631 for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2632 init_completion(&wm5100->fll[i].lock);
2633
2634 if (pdata)
2635 wm5100->pdata = *pdata;
2636
2637 i2c_set_clientdata(i2c, wm5100);
2638
588ac5e0
MB		 2639 for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2640 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2641
2642 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm5100->core_supplies),
2643 wm5100->core_supplies);
2644 if (ret != 0) {
2645 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2646 ret);
2647 goto err_regmap;
2648 }
2649
2650 wm5100->cpvdd = regulator_get(&i2c->dev, "CPVDD");
2651 if (IS_ERR(wm5100->cpvdd)) {
2652 ret = PTR_ERR(wm5100->cpvdd);
2653 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
2654 goto err_core;
2655 }
2656
2657 wm5100->dbvdd2 = regulator_get(&i2c->dev, "DBVDD2");
2658 if (IS_ERR(wm5100->dbvdd2)) {
2659 ret = PTR_ERR(wm5100->dbvdd2);
2660 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2661 goto err_cpvdd;
2662 }
2663
2664 wm5100->dbvdd3 = regulator_get(&i2c->dev, "DBVDD3");
2665 if (IS_ERR(wm5100->dbvdd3)) {
2666 ret = PTR_ERR(wm5100->dbvdd3);
2667 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2668 goto err_dbvdd2;
2669 }
2670
2671 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2672 wm5100->core_supplies);
2673 if (ret != 0) {
2674 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2675 ret);
2676 goto err_dbvdd3;
2677 }
2678
2679 if (wm5100->pdata.ldo_ena) {
2680 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2681 GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2682 if (ret < 0) {
2683 dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2684 wm5100->pdata.ldo_ena, ret);
2685 goto err_enable;
2686 }
2687 msleep(2);
2688 }
2689
2690 if (wm5100->pdata.reset) {
2691 ret = gpio_request_one(wm5100->pdata.reset,
2692 GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2693 if (ret < 0) {
2694 dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2695 wm5100->pdata.reset, ret);
2696 goto err_ldo;
2697 }
2698 }
2699
2700 ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, &reg);
2701 if (ret < 0) {
2702 dev_err(&i2c->dev, "Failed to read ID register\n");
2703 goto err_reset;
2704 }
2705 switch (reg) {
2706 case 0x8997:
2707 case 0x5100:
2708 break;
2709
2710 default:
2711 dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2712 ret = -EINVAL;
2713 goto err_reset;
2714 }
2715
2716 ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, &reg);
2717 if (ret < 0) {
2718 dev_err(&i2c->dev, "Failed to read revision register\n");
2719 goto err_reset;
2720 }
2721 wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2722
2723 dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2724
2725 ret = wm5100_reset(wm5100);
2726 if (ret < 0) {
2727 dev_err(&i2c->dev, "Failed to issue reset\n");
2728 goto err_reset;
2729 }
2730
9db16e4c
MB		 2731 wm5100_init_gpio(i2c);
2732
d9b5e9c6
MB		 2733 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2734 if (!wm5100->pdata.gpio_defaults[i])
2735 continue;
2736
2737 regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2738 wm5100->pdata.gpio_defaults[i]);
2739 }
2740
2741 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2742 regmap_update_bits(wm5100->regmap, WM5100_IN1L_CONTROL,
2743 WM5100_IN1_MODE_MASK |
2744 WM5100_IN1_DMIC_SUP_MASK,
2745 (wm5100->pdata.in_mode[i] <<
2746 WM5100_IN1_MODE_SHIFT) |
2747 (wm5100->pdata.dmic_sup[i] <<
2748 WM5100_IN1_DMIC_SUP_SHIFT));
2749 }
2750
6d4baf08
MB		 2751 ret = snd_soc_register_codec(&i2c->dev,
2752 &soc_codec_dev_wm5100, wm5100_dai,
2753 ARRAY_SIZE(wm5100_dai));
2754 if (ret < 0) {
2755 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
588ac5e0 2756 goto err_reset;
6d4baf08
MB		 2757 }
2758
2759 return ret;
bd132ec5 2760
588ac5e0 2761err_reset:
9db16e4c 2762 wm5100_free_gpio(i2c);
588ac5e0
MB		 2763 if (wm5100->pdata.reset) {
2764 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
2765 gpio_free(wm5100->pdata.reset);
2766 }
2767err_ldo:
2768 if (wm5100->pdata.ldo_ena) {
2769 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2770 gpio_free(wm5100->pdata.ldo_ena);
2771 }
2772err_enable:
2773 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2774 wm5100->core_supplies);
2775err_dbvdd3:
2776 regulator_put(wm5100->dbvdd3);
2777err_dbvdd2:
2778 regulator_put(wm5100->dbvdd2);
2779err_cpvdd:
2780 regulator_put(wm5100->cpvdd);
2781err_core:
2782 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2783 wm5100->core_supplies);
bd132ec5
MB		 2784err_regmap:
2785 regmap_exit(wm5100->regmap);
a81b82c0 2786err:
bd132ec5 2787 return ret;
6d4baf08
MB		 2788}
2789
2790static __devexit int wm5100_i2c_remove(struct i2c_client *client)
2791{
bd132ec5
MB		 2792 struct wm5100_priv *wm5100 = i2c_get_clientdata(client);
2793
6d4baf08 2794 snd_soc_unregister_codec(&client->dev);
9db16e4c 2795 wm5100_free_gpio(client);
588ac5e0
MB		 2796 if (wm5100->pdata.reset) {
2797 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
2798 gpio_free(wm5100->pdata.reset);
2799 }
2800 if (wm5100->pdata.ldo_ena) {
2801 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2802 gpio_free(wm5100->pdata.ldo_ena);
2803 }
2804 regulator_put(wm5100->dbvdd3);
2805 regulator_put(wm5100->dbvdd2);
2806 regulator_put(wm5100->cpvdd);
2807 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2808 wm5100->core_supplies);
bd132ec5 2809 regmap_exit(wm5100->regmap);
bd132ec5 2810
6d4baf08
MB		 2811 return 0;
2812}
2813
2814static const struct i2c_device_id wm5100_i2c_id[] = {
2815 { "wm5100", 0 },
2816 { }
2817};
2818MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2819
2820static struct i2c_driver wm5100_i2c_driver = {
2821 .driver = {
2822 .name = "wm5100",
2823 .owner = THIS_MODULE,
2824 },
2825 .probe = wm5100_i2c_probe,
2826 .remove = __devexit_p(wm5100_i2c_remove),
2827 .id_table = wm5100_i2c_id,
2828};
2829
2830static int __init wm5100_modinit(void)
2831{
2832 return i2c_add_driver(&wm5100_i2c_driver);
2833}
2834module_init(wm5100_modinit);
2835
2836static void __exit wm5100_exit(void)
2837{
2838 i2c_del_driver(&wm5100_i2c_driver);
2839}
2840module_exit(wm5100_exit);
2841
2842MODULE_DESCRIPTION("ASoC WM5100 driver");
2843MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2844MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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