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Merge tag 'regmap-patch-initial' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / sound / soc / codecs / wm5100.c
CommitLineData
6d4baf08
MB		 1/*
2 * wm5100.c -- WM5100 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/gcd.h>
19#include <linux/gpio.h>
20#include <linux/i2c.h>
6d4baf08
MB		 21#include <linux/regulator/consumer.h>
22#include <linux/regulator/fixed.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
ba896ede 28#include <sound/jack.h>
6d4baf08
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <sound/wm5100.h>
32
33#include "wm5100.h"
34
35#define WM5100_NUM_CORE_SUPPLIES 2
36static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
37 "DBVDD1",
38 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
39};
40
41#define WM5100_AIFS 3
42#define WM5100_SYNC_SRS 3
43
44struct wm5100_fll {
45 int fref;
46 int fout;
47 int src;
48 struct completion lock;
49};
50
51/* codec private data */
52struct wm5100_priv {
46c1a877 53 struct device *dev;
bd132ec5 54 struct regmap *regmap;
6d4baf08
MB		 55 struct snd_soc_codec *codec;
56
57 struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
58 struct regulator *cpvdd;
7aefb086
MB		 59 struct regulator *dbvdd2;
60 struct regulator *dbvdd3;
6d4baf08
MB		 61
62 int rev;
63
64 int sysclk;
65 int asyncclk;
66
67 bool aif_async[WM5100_AIFS];
68 bool aif_symmetric[WM5100_AIFS];
69 int sr_ref[WM5100_SYNC_SRS];
70
71 bool out_ena[2];
72
ba896ede
MB		 73 struct snd_soc_jack *jack;
74 bool jack_detecting;
75 bool jack_mic;
76 int jack_mode;
77
6d4baf08
MB		 78 struct wm5100_fll fll[2];
79
80 struct wm5100_pdata pdata;
81
82#ifdef CONFIG_GPIOLIB
83 struct gpio_chip gpio_chip;
84#endif
85};
86
87static int wm5100_sr_code[] = {
88 0,
89 12000,
90 24000,
91 48000,
92 96000,
93 192000,
94 384000,
95 768000,
96 0,
97 11025,
98 22050,
99 44100,
100 88200,
101 176400,
102 352800,
103 705600,
104 4000,
105 8000,
106 16000,
107 32000,
108 64000,
109 128000,
110 256000,
111 512000,
112};
113
114static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
115 WM5100_CLOCKING_4,
116 WM5100_CLOCKING_5,
117 WM5100_CLOCKING_6,
118};
119
120static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
121{
122 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
123 int sr_code, sr_free, i;
124
125 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
126 if (wm5100_sr_code[i] == rate)
127 break;
128 if (i == ARRAY_SIZE(wm5100_sr_code)) {
129 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
130 return -EINVAL;
131 }
132 sr_code = i;
133
134 if ((wm5100->sysclk % rate) == 0) {
135 /* Is this rate already in use? */
136 sr_free = -1;
137 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
138 if (!wm5100->sr_ref[i] && sr_free == -1) {
139 sr_free = i;
140 continue;
141 }
142 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
143 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
144 break;
145 }
146
147 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
148 wm5100->sr_ref[i]++;
149 dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
150 rate, i, wm5100->sr_ref[i]);
151 return i;
152 }
153
154 if (sr_free == -1) {
155 dev_err(codec->dev, "All SR slots already in use\n");
156 return -EBUSY;
157 }
158
159 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
160 sr_free, rate);
161 wm5100->sr_ref[sr_free]++;
162 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
163 WM5100_SAMPLE_RATE_1_MASK,
164 sr_code);
165
166 return sr_free;
167
168 } else {
169 dev_err(codec->dev,
170 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
171 rate, wm5100->sysclk, wm5100->asyncclk);
172 return -EINVAL;
173 }
174}
175
176static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
177{
178 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
179 int i, sr_code;
180
181 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
182 if (wm5100_sr_code[i] == rate)
183 break;
184 if (i == ARRAY_SIZE(wm5100_sr_code)) {
185 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
186 return;
187 }
188 sr_code = wm5100_sr_code[i];
189
190 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
191 if (!wm5100->sr_ref[i])
192 continue;
193
194 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
195 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
196 break;
197 }
198 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
199 wm5100->sr_ref[i]--;
200 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
201 rate, wm5100->sr_ref[i]);
202 } else {
203 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
204 rate);
205 }
206}
207
588ac5e0 208static int wm5100_reset(struct wm5100_priv *wm5100)
6d4baf08 209{
6d4baf08
MB		 210 if (wm5100->pdata.reset) {
211 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
212 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
213
214 return 0;
215 } else {
588ac5e0 216 return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
6d4baf08
MB		 217 }
218}
219
220static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
221static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
222static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
223static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
224static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
225
226static const char *wm5100_mixer_texts[] = {
227 "None",
228 "Tone Generator 1",
229 "Tone Generator 2",
230 "AEC loopback",
231 "IN1L",
232 "IN1R",
233 "IN2L",
234 "IN2R",
235 "IN3L",
236 "IN3R",
237 "IN4L",
238 "IN4R",
239 "AIF1RX1",
240 "AIF1RX2",
241 "AIF1RX3",
242 "AIF1RX4",
243 "AIF1RX5",
244 "AIF1RX6",
245 "AIF1RX7",
246 "AIF1RX8",
247 "AIF2RX1",
248 "AIF2RX2",
249 "AIF3RX1",
250 "AIF3RX2",
251 "EQ1",
252 "EQ2",
253 "EQ3",
254 "EQ4",
255 "DRC1L",
256 "DRC1R",
257 "LHPF1",
258 "LHPF2",
259 "LHPF3",
260 "LHPF4",
261 "DSP1.1",
262 "DSP1.2",
263 "DSP1.3",
264 "DSP1.4",
265 "DSP1.5",
266 "DSP1.6",
267 "DSP2.1",
268 "DSP2.2",
269 "DSP2.3",
270 "DSP2.4",
271 "DSP2.5",
272 "DSP2.6",
273 "DSP3.1",
274 "DSP3.2",
275 "DSP3.3",
276 "DSP3.4",
277 "DSP3.5",
278 "DSP3.6",
279 "ASRC1L",
280 "ASRC1R",
281 "ASRC2L",
282 "ASRC2R",
283 "ISRC1INT1",
284 "ISRC1INT2",
285 "ISRC1INT3",
286 "ISRC1INT4",
287 "ISRC2INT1",
288 "ISRC2INT2",
289 "ISRC2INT3",
290 "ISRC2INT4",
291 "ISRC1DEC1",
292 "ISRC1DEC2",
293 "ISRC1DEC3",
294 "ISRC1DEC4",
295 "ISRC2DEC1",
296 "ISRC2DEC2",
297 "ISRC2DEC3",
298 "ISRC2DEC4",
299};
300
301static int wm5100_mixer_values[] = {
302 0x00,
303 0x04, /* Tone */
304 0x05,
305 0x08, /* AEC */
306 0x10, /* Input */
307 0x11,
308 0x12,
309 0x13,
310 0x14,
311 0x15,
312 0x16,
313 0x17,
314 0x20, /* AIF */
315 0x21,
316 0x22,
317 0x23,
318 0x24,
319 0x25,
320 0x26,
321 0x27,
322 0x28,
323 0x29,
324 0x30, /* AIF3 - check */
325 0x31,
326 0x50, /* EQ */
327 0x51,
328 0x52,
329 0x53,
330 0x54,
331 0x58, /* DRC */
332 0x59,
333 0x60, /* LHPF1 */
334 0x61, /* LHPF2 */
335 0x62, /* LHPF3 */
336 0x63, /* LHPF4 */
337 0x68, /* DSP1 */
338 0x69,
339 0x6a,
340 0x6b,
341 0x6c,
342 0x6d,
343 0x70, /* DSP2 */
344 0x71,
345 0x72,
346 0x73,
347 0x74,
348 0x75,
349 0x78, /* DSP3 */
350 0x79,
351 0x7a,
352 0x7b,
353 0x7c,
354 0x7d,
355 0x90, /* ASRC1 */
356 0x91,
357 0x92, /* ASRC2 */
358 0x93,
359 0xa0, /* ISRC1DEC1 */
360 0xa1,
361 0xa2,
362 0xa3,
363 0xa4, /* ISRC1INT1 */
364 0xa5,
365 0xa6,
366 0xa7,
367 0xa8, /* ISRC2DEC1 */
368 0xa9,
369 0xaa,
370 0xab,
371 0xac, /* ISRC2INT1 */
372 0xad,
373 0xae,
374 0xaf,
375};
376
377#define WM5100_MIXER_CONTROLS(name, base) \
378 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
379 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
380 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
381 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
382 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
383 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
384 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
385 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
386
387#define WM5100_MUX_ENUM_DECL(name, reg) \
388 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
389 wm5100_mixer_texts, wm5100_mixer_values)
390
391#define WM5100_MUX_CTL_DECL(name) \
392 const struct snd_kcontrol_new name##_mux = \
393 SOC_DAPM_VALUE_ENUM("Route", name##_enum)
394
395#define WM5100_MIXER_ENUMS(name, base_reg) \
396 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
397 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
398 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
399 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
400 static WM5100_MUX_CTL_DECL(name##_in1); \
401 static WM5100_MUX_CTL_DECL(name##_in2); \
402 static WM5100_MUX_CTL_DECL(name##_in3); \
403 static WM5100_MUX_CTL_DECL(name##_in4)
404
405WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
406WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
407WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
408WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
409WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
410WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
411
412WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
413WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
414WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
415WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
416WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
417WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
418
419WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
420WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
421
422WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
423WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
424WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
425WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
426WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
427WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
428WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
429WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
430
431WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
432WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
433
434WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
435WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
436
437WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
438WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
439WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
440WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
441
442WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
443WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
444
445WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
446WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
447WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
448WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
449
450#define WM5100_MUX(name, ctrl) \
451 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
452
453#define WM5100_MIXER_WIDGETS(name, name_str) \
454 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
455 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
456 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
457 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
458 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
459
460#define WM5100_MIXER_INPUT_ROUTES(name) \
461 { name, "Tone Generator 1", "Tone Generator 1" }, \
462 { name, "Tone Generator 2", "Tone Generator 2" }, \
463 { name, "IN1L", "IN1L PGA" }, \
464 { name, "IN1R", "IN1R PGA" }, \
465 { name, "IN2L", "IN2L PGA" }, \
466 { name, "IN2R", "IN2R PGA" }, \
467 { name, "IN3L", "IN3L PGA" }, \
468 { name, "IN3R", "IN3R PGA" }, \
469 { name, "IN4L", "IN4L PGA" }, \
470 { name, "IN4R", "IN4R PGA" }, \
471 { name, "AIF1RX1", "AIF1RX1" }, \
472 { name, "AIF1RX2", "AIF1RX2" }, \
473 { name, "AIF1RX3", "AIF1RX3" }, \
474 { name, "AIF1RX4", "AIF1RX4" }, \
475 { name, "AIF1RX5", "AIF1RX5" }, \
476 { name, "AIF1RX6", "AIF1RX6" }, \
477 { name, "AIF1RX7", "AIF1RX7" }, \
478 { name, "AIF1RX8", "AIF1RX8" }, \
479 { name, "AIF2RX1", "AIF2RX1" }, \
480 { name, "AIF2RX2", "AIF2RX2" }, \
481 { name, "AIF3RX1", "AIF3RX1" }, \
482 { name, "AIF3RX2", "AIF3RX2" }, \
483 { name, "EQ1", "EQ1" }, \
484 { name, "EQ2", "EQ2" }, \
485 { name, "EQ3", "EQ3" }, \
486 { name, "EQ4", "EQ4" }, \
487 { name, "DRC1L", "DRC1L" }, \
488 { name, "DRC1R", "DRC1R" }, \
489 { name, "LHPF1", "LHPF1" }, \
490 { name, "LHPF2", "LHPF2" }, \
491 { name, "LHPF3", "LHPF3" }, \
492 { name, "LHPF4", "LHPF4" }
493
494#define WM5100_MIXER_ROUTES(widget, name) \
495 { widget, NULL, name " Mixer" }, \
496 { name " Mixer", NULL, name " Input 1" }, \
497 { name " Mixer", NULL, name " Input 2" }, \
498 { name " Mixer", NULL, name " Input 3" }, \
499 { name " Mixer", NULL, name " Input 4" }, \
500 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
501 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
502 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
503 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
504
505static const char *wm5100_lhpf_mode_text[] = {
506 "Low-pass", "High-pass"
507};
508
509static const struct soc_enum wm5100_lhpf1_mode =
510 SOC_ENUM_SINGLE(WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT, 2,
511 wm5100_lhpf_mode_text);
512
513static const struct soc_enum wm5100_lhpf2_mode =
514 SOC_ENUM_SINGLE(WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT, 2,
515 wm5100_lhpf_mode_text);
516
517static const struct soc_enum wm5100_lhpf3_mode =
518 SOC_ENUM_SINGLE(WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT, 2,
519 wm5100_lhpf_mode_text);
520
521static const struct soc_enum wm5100_lhpf4_mode =
522 SOC_ENUM_SINGLE(WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT, 2,
523 wm5100_lhpf_mode_text);
524
525static const struct snd_kcontrol_new wm5100_snd_controls[] = {
526SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
527 WM5100_IN1_OSR_SHIFT, 1, 0),
528SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
529 WM5100_IN2_OSR_SHIFT, 1, 0),
530SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
531 WM5100_IN3_OSR_SHIFT, 1, 0),
532SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
533 WM5100_IN4_OSR_SHIFT, 1, 0),
534
535/* Only applicable for analogue inputs */
536SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
537 WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
538SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
539 WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
540SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
541 WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
542SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
543 WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
544
545SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
546 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
547 0, digital_tlv),
548SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
549 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
550 0, digital_tlv),
551SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
552 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
553 0, digital_tlv),
554SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
555 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
556 0, digital_tlv),
557
558SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
559 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
560SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
561 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
562SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
563 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
564SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
565 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
566
567SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
568 WM5100_OUT1_OSR_SHIFT, 1, 0),
569SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
570 WM5100_OUT2_OSR_SHIFT, 1, 0),
571SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
572 WM5100_OUT3_OSR_SHIFT, 1, 0),
573SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
574 WM5100_OUT4_OSR_SHIFT, 1, 0),
575SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
576 WM5100_OUT5_OSR_SHIFT, 1, 0),
577SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
578 WM5100_OUT6_OSR_SHIFT, 1, 0),
579
580SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
581 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
582 digital_tlv),
583SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
584 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
585 digital_tlv),
586SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
587 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
588 digital_tlv),
589SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
590 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
591 digital_tlv),
592SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
593 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
594 digital_tlv),
595SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
596 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
597 digital_tlv),
598
599SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
600 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
601SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
602 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
603SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
604 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
605SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
606 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
607SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
608 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
609SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
610 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
611
612/* FIXME: Only valid from -12dB to 0dB (52-64) */
613SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
614 WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
615SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
616 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
617SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
618 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
619
620SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
621 WM5100_SPK1R_MUTE_SHIFT, 1, 1),
622SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
623 WM5100_SPK2R_MUTE_SHIFT, 1, 1),
624
625SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
626 24, 0, eq_tlv),
627SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
628 24, 0, eq_tlv),
629SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
630 24, 0, eq_tlv),
631SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
632 24, 0, eq_tlv),
633SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
634 24, 0, eq_tlv),
635
636SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
637 24, 0, eq_tlv),
638SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
639 24, 0, eq_tlv),
640SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
641 24, 0, eq_tlv),
642SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
643 24, 0, eq_tlv),
644SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
645 24, 0, eq_tlv),
646
647SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
648 24, 0, eq_tlv),
649SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
650 24, 0, eq_tlv),
651SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
652 24, 0, eq_tlv),
653SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
654 24, 0, eq_tlv),
655SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
656 24, 0, eq_tlv),
657
658SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
659 24, 0, eq_tlv),
660SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
661 24, 0, eq_tlv),
662SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
663 24, 0, eq_tlv),
664SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
665 24, 0, eq_tlv),
666SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
667 24, 0, eq_tlv),
668
669SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
670SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
671SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
672SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
673
674WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
675WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
676WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
677WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
678WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
679WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
680
681WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
682WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
683WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
684WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
685WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
686WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
687
688WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
689WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
690
691WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
692WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
693WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
694WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
695WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
696WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
697WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
698WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
699
700WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
701WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
702
703WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
704WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
705
706WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
707WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
708WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
709WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
710
711WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
712WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
713
714WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
715WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
716WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
717WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
718};
719
720static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
721 enum snd_soc_dapm_type event, int subseq)
722{
723 struct snd_soc_codec *codec = container_of(dapm,
724 struct snd_soc_codec, dapm);
725 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
726 u16 val, expect, i;
727
728 /* Wait for the outputs to flag themselves as enabled */
729 if (wm5100->out_ena[0]) {
730 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
731 for (i = 0; i < 200; i++) {
732 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
733 if (val == expect) {
734 wm5100->out_ena[0] = false;
735 break;
736 }
737 }
738 if (i == 200) {
739 dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
740 expect);
741 }
742 }
743
744 if (wm5100->out_ena[1]) {
745 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
746 for (i = 0; i < 200; i++) {
747 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
748 if (val == expect) {
749 wm5100->out_ena[1] = false;
750 break;
751 }
752 }
753 if (i == 200) {
754 dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
755 expect);
756 }
757 }
758}
759
760static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
761 struct snd_kcontrol *kcontrol,
762 int event)
763{
764 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec);
765
766 switch (w->reg) {
767 case WM5100_CHANNEL_ENABLES_1:
768 wm5100->out_ena[0] = true;
769 break;
770 case WM5100_OUTPUT_ENABLES_2:
771 wm5100->out_ena[0] = true;
772 break;
773 default:
774 break;
775 }
776
777 return 0;
778}
779
780static int wm5100_cp_ev(struct snd_soc_dapm_widget *w,
781 struct snd_kcontrol *kcontrol,
782 int event)
783{
784 struct snd_soc_codec *codec = w->codec;
785 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
786 int ret;
787
788 switch (event) {
789 case SND_SOC_DAPM_PRE_PMU:
790 ret = regulator_enable(wm5100->cpvdd);
791 if (ret != 0) {
792 dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
793 ret);
794 return ret;
795 }
796 return ret;
797
798 case SND_SOC_DAPM_POST_PMD:
799 ret = regulator_disable_deferred(wm5100->cpvdd, 20);
800 if (ret != 0) {
801 dev_err(codec->dev, "Failed to disable CPVDD: %d\n",
802 ret);
803 return ret;
804 }
805 return ret;
806
807 default:
808 BUG();
809 return 0;
810 }
811}
812
7aefb086
MB		 813static int wm5100_dbvdd_ev(struct snd_soc_dapm_widget *w,
814 struct snd_kcontrol *kcontrol,
815 int event)
816{
817 struct snd_soc_codec *codec = w->codec;
818 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
819 struct regulator *regulator;
820 int ret;
821
822 switch (w->shift) {
823 case 2:
824 regulator = wm5100->dbvdd2;
825 break;
826 case 3:
827 regulator = wm5100->dbvdd3;
828 break;
829 default:
830 BUG();
831 return 0;
832 }
833
834 switch (event) {
835 case SND_SOC_DAPM_PRE_PMU:
836 ret = regulator_enable(regulator);
837 if (ret != 0) {
838 dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
839 w->shift, ret);
840 return ret;
841 }
842 return ret;
843
844 case SND_SOC_DAPM_POST_PMD:
845 ret = regulator_disable(regulator);
846 if (ret != 0) {
847 dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
848 w->shift, ret);
849 return ret;
850 }
851 return ret;
852
853 default:
854 BUG();
855 return 0;
856 }
857}
858
46c1a877 859static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
6d4baf08
MB		 860{
861 if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
46c1a877 862 dev_crit(wm5100->dev, "Speaker shutdown warning\n");
6d4baf08 863 if (val & WM5100_SPK_SHUTDOWN_EINT)
46c1a877 864 dev_crit(wm5100->dev, "Speaker shutdown\n");
6d4baf08 865 if (val & WM5100_CLKGEN_ERR_EINT)
46c1a877 866 dev_crit(wm5100->dev, "SYSCLK underclocked\n");
6d4baf08 867 if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
46c1a877 868 dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
6d4baf08
MB		 869}
870
46c1a877 871static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
6d4baf08
MB		 872{
873 if (val & WM5100_AIF3_ERR_EINT)
46c1a877 874 dev_err(wm5100->dev, "AIF3 configuration error\n");
6d4baf08 875 if (val & WM5100_AIF2_ERR_EINT)
46c1a877 876 dev_err(wm5100->dev, "AIF2 configuration error\n");
6d4baf08 877 if (val & WM5100_AIF1_ERR_EINT)
46c1a877 878 dev_err(wm5100->dev, "AIF1 configuration error\n");
6d4baf08 879 if (val & WM5100_CTRLIF_ERR_EINT)
46c1a877 880 dev_err(wm5100->dev, "Control interface error\n");
6d4baf08 881 if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
46c1a877 882 dev_err(wm5100->dev, "ISRC2 underclocked\n");
6d4baf08 883 if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
46c1a877 884 dev_err(wm5100->dev, "ISRC1 underclocked\n");
6d4baf08 885 if (val & WM5100_FX_UNDERCLOCKED_EINT)
46c1a877 886 dev_err(wm5100->dev, "FX underclocked\n");
6d4baf08 887 if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
46c1a877 888 dev_err(wm5100->dev, "AIF3 underclocked\n");
6d4baf08 889 if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
46c1a877 890 dev_err(wm5100->dev, "AIF2 underclocked\n");
6d4baf08 891 if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
46c1a877 892 dev_err(wm5100->dev, "AIF1 underclocked\n");
6d4baf08 893 if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
46c1a877 894 dev_err(wm5100->dev, "ASRC underclocked\n");
6d4baf08 895 if (val & WM5100_DAC_UNDERCLOCKED_EINT)
46c1a877 896 dev_err(wm5100->dev, "DAC underclocked\n");
6d4baf08 897 if (val & WM5100_ADC_UNDERCLOCKED_EINT)
46c1a877 898 dev_err(wm5100->dev, "ADC underclocked\n");
6d4baf08 899 if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
46c1a877 900 dev_err(wm5100->dev, "Mixer underclocked\n");
6d4baf08
MB		 901}
902
903static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
904 struct snd_kcontrol *kcontrol,
905 int event)
906{
907 struct snd_soc_codec *codec = w->codec;
46c1a877 908 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
6d4baf08
MB		 909 int ret;
910
911 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
912 ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
913 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
914 WM5100_CLKGEN_ERR_ASYNC_STS;
46c1a877 915 wm5100_log_status3(wm5100, ret);
6d4baf08
MB		 916
917 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
46c1a877 918 wm5100_log_status4(wm5100, ret);
6d4baf08
MB		 919
920 return 0;
921}
922
923static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
924SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
925 NULL, 0),
926SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
927 0, NULL, 0),
928
929SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
930 wm5100_cp_ev,
931 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
932SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
933 NULL, 0),
934SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
935 WM5100_CP2_BYPASS_SHIFT, 1, wm5100_cp_ev,
936 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
7aefb086
MB		 937SND_SOC_DAPM_SUPPLY("DBVDD2", SND_SOC_NOPM, 2, 0, wm5100_dbvdd_ev,
938 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
939SND_SOC_DAPM_SUPPLY("DBVDD3", SND_SOC_NOPM, 3, 0, wm5100_dbvdd_ev,
940 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
6d4baf08
MB		 941
942SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
943 0, NULL, 0),
944SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
945 0, NULL, 0),
946SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
947 0, NULL, 0),
948
949SND_SOC_DAPM_INPUT("IN1L"),
950SND_SOC_DAPM_INPUT("IN1R"),
951SND_SOC_DAPM_INPUT("IN2L"),
952SND_SOC_DAPM_INPUT("IN2R"),
953SND_SOC_DAPM_INPUT("IN3L"),
954SND_SOC_DAPM_INPUT("IN3R"),
955SND_SOC_DAPM_INPUT("IN4L"),
956SND_SOC_DAPM_INPUT("IN4R"),
dea8e237 957SND_SOC_DAPM_SIGGEN("TONE"),
6d4baf08
MB		 958
959SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
960 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
961SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
962 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
963SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
964 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
965SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
966 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
967SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
968 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
969SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
970 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
971SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
972 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
973SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
974 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
975
976SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
977 WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
978SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
979 WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
980
981SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
982 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
983SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
984 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
985SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
986 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
987SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
988 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
989SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
990 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
991SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
992 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
993SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
994 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
995SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
996 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
997
998SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
999 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
1000SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
1001 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
1002
1003SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
1004 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
1005SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
1006 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
1007
1008SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
1009 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
1010SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
1011 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
1012SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
1013 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
1014SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
1015 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
1016SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
1017 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
1018SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
1019 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
1020SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
1021 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
1022SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
1023 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
1024
1025SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
1026 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
1027SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
1028 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
1029
1030SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
1031 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
1032SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
1033 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
1034
1035SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
1036 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1037SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
1038 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1039SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
1040 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1041SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
1042 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1043SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
1044 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1045SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
1046 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1047SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
1048 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1049SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
1050 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1051SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
1052 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1053SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
1054 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1055SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
1056 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1057SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
1058 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1059SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
1060 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1061SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
1062 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1063
1064SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
1065SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
1066SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1067SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1068
1069SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1070 NULL, 0),
1071SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1072 NULL, 0),
1073
1074SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1075 NULL, 0),
1076SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1077 NULL, 0),
1078SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1079 NULL, 0),
1080SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1081 NULL, 0),
1082
1083WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1084WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1085WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1086WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1087
1088WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1089WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1090
1091WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1092WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1093WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1094WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1095
1096WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1097WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1098WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1099WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1100WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1101WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1102WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1103WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1104
1105WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1106WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1107
1108WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1109WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1110
1111WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1112WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1113WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1114WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1115WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1116WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1117
1118WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1119WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1120WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1121WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1122WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1123WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1124
1125WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1126WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1127
1128SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1129SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1130SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1131SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1132SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1133SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1134SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1135SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1136SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1137SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1138SND_SOC_DAPM_OUTPUT("PWM1"),
1139SND_SOC_DAPM_OUTPUT("PWM2"),
1140};
1141
1142/* We register a _POST event if we don't have IRQ support so we can
1143 * look at the error status from the CODEC - if we've got the IRQ
1144 * hooked up then we will get prompted to look by an interrupt.
1145 */
1146static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1147SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1148};
1149
1150static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1151 { "IN1L", NULL, "SYSCLK" },
1152 { "IN1R", NULL, "SYSCLK" },
1153 { "IN2L", NULL, "SYSCLK" },
1154 { "IN2R", NULL, "SYSCLK" },
1155 { "IN3L", NULL, "SYSCLK" },
1156 { "IN3R", NULL, "SYSCLK" },
1157 { "IN4L", NULL, "SYSCLK" },
1158 { "IN4R", NULL, "SYSCLK" },
1159
1160 { "OUT1L", NULL, "SYSCLK" },
1161 { "OUT1R", NULL, "SYSCLK" },
1162 { "OUT2L", NULL, "SYSCLK" },
1163 { "OUT2R", NULL, "SYSCLK" },
1164 { "OUT3L", NULL, "SYSCLK" },
1165 { "OUT3R", NULL, "SYSCLK" },
1166 { "OUT4L", NULL, "SYSCLK" },
1167 { "OUT4R", NULL, "SYSCLK" },
1168 { "OUT5L", NULL, "SYSCLK" },
1169 { "OUT5R", NULL, "SYSCLK" },
1170 { "OUT6L", NULL, "SYSCLK" },
1171 { "OUT6R", NULL, "SYSCLK" },
1172
1173 { "AIF1RX1", NULL, "SYSCLK" },
1174 { "AIF1RX2", NULL, "SYSCLK" },
1175 { "AIF1RX3", NULL, "SYSCLK" },
1176 { "AIF1RX4", NULL, "SYSCLK" },
1177 { "AIF1RX5", NULL, "SYSCLK" },
1178 { "AIF1RX6", NULL, "SYSCLK" },
1179 { "AIF1RX7", NULL, "SYSCLK" },
1180 { "AIF1RX8", NULL, "SYSCLK" },
1181
1182 { "AIF2RX1", NULL, "SYSCLK" },
7aefb086 1183 { "AIF2RX1", NULL, "DBVDD2" },
6d4baf08 1184 { "AIF2RX2", NULL, "SYSCLK" },
7aefb086 1185 { "AIF2RX2", NULL, "DBVDD2" },
6d4baf08
MB		 1186
1187 { "AIF3RX1", NULL, "SYSCLK" },
7aefb086 1188 { "AIF3RX1", NULL, "DBVDD3" },
6d4baf08 1189 { "AIF3RX2", NULL, "SYSCLK" },
7aefb086 1190 { "AIF3RX2", NULL, "DBVDD3" },
6d4baf08
MB		 1191
1192 { "AIF1TX1", NULL, "SYSCLK" },
1193 { "AIF1TX2", NULL, "SYSCLK" },
1194 { "AIF1TX3", NULL, "SYSCLK" },
1195 { "AIF1TX4", NULL, "SYSCLK" },
1196 { "AIF1TX5", NULL, "SYSCLK" },
1197 { "AIF1TX6", NULL, "SYSCLK" },
1198 { "AIF1TX7", NULL, "SYSCLK" },
1199 { "AIF1TX8", NULL, "SYSCLK" },
1200
1201 { "AIF2TX1", NULL, "SYSCLK" },
7aefb086 1202 { "AIF2TX1", NULL, "DBVDD2" },
6d4baf08 1203 { "AIF2TX2", NULL, "SYSCLK" },
7aefb086 1204 { "AIF2TX2", NULL, "DBVDD2" },
6d4baf08
MB		 1205
1206 { "AIF3TX1", NULL, "SYSCLK" },
7aefb086 1207 { "AIF3TX1", NULL, "DBVDD3" },
6d4baf08 1208 { "AIF3TX2", NULL, "SYSCLK" },
7aefb086 1209 { "AIF3TX2", NULL, "DBVDD3" },
6d4baf08
MB		 1210
1211 { "MICBIAS1", NULL, "CP2" },
1212 { "MICBIAS2", NULL, "CP2" },
1213 { "MICBIAS3", NULL, "CP2" },
1214
1215 { "IN1L PGA", NULL, "CP2" },
1216 { "IN1R PGA", NULL, "CP2" },
1217 { "IN2L PGA", NULL, "CP2" },
1218 { "IN2R PGA", NULL, "CP2" },
1219 { "IN3L PGA", NULL, "CP2" },
1220 { "IN3R PGA", NULL, "CP2" },
1221 { "IN4L PGA", NULL, "CP2" },
1222 { "IN4R PGA", NULL, "CP2" },
1223
1224 { "IN1L PGA", NULL, "CP2 Active" },
1225 { "IN1R PGA", NULL, "CP2 Active" },
1226 { "IN2L PGA", NULL, "CP2 Active" },
1227 { "IN2R PGA", NULL, "CP2 Active" },
1228 { "IN3L PGA", NULL, "CP2 Active" },
1229 { "IN3R PGA", NULL, "CP2 Active" },
1230 { "IN4L PGA", NULL, "CP2 Active" },
1231 { "IN4R PGA", NULL, "CP2 Active" },
1232
1233 { "OUT1L", NULL, "CP1" },
1234 { "OUT1R", NULL, "CP1" },
1235 { "OUT2L", NULL, "CP1" },
1236 { "OUT2R", NULL, "CP1" },
1237 { "OUT3L", NULL, "CP1" },
1238 { "OUT3R", NULL, "CP1" },
1239
1240 { "Tone Generator 1", NULL, "TONE" },
1241 { "Tone Generator 2", NULL, "TONE" },
1242
1243 { "IN1L PGA", NULL, "IN1L" },
1244 { "IN1R PGA", NULL, "IN1R" },
1245 { "IN2L PGA", NULL, "IN2L" },
1246 { "IN2R PGA", NULL, "IN2R" },
1247 { "IN3L PGA", NULL, "IN3L" },
1248 { "IN3R PGA", NULL, "IN3R" },
1249 { "IN4L PGA", NULL, "IN4L" },
1250 { "IN4R PGA", NULL, "IN4R" },
1251
1252 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1253 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1254 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1255 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1256 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1257 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1258
1259 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1260 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1261 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1262 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1263 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1264 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1265
1266 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1267 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1268
1269 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1270 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1271 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1272 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1273 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1274 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1275 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1276 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1277
1278 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1279 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1280
1281 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1282 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1283
1284 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1285 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1286 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1287 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1288
1289 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1290 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1291
1292 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1293 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1294 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1295 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1296
1297 { "HPOUT1L", NULL, "OUT1L" },
1298 { "HPOUT1R", NULL, "OUT1R" },
1299 { "HPOUT2L", NULL, "OUT2L" },
1300 { "HPOUT2R", NULL, "OUT2R" },
1301 { "HPOUT3L", NULL, "OUT3L" },
1302 { "HPOUT3R", NULL, "OUT3R" },
1303 { "SPKOUTL", NULL, "OUT4L" },
1304 { "SPKOUTR", NULL, "OUT4R" },
1305 { "SPKDAT1", NULL, "OUT5L" },
1306 { "SPKDAT1", NULL, "OUT5R" },
1307 { "SPKDAT2", NULL, "OUT6L" },
1308 { "SPKDAT2", NULL, "OUT6R" },
1309 { "PWM1", NULL, "PWM1 Driver" },
1310 { "PWM2", NULL, "PWM2 Driver" },
1311};
1312
1313static struct {
1314 int reg;
1315 int val;
1316} wm5100_reva_patches[] = {
1317 { WM5100_AUDIO_IF_1_10, 0 },
1318 { WM5100_AUDIO_IF_1_11, 1 },
1319 { WM5100_AUDIO_IF_1_12, 2 },
1320 { WM5100_AUDIO_IF_1_13, 3 },
1321 { WM5100_AUDIO_IF_1_14, 4 },
1322 { WM5100_AUDIO_IF_1_15, 5 },
1323 { WM5100_AUDIO_IF_1_16, 6 },
1324 { WM5100_AUDIO_IF_1_17, 7 },
1325
1326 { WM5100_AUDIO_IF_1_18, 0 },
1327 { WM5100_AUDIO_IF_1_19, 1 },
1328 { WM5100_AUDIO_IF_1_20, 2 },
1329 { WM5100_AUDIO_IF_1_21, 3 },
1330 { WM5100_AUDIO_IF_1_22, 4 },
1331 { WM5100_AUDIO_IF_1_23, 5 },
1332 { WM5100_AUDIO_IF_1_24, 6 },
1333 { WM5100_AUDIO_IF_1_25, 7 },
1334
1335 { WM5100_AUDIO_IF_2_10, 0 },
1336 { WM5100_AUDIO_IF_2_11, 1 },
1337
1338 { WM5100_AUDIO_IF_2_18, 0 },
1339 { WM5100_AUDIO_IF_2_19, 1 },
1340
1341 { WM5100_AUDIO_IF_3_10, 0 },
1342 { WM5100_AUDIO_IF_3_11, 1 },
1343
1344 { WM5100_AUDIO_IF_3_18, 0 },
1345 { WM5100_AUDIO_IF_3_19, 1 },
1346};
1347
1348static int wm5100_set_bias_level(struct snd_soc_codec *codec,
1349 enum snd_soc_bias_level level)
1350{
1351 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1352 int ret, i;
1353
1354 switch (level) {
1355 case SND_SOC_BIAS_ON:
1356 break;
1357
1358 case SND_SOC_BIAS_PREPARE:
1359 break;
1360
1361 case SND_SOC_BIAS_STANDBY:
1362 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1363 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
1364 wm5100->core_supplies);
1365 if (ret != 0) {
1366 dev_err(codec->dev,
1367 "Failed to enable supplies: %d\n",
1368 ret);
1369 return ret;
1370 }
1371
1372 if (wm5100->pdata.ldo_ena) {
1373 gpio_set_value_cansleep(wm5100->pdata.ldo_ena,
1374 1);
1375 msleep(2);
1376 }
1377
bd132ec5 1378 regcache_cache_only(wm5100->regmap, false);
6d4baf08
MB		 1379
1380 switch (wm5100->rev) {
1381 case 0:
495174a8 1382 regcache_cache_bypass(wm5100->regmap, true);
6d4baf08
MB		 1383 snd_soc_write(codec, 0x11, 0x3);
1384 snd_soc_write(codec, 0x203, 0xc);
1385 snd_soc_write(codec, 0x206, 0);
1386 snd_soc_write(codec, 0x207, 0xf0);
1387 snd_soc_write(codec, 0x208, 0x3c);
1388 snd_soc_write(codec, 0x209, 0);
1389 snd_soc_write(codec, 0x211, 0x20d8);
1390 snd_soc_write(codec, 0x11, 0);
1391
1392 for (i = 0;
1393 i < ARRAY_SIZE(wm5100_reva_patches);
1394 i++)
1395 snd_soc_write(codec,
1396 wm5100_reva_patches[i].reg,
1397 wm5100_reva_patches[i].val);
495174a8 1398 regcache_cache_bypass(wm5100->regmap, false);
6d4baf08
MB		 1399 break;
1400 default:
1401 break;
1402 }
1403
60bf5b07 1404 regcache_sync(wm5100->regmap);
6d4baf08
MB		 1405 }
1406 break;
1407
1408 case SND_SOC_BIAS_OFF:
e53e4173 1409 regcache_cache_only(wm5100->regmap, true);
6d4baf08
MB		 1410 if (wm5100->pdata.ldo_ena)
1411 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
1412 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
1413 wm5100->core_supplies);
1414 break;
1415 }
1416 codec->dapm.bias_level = level;
1417
1418 return 0;
1419}
1420
1421static int wm5100_dai_to_base(struct snd_soc_dai *dai)
1422{
1423 switch (dai->id) {
1424 case 0:
1425 return WM5100_AUDIO_IF_1_1 - 1;
1426 case 1:
1427 return WM5100_AUDIO_IF_2_1 - 1;
1428 case 2:
1429 return WM5100_AUDIO_IF_3_1 - 1;
1430 default:
1431 BUG();
1432 return -EINVAL;
1433 }
1434}
1435
1436static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1437{
1438 struct snd_soc_codec *codec = dai->codec;
1439 int lrclk, bclk, mask, base;
1440
1441 base = wm5100_dai_to_base(dai);
1442 if (base < 0)
1443 return base;
1444
1445 lrclk = 0;
1446 bclk = 0;
1447
1448 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1449 case SND_SOC_DAIFMT_DSP_A:
1450 mask = 0;
1451 break;
1452 case SND_SOC_DAIFMT_DSP_B:
1453 mask = 1;
1454 break;
1455 case SND_SOC_DAIFMT_I2S:
1456 mask = 2;
1457 break;
1458 case SND_SOC_DAIFMT_LEFT_J:
1459 mask = 3;
1460 break;
1461 default:
1462 dev_err(codec->dev, "Unsupported DAI format %d\n",
1463 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1464 return -EINVAL;
1465 }
1466
1467 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1468 case SND_SOC_DAIFMT_CBS_CFS:
1469 break;
1470 case SND_SOC_DAIFMT_CBS_CFM:
1471 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1472 break;
1473 case SND_SOC_DAIFMT_CBM_CFS:
1474 bclk |= WM5100_AIF1_BCLK_MSTR;
1475 break;
1476 case SND_SOC_DAIFMT_CBM_CFM:
1477 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1478 bclk |= WM5100_AIF1_BCLK_MSTR;
1479 break;
1480 default:
1481 dev_err(codec->dev, "Unsupported master mode %d\n",
1482 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1483 return -EINVAL;
1484 }
1485
1486 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1487 case SND_SOC_DAIFMT_NB_NF:
1488 break;
1489 case SND_SOC_DAIFMT_IB_IF:
1490 bclk |= WM5100_AIF1_BCLK_INV;
1491 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1492 break;
1493 case SND_SOC_DAIFMT_IB_NF:
1494 bclk |= WM5100_AIF1_BCLK_INV;
1495 break;
1496 case SND_SOC_DAIFMT_NB_IF:
1497 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1498 break;
1499 default:
1500 return -EINVAL;
1501 }
1502
1503 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1504 WM5100_AIF1_BCLK_INV, bclk);
1505 snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1506 WM5100_AIF1TX_LRCLK_INV, lrclk);
1507 snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1508 WM5100_AIF1TX_LRCLK_INV, lrclk);
1509 snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1510
1511 return 0;
1512}
1513
1514#define WM5100_NUM_BCLK_RATES 19
1515
1516static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1517 32000,
1518 48000,
1519 64000,
1520 96000,
1521 128000,
1522 192000,
d73ec75c 1523 256000,
6d4baf08
MB		 1524 384000,
1525 512000,
1526 768000,
1527 1024000,
1528 1536000,
1529 2048000,
1530 3072000,
1531 4096000,
1532 6144000,
1533 8192000,
1534 12288000,
1535 24576000,
1536};
1537
1538static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1539 29400,
1540 44100,
1541 58800,
1542 88200,
1543 117600,
1544 176400,
1545 235200,
1546 352800,
1547 470400,
1548 705600,
1549 940800,
1550 1411200,
1551 1881600,
1552 2882400,
1553 3763200,
1554 5644800,
1555 7526400,
1556 11289600,
1557 22579600,
1558};
1559
1560static int wm5100_hw_params(struct snd_pcm_substream *substream,
1561 struct snd_pcm_hw_params *params,
1562 struct snd_soc_dai *dai)
1563{
1564 struct snd_soc_codec *codec = dai->codec;
1565 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1566 bool async = wm5100->aif_async[dai->id];
1567 int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1568 int *bclk_rates;
1569
1570 base = wm5100_dai_to_base(dai);
1571 if (base < 0)
1572 return base;
1573
1574 /* Data sizes if not using TDM */
1575 wl = snd_pcm_format_width(params_format(params));
1576 if (wl < 0)
1577 return wl;
1578 fl = snd_soc_params_to_frame_size(params);
1579 if (fl < 0)
1580 return fl;
1581
1582 dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1583 wl, fl);
1584
1585 /* Target BCLK rate */
1586 bclk = snd_soc_params_to_bclk(params);
1587 if (bclk < 0)
1588 return bclk;
1589
1590 /* Root for BCLK depends on SYS/ASYNCCLK */
1591 if (!async) {
1592 aif_rate = wm5100->sysclk;
1593 sr = wm5100_alloc_sr(codec, params_rate(params));
1594 if (sr < 0)
1595 return sr;
1596 } else {
1597 /* If we're in ASYNCCLK set the ASYNC sample rate */
1598 aif_rate = wm5100->asyncclk;
1599 sr = 3;
1600
1601 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1602 if (params_rate(params) == wm5100_sr_code[i])
1603 break;
1604 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1605 dev_err(codec->dev, "Invalid rate %dHzn",
1606 params_rate(params));
1607 return -EINVAL;
1608 }
1609
1610 /* TODO: We should really check for symmetry */
1611 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1612 WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1613 }
1614
1615 if (!aif_rate) {
1616 dev_err(codec->dev, "%s has no rate set\n",
1617 async ? "ASYNCCLK" : "SYSCLK");
1618 return -EINVAL;
1619 }
1620
1621 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1622 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1623
1624 if (aif_rate % 4000)
1625 bclk_rates = wm5100_bclk_rates_cd;
1626 else
1627 bclk_rates = wm5100_bclk_rates_dat;
1628
1629 for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1630 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1631 break;
1632 if (i == WM5100_NUM_BCLK_RATES) {
1633 dev_err(codec->dev,
1634 "No valid BCLK for %dHz found from %dHz %s\n",
1635 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1636 return -EINVAL;
1637 }
1638
1639 bclk = i;
1640 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1641 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1642
1643 lrclk = bclk_rates[bclk] / params_rate(params);
1644 dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1645 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1646 wm5100->aif_symmetric[dai->id])
1647 snd_soc_update_bits(codec, base + 7,
1648 WM5100_AIF1RX_BCPF_MASK, lrclk);
1649 else
1650 snd_soc_update_bits(codec, base + 6,
1651 WM5100_AIF1TX_BCPF_MASK, lrclk);
1652
1653 i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1654 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1655 snd_soc_update_bits(codec, base + 9,
1656 WM5100_AIF1RX_WL_MASK |
1657 WM5100_AIF1RX_SLOT_LEN_MASK, i);
1658 else
1659 snd_soc_update_bits(codec, base + 8,
1660 WM5100_AIF1TX_WL_MASK |
1661 WM5100_AIF1TX_SLOT_LEN_MASK, i);
1662
1663 snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1664
1665 return 0;
1666}
1667
85e7652d 1668static const struct snd_soc_dai_ops wm5100_dai_ops = {
6d4baf08
MB		 1669 .set_fmt = wm5100_set_fmt,
1670 .hw_params = wm5100_hw_params,
1671};
1672
1673static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1674 int source, unsigned int freq, int dir)
1675{
1676 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1677 int *rate_store;
1678 int fval, audio_rate, ret, reg;
1679
1680 switch (clk_id) {
1681 case WM5100_CLK_SYSCLK:
1682 reg = WM5100_CLOCKING_3;
1683 rate_store = &wm5100->sysclk;
1684 break;
1685 case WM5100_CLK_ASYNCCLK:
1686 reg = WM5100_CLOCKING_7;
1687 rate_store = &wm5100->asyncclk;
1688 break;
1689 case WM5100_CLK_32KHZ:
1690 /* The 32kHz clock is slightly different to the others */
1691 switch (source) {
1692 case WM5100_CLKSRC_MCLK1:
1693 case WM5100_CLKSRC_MCLK2:
1694 case WM5100_CLKSRC_SYSCLK:
1695 snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1696 WM5100_CLK_32K_SRC_MASK,
1697 source);
1698 break;
1699 default:
1700 return -EINVAL;
1701 }
1702 return 0;
1703
1704 case WM5100_CLK_AIF1:
1705 case WM5100_CLK_AIF2:
1706 case WM5100_CLK_AIF3:
1707 /* Not real clocks, record which clock domain they're in */
1708 switch (source) {
1709 case WM5100_CLKSRC_SYSCLK:
1710 wm5100->aif_async[clk_id - 1] = false;
1711 break;
1712 case WM5100_CLKSRC_ASYNCCLK:
1713 wm5100->aif_async[clk_id - 1] = true;
1714 break;
1715 default:
1716 dev_err(codec->dev, "Invalid source %d\n", source);
1717 return -EINVAL;
1718 }
1719 return 0;
1720
1721 case WM5100_CLK_OPCLK:
1722 switch (freq) {
1723 case 5644800:
1724 case 6144000:
1725 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1726 WM5100_OPCLK_SEL_MASK, 0);
1727 break;
1728 case 11289600:
1729 case 12288000:
1730 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1731 WM5100_OPCLK_SEL_MASK, 0);
1732 break;
1733 case 22579200:
1734 case 24576000:
1735 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1736 WM5100_OPCLK_SEL_MASK, 0);
1737 break;
1738 default:
1739 dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1740 freq);
1741 return -EINVAL;
1742 }
1743 return 0;
1744
1745 default:
1746 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1747 return -EINVAL;
1748 }
1749
1750 switch (source) {
1751 case WM5100_CLKSRC_SYSCLK:
1752 case WM5100_CLKSRC_ASYNCCLK:
1753 dev_err(codec->dev, "Invalid source %d\n", source);
1754 return -EINVAL;
1755 }
1756
1757 switch (freq) {
1758 case 5644800:
1759 case 6144000:
1760 fval = 0;
1761 break;
1762 case 11289600:
1763 case 12288000:
1764 fval = 1;
1765 break;
1766 case 22579200:
11c2b5f2 1767 case 24576000:
6d4baf08
MB		 1768 fval = 2;
1769 break;
1770 default:
1771 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1772 return -EINVAL;
1773 }
1774
1775 switch (freq) {
1776 case 5644800:
1777 case 11289600:
1778 case 22579200:
1779 audio_rate = 44100;
1780 break;
1781
1782 case 6144000:
1783 case 12288000:
11c2b5f2 1784 case 24576000:
6d4baf08
MB		 1785 audio_rate = 48000;
1786 break;
1787
1788 default:
1789 BUG();
1790 audio_rate = 0;
1791 break;
1792 }
1793
1794 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1795 * match.
1796 */
1797
1798 snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1799 WM5100_SYSCLK_SRC_MASK,
1800 fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1801
1802 /* If this is SYSCLK then configure the clock rate for the
1803 * internal audio functions to the natural sample rate for
1804 * this clock rate.
1805 */
1806 if (clk_id == WM5100_CLK_SYSCLK) {
1807 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1808 audio_rate);
1809 if (0 && *rate_store)
1810 wm5100_free_sr(codec, audio_rate);
1811 ret = wm5100_alloc_sr(codec, audio_rate);
1812 if (ret != 0)
1813 dev_warn(codec->dev, "Primary audio slot is %d\n",
1814 ret);
1815 }
1816
1817 *rate_store = freq;
1818
1819 return 0;
1820}
1821
1822struct _fll_div {
1823 u16 fll_fratio;
1824 u16 fll_outdiv;
1825 u16 fll_refclk_div;
1826 u16 n;
1827 u16 theta;
1828 u16 lambda;
1829};
1830
1831static struct {
1832 unsigned int min;
1833 unsigned int max;
1834 u16 fll_fratio;
1835 int ratio;
1836} fll_fratios[] = {
1837 { 0, 64000, 4, 16 },
1838 { 64000, 128000, 3, 8 },
1839 { 128000, 256000, 2, 4 },
1840 { 256000, 1000000, 1, 2 },
1841 { 1000000, 13500000, 0, 1 },
1842};
1843
1844static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1845 unsigned int Fout)
1846{
1847 unsigned int target;
1848 unsigned int div;
1849 unsigned int fratio, gcd_fll;
1850 int i;
1851
1852 /* Fref must be <=13.5MHz */
1853 div = 1;
1854 fll_div->fll_refclk_div = 0;
1855 while ((Fref / div) > 13500000) {
1856 div *= 2;
1857 fll_div->fll_refclk_div++;
1858
1859 if (div > 8) {
1860 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1861 Fref);
1862 return -EINVAL;
1863 }
1864 }
1865
1866 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1867
1868 /* Apply the division for our remaining calculations */
1869 Fref /= div;
1870
1871 /* Fvco should be 90-100MHz; don't check the upper bound */
1872 div = 2;
1873 while (Fout * div < 90000000) {
1874 div++;
1875 if (div > 64) {
1876 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1877 Fout);
1878 return -EINVAL;
1879 }
1880 }
1881 target = Fout * div;
1882 fll_div->fll_outdiv = div - 1;
1883
1884 pr_debug("FLL Fvco=%dHz\n", target);
1885
1886 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1887 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1888 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1889 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1890 fratio = fll_fratios[i].ratio;
1891 break;
1892 }
1893 }
1894 if (i == ARRAY_SIZE(fll_fratios)) {
1895 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1896 return -EINVAL;
1897 }
1898
1899 fll_div->n = target / (fratio * Fref);
1900
1901 if (target % Fref == 0) {
1902 fll_div->theta = 0;
1903 fll_div->lambda = 0;
1904 } else {
1905 gcd_fll = gcd(target, fratio * Fref);
1906
1907 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1908 / gcd_fll;
1909 fll_div->lambda = (fratio * Fref) / gcd_fll;
1910 }
1911
1912 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1913 fll_div->n, fll_div->theta, fll_div->lambda);
1914 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1915 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1916 fll_div->fll_refclk_div);
1917
1918 return 0;
1919}
1920
1921static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1922 unsigned int Fref, unsigned int Fout)
1923{
1924 struct i2c_client *i2c = to_i2c_client(codec->dev);
1925 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1926 struct _fll_div factors;
1927 struct wm5100_fll *fll;
1928 int ret, base, lock, i, timeout;
1929
1930 switch (fll_id) {
1931 case WM5100_FLL1:
1932 fll = &wm5100->fll[0];
1933 base = WM5100_FLL1_CONTROL_1 - 1;
1934 lock = WM5100_FLL1_LOCK_STS;
1935 break;
1936 case WM5100_FLL2:
1937 fll = &wm5100->fll[1];
1938 base = WM5100_FLL2_CONTROL_2 - 1;
1939 lock = WM5100_FLL2_LOCK_STS;
1940 break;
1941 default:
1942 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1943 return -EINVAL;
1944 }
1945
1946 if (!Fout) {
1947 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1948 fll->fout = 0;
1949 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1950 return 0;
1951 }
1952
1953 switch (source) {
1954 case WM5100_FLL_SRC_MCLK1:
1955 case WM5100_FLL_SRC_MCLK2:
1956 case WM5100_FLL_SRC_FLL1:
1957 case WM5100_FLL_SRC_FLL2:
1958 case WM5100_FLL_SRC_AIF1BCLK:
1959 case WM5100_FLL_SRC_AIF2BCLK:
1960 case WM5100_FLL_SRC_AIF3BCLK:
1961 break;
1962 default:
1963 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1964 return -EINVAL;
1965 }
1966
1967 ret = fll_factors(&factors, Fref, Fout);
1968 if (ret < 0)
1969 return ret;
1970
1971 /* Disable the FLL while we reconfigure */
1972 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1973
1974 snd_soc_update_bits(codec, base + 2,
1975 WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1976 (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1977 factors.fll_fratio);
1978 snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1979 factors.theta);
1980 snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1981 snd_soc_update_bits(codec, base + 6,
1982 WM5100_FLL1_REFCLK_DIV_MASK |
1983 WM5100_FLL1_REFCLK_SRC_MASK,
1984 (factors.fll_refclk_div
1985 << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1986 snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1987 factors.lambda);
1988
1989 /* Clear any pending completions */
1990 try_wait_for_completion(&fll->lock);
1991
1992 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1993
1994 if (i2c->irq)
1995 timeout = 2;
1996 else
1997 timeout = 50;
1998
bd132ec5
MB		 1999 snd_soc_update_bits(codec, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
2000 WM5100_SYSCLK_ENA);
2001
6d4baf08
MB		 2002 /* Poll for the lock; will use interrupt when we can test */
2003 for (i = 0; i < timeout; i++) {
2004 if (i2c->irq) {
2005 ret = wait_for_completion_timeout(&fll->lock,
2006 msecs_to_jiffies(25));
2007 if (ret > 0)
2008 break;
2009 } else {
2010 msleep(1);
2011 }
2012
2013 ret = snd_soc_read(codec,
2014 WM5100_INTERRUPT_RAW_STATUS_3);
2015 if (ret < 0) {
2016 dev_err(codec->dev,
2017 "Failed to read FLL status: %d\n",
2018 ret);
2019 continue;
2020 }
2021 if (ret & lock)
2022 break;
2023 }
2024 if (i == timeout) {
2025 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
2026 return -ETIMEDOUT;
2027 }
2028
2029 fll->src = source;
2030 fll->fref = Fref;
2031 fll->fout = Fout;
2032
2033 dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
2034 Fref, Fout);
2035
2036 return 0;
2037}
2038
2039/* Actually go much higher */
2040#define WM5100_RATES SNDRV_PCM_RATE_8000_192000
2041
2042#define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2043 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2044
2045static struct snd_soc_dai_driver wm5100_dai[] = {
2046 {
2047 .name = "wm5100-aif1",
2048 .playback = {
2049 .stream_name = "AIF1 Playback",
2050 .channels_min = 2,
2051 .channels_max = 2,
2052 .rates = WM5100_RATES,
2053 .formats = WM5100_FORMATS,
2054 },
2055 .capture = {
2056 .stream_name = "AIF1 Capture",
2057 .channels_min = 2,
2058 .channels_max = 2,
2059 .rates = WM5100_RATES,
2060 .formats = WM5100_FORMATS,
2061 },
2062 .ops = &wm5100_dai_ops,
2063 },
2064 {
2065 .name = "wm5100-aif2",
2066 .id = 1,
2067 .playback = {
2068 .stream_name = "AIF2 Playback",
2069 .channels_min = 2,
2070 .channels_max = 2,
2071 .rates = WM5100_RATES,
2072 .formats = WM5100_FORMATS,
2073 },
2074 .capture = {
2075 .stream_name = "AIF2 Capture",
2076 .channels_min = 2,
2077 .channels_max = 2,
2078 .rates = WM5100_RATES,
2079 .formats = WM5100_FORMATS,
2080 },
2081 .ops = &wm5100_dai_ops,
2082 },
2083 {
2084 .name = "wm5100-aif3",
2085 .id = 2,
2086 .playback = {
2087 .stream_name = "AIF3 Playback",
2088 .channels_min = 2,
2089 .channels_max = 2,
2090 .rates = WM5100_RATES,
2091 .formats = WM5100_FORMATS,
2092 },
2093 .capture = {
2094 .stream_name = "AIF3 Capture",
2095 .channels_min = 2,
2096 .channels_max = 2,
2097 .rates = WM5100_RATES,
2098 .formats = WM5100_FORMATS,
2099 },
2100 .ops = &wm5100_dai_ops,
2101 },
2102};
2103
2104static int wm5100_dig_vu[] = {
2105 WM5100_ADC_DIGITAL_VOLUME_1L,
2106 WM5100_ADC_DIGITAL_VOLUME_1R,
2107 WM5100_ADC_DIGITAL_VOLUME_2L,
2108 WM5100_ADC_DIGITAL_VOLUME_2R,
2109 WM5100_ADC_DIGITAL_VOLUME_3L,
2110 WM5100_ADC_DIGITAL_VOLUME_3R,
2111 WM5100_ADC_DIGITAL_VOLUME_4L,
2112 WM5100_ADC_DIGITAL_VOLUME_4R,
2113
2114 WM5100_DAC_DIGITAL_VOLUME_1L,
2115 WM5100_DAC_DIGITAL_VOLUME_1R,
2116 WM5100_DAC_DIGITAL_VOLUME_2L,
2117 WM5100_DAC_DIGITAL_VOLUME_2R,
2118 WM5100_DAC_DIGITAL_VOLUME_3L,
2119 WM5100_DAC_DIGITAL_VOLUME_3R,
2120 WM5100_DAC_DIGITAL_VOLUME_4L,
2121 WM5100_DAC_DIGITAL_VOLUME_4R,
2122 WM5100_DAC_DIGITAL_VOLUME_5L,
2123 WM5100_DAC_DIGITAL_VOLUME_5R,
2124 WM5100_DAC_DIGITAL_VOLUME_6L,
2125 WM5100_DAC_DIGITAL_VOLUME_6R,
2126};
2127
46c1a877 2128static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
ba896ede 2129{
ba896ede
MB		 2130 struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
2131
2132 BUG_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes));
2133
2134 gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
46c1a877
MB		 2135 regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
2136 WM5100_ACCDET_BIAS_SRC_MASK |
2137 WM5100_ACCDET_SRC,
2138 (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
2139 mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
2140 regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
2141 WM5100_HPCOM_SRC,
2142 mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
ba896ede
MB		 2143
2144 wm5100->jack_mode = the_mode;
2145
46c1a877 2146 dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
ba896ede
MB		 2147 wm5100->jack_mode);
2148}
2149
46c1a877 2150static void wm5100_micd_irq(struct wm5100_priv *wm5100)
ba896ede 2151{
46c1a877
MB		 2152 unsigned int val;
2153 int ret;
ba896ede 2154
46c1a877
MB		 2155 ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
2156 if (ret != 0) {
2157 dev_err(wm5100->dev, "Failed to read micropone status: %d\n",
2158 ret);
2159 return;
2160 }
ba896ede 2161
46c1a877 2162 dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
ba896ede
MB		 2163
2164 if (!(val & WM5100_ACCDET_VALID)) {
46c1a877 2165 dev_warn(wm5100->dev, "Microphone detection state invalid\n");
ba896ede
MB		 2166 return;
2167 }
2168
2169 /* No accessory, reset everything and report removal */
2170 if (!(val & WM5100_ACCDET_STS)) {
46c1a877 2171 dev_dbg(wm5100->dev, "Jack removal detected\n");
ba896ede
MB		 2172 wm5100->jack_mic = false;
2173 wm5100->jack_detecting = true;
2174 snd_soc_jack_report(wm5100->jack, 0,
2175 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2176 SND_JACK_BTN_0);
2177
46c1a877
MB		 2178 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2179 WM5100_ACCDET_RATE_MASK,
2180 WM5100_ACCDET_RATE_MASK);
ba896ede
MB		 2181 return;
2182 }
2183
2184 /* If the measurement is very high we've got a microphone,
2185 * either we just detected one or if we already reported then
2186 * we've got a button release event.
2187 */
2188 if (val & 0x400) {
2189 if (wm5100->jack_detecting) {
46c1a877 2190 dev_dbg(wm5100->dev, "Microphone detected\n");
ba896ede
MB		 2191 wm5100->jack_mic = true;
2192 snd_soc_jack_report(wm5100->jack,
2193 SND_JACK_HEADSET,
2194 SND_JACK_HEADSET | SND_JACK_BTN_0);
2195
2196 /* Increase poll rate to give better responsiveness
2197 * for buttons */
46c1a877
MB		 2198 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2199 WM5100_ACCDET_RATE_MASK,
2200 5 << WM5100_ACCDET_RATE_SHIFT);
ba896ede 2201 } else {
46c1a877 2202 dev_dbg(wm5100->dev, "Mic button up\n");
ba896ede
MB		 2203 snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2204 }
2205
2206 return;
2207 }
2208
2209 /* If we detected a lower impedence during initial startup
2210 * then we probably have the wrong polarity, flip it. Don't
2211 * do this for the lowest impedences to speed up detection of
2212 * plain headphones.
2213 */
2214 if (wm5100->jack_detecting && (val & 0x3f8)) {
46c1a877 2215 wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
ba896ede
MB		 2216
2217 return;
2218 }
2219
2220 /* Don't distinguish between buttons, just report any low
2221 * impedence as BTN_0.
2222 */
2223 if (val & 0x3fc) {
2224 if (wm5100->jack_mic) {
46c1a877 2225 dev_dbg(wm5100->dev, "Mic button detected\n");
ba896ede
MB		 2226 snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2227 SND_JACK_BTN_0);
2228 } else if (wm5100->jack_detecting) {
46c1a877 2229 dev_dbg(wm5100->dev, "Headphone detected\n");
ba896ede
MB		 2230 snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
2231 SND_JACK_HEADPHONE);
2232
2233 /* Increase the detection rate a bit for
2234 * responsiveness.
2235 */
46c1a877
MB		 2236 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2237 WM5100_ACCDET_RATE_MASK,
2238 7 << WM5100_ACCDET_RATE_SHIFT);
ba896ede
MB		 2239 }
2240 }
2241}
2242
2243int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2244{
2245 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2246
2247 if (jack) {
2248 wm5100->jack = jack;
2249 wm5100->jack_detecting = true;
2250
46c1a877 2251 wm5100_set_detect_mode(wm5100, 0);
ba896ede
MB		 2252
2253 /* Slowest detection rate, gives debounce for initial
2254 * detection */
2255 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2256 WM5100_ACCDET_BIAS_STARTTIME_MASK |
2257 WM5100_ACCDET_RATE_MASK,
2258 (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2259 WM5100_ACCDET_RATE_MASK);
2260
2261 /* We need the charge pump to power MICBIAS */
2262 snd_soc_dapm_force_enable_pin(&codec->dapm, "CP2");
2263 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2264 snd_soc_dapm_sync(&codec->dapm);
2265
2266 /* We start off just enabling microphone detection - even a
2267 * plain headphone will trigger detection.
2268 */
2269 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2270 WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2271
2272 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2273 WM5100_IM_ACCDET_EINT, 0);
2274 } else {
2275 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2276 WM5100_IM_HPDET_EINT |
2277 WM5100_IM_ACCDET_EINT,
2278 WM5100_IM_HPDET_EINT |
2279 WM5100_IM_ACCDET_EINT);
2280 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2281 WM5100_ACCDET_ENA, 0);
2282 wm5100->jack = NULL;
2283 }
2284
2285 return 0;
2286}
2287
6d4baf08
MB		 2288static irqreturn_t wm5100_irq(int irq, void *data)
2289{
46c1a877 2290 struct wm5100_priv *wm5100 = data;
6d4baf08 2291 irqreturn_t status = IRQ_NONE;
46c1a877
MB		 2292 unsigned int irq_val, mask_val;
2293 int ret;
6d4baf08 2294
46c1a877
MB		 2295 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
2296 if (ret < 0) {
2297 dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
2298 ret);
6d4baf08
MB		 2299 irq_val = 0;
2300 }
6d4baf08 2301
46c1a877
MB		 2302 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
2303 &mask_val);
2304 if (ret < 0) {
2305 dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
2306 ret);
2307 mask_val = 0xffff;
2308 }
2309
2310 irq_val &= ~mask_val;
2311
2312 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
6d4baf08
MB		 2313
2314 if (irq_val)
2315 status = IRQ_HANDLED;
2316
46c1a877 2317 wm5100_log_status3(wm5100, irq_val);
6d4baf08
MB		 2318
2319 if (irq_val & WM5100_FLL1_LOCK_EINT) {
46c1a877 2320 dev_dbg(wm5100->dev, "FLL1 locked\n");
6d4baf08
MB		 2321 complete(&wm5100->fll[0].lock);
2322 }
2323 if (irq_val & WM5100_FLL2_LOCK_EINT) {
46c1a877 2324 dev_dbg(wm5100->dev, "FLL2 locked\n");
6d4baf08
MB		 2325 complete(&wm5100->fll[1].lock);
2326 }
2327
ba896ede 2328 if (irq_val & WM5100_ACCDET_EINT)
46c1a877 2329 wm5100_micd_irq(wm5100);
ba896ede 2330
46c1a877
MB		 2331 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
2332 if (ret < 0) {
2333 dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
2334 ret);
6d4baf08
MB		 2335 irq_val = 0;
2336 }
46c1a877
MB		 2337
2338 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
2339 &mask_val);
2340 if (ret < 0) {
2341 dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
2342 ret);
2343 mask_val = 0xffff;
2344 }
2345
2346 irq_val &= ~mask_val;
6d4baf08
MB		 2347
2348 if (irq_val)
2349 status = IRQ_HANDLED;
2350
46c1a877 2351 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
6d4baf08 2352
46c1a877 2353 wm5100_log_status4(wm5100, irq_val);
6d4baf08
MB		 2354
2355 return status;
2356}
2357
2358static irqreturn_t wm5100_edge_irq(int irq, void *data)
2359{
2360 irqreturn_t ret = IRQ_NONE;
2361 irqreturn_t val;
2362
2363 do {
2364 val = wm5100_irq(irq, data);
2365 if (val != IRQ_NONE)
2366 ret = val;
2367 } while (val != IRQ_NONE);
2368
2369 return ret;
2370}
2371
2372#ifdef CONFIG_GPIOLIB
2373static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2374{
2375 return container_of(chip, struct wm5100_priv, gpio_chip);
2376}
2377
2378static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2379{
2380 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
6d4baf08 2381
9db16e4c
MB		 2382 regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2383 WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
6d4baf08
MB		 2384}
2385
2386static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2387 unsigned offset, int value)
2388{
2389 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
64964e82 2390 int val, ret;
6d4baf08
MB		 2391
2392 val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2393
9db16e4c
MB		 2394 ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2395 WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2396 WM5100_GP1_LVL, val);
64964e82
MB		 2397 if (ret < 0)
2398 return ret;
2399 else
2400 return 0;
6d4baf08
MB		 2401}
2402
2403static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2404{
2405 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
9db16e4c 2406 unsigned int reg;
6d4baf08
MB		 2407 int ret;
2408
9db16e4c 2409 ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, &reg);
6d4baf08
MB		 2410 if (ret < 0)
2411 return ret;
2412
9db16e4c 2413 return (reg & WM5100_GP1_LVL) != 0;
6d4baf08
MB		 2414}
2415
2416static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2417{
2418 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
6d4baf08 2419
9db16e4c
MB		 2420 return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2421 WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2422 (1 << WM5100_GP1_FN_SHIFT) |
2423 (1 << WM5100_GP1_DIR_SHIFT));
6d4baf08
MB		 2424}
2425
2426static struct gpio_chip wm5100_template_chip = {
2427 .label = "wm5100",
2428 .owner = THIS_MODULE,
2429 .direction_output = wm5100_gpio_direction_out,
2430 .set = wm5100_gpio_set,
2431 .direction_input = wm5100_gpio_direction_in,
2432 .get = wm5100_gpio_get,
2433 .can_sleep = 1,
2434};
2435
9db16e4c 2436static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08 2437{
9db16e4c 2438 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08
MB		 2439 int ret;
2440
2441 wm5100->gpio_chip = wm5100_template_chip;
2442 wm5100->gpio_chip.ngpio = 6;
9db16e4c 2443 wm5100->gpio_chip.dev = &i2c->dev;
6d4baf08
MB		 2444
2445 if (wm5100->pdata.gpio_base)
2446 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2447 else
2448 wm5100->gpio_chip.base = -1;
2449
2450 ret = gpiochip_add(&wm5100->gpio_chip);
2451 if (ret != 0)
9db16e4c 2452 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
6d4baf08
MB		 2453}
2454
9db16e4c 2455static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08 2456{
9db16e4c 2457 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08
MB		 2458 int ret;
2459
2460 ret = gpiochip_remove(&wm5100->gpio_chip);
2461 if (ret != 0)
9db16e4c 2462 dev_err(&i2c->dev, "Failed to remove GPIOs: %d\n", ret);
6d4baf08
MB		 2463}
2464#else
9db16e4c 2465static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2466{
2467}
2468
9db16e4c 2469static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2470{
2471}
2472#endif
2473
2474static int wm5100_probe(struct snd_soc_codec *codec)
2475{
2476 struct i2c_client *i2c = to_i2c_client(codec->dev);
2477 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
09452f23 2478 int ret, i;
6d4baf08
MB		 2479
2480 wm5100->codec = codec;
bd132ec5 2481 codec->control_data = wm5100->regmap;
6d4baf08 2482
bd132ec5 2483 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
6d4baf08
MB		 2484 if (ret != 0) {
2485 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2486 return ret;
2487 }
2488
bd132ec5 2489 regcache_cache_only(wm5100->regmap, true);
6d4baf08 2490
6d4baf08
MB		 2491
2492 for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2493 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2494 WM5100_OUT_VU);
2495
6d4baf08
MB		 2496 /* Don't debounce interrupts to support use of SYSCLK only */
2497 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2498 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2499
2500 /* TODO: check if we're symmetric */
2501
09452f23 2502 if (i2c->irq)
6d4baf08
MB		 2503 snd_soc_dapm_new_controls(&codec->dapm,
2504 wm5100_dapm_widgets_noirq,
2505 ARRAY_SIZE(wm5100_dapm_widgets_noirq));
6d4baf08
MB		 2506
2507 if (wm5100->pdata.hp_pol) {
2508 ret = gpio_request_one(wm5100->pdata.hp_pol,
2509 GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2510 if (ret < 0) {
2511 dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2512 wm5100->pdata.hp_pol, ret);
2513 goto err_gpio;
2514 }
2515 }
2516
2517 /* We'll get woken up again when the system has something useful
2518 * for us to do.
2519 */
2520 if (wm5100->pdata.ldo_ena)
2521 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2522 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2523 wm5100->core_supplies);
2524
2525 return 0;
2526
2527err_gpio:
6d4baf08
MB		 2528
2529 return ret;
2530}
2531
2532static int wm5100_remove(struct snd_soc_codec *codec)
2533{
2534 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
0a742681 2535 struct i2c_client *i2c = to_i2c_client(codec->dev);
6d4baf08 2536
6d4baf08
MB		 2537 if (wm5100->pdata.hp_pol) {
2538 gpio_free(wm5100->pdata.hp_pol);
2539 }
46c1a877 2540
6d4baf08
MB		 2541 return 0;
2542}
2543
1b39bf34
MB		 2544static int wm5100_soc_volatile(struct snd_soc_codec *codec,
2545 unsigned int reg)
2546{
2547 return true;
2548}
2549
2550
6d4baf08
MB		 2551static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2552 .probe = wm5100_probe,
2553 .remove = wm5100_remove,
2554
2555 .set_sysclk = wm5100_set_sysclk,
2556 .set_pll = wm5100_set_fll,
2557 .set_bias_level = wm5100_set_bias_level,
2558 .idle_bias_off = 1,
1b39bf34
MB		 2559 .reg_cache_size = WM5100_MAX_REGISTER,
2560 .volatile_register = wm5100_soc_volatile,
6d4baf08
MB		 2561
2562 .seq_notifier = wm5100_seq_notifier,
2563 .controls = wm5100_snd_controls,
2564 .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2565 .dapm_widgets = wm5100_dapm_widgets,
2566 .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2567 .dapm_routes = wm5100_dapm_routes,
2568 .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
bd132ec5 2569};
6d4baf08 2570
bd132ec5
MB		 2571static const struct regmap_config wm5100_regmap = {
2572 .reg_bits = 16,
2573 .val_bits = 16,
6d4baf08 2574
bd132ec5
MB		 2575 .max_register = WM5100_MAX_REGISTER,
2576 .reg_defaults = wm5100_reg_defaults,
2577 .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2578 .volatile_reg = wm5100_volatile_register,
2579 .readable_reg = wm5100_readable_register,
2580 .cache_type = REGCACHE_RBTREE,
6d4baf08
MB		 2581};
2582
2583static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2584 const struct i2c_device_id *id)
2585{
2586 struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2587 struct wm5100_priv *wm5100;
588ac5e0 2588 unsigned int reg;
09452f23 2589 int ret, i, irq_flags;
6d4baf08 2590
a81b82c0
MB		 2591 wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2592 GFP_KERNEL);
6d4baf08
MB		 2593 if (wm5100 == NULL)
2594 return -ENOMEM;
2595
46c1a877
MB		 2596 wm5100->dev = &i2c->dev;
2597
bd132ec5
MB		 2598 wm5100->regmap = regmap_init_i2c(i2c, &wm5100_regmap);
2599 if (IS_ERR(wm5100->regmap)) {
2600 ret = PTR_ERR(wm5100->regmap);
2601 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2602 ret);
a81b82c0 2603 goto err;
bd132ec5
MB		 2604 }
2605
6d4baf08
MB		 2606 for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2607 init_completion(&wm5100->fll[i].lock);
2608
2609 if (pdata)
2610 wm5100->pdata = *pdata;
2611
2612 i2c_set_clientdata(i2c, wm5100);
2613
588ac5e0
MB		 2614 for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2615 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2616
2617 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm5100->core_supplies),
2618 wm5100->core_supplies);
2619 if (ret != 0) {
2620 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2621 ret);
2622 goto err_regmap;
2623 }
2624
2625 wm5100->cpvdd = regulator_get(&i2c->dev, "CPVDD");
2626 if (IS_ERR(wm5100->cpvdd)) {
2627 ret = PTR_ERR(wm5100->cpvdd);
2628 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
2629 goto err_core;
2630 }
2631
2632 wm5100->dbvdd2 = regulator_get(&i2c->dev, "DBVDD2");
2633 if (IS_ERR(wm5100->dbvdd2)) {
2634 ret = PTR_ERR(wm5100->dbvdd2);
2635 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2636 goto err_cpvdd;
2637 }
2638
2639 wm5100->dbvdd3 = regulator_get(&i2c->dev, "DBVDD3");
2640 if (IS_ERR(wm5100->dbvdd3)) {
2641 ret = PTR_ERR(wm5100->dbvdd3);
2642 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2643 goto err_dbvdd2;
2644 }
2645
2646 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2647 wm5100->core_supplies);
2648 if (ret != 0) {
2649 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2650 ret);
2651 goto err_dbvdd3;
2652 }
2653
2654 if (wm5100->pdata.ldo_ena) {
2655 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2656 GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2657 if (ret < 0) {
2658 dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2659 wm5100->pdata.ldo_ena, ret);
2660 goto err_enable;
2661 }
2662 msleep(2);
2663 }
2664
2665 if (wm5100->pdata.reset) {
2666 ret = gpio_request_one(wm5100->pdata.reset,
2667 GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2668 if (ret < 0) {
2669 dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2670 wm5100->pdata.reset, ret);
2671 goto err_ldo;
2672 }
2673 }
2674
2675 ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, &reg);
2676 if (ret < 0) {
0132615d 2677 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
588ac5e0
MB		 2678 goto err_reset;
2679 }
2680 switch (reg) {
2681 case 0x8997:
2682 case 0x5100:
2683 break;
2684
2685 default:
2686 dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2687 ret = -EINVAL;
2688 goto err_reset;
2689 }
2690
2691 ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, &reg);
2692 if (ret < 0) {
2693 dev_err(&i2c->dev, "Failed to read revision register\n");
2694 goto err_reset;
2695 }
2696 wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2697
2698 dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2699
2700 ret = wm5100_reset(wm5100);
2701 if (ret < 0) {
2702 dev_err(&i2c->dev, "Failed to issue reset\n");
2703 goto err_reset;
2704 }
2705
9db16e4c
MB		 2706 wm5100_init_gpio(i2c);
2707
d9b5e9c6
MB		 2708 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2709 if (!wm5100->pdata.gpio_defaults[i])
2710 continue;
2711
2712 regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2713 wm5100->pdata.gpio_defaults[i]);
2714 }
2715
2716 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2717 regmap_update_bits(wm5100->regmap, WM5100_IN1L_CONTROL,
2718 WM5100_IN1_MODE_MASK |
2719 WM5100_IN1_DMIC_SUP_MASK,
2720 (wm5100->pdata.in_mode[i] <<
2721 WM5100_IN1_MODE_SHIFT) |
2722 (wm5100->pdata.dmic_sup[i] <<
2723 WM5100_IN1_DMIC_SUP_SHIFT));
2724 }
2725
09452f23
MB		 2726 if (i2c->irq) {
2727 if (wm5100->pdata.irq_flags)
2728 irq_flags = wm5100->pdata.irq_flags;
2729 else
2730 irq_flags = IRQF_TRIGGER_LOW;
2731
2732 irq_flags |= IRQF_ONESHOT;
2733
2734 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2735 ret = request_threaded_irq(i2c->irq, NULL,
2736 wm5100_edge_irq, irq_flags,
2737 "wm5100", wm5100);
2738 else
2739 ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2740 irq_flags, "wm5100",
2741 wm5100);
2742
2743 if (ret != 0) {
2744 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2745 i2c->irq, ret);
2746 } else {
2747 /* Enable default interrupts */
2748 regmap_update_bits(wm5100->regmap,
2749 WM5100_INTERRUPT_STATUS_3_MASK,
2750 WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2751 WM5100_IM_SPK_SHUTDOWN_EINT |
2752 WM5100_IM_ASRC2_LOCK_EINT |
2753 WM5100_IM_ASRC1_LOCK_EINT |
2754 WM5100_IM_FLL2_LOCK_EINT |
2755 WM5100_IM_FLL1_LOCK_EINT |
2756 WM5100_CLKGEN_ERR_EINT |
2757 WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2758
2759 regmap_update_bits(wm5100->regmap,
2760 WM5100_INTERRUPT_STATUS_4_MASK,
2761 WM5100_AIF3_ERR_EINT |
2762 WM5100_AIF2_ERR_EINT |
2763 WM5100_AIF1_ERR_EINT |
2764 WM5100_CTRLIF_ERR_EINT |
2765 WM5100_ISRC2_UNDERCLOCKED_EINT |
2766 WM5100_ISRC1_UNDERCLOCKED_EINT |
2767 WM5100_FX_UNDERCLOCKED_EINT |
2768 WM5100_AIF3_UNDERCLOCKED_EINT |
2769 WM5100_AIF2_UNDERCLOCKED_EINT |
2770 WM5100_AIF1_UNDERCLOCKED_EINT |
2771 WM5100_ASRC_UNDERCLOCKED_EINT |
2772 WM5100_DAC_UNDERCLOCKED_EINT |
2773 WM5100_ADC_UNDERCLOCKED_EINT |
2774 WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2775 }
2776 }
2777
6d4baf08
MB		 2778 ret = snd_soc_register_codec(&i2c->dev,
2779 &soc_codec_dev_wm5100, wm5100_dai,
2780 ARRAY_SIZE(wm5100_dai));
2781 if (ret < 0) {
2782 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
588ac5e0 2783 goto err_reset;
6d4baf08
MB		 2784 }
2785
2786 return ret;
bd132ec5 2787
588ac5e0 2788err_reset:
09452f23
MB		 2789 if (i2c->irq)
2790 free_irq(i2c->irq, wm5100);
9db16e4c 2791 wm5100_free_gpio(i2c);
588ac5e0 2792 if (wm5100->pdata.reset) {
2688738e 2793 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
588ac5e0
MB		 2794 gpio_free(wm5100->pdata.reset);
2795 }
2796err_ldo:
2797 if (wm5100->pdata.ldo_ena) {
2798 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2799 gpio_free(wm5100->pdata.ldo_ena);
2800 }
2801err_enable:
2802 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2803 wm5100->core_supplies);
2804err_dbvdd3:
2805 regulator_put(wm5100->dbvdd3);
2806err_dbvdd2:
2807 regulator_put(wm5100->dbvdd2);
2808err_cpvdd:
2809 regulator_put(wm5100->cpvdd);
2810err_core:
2811 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2812 wm5100->core_supplies);
bd132ec5
MB		 2813err_regmap:
2814 regmap_exit(wm5100->regmap);
a81b82c0 2815err:
bd132ec5 2816 return ret;
6d4baf08
MB		 2817}
2818
09452f23 2819static __devexit int wm5100_i2c_remove(struct i2c_client *i2c)
6d4baf08 2820{
09452f23 2821 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
bd132ec5 2822
09452f23
MB		 2823 snd_soc_unregister_codec(&i2c->dev);
2824 if (i2c->irq)
2825 free_irq(i2c->irq, wm5100);
2826 wm5100_free_gpio(i2c);
588ac5e0 2827 if (wm5100->pdata.reset) {
2688738e 2828 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
588ac5e0
MB		 2829 gpio_free(wm5100->pdata.reset);
2830 }
2831 if (wm5100->pdata.ldo_ena) {
2832 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2833 gpio_free(wm5100->pdata.ldo_ena);
2834 }
2835 regulator_put(wm5100->dbvdd3);
2836 regulator_put(wm5100->dbvdd2);
2837 regulator_put(wm5100->cpvdd);
2838 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2839 wm5100->core_supplies);
bd132ec5 2840 regmap_exit(wm5100->regmap);
bd132ec5 2841
6d4baf08
MB		 2842 return 0;
2843}
2844
2845static const struct i2c_device_id wm5100_i2c_id[] = {
2846 { "wm5100", 0 },
2847 { }
2848};
2849MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2850
2851static struct i2c_driver wm5100_i2c_driver = {
2852 .driver = {
2853 .name = "wm5100",
2854 .owner = THIS_MODULE,
2855 },
2856 .probe = wm5100_i2c_probe,
2857 .remove = __devexit_p(wm5100_i2c_remove),
2858 .id_table = wm5100_i2c_id,
2859};
2860
2861static int __init wm5100_modinit(void)
2862{
2863 return i2c_add_driver(&wm5100_i2c_driver);
2864}
2865module_init(wm5100_modinit);
2866
2867static void __exit wm5100_exit(void)
2868{
2869 i2c_del_driver(&wm5100_i2c_driver);
2870}
2871module_exit(wm5100_exit);
2872
2873MODULE_DESCRIPTION("ASoC WM5100 driver");
2874MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2875MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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