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ASoC: Provide REGULATOR_SUPPLY widget type
[deliverable/linux.git] / sound / soc / codecs / wm5100.c
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6d4baf08
MB		 1/*
2 * wm5100.c -- WM5100 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/gcd.h>
19#include <linux/gpio.h>
20#include <linux/i2c.h>
6d4baf08
MB		 21#include <linux/regulator/consumer.h>
22#include <linux/regulator/fixed.h>
23#include <linux/slab.h>
24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
ba896ede 28#include <sound/jack.h>
6d4baf08
MB		 29#include <sound/initval.h>
30#include <sound/tlv.h>
31#include <sound/wm5100.h>
32
33#include "wm5100.h"
34
35#define WM5100_NUM_CORE_SUPPLIES 2
36static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
37 "DBVDD1",
38 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
39};
40
41#define WM5100_AIFS 3
42#define WM5100_SYNC_SRS 3
43
44struct wm5100_fll {
45 int fref;
46 int fout;
47 int src;
48 struct completion lock;
49};
50
51/* codec private data */
52struct wm5100_priv {
46c1a877 53 struct device *dev;
bd132ec5 54 struct regmap *regmap;
6d4baf08
MB		 55 struct snd_soc_codec *codec;
56
57 struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
58 struct regulator *cpvdd;
7aefb086
MB		 59 struct regulator *dbvdd2;
60 struct regulator *dbvdd3;
6d4baf08
MB		 61
62 int rev;
63
64 int sysclk;
65 int asyncclk;
66
67 bool aif_async[WM5100_AIFS];
68 bool aif_symmetric[WM5100_AIFS];
69 int sr_ref[WM5100_SYNC_SRS];
70
71 bool out_ena[2];
72
ba896ede
MB		 73 struct snd_soc_jack *jack;
74 bool jack_detecting;
75 bool jack_mic;
76 int jack_mode;
77
6d4baf08
MB		 78 struct wm5100_fll fll[2];
79
80 struct wm5100_pdata pdata;
81
82#ifdef CONFIG_GPIOLIB
83 struct gpio_chip gpio_chip;
84#endif
85};
86
87static int wm5100_sr_code[] = {
88 0,
89 12000,
90 24000,
91 48000,
92 96000,
93 192000,
94 384000,
95 768000,
96 0,
97 11025,
98 22050,
99 44100,
100 88200,
101 176400,
102 352800,
103 705600,
104 4000,
105 8000,
106 16000,
107 32000,
108 64000,
109 128000,
110 256000,
111 512000,
112};
113
114static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
115 WM5100_CLOCKING_4,
116 WM5100_CLOCKING_5,
117 WM5100_CLOCKING_6,
118};
119
120static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
121{
122 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
123 int sr_code, sr_free, i;
124
125 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
126 if (wm5100_sr_code[i] == rate)
127 break;
128 if (i == ARRAY_SIZE(wm5100_sr_code)) {
129 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
130 return -EINVAL;
131 }
132 sr_code = i;
133
134 if ((wm5100->sysclk % rate) == 0) {
135 /* Is this rate already in use? */
136 sr_free = -1;
137 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
138 if (!wm5100->sr_ref[i] && sr_free == -1) {
139 sr_free = i;
140 continue;
141 }
142 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
143 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
144 break;
145 }
146
147 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
148 wm5100->sr_ref[i]++;
149 dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
150 rate, i, wm5100->sr_ref[i]);
151 return i;
152 }
153
154 if (sr_free == -1) {
155 dev_err(codec->dev, "All SR slots already in use\n");
156 return -EBUSY;
157 }
158
159 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
160 sr_free, rate);
161 wm5100->sr_ref[sr_free]++;
162 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
163 WM5100_SAMPLE_RATE_1_MASK,
164 sr_code);
165
166 return sr_free;
167
168 } else {
169 dev_err(codec->dev,
170 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
171 rate, wm5100->sysclk, wm5100->asyncclk);
172 return -EINVAL;
173 }
174}
175
176static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
177{
178 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
179 int i, sr_code;
180
181 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
182 if (wm5100_sr_code[i] == rate)
183 break;
184 if (i == ARRAY_SIZE(wm5100_sr_code)) {
185 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
186 return;
187 }
188 sr_code = wm5100_sr_code[i];
189
190 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
191 if (!wm5100->sr_ref[i])
192 continue;
193
194 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
195 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
196 break;
197 }
198 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
199 wm5100->sr_ref[i]--;
200 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
201 rate, wm5100->sr_ref[i]);
202 } else {
203 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
204 rate);
205 }
206}
207
588ac5e0 208static int wm5100_reset(struct wm5100_priv *wm5100)
6d4baf08 209{
6d4baf08
MB		 210 if (wm5100->pdata.reset) {
211 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
212 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
213
214 return 0;
215 } else {
588ac5e0 216 return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
6d4baf08
MB		 217 }
218}
219
220static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
221static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
222static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
223static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
224static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
225
226static const char *wm5100_mixer_texts[] = {
227 "None",
228 "Tone Generator 1",
229 "Tone Generator 2",
230 "AEC loopback",
231 "IN1L",
232 "IN1R",
233 "IN2L",
234 "IN2R",
235 "IN3L",
236 "IN3R",
237 "IN4L",
238 "IN4R",
239 "AIF1RX1",
240 "AIF1RX2",
241 "AIF1RX3",
242 "AIF1RX4",
243 "AIF1RX5",
244 "AIF1RX6",
245 "AIF1RX7",
246 "AIF1RX8",
247 "AIF2RX1",
248 "AIF2RX2",
249 "AIF3RX1",
250 "AIF3RX2",
251 "EQ1",
252 "EQ2",
253 "EQ3",
254 "EQ4",
255 "DRC1L",
256 "DRC1R",
257 "LHPF1",
258 "LHPF2",
259 "LHPF3",
260 "LHPF4",
261 "DSP1.1",
262 "DSP1.2",
263 "DSP1.3",
264 "DSP1.4",
265 "DSP1.5",
266 "DSP1.6",
267 "DSP2.1",
268 "DSP2.2",
269 "DSP2.3",
270 "DSP2.4",
271 "DSP2.5",
272 "DSP2.6",
273 "DSP3.1",
274 "DSP3.2",
275 "DSP3.3",
276 "DSP3.4",
277 "DSP3.5",
278 "DSP3.6",
279 "ASRC1L",
280 "ASRC1R",
281 "ASRC2L",
282 "ASRC2R",
283 "ISRC1INT1",
284 "ISRC1INT2",
285 "ISRC1INT3",
286 "ISRC1INT4",
287 "ISRC2INT1",
288 "ISRC2INT2",
289 "ISRC2INT3",
290 "ISRC2INT4",
291 "ISRC1DEC1",
292 "ISRC1DEC2",
293 "ISRC1DEC3",
294 "ISRC1DEC4",
295 "ISRC2DEC1",
296 "ISRC2DEC2",
297 "ISRC2DEC3",
298 "ISRC2DEC4",
299};
300
301static int wm5100_mixer_values[] = {
302 0x00,
303 0x04, /* Tone */
304 0x05,
305 0x08, /* AEC */
306 0x10, /* Input */
307 0x11,
308 0x12,
309 0x13,
310 0x14,
311 0x15,
312 0x16,
313 0x17,
314 0x20, /* AIF */
315 0x21,
316 0x22,
317 0x23,
318 0x24,
319 0x25,
320 0x26,
321 0x27,
322 0x28,
323 0x29,
324 0x30, /* AIF3 - check */
325 0x31,
326 0x50, /* EQ */
327 0x51,
328 0x52,
329 0x53,
330 0x54,
331 0x58, /* DRC */
332 0x59,
333 0x60, /* LHPF1 */
334 0x61, /* LHPF2 */
335 0x62, /* LHPF3 */
336 0x63, /* LHPF4 */
337 0x68, /* DSP1 */
338 0x69,
339 0x6a,
340 0x6b,
341 0x6c,
342 0x6d,
343 0x70, /* DSP2 */
344 0x71,
345 0x72,
346 0x73,
347 0x74,
348 0x75,
349 0x78, /* DSP3 */
350 0x79,
351 0x7a,
352 0x7b,
353 0x7c,
354 0x7d,
355 0x90, /* ASRC1 */
356 0x91,
357 0x92, /* ASRC2 */
358 0x93,
359 0xa0, /* ISRC1DEC1 */
360 0xa1,
361 0xa2,
362 0xa3,
363 0xa4, /* ISRC1INT1 */
364 0xa5,
365 0xa6,
366 0xa7,
367 0xa8, /* ISRC2DEC1 */
368 0xa9,
369 0xaa,
370 0xab,
371 0xac, /* ISRC2INT1 */
372 0xad,
373 0xae,
374 0xaf,
375};
376
377#define WM5100_MIXER_CONTROLS(name, base) \
378 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
379 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
380 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
381 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
382 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
383 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
384 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
385 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
386
387#define WM5100_MUX_ENUM_DECL(name, reg) \
388 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
389 wm5100_mixer_texts, wm5100_mixer_values)
390
391#define WM5100_MUX_CTL_DECL(name) \
392 const struct snd_kcontrol_new name##_mux = \
393 SOC_DAPM_VALUE_ENUM("Route", name##_enum)
394
395#define WM5100_MIXER_ENUMS(name, base_reg) \
396 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
397 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
398 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
399 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
400 static WM5100_MUX_CTL_DECL(name##_in1); \
401 static WM5100_MUX_CTL_DECL(name##_in2); \
402 static WM5100_MUX_CTL_DECL(name##_in3); \
403 static WM5100_MUX_CTL_DECL(name##_in4)
404
405WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
406WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
407WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
408WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
409WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
410WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
411
412WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
413WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
414WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
415WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
416WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
417WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
418
419WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
420WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
421
422WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
423WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
424WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
425WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
426WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
427WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
428WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
429WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
430
431WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
432WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
433
434WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
435WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
436
437WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
438WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
439WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
440WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
441
442WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
443WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
444
445WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
446WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
447WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
448WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
449
450#define WM5100_MUX(name, ctrl) \
451 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
452
453#define WM5100_MIXER_WIDGETS(name, name_str) \
454 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
455 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
456 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
457 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
458 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
459
460#define WM5100_MIXER_INPUT_ROUTES(name) \
461 { name, "Tone Generator 1", "Tone Generator 1" }, \
462 { name, "Tone Generator 2", "Tone Generator 2" }, \
463 { name, "IN1L", "IN1L PGA" }, \
464 { name, "IN1R", "IN1R PGA" }, \
465 { name, "IN2L", "IN2L PGA" }, \
466 { name, "IN2R", "IN2R PGA" }, \
467 { name, "IN3L", "IN3L PGA" }, \
468 { name, "IN3R", "IN3R PGA" }, \
469 { name, "IN4L", "IN4L PGA" }, \
470 { name, "IN4R", "IN4R PGA" }, \
471 { name, "AIF1RX1", "AIF1RX1" }, \
472 { name, "AIF1RX2", "AIF1RX2" }, \
473 { name, "AIF1RX3", "AIF1RX3" }, \
474 { name, "AIF1RX4", "AIF1RX4" }, \
475 { name, "AIF1RX5", "AIF1RX5" }, \
476 { name, "AIF1RX6", "AIF1RX6" }, \
477 { name, "AIF1RX7", "AIF1RX7" }, \
478 { name, "AIF1RX8", "AIF1RX8" }, \
479 { name, "AIF2RX1", "AIF2RX1" }, \
480 { name, "AIF2RX2", "AIF2RX2" }, \
481 { name, "AIF3RX1", "AIF3RX1" }, \
482 { name, "AIF3RX2", "AIF3RX2" }, \
483 { name, "EQ1", "EQ1" }, \
484 { name, "EQ2", "EQ2" }, \
485 { name, "EQ3", "EQ3" }, \
486 { name, "EQ4", "EQ4" }, \
487 { name, "DRC1L", "DRC1L" }, \
488 { name, "DRC1R", "DRC1R" }, \
489 { name, "LHPF1", "LHPF1" }, \
490 { name, "LHPF2", "LHPF2" }, \
491 { name, "LHPF3", "LHPF3" }, \
492 { name, "LHPF4", "LHPF4" }
493
494#define WM5100_MIXER_ROUTES(widget, name) \
495 { widget, NULL, name " Mixer" }, \
496 { name " Mixer", NULL, name " Input 1" }, \
497 { name " Mixer", NULL, name " Input 2" }, \
498 { name " Mixer", NULL, name " Input 3" }, \
499 { name " Mixer", NULL, name " Input 4" }, \
500 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
501 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
502 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
503 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
504
505static const char *wm5100_lhpf_mode_text[] = {
506 "Low-pass", "High-pass"
507};
508
509static const struct soc_enum wm5100_lhpf1_mode =
510 SOC_ENUM_SINGLE(WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT, 2,
511 wm5100_lhpf_mode_text);
512
513static const struct soc_enum wm5100_lhpf2_mode =
514 SOC_ENUM_SINGLE(WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT, 2,
515 wm5100_lhpf_mode_text);
516
517static const struct soc_enum wm5100_lhpf3_mode =
518 SOC_ENUM_SINGLE(WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT, 2,
519 wm5100_lhpf_mode_text);
520
521static const struct soc_enum wm5100_lhpf4_mode =
522 SOC_ENUM_SINGLE(WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT, 2,
523 wm5100_lhpf_mode_text);
524
525static const struct snd_kcontrol_new wm5100_snd_controls[] = {
526SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
527 WM5100_IN1_OSR_SHIFT, 1, 0),
528SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
529 WM5100_IN2_OSR_SHIFT, 1, 0),
530SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
531 WM5100_IN3_OSR_SHIFT, 1, 0),
532SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
533 WM5100_IN4_OSR_SHIFT, 1, 0),
534
535/* Only applicable for analogue inputs */
536SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
537 WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
538SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
539 WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
540SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
541 WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
542SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
543 WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
544
545SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
546 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
547 0, digital_tlv),
548SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
549 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
550 0, digital_tlv),
551SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
552 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
553 0, digital_tlv),
554SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
555 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
556 0, digital_tlv),
557
558SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
559 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
560SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
561 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
562SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
563 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
564SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
565 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
566
567SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
568 WM5100_OUT1_OSR_SHIFT, 1, 0),
569SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
570 WM5100_OUT2_OSR_SHIFT, 1, 0),
571SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
572 WM5100_OUT3_OSR_SHIFT, 1, 0),
573SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
574 WM5100_OUT4_OSR_SHIFT, 1, 0),
575SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
576 WM5100_OUT5_OSR_SHIFT, 1, 0),
577SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
578 WM5100_OUT6_OSR_SHIFT, 1, 0),
579
580SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
581 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
582 digital_tlv),
583SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
584 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
585 digital_tlv),
586SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
587 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
588 digital_tlv),
589SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
590 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
591 digital_tlv),
592SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
593 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
594 digital_tlv),
595SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
596 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
597 digital_tlv),
598
599SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
600 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
601SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
602 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
603SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
604 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
605SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
606 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
607SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
608 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
609SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
610 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
611
612/* FIXME: Only valid from -12dB to 0dB (52-64) */
613SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
614 WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
615SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
616 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
617SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
618 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
619
620SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
621 WM5100_SPK1R_MUTE_SHIFT, 1, 1),
622SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
623 WM5100_SPK2R_MUTE_SHIFT, 1, 1),
624
625SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
626 24, 0, eq_tlv),
627SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
628 24, 0, eq_tlv),
629SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
630 24, 0, eq_tlv),
631SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
632 24, 0, eq_tlv),
633SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
634 24, 0, eq_tlv),
635
636SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
637 24, 0, eq_tlv),
638SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
639 24, 0, eq_tlv),
640SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
641 24, 0, eq_tlv),
642SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
643 24, 0, eq_tlv),
644SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
645 24, 0, eq_tlv),
646
647SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
648 24, 0, eq_tlv),
649SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
650 24, 0, eq_tlv),
651SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
652 24, 0, eq_tlv),
653SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
654 24, 0, eq_tlv),
655SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
656 24, 0, eq_tlv),
657
658SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
659 24, 0, eq_tlv),
660SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
661 24, 0, eq_tlv),
662SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
663 24, 0, eq_tlv),
664SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
665 24, 0, eq_tlv),
666SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
667 24, 0, eq_tlv),
668
669SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
670SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
671SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
672SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
673
674WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
675WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
676WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
677WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
678WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
679WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
680
681WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
682WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
683WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
684WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
685WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
686WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
687
688WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
689WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
690
691WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
692WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
693WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
694WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
695WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
696WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
697WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
698WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
699
700WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
701WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
702
703WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
704WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
705
706WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
707WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
708WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
709WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
710
711WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
712WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
713
714WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
715WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
716WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
717WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
718};
719
720static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
721 enum snd_soc_dapm_type event, int subseq)
722{
723 struct snd_soc_codec *codec = container_of(dapm,
724 struct snd_soc_codec, dapm);
725 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
726 u16 val, expect, i;
727
728 /* Wait for the outputs to flag themselves as enabled */
729 if (wm5100->out_ena[0]) {
730 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
731 for (i = 0; i < 200; i++) {
732 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
733 if (val == expect) {
734 wm5100->out_ena[0] = false;
735 break;
736 }
737 }
738 if (i == 200) {
739 dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
740 expect);
741 }
742 }
743
744 if (wm5100->out_ena[1]) {
745 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
746 for (i = 0; i < 200; i++) {
747 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
748 if (val == expect) {
749 wm5100->out_ena[1] = false;
750 break;
751 }
752 }
753 if (i == 200) {
754 dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
755 expect);
756 }
757 }
758}
759
760static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
761 struct snd_kcontrol *kcontrol,
762 int event)
763{
764 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec);
765
766 switch (w->reg) {
767 case WM5100_CHANNEL_ENABLES_1:
768 wm5100->out_ena[0] = true;
769 break;
770 case WM5100_OUTPUT_ENABLES_2:
771 wm5100->out_ena[0] = true;
772 break;
773 default:
774 break;
775 }
776
777 return 0;
778}
779
780static int wm5100_cp_ev(struct snd_soc_dapm_widget *w,
781 struct snd_kcontrol *kcontrol,
782 int event)
783{
784 struct snd_soc_codec *codec = w->codec;
785 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
786 int ret;
787
788 switch (event) {
789 case SND_SOC_DAPM_PRE_PMU:
790 ret = regulator_enable(wm5100->cpvdd);
791 if (ret != 0) {
792 dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
793 ret);
794 return ret;
795 }
796 return ret;
797
798 case SND_SOC_DAPM_POST_PMD:
799 ret = regulator_disable_deferred(wm5100->cpvdd, 20);
800 if (ret != 0) {
801 dev_err(codec->dev, "Failed to disable CPVDD: %d\n",
802 ret);
803 return ret;
804 }
805 return ret;
806
807 default:
808 BUG();
809 return 0;
810 }
811}
812
7aefb086
MB		 813static int wm5100_dbvdd_ev(struct snd_soc_dapm_widget *w,
814 struct snd_kcontrol *kcontrol,
815 int event)
816{
817 struct snd_soc_codec *codec = w->codec;
818 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
819 struct regulator *regulator;
820 int ret;
821
822 switch (w->shift) {
823 case 2:
824 regulator = wm5100->dbvdd2;
825 break;
826 case 3:
827 regulator = wm5100->dbvdd3;
828 break;
829 default:
830 BUG();
831 return 0;
832 }
833
834 switch (event) {
835 case SND_SOC_DAPM_PRE_PMU:
836 ret = regulator_enable(regulator);
837 if (ret != 0) {
838 dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
839 w->shift, ret);
840 return ret;
841 }
842 return ret;
843
844 case SND_SOC_DAPM_POST_PMD:
845 ret = regulator_disable(regulator);
846 if (ret != 0) {
847 dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
848 w->shift, ret);
849 return ret;
850 }
851 return ret;
852
853 default:
854 BUG();
855 return 0;
856 }
857}
858
46c1a877 859static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
6d4baf08
MB		 860{
861 if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
46c1a877 862 dev_crit(wm5100->dev, "Speaker shutdown warning\n");
6d4baf08 863 if (val & WM5100_SPK_SHUTDOWN_EINT)
46c1a877 864 dev_crit(wm5100->dev, "Speaker shutdown\n");
6d4baf08 865 if (val & WM5100_CLKGEN_ERR_EINT)
46c1a877 866 dev_crit(wm5100->dev, "SYSCLK underclocked\n");
6d4baf08 867 if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
46c1a877 868 dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
6d4baf08
MB		 869}
870
46c1a877 871static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
6d4baf08
MB		 872{
873 if (val & WM5100_AIF3_ERR_EINT)
46c1a877 874 dev_err(wm5100->dev, "AIF3 configuration error\n");
6d4baf08 875 if (val & WM5100_AIF2_ERR_EINT)
46c1a877 876 dev_err(wm5100->dev, "AIF2 configuration error\n");
6d4baf08 877 if (val & WM5100_AIF1_ERR_EINT)
46c1a877 878 dev_err(wm5100->dev, "AIF1 configuration error\n");
6d4baf08 879 if (val & WM5100_CTRLIF_ERR_EINT)
46c1a877 880 dev_err(wm5100->dev, "Control interface error\n");
6d4baf08 881 if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
46c1a877 882 dev_err(wm5100->dev, "ISRC2 underclocked\n");
6d4baf08 883 if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
46c1a877 884 dev_err(wm5100->dev, "ISRC1 underclocked\n");
6d4baf08 885 if (val & WM5100_FX_UNDERCLOCKED_EINT)
46c1a877 886 dev_err(wm5100->dev, "FX underclocked\n");
6d4baf08 887 if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
46c1a877 888 dev_err(wm5100->dev, "AIF3 underclocked\n");
6d4baf08 889 if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
46c1a877 890 dev_err(wm5100->dev, "AIF2 underclocked\n");
6d4baf08 891 if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
46c1a877 892 dev_err(wm5100->dev, "AIF1 underclocked\n");
6d4baf08 893 if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
46c1a877 894 dev_err(wm5100->dev, "ASRC underclocked\n");
6d4baf08 895 if (val & WM5100_DAC_UNDERCLOCKED_EINT)
46c1a877 896 dev_err(wm5100->dev, "DAC underclocked\n");
6d4baf08 897 if (val & WM5100_ADC_UNDERCLOCKED_EINT)
46c1a877 898 dev_err(wm5100->dev, "ADC underclocked\n");
6d4baf08 899 if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
46c1a877 900 dev_err(wm5100->dev, "Mixer underclocked\n");
6d4baf08
MB		 901}
902
903static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
904 struct snd_kcontrol *kcontrol,
905 int event)
906{
907 struct snd_soc_codec *codec = w->codec;
46c1a877 908 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
6d4baf08
MB		 909 int ret;
910
911 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
912 ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
913 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
914 WM5100_CLKGEN_ERR_ASYNC_STS;
46c1a877 915 wm5100_log_status3(wm5100, ret);
6d4baf08
MB		 916
917 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
46c1a877 918 wm5100_log_status4(wm5100, ret);
6d4baf08
MB		 919
920 return 0;
921}
922
923static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
924SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
925 NULL, 0),
926SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
927 0, NULL, 0),
928
929SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
930 wm5100_cp_ev,
931 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
932SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
933 NULL, 0),
934SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
935 WM5100_CP2_BYPASS_SHIFT, 1, wm5100_cp_ev,
936 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
7aefb086
MB		 937SND_SOC_DAPM_SUPPLY("DBVDD2", SND_SOC_NOPM, 2, 0, wm5100_dbvdd_ev,
938 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
939SND_SOC_DAPM_SUPPLY("DBVDD3", SND_SOC_NOPM, 3, 0, wm5100_dbvdd_ev,
940 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
6d4baf08
MB		 941
942SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
943 0, NULL, 0),
944SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
945 0, NULL, 0),
946SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
947 0, NULL, 0),
948
949SND_SOC_DAPM_INPUT("IN1L"),
950SND_SOC_DAPM_INPUT("IN1R"),
951SND_SOC_DAPM_INPUT("IN2L"),
952SND_SOC_DAPM_INPUT("IN2R"),
953SND_SOC_DAPM_INPUT("IN3L"),
954SND_SOC_DAPM_INPUT("IN3R"),
955SND_SOC_DAPM_INPUT("IN4L"),
956SND_SOC_DAPM_INPUT("IN4R"),
dea8e237 957SND_SOC_DAPM_SIGGEN("TONE"),
6d4baf08
MB		 958
959SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
960 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
961SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
962 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
963SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
964 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
965SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
966 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
967SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
968 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
969SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
970 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
971SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
972 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
973SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
974 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
975
976SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
977 WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
978SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
979 WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
980
981SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
982 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
983SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
984 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
985SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
986 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
987SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
988 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
989SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
990 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
991SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
992 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
993SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
994 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
995SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
996 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
997
998SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
999 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
1000SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
1001 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
1002
1003SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
1004 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
1005SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
1006 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
1007
1008SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
1009 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
1010SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
1011 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
1012SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
1013 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
1014SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
1015 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
1016SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
1017 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
1018SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
1019 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
1020SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
1021 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
1022SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
1023 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
1024
1025SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
1026 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
1027SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
1028 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
1029
1030SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
1031 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
1032SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
1033 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
1034
1035SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
1036 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1037SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
1038 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1039SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
1040 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1041SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
1042 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1043SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
1044 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1045SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
1046 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1047SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
1048 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1049SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
1050 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1051SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
1052 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1053SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
1054 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1055SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
1056 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1057SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
1058 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1059SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
1060 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1061SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
1062 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1063
1064SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
1065SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
1066SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1067SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1068
1069SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1070 NULL, 0),
1071SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1072 NULL, 0),
1073
1074SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1075 NULL, 0),
1076SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1077 NULL, 0),
1078SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1079 NULL, 0),
1080SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1081 NULL, 0),
1082
1083WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1084WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1085WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1086WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1087
1088WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1089WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1090
1091WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1092WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1093WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1094WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1095
1096WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1097WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1098WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1099WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1100WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1101WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1102WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1103WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1104
1105WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1106WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1107
1108WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1109WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1110
1111WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1112WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1113WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1114WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1115WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1116WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1117
1118WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1119WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1120WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1121WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1122WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1123WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1124
1125WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1126WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1127
1128SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1129SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1130SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1131SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1132SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1133SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1134SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1135SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1136SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1137SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1138SND_SOC_DAPM_OUTPUT("PWM1"),
1139SND_SOC_DAPM_OUTPUT("PWM2"),
1140};
1141
1142/* We register a _POST event if we don't have IRQ support so we can
1143 * look at the error status from the CODEC - if we've got the IRQ
1144 * hooked up then we will get prompted to look by an interrupt.
1145 */
1146static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1147SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1148};
1149
1150static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1151 { "IN1L", NULL, "SYSCLK" },
1152 { "IN1R", NULL, "SYSCLK" },
1153 { "IN2L", NULL, "SYSCLK" },
1154 { "IN2R", NULL, "SYSCLK" },
1155 { "IN3L", NULL, "SYSCLK" },
1156 { "IN3R", NULL, "SYSCLK" },
1157 { "IN4L", NULL, "SYSCLK" },
1158 { "IN4R", NULL, "SYSCLK" },
1159
1160 { "OUT1L", NULL, "SYSCLK" },
1161 { "OUT1R", NULL, "SYSCLK" },
1162 { "OUT2L", NULL, "SYSCLK" },
1163 { "OUT2R", NULL, "SYSCLK" },
1164 { "OUT3L", NULL, "SYSCLK" },
1165 { "OUT3R", NULL, "SYSCLK" },
1166 { "OUT4L", NULL, "SYSCLK" },
1167 { "OUT4R", NULL, "SYSCLK" },
1168 { "OUT5L", NULL, "SYSCLK" },
1169 { "OUT5R", NULL, "SYSCLK" },
1170 { "OUT6L", NULL, "SYSCLK" },
1171 { "OUT6R", NULL, "SYSCLK" },
1172
1173 { "AIF1RX1", NULL, "SYSCLK" },
1174 { "AIF1RX2", NULL, "SYSCLK" },
1175 { "AIF1RX3", NULL, "SYSCLK" },
1176 { "AIF1RX4", NULL, "SYSCLK" },
1177 { "AIF1RX5", NULL, "SYSCLK" },
1178 { "AIF1RX6", NULL, "SYSCLK" },
1179 { "AIF1RX7", NULL, "SYSCLK" },
1180 { "AIF1RX8", NULL, "SYSCLK" },
1181
1182 { "AIF2RX1", NULL, "SYSCLK" },
7aefb086 1183 { "AIF2RX1", NULL, "DBVDD2" },
6d4baf08 1184 { "AIF2RX2", NULL, "SYSCLK" },
7aefb086 1185 { "AIF2RX2", NULL, "DBVDD2" },
6d4baf08
MB		 1186
1187 { "AIF3RX1", NULL, "SYSCLK" },
7aefb086 1188 { "AIF3RX1", NULL, "DBVDD3" },
6d4baf08 1189 { "AIF3RX2", NULL, "SYSCLK" },
7aefb086 1190 { "AIF3RX2", NULL, "DBVDD3" },
6d4baf08
MB		 1191
1192 { "AIF1TX1", NULL, "SYSCLK" },
1193 { "AIF1TX2", NULL, "SYSCLK" },
1194 { "AIF1TX3", NULL, "SYSCLK" },
1195 { "AIF1TX4", NULL, "SYSCLK" },
1196 { "AIF1TX5", NULL, "SYSCLK" },
1197 { "AIF1TX6", NULL, "SYSCLK" },
1198 { "AIF1TX7", NULL, "SYSCLK" },
1199 { "AIF1TX8", NULL, "SYSCLK" },
1200
1201 { "AIF2TX1", NULL, "SYSCLK" },
7aefb086 1202 { "AIF2TX1", NULL, "DBVDD2" },
6d4baf08 1203 { "AIF2TX2", NULL, "SYSCLK" },
7aefb086 1204 { "AIF2TX2", NULL, "DBVDD2" },
6d4baf08
MB		 1205
1206 { "AIF3TX1", NULL, "SYSCLK" },
7aefb086 1207 { "AIF3TX1", NULL, "DBVDD3" },
6d4baf08 1208 { "AIF3TX2", NULL, "SYSCLK" },
7aefb086 1209 { "AIF3TX2", NULL, "DBVDD3" },
6d4baf08
MB		 1210
1211 { "MICBIAS1", NULL, "CP2" },
1212 { "MICBIAS2", NULL, "CP2" },
1213 { "MICBIAS3", NULL, "CP2" },
1214
1215 { "IN1L PGA", NULL, "CP2" },
1216 { "IN1R PGA", NULL, "CP2" },
1217 { "IN2L PGA", NULL, "CP2" },
1218 { "IN2R PGA", NULL, "CP2" },
1219 { "IN3L PGA", NULL, "CP2" },
1220 { "IN3R PGA", NULL, "CP2" },
1221 { "IN4L PGA", NULL, "CP2" },
1222 { "IN4R PGA", NULL, "CP2" },
1223
1224 { "IN1L PGA", NULL, "CP2 Active" },
1225 { "IN1R PGA", NULL, "CP2 Active" },
1226 { "IN2L PGA", NULL, "CP2 Active" },
1227 { "IN2R PGA", NULL, "CP2 Active" },
1228 { "IN3L PGA", NULL, "CP2 Active" },
1229 { "IN3R PGA", NULL, "CP2 Active" },
1230 { "IN4L PGA", NULL, "CP2 Active" },
1231 { "IN4R PGA", NULL, "CP2 Active" },
1232
1233 { "OUT1L", NULL, "CP1" },
1234 { "OUT1R", NULL, "CP1" },
1235 { "OUT2L", NULL, "CP1" },
1236 { "OUT2R", NULL, "CP1" },
1237 { "OUT3L", NULL, "CP1" },
1238 { "OUT3R", NULL, "CP1" },
1239
1240 { "Tone Generator 1", NULL, "TONE" },
1241 { "Tone Generator 2", NULL, "TONE" },
1242
1243 { "IN1L PGA", NULL, "IN1L" },
1244 { "IN1R PGA", NULL, "IN1R" },
1245 { "IN2L PGA", NULL, "IN2L" },
1246 { "IN2R PGA", NULL, "IN2R" },
1247 { "IN3L PGA", NULL, "IN3L" },
1248 { "IN3R PGA", NULL, "IN3R" },
1249 { "IN4L PGA", NULL, "IN4L" },
1250 { "IN4R PGA", NULL, "IN4R" },
1251
1252 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1253 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1254 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1255 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1256 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1257 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1258
1259 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1260 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1261 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1262 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1263 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1264 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1265
1266 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1267 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1268
1269 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1270 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1271 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1272 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1273 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1274 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1275 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1276 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1277
1278 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1279 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1280
1281 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1282 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1283
1284 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1285 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1286 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1287 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1288
1289 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1290 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1291
1292 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1293 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1294 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1295 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1296
1297 { "HPOUT1L", NULL, "OUT1L" },
1298 { "HPOUT1R", NULL, "OUT1R" },
1299 { "HPOUT2L", NULL, "OUT2L" },
1300 { "HPOUT2R", NULL, "OUT2R" },
1301 { "HPOUT3L", NULL, "OUT3L" },
1302 { "HPOUT3R", NULL, "OUT3R" },
1303 { "SPKOUTL", NULL, "OUT4L" },
1304 { "SPKOUTR", NULL, "OUT4R" },
1305 { "SPKDAT1", NULL, "OUT5L" },
1306 { "SPKDAT1", NULL, "OUT5R" },
1307 { "SPKDAT2", NULL, "OUT6L" },
1308 { "SPKDAT2", NULL, "OUT6R" },
1309 { "PWM1", NULL, "PWM1 Driver" },
1310 { "PWM2", NULL, "PWM2 Driver" },
1311};
1312
15b52f10 1313static const __devinitdata struct reg_default wm5100_reva_patches[] = {
6d4baf08
MB		 1314 { WM5100_AUDIO_IF_1_10, 0 },
1315 { WM5100_AUDIO_IF_1_11, 1 },
1316 { WM5100_AUDIO_IF_1_12, 2 },
1317 { WM5100_AUDIO_IF_1_13, 3 },
1318 { WM5100_AUDIO_IF_1_14, 4 },
1319 { WM5100_AUDIO_IF_1_15, 5 },
1320 { WM5100_AUDIO_IF_1_16, 6 },
1321 { WM5100_AUDIO_IF_1_17, 7 },
1322
1323 { WM5100_AUDIO_IF_1_18, 0 },
1324 { WM5100_AUDIO_IF_1_19, 1 },
1325 { WM5100_AUDIO_IF_1_20, 2 },
1326 { WM5100_AUDIO_IF_1_21, 3 },
1327 { WM5100_AUDIO_IF_1_22, 4 },
1328 { WM5100_AUDIO_IF_1_23, 5 },
1329 { WM5100_AUDIO_IF_1_24, 6 },
1330 { WM5100_AUDIO_IF_1_25, 7 },
1331
1332 { WM5100_AUDIO_IF_2_10, 0 },
1333 { WM5100_AUDIO_IF_2_11, 1 },
1334
1335 { WM5100_AUDIO_IF_2_18, 0 },
1336 { WM5100_AUDIO_IF_2_19, 1 },
1337
1338 { WM5100_AUDIO_IF_3_10, 0 },
1339 { WM5100_AUDIO_IF_3_11, 1 },
1340
1341 { WM5100_AUDIO_IF_3_18, 0 },
1342 { WM5100_AUDIO_IF_3_19, 1 },
1343};
1344
1345static int wm5100_set_bias_level(struct snd_soc_codec *codec,
1346 enum snd_soc_bias_level level)
1347{
1348 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
5509f2f8 1349 int ret;
6d4baf08
MB		 1350
1351 switch (level) {
1352 case SND_SOC_BIAS_ON:
1353 break;
1354
1355 case SND_SOC_BIAS_PREPARE:
1356 break;
1357
1358 case SND_SOC_BIAS_STANDBY:
1359 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1360 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
1361 wm5100->core_supplies);
1362 if (ret != 0) {
1363 dev_err(codec->dev,
1364 "Failed to enable supplies: %d\n",
1365 ret);
1366 return ret;
1367 }
1368
1369 if (wm5100->pdata.ldo_ena) {
1370 gpio_set_value_cansleep(wm5100->pdata.ldo_ena,
1371 1);
1372 msleep(2);
1373 }
1374
bd132ec5 1375 regcache_cache_only(wm5100->regmap, false);
60bf5b07 1376 regcache_sync(wm5100->regmap);
6d4baf08
MB		 1377 }
1378 break;
1379
1380 case SND_SOC_BIAS_OFF:
e53e4173 1381 regcache_cache_only(wm5100->regmap, true);
6d4baf08
MB		 1382 if (wm5100->pdata.ldo_ena)
1383 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
1384 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
1385 wm5100->core_supplies);
1386 break;
1387 }
1388 codec->dapm.bias_level = level;
1389
1390 return 0;
1391}
1392
1393static int wm5100_dai_to_base(struct snd_soc_dai *dai)
1394{
1395 switch (dai->id) {
1396 case 0:
1397 return WM5100_AUDIO_IF_1_1 - 1;
1398 case 1:
1399 return WM5100_AUDIO_IF_2_1 - 1;
1400 case 2:
1401 return WM5100_AUDIO_IF_3_1 - 1;
1402 default:
1403 BUG();
1404 return -EINVAL;
1405 }
1406}
1407
1408static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1409{
1410 struct snd_soc_codec *codec = dai->codec;
1411 int lrclk, bclk, mask, base;
1412
1413 base = wm5100_dai_to_base(dai);
1414 if (base < 0)
1415 return base;
1416
1417 lrclk = 0;
1418 bclk = 0;
1419
1420 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1421 case SND_SOC_DAIFMT_DSP_A:
1422 mask = 0;
1423 break;
1424 case SND_SOC_DAIFMT_DSP_B:
1425 mask = 1;
1426 break;
1427 case SND_SOC_DAIFMT_I2S:
1428 mask = 2;
1429 break;
1430 case SND_SOC_DAIFMT_LEFT_J:
1431 mask = 3;
1432 break;
1433 default:
1434 dev_err(codec->dev, "Unsupported DAI format %d\n",
1435 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1436 return -EINVAL;
1437 }
1438
1439 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1440 case SND_SOC_DAIFMT_CBS_CFS:
1441 break;
1442 case SND_SOC_DAIFMT_CBS_CFM:
1443 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1444 break;
1445 case SND_SOC_DAIFMT_CBM_CFS:
1446 bclk |= WM5100_AIF1_BCLK_MSTR;
1447 break;
1448 case SND_SOC_DAIFMT_CBM_CFM:
1449 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1450 bclk |= WM5100_AIF1_BCLK_MSTR;
1451 break;
1452 default:
1453 dev_err(codec->dev, "Unsupported master mode %d\n",
1454 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1455 return -EINVAL;
1456 }
1457
1458 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1459 case SND_SOC_DAIFMT_NB_NF:
1460 break;
1461 case SND_SOC_DAIFMT_IB_IF:
1462 bclk |= WM5100_AIF1_BCLK_INV;
1463 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1464 break;
1465 case SND_SOC_DAIFMT_IB_NF:
1466 bclk |= WM5100_AIF1_BCLK_INV;
1467 break;
1468 case SND_SOC_DAIFMT_NB_IF:
1469 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1470 break;
1471 default:
1472 return -EINVAL;
1473 }
1474
1475 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1476 WM5100_AIF1_BCLK_INV, bclk);
1477 snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1478 WM5100_AIF1TX_LRCLK_INV, lrclk);
1479 snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1480 WM5100_AIF1TX_LRCLK_INV, lrclk);
1481 snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1482
1483 return 0;
1484}
1485
1486#define WM5100_NUM_BCLK_RATES 19
1487
1488static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1489 32000,
1490 48000,
1491 64000,
1492 96000,
1493 128000,
1494 192000,
d73ec75c 1495 256000,
6d4baf08
MB		 1496 384000,
1497 512000,
1498 768000,
1499 1024000,
1500 1536000,
1501 2048000,
1502 3072000,
1503 4096000,
1504 6144000,
1505 8192000,
1506 12288000,
1507 24576000,
1508};
1509
1510static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1511 29400,
1512 44100,
1513 58800,
1514 88200,
1515 117600,
1516 176400,
1517 235200,
1518 352800,
1519 470400,
1520 705600,
1521 940800,
1522 1411200,
1523 1881600,
1524 2882400,
1525 3763200,
1526 5644800,
1527 7526400,
1528 11289600,
1529 22579600,
1530};
1531
1532static int wm5100_hw_params(struct snd_pcm_substream *substream,
1533 struct snd_pcm_hw_params *params,
1534 struct snd_soc_dai *dai)
1535{
1536 struct snd_soc_codec *codec = dai->codec;
1537 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1538 bool async = wm5100->aif_async[dai->id];
1539 int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1540 int *bclk_rates;
1541
1542 base = wm5100_dai_to_base(dai);
1543 if (base < 0)
1544 return base;
1545
1546 /* Data sizes if not using TDM */
1547 wl = snd_pcm_format_width(params_format(params));
1548 if (wl < 0)
1549 return wl;
1550 fl = snd_soc_params_to_frame_size(params);
1551 if (fl < 0)
1552 return fl;
1553
1554 dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1555 wl, fl);
1556
1557 /* Target BCLK rate */
1558 bclk = snd_soc_params_to_bclk(params);
1559 if (bclk < 0)
1560 return bclk;
1561
1562 /* Root for BCLK depends on SYS/ASYNCCLK */
1563 if (!async) {
1564 aif_rate = wm5100->sysclk;
1565 sr = wm5100_alloc_sr(codec, params_rate(params));
1566 if (sr < 0)
1567 return sr;
1568 } else {
1569 /* If we're in ASYNCCLK set the ASYNC sample rate */
1570 aif_rate = wm5100->asyncclk;
1571 sr = 3;
1572
1573 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1574 if (params_rate(params) == wm5100_sr_code[i])
1575 break;
1576 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1577 dev_err(codec->dev, "Invalid rate %dHzn",
1578 params_rate(params));
1579 return -EINVAL;
1580 }
1581
1582 /* TODO: We should really check for symmetry */
1583 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1584 WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1585 }
1586
1587 if (!aif_rate) {
1588 dev_err(codec->dev, "%s has no rate set\n",
1589 async ? "ASYNCCLK" : "SYSCLK");
1590 return -EINVAL;
1591 }
1592
1593 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1594 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1595
1596 if (aif_rate % 4000)
1597 bclk_rates = wm5100_bclk_rates_cd;
1598 else
1599 bclk_rates = wm5100_bclk_rates_dat;
1600
1601 for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1602 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1603 break;
1604 if (i == WM5100_NUM_BCLK_RATES) {
1605 dev_err(codec->dev,
1606 "No valid BCLK for %dHz found from %dHz %s\n",
1607 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1608 return -EINVAL;
1609 }
1610
1611 bclk = i;
1612 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1613 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1614
1615 lrclk = bclk_rates[bclk] / params_rate(params);
1616 dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1617 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1618 wm5100->aif_symmetric[dai->id])
1619 snd_soc_update_bits(codec, base + 7,
1620 WM5100_AIF1RX_BCPF_MASK, lrclk);
1621 else
1622 snd_soc_update_bits(codec, base + 6,
1623 WM5100_AIF1TX_BCPF_MASK, lrclk);
1624
1625 i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1626 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1627 snd_soc_update_bits(codec, base + 9,
1628 WM5100_AIF1RX_WL_MASK |
1629 WM5100_AIF1RX_SLOT_LEN_MASK, i);
1630 else
1631 snd_soc_update_bits(codec, base + 8,
1632 WM5100_AIF1TX_WL_MASK |
1633 WM5100_AIF1TX_SLOT_LEN_MASK, i);
1634
1635 snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1636
1637 return 0;
1638}
1639
85e7652d 1640static const struct snd_soc_dai_ops wm5100_dai_ops = {
6d4baf08
MB		 1641 .set_fmt = wm5100_set_fmt,
1642 .hw_params = wm5100_hw_params,
1643};
1644
1645static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1646 int source, unsigned int freq, int dir)
1647{
1648 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1649 int *rate_store;
1650 int fval, audio_rate, ret, reg;
1651
1652 switch (clk_id) {
1653 case WM5100_CLK_SYSCLK:
1654 reg = WM5100_CLOCKING_3;
1655 rate_store = &wm5100->sysclk;
1656 break;
1657 case WM5100_CLK_ASYNCCLK:
1658 reg = WM5100_CLOCKING_7;
1659 rate_store = &wm5100->asyncclk;
1660 break;
1661 case WM5100_CLK_32KHZ:
1662 /* The 32kHz clock is slightly different to the others */
1663 switch (source) {
1664 case WM5100_CLKSRC_MCLK1:
1665 case WM5100_CLKSRC_MCLK2:
1666 case WM5100_CLKSRC_SYSCLK:
1667 snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1668 WM5100_CLK_32K_SRC_MASK,
1669 source);
1670 break;
1671 default:
1672 return -EINVAL;
1673 }
1674 return 0;
1675
1676 case WM5100_CLK_AIF1:
1677 case WM5100_CLK_AIF2:
1678 case WM5100_CLK_AIF3:
1679 /* Not real clocks, record which clock domain they're in */
1680 switch (source) {
1681 case WM5100_CLKSRC_SYSCLK:
1682 wm5100->aif_async[clk_id - 1] = false;
1683 break;
1684 case WM5100_CLKSRC_ASYNCCLK:
1685 wm5100->aif_async[clk_id - 1] = true;
1686 break;
1687 default:
1688 dev_err(codec->dev, "Invalid source %d\n", source);
1689 return -EINVAL;
1690 }
1691 return 0;
1692
1693 case WM5100_CLK_OPCLK:
1694 switch (freq) {
1695 case 5644800:
1696 case 6144000:
1697 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1698 WM5100_OPCLK_SEL_MASK, 0);
1699 break;
1700 case 11289600:
1701 case 12288000:
1702 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1703 WM5100_OPCLK_SEL_MASK, 0);
1704 break;
1705 case 22579200:
1706 case 24576000:
1707 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1708 WM5100_OPCLK_SEL_MASK, 0);
1709 break;
1710 default:
1711 dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1712 freq);
1713 return -EINVAL;
1714 }
1715 return 0;
1716
1717 default:
1718 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1719 return -EINVAL;
1720 }
1721
1722 switch (source) {
1723 case WM5100_CLKSRC_SYSCLK:
1724 case WM5100_CLKSRC_ASYNCCLK:
1725 dev_err(codec->dev, "Invalid source %d\n", source);
1726 return -EINVAL;
1727 }
1728
1729 switch (freq) {
1730 case 5644800:
1731 case 6144000:
1732 fval = 0;
1733 break;
1734 case 11289600:
1735 case 12288000:
1736 fval = 1;
1737 break;
1738 case 22579200:
11c2b5f2 1739 case 24576000:
6d4baf08
MB		 1740 fval = 2;
1741 break;
1742 default:
1743 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1744 return -EINVAL;
1745 }
1746
1747 switch (freq) {
1748 case 5644800:
1749 case 11289600:
1750 case 22579200:
1751 audio_rate = 44100;
1752 break;
1753
1754 case 6144000:
1755 case 12288000:
11c2b5f2 1756 case 24576000:
6d4baf08
MB		 1757 audio_rate = 48000;
1758 break;
1759
1760 default:
1761 BUG();
1762 audio_rate = 0;
1763 break;
1764 }
1765
1766 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1767 * match.
1768 */
1769
1770 snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1771 WM5100_SYSCLK_SRC_MASK,
1772 fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1773
1774 /* If this is SYSCLK then configure the clock rate for the
1775 * internal audio functions to the natural sample rate for
1776 * this clock rate.
1777 */
1778 if (clk_id == WM5100_CLK_SYSCLK) {
1779 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1780 audio_rate);
1781 if (0 && *rate_store)
1782 wm5100_free_sr(codec, audio_rate);
1783 ret = wm5100_alloc_sr(codec, audio_rate);
1784 if (ret != 0)
1785 dev_warn(codec->dev, "Primary audio slot is %d\n",
1786 ret);
1787 }
1788
1789 *rate_store = freq;
1790
1791 return 0;
1792}
1793
1794struct _fll_div {
1795 u16 fll_fratio;
1796 u16 fll_outdiv;
1797 u16 fll_refclk_div;
1798 u16 n;
1799 u16 theta;
1800 u16 lambda;
1801};
1802
1803static struct {
1804 unsigned int min;
1805 unsigned int max;
1806 u16 fll_fratio;
1807 int ratio;
1808} fll_fratios[] = {
1809 { 0, 64000, 4, 16 },
1810 { 64000, 128000, 3, 8 },
1811 { 128000, 256000, 2, 4 },
1812 { 256000, 1000000, 1, 2 },
1813 { 1000000, 13500000, 0, 1 },
1814};
1815
1816static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1817 unsigned int Fout)
1818{
1819 unsigned int target;
1820 unsigned int div;
1821 unsigned int fratio, gcd_fll;
1822 int i;
1823
1824 /* Fref must be <=13.5MHz */
1825 div = 1;
1826 fll_div->fll_refclk_div = 0;
1827 while ((Fref / div) > 13500000) {
1828 div *= 2;
1829 fll_div->fll_refclk_div++;
1830
1831 if (div > 8) {
1832 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1833 Fref);
1834 return -EINVAL;
1835 }
1836 }
1837
1838 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1839
1840 /* Apply the division for our remaining calculations */
1841 Fref /= div;
1842
1843 /* Fvco should be 90-100MHz; don't check the upper bound */
1844 div = 2;
1845 while (Fout * div < 90000000) {
1846 div++;
1847 if (div > 64) {
1848 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1849 Fout);
1850 return -EINVAL;
1851 }
1852 }
1853 target = Fout * div;
1854 fll_div->fll_outdiv = div - 1;
1855
1856 pr_debug("FLL Fvco=%dHz\n", target);
1857
1858 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1859 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1860 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1861 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1862 fratio = fll_fratios[i].ratio;
1863 break;
1864 }
1865 }
1866 if (i == ARRAY_SIZE(fll_fratios)) {
1867 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1868 return -EINVAL;
1869 }
1870
1871 fll_div->n = target / (fratio * Fref);
1872
1873 if (target % Fref == 0) {
1874 fll_div->theta = 0;
1875 fll_div->lambda = 0;
1876 } else {
1877 gcd_fll = gcd(target, fratio * Fref);
1878
1879 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1880 / gcd_fll;
1881 fll_div->lambda = (fratio * Fref) / gcd_fll;
1882 }
1883
1884 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1885 fll_div->n, fll_div->theta, fll_div->lambda);
1886 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1887 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1888 fll_div->fll_refclk_div);
1889
1890 return 0;
1891}
1892
1893static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1894 unsigned int Fref, unsigned int Fout)
1895{
1896 struct i2c_client *i2c = to_i2c_client(codec->dev);
1897 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1898 struct _fll_div factors;
1899 struct wm5100_fll *fll;
1900 int ret, base, lock, i, timeout;
1901
1902 switch (fll_id) {
1903 case WM5100_FLL1:
1904 fll = &wm5100->fll[0];
1905 base = WM5100_FLL1_CONTROL_1 - 1;
1906 lock = WM5100_FLL1_LOCK_STS;
1907 break;
1908 case WM5100_FLL2:
1909 fll = &wm5100->fll[1];
1910 base = WM5100_FLL2_CONTROL_2 - 1;
1911 lock = WM5100_FLL2_LOCK_STS;
1912 break;
1913 default:
1914 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1915 return -EINVAL;
1916 }
1917
1918 if (!Fout) {
1919 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1920 fll->fout = 0;
1921 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1922 return 0;
1923 }
1924
1925 switch (source) {
1926 case WM5100_FLL_SRC_MCLK1:
1927 case WM5100_FLL_SRC_MCLK2:
1928 case WM5100_FLL_SRC_FLL1:
1929 case WM5100_FLL_SRC_FLL2:
1930 case WM5100_FLL_SRC_AIF1BCLK:
1931 case WM5100_FLL_SRC_AIF2BCLK:
1932 case WM5100_FLL_SRC_AIF3BCLK:
1933 break;
1934 default:
1935 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1936 return -EINVAL;
1937 }
1938
1939 ret = fll_factors(&factors, Fref, Fout);
1940 if (ret < 0)
1941 return ret;
1942
1943 /* Disable the FLL while we reconfigure */
1944 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1945
1946 snd_soc_update_bits(codec, base + 2,
1947 WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1948 (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1949 factors.fll_fratio);
1950 snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1951 factors.theta);
1952 snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1953 snd_soc_update_bits(codec, base + 6,
1954 WM5100_FLL1_REFCLK_DIV_MASK |
1955 WM5100_FLL1_REFCLK_SRC_MASK,
1956 (factors.fll_refclk_div
1957 << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1958 snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1959 factors.lambda);
1960
1961 /* Clear any pending completions */
1962 try_wait_for_completion(&fll->lock);
1963
1964 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1965
1966 if (i2c->irq)
1967 timeout = 2;
1968 else
1969 timeout = 50;
1970
bd132ec5
MB		 1971 snd_soc_update_bits(codec, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
1972 WM5100_SYSCLK_ENA);
1973
6d4baf08
MB		 1974 /* Poll for the lock; will use interrupt when we can test */
1975 for (i = 0; i < timeout; i++) {
1976 if (i2c->irq) {
1977 ret = wait_for_completion_timeout(&fll->lock,
1978 msecs_to_jiffies(25));
1979 if (ret > 0)
1980 break;
1981 } else {
1982 msleep(1);
1983 }
1984
1985 ret = snd_soc_read(codec,
1986 WM5100_INTERRUPT_RAW_STATUS_3);
1987 if (ret < 0) {
1988 dev_err(codec->dev,
1989 "Failed to read FLL status: %d\n",
1990 ret);
1991 continue;
1992 }
1993 if (ret & lock)
1994 break;
1995 }
1996 if (i == timeout) {
1997 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
1998 return -ETIMEDOUT;
1999 }
2000
2001 fll->src = source;
2002 fll->fref = Fref;
2003 fll->fout = Fout;
2004
2005 dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
2006 Fref, Fout);
2007
2008 return 0;
2009}
2010
2011/* Actually go much higher */
2012#define WM5100_RATES SNDRV_PCM_RATE_8000_192000
2013
2014#define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2015 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2016
2017static struct snd_soc_dai_driver wm5100_dai[] = {
2018 {
2019 .name = "wm5100-aif1",
2020 .playback = {
2021 .stream_name = "AIF1 Playback",
2022 .channels_min = 2,
2023 .channels_max = 2,
2024 .rates = WM5100_RATES,
2025 .formats = WM5100_FORMATS,
2026 },
2027 .capture = {
2028 .stream_name = "AIF1 Capture",
2029 .channels_min = 2,
2030 .channels_max = 2,
2031 .rates = WM5100_RATES,
2032 .formats = WM5100_FORMATS,
2033 },
2034 .ops = &wm5100_dai_ops,
2035 },
2036 {
2037 .name = "wm5100-aif2",
2038 .id = 1,
2039 .playback = {
2040 .stream_name = "AIF2 Playback",
2041 .channels_min = 2,
2042 .channels_max = 2,
2043 .rates = WM5100_RATES,
2044 .formats = WM5100_FORMATS,
2045 },
2046 .capture = {
2047 .stream_name = "AIF2 Capture",
2048 .channels_min = 2,
2049 .channels_max = 2,
2050 .rates = WM5100_RATES,
2051 .formats = WM5100_FORMATS,
2052 },
2053 .ops = &wm5100_dai_ops,
2054 },
2055 {
2056 .name = "wm5100-aif3",
2057 .id = 2,
2058 .playback = {
2059 .stream_name = "AIF3 Playback",
2060 .channels_min = 2,
2061 .channels_max = 2,
2062 .rates = WM5100_RATES,
2063 .formats = WM5100_FORMATS,
2064 },
2065 .capture = {
2066 .stream_name = "AIF3 Capture",
2067 .channels_min = 2,
2068 .channels_max = 2,
2069 .rates = WM5100_RATES,
2070 .formats = WM5100_FORMATS,
2071 },
2072 .ops = &wm5100_dai_ops,
2073 },
2074};
2075
2076static int wm5100_dig_vu[] = {
2077 WM5100_ADC_DIGITAL_VOLUME_1L,
2078 WM5100_ADC_DIGITAL_VOLUME_1R,
2079 WM5100_ADC_DIGITAL_VOLUME_2L,
2080 WM5100_ADC_DIGITAL_VOLUME_2R,
2081 WM5100_ADC_DIGITAL_VOLUME_3L,
2082 WM5100_ADC_DIGITAL_VOLUME_3R,
2083 WM5100_ADC_DIGITAL_VOLUME_4L,
2084 WM5100_ADC_DIGITAL_VOLUME_4R,
2085
2086 WM5100_DAC_DIGITAL_VOLUME_1L,
2087 WM5100_DAC_DIGITAL_VOLUME_1R,
2088 WM5100_DAC_DIGITAL_VOLUME_2L,
2089 WM5100_DAC_DIGITAL_VOLUME_2R,
2090 WM5100_DAC_DIGITAL_VOLUME_3L,
2091 WM5100_DAC_DIGITAL_VOLUME_3R,
2092 WM5100_DAC_DIGITAL_VOLUME_4L,
2093 WM5100_DAC_DIGITAL_VOLUME_4R,
2094 WM5100_DAC_DIGITAL_VOLUME_5L,
2095 WM5100_DAC_DIGITAL_VOLUME_5R,
2096 WM5100_DAC_DIGITAL_VOLUME_6L,
2097 WM5100_DAC_DIGITAL_VOLUME_6R,
2098};
2099
46c1a877 2100static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
ba896ede 2101{
ba896ede
MB		 2102 struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
2103
2104 BUG_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes));
2105
2106 gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
46c1a877
MB		 2107 regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
2108 WM5100_ACCDET_BIAS_SRC_MASK |
2109 WM5100_ACCDET_SRC,
2110 (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
2111 mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
2112 regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
2113 WM5100_HPCOM_SRC,
2114 mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
ba896ede
MB		 2115
2116 wm5100->jack_mode = the_mode;
2117
46c1a877 2118 dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
ba896ede
MB		 2119 wm5100->jack_mode);
2120}
2121
46c1a877 2122static void wm5100_micd_irq(struct wm5100_priv *wm5100)
ba896ede 2123{
46c1a877
MB		 2124 unsigned int val;
2125 int ret;
ba896ede 2126
46c1a877
MB		 2127 ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
2128 if (ret != 0) {
2129 dev_err(wm5100->dev, "Failed to read micropone status: %d\n",
2130 ret);
2131 return;
2132 }
ba896ede 2133
46c1a877 2134 dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
ba896ede
MB		 2135
2136 if (!(val & WM5100_ACCDET_VALID)) {
46c1a877 2137 dev_warn(wm5100->dev, "Microphone detection state invalid\n");
ba896ede
MB		 2138 return;
2139 }
2140
2141 /* No accessory, reset everything and report removal */
2142 if (!(val & WM5100_ACCDET_STS)) {
46c1a877 2143 dev_dbg(wm5100->dev, "Jack removal detected\n");
ba896ede
MB		 2144 wm5100->jack_mic = false;
2145 wm5100->jack_detecting = true;
2146 snd_soc_jack_report(wm5100->jack, 0,
2147 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2148 SND_JACK_BTN_0);
2149
46c1a877
MB		 2150 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2151 WM5100_ACCDET_RATE_MASK,
2152 WM5100_ACCDET_RATE_MASK);
ba896ede
MB		 2153 return;
2154 }
2155
2156 /* If the measurement is very high we've got a microphone,
2157 * either we just detected one or if we already reported then
2158 * we've got a button release event.
2159 */
2160 if (val & 0x400) {
2161 if (wm5100->jack_detecting) {
46c1a877 2162 dev_dbg(wm5100->dev, "Microphone detected\n");
ba896ede
MB		 2163 wm5100->jack_mic = true;
2164 snd_soc_jack_report(wm5100->jack,
2165 SND_JACK_HEADSET,
2166 SND_JACK_HEADSET | SND_JACK_BTN_0);
2167
2168 /* Increase poll rate to give better responsiveness
2169 * for buttons */
46c1a877
MB		 2170 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2171 WM5100_ACCDET_RATE_MASK,
2172 5 << WM5100_ACCDET_RATE_SHIFT);
ba896ede 2173 } else {
46c1a877 2174 dev_dbg(wm5100->dev, "Mic button up\n");
ba896ede
MB		 2175 snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2176 }
2177
2178 return;
2179 }
2180
2181 /* If we detected a lower impedence during initial startup
2182 * then we probably have the wrong polarity, flip it. Don't
2183 * do this for the lowest impedences to speed up detection of
2184 * plain headphones.
2185 */
2186 if (wm5100->jack_detecting && (val & 0x3f8)) {
46c1a877 2187 wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
ba896ede
MB		 2188
2189 return;
2190 }
2191
2192 /* Don't distinguish between buttons, just report any low
2193 * impedence as BTN_0.
2194 */
2195 if (val & 0x3fc) {
2196 if (wm5100->jack_mic) {
46c1a877 2197 dev_dbg(wm5100->dev, "Mic button detected\n");
ba896ede
MB		 2198 snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2199 SND_JACK_BTN_0);
2200 } else if (wm5100->jack_detecting) {
46c1a877 2201 dev_dbg(wm5100->dev, "Headphone detected\n");
ba896ede
MB		 2202 snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
2203 SND_JACK_HEADPHONE);
2204
2205 /* Increase the detection rate a bit for
2206 * responsiveness.
2207 */
46c1a877
MB		 2208 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2209 WM5100_ACCDET_RATE_MASK,
2210 7 << WM5100_ACCDET_RATE_SHIFT);
ba896ede
MB		 2211 }
2212 }
2213}
2214
2215int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2216{
2217 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2218
2219 if (jack) {
2220 wm5100->jack = jack;
2221 wm5100->jack_detecting = true;
2222
46c1a877 2223 wm5100_set_detect_mode(wm5100, 0);
ba896ede
MB		 2224
2225 /* Slowest detection rate, gives debounce for initial
2226 * detection */
2227 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2228 WM5100_ACCDET_BIAS_STARTTIME_MASK |
2229 WM5100_ACCDET_RATE_MASK,
2230 (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2231 WM5100_ACCDET_RATE_MASK);
2232
2233 /* We need the charge pump to power MICBIAS */
2234 snd_soc_dapm_force_enable_pin(&codec->dapm, "CP2");
2235 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2236 snd_soc_dapm_sync(&codec->dapm);
2237
2238 /* We start off just enabling microphone detection - even a
2239 * plain headphone will trigger detection.
2240 */
2241 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2242 WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2243
2244 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2245 WM5100_IM_ACCDET_EINT, 0);
2246 } else {
2247 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2248 WM5100_IM_HPDET_EINT |
2249 WM5100_IM_ACCDET_EINT,
2250 WM5100_IM_HPDET_EINT |
2251 WM5100_IM_ACCDET_EINT);
2252 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2253 WM5100_ACCDET_ENA, 0);
2254 wm5100->jack = NULL;
2255 }
2256
2257 return 0;
2258}
2259
6d4baf08
MB		 2260static irqreturn_t wm5100_irq(int irq, void *data)
2261{
46c1a877 2262 struct wm5100_priv *wm5100 = data;
6d4baf08 2263 irqreturn_t status = IRQ_NONE;
46c1a877
MB		 2264 unsigned int irq_val, mask_val;
2265 int ret;
6d4baf08 2266
46c1a877
MB		 2267 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
2268 if (ret < 0) {
2269 dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
2270 ret);
6d4baf08
MB		 2271 irq_val = 0;
2272 }
6d4baf08 2273
46c1a877
MB		 2274 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
2275 &mask_val);
2276 if (ret < 0) {
2277 dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
2278 ret);
2279 mask_val = 0xffff;
2280 }
2281
2282 irq_val &= ~mask_val;
2283
2284 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
6d4baf08
MB		 2285
2286 if (irq_val)
2287 status = IRQ_HANDLED;
2288
46c1a877 2289 wm5100_log_status3(wm5100, irq_val);
6d4baf08
MB		 2290
2291 if (irq_val & WM5100_FLL1_LOCK_EINT) {
46c1a877 2292 dev_dbg(wm5100->dev, "FLL1 locked\n");
6d4baf08
MB		 2293 complete(&wm5100->fll[0].lock);
2294 }
2295 if (irq_val & WM5100_FLL2_LOCK_EINT) {
46c1a877 2296 dev_dbg(wm5100->dev, "FLL2 locked\n");
6d4baf08
MB		 2297 complete(&wm5100->fll[1].lock);
2298 }
2299
ba896ede 2300 if (irq_val & WM5100_ACCDET_EINT)
46c1a877 2301 wm5100_micd_irq(wm5100);
ba896ede 2302
46c1a877
MB		 2303 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
2304 if (ret < 0) {
2305 dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
2306 ret);
6d4baf08
MB		 2307 irq_val = 0;
2308 }
46c1a877
MB		 2309
2310 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
2311 &mask_val);
2312 if (ret < 0) {
2313 dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
2314 ret);
2315 mask_val = 0xffff;
2316 }
2317
2318 irq_val &= ~mask_val;
6d4baf08
MB		 2319
2320 if (irq_val)
2321 status = IRQ_HANDLED;
2322
46c1a877 2323 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
6d4baf08 2324
46c1a877 2325 wm5100_log_status4(wm5100, irq_val);
6d4baf08
MB		 2326
2327 return status;
2328}
2329
2330static irqreturn_t wm5100_edge_irq(int irq, void *data)
2331{
2332 irqreturn_t ret = IRQ_NONE;
2333 irqreturn_t val;
2334
2335 do {
2336 val = wm5100_irq(irq, data);
2337 if (val != IRQ_NONE)
2338 ret = val;
2339 } while (val != IRQ_NONE);
2340
2341 return ret;
2342}
2343
2344#ifdef CONFIG_GPIOLIB
2345static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2346{
2347 return container_of(chip, struct wm5100_priv, gpio_chip);
2348}
2349
2350static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2351{
2352 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
6d4baf08 2353
9db16e4c
MB		 2354 regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2355 WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
6d4baf08
MB		 2356}
2357
2358static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2359 unsigned offset, int value)
2360{
2361 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
64964e82 2362 int val, ret;
6d4baf08
MB		 2363
2364 val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2365
9db16e4c
MB		 2366 ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2367 WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2368 WM5100_GP1_LVL, val);
64964e82
MB		 2369 if (ret < 0)
2370 return ret;
2371 else
2372 return 0;
6d4baf08
MB		 2373}
2374
2375static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2376{
2377 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
9db16e4c 2378 unsigned int reg;
6d4baf08
MB		 2379 int ret;
2380
9db16e4c 2381 ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, &reg);
6d4baf08
MB		 2382 if (ret < 0)
2383 return ret;
2384
9db16e4c 2385 return (reg & WM5100_GP1_LVL) != 0;
6d4baf08
MB		 2386}
2387
2388static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2389{
2390 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
6d4baf08 2391
9db16e4c
MB		 2392 return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2393 WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2394 (1 << WM5100_GP1_FN_SHIFT) |
2395 (1 << WM5100_GP1_DIR_SHIFT));
6d4baf08
MB		 2396}
2397
2398static struct gpio_chip wm5100_template_chip = {
2399 .label = "wm5100",
2400 .owner = THIS_MODULE,
2401 .direction_output = wm5100_gpio_direction_out,
2402 .set = wm5100_gpio_set,
2403 .direction_input = wm5100_gpio_direction_in,
2404 .get = wm5100_gpio_get,
2405 .can_sleep = 1,
2406};
2407
9db16e4c 2408static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08 2409{
9db16e4c 2410 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08
MB		 2411 int ret;
2412
2413 wm5100->gpio_chip = wm5100_template_chip;
2414 wm5100->gpio_chip.ngpio = 6;
9db16e4c 2415 wm5100->gpio_chip.dev = &i2c->dev;
6d4baf08
MB		 2416
2417 if (wm5100->pdata.gpio_base)
2418 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2419 else
2420 wm5100->gpio_chip.base = -1;
2421
2422 ret = gpiochip_add(&wm5100->gpio_chip);
2423 if (ret != 0)
9db16e4c 2424 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
6d4baf08
MB		 2425}
2426
9db16e4c 2427static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08 2428{
9db16e4c 2429 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08
MB		 2430 int ret;
2431
2432 ret = gpiochip_remove(&wm5100->gpio_chip);
2433 if (ret != 0)
9db16e4c 2434 dev_err(&i2c->dev, "Failed to remove GPIOs: %d\n", ret);
6d4baf08
MB		 2435}
2436#else
9db16e4c 2437static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2438{
2439}
2440
9db16e4c 2441static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2442{
2443}
2444#endif
2445
2446static int wm5100_probe(struct snd_soc_codec *codec)
2447{
2448 struct i2c_client *i2c = to_i2c_client(codec->dev);
2449 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
09452f23 2450 int ret, i;
6d4baf08
MB		 2451
2452 wm5100->codec = codec;
bd132ec5 2453 codec->control_data = wm5100->regmap;
6d4baf08 2454
bd132ec5 2455 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
6d4baf08
MB		 2456 if (ret != 0) {
2457 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2458 return ret;
2459 }
2460
bd132ec5 2461 regcache_cache_only(wm5100->regmap, true);
6d4baf08 2462
6d4baf08
MB		 2463
2464 for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2465 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2466 WM5100_OUT_VU);
2467
6d4baf08
MB		 2468 /* Don't debounce interrupts to support use of SYSCLK only */
2469 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2470 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2471
2472 /* TODO: check if we're symmetric */
2473
09452f23 2474 if (i2c->irq)
6d4baf08
MB		 2475 snd_soc_dapm_new_controls(&codec->dapm,
2476 wm5100_dapm_widgets_noirq,
2477 ARRAY_SIZE(wm5100_dapm_widgets_noirq));
6d4baf08
MB		 2478
2479 if (wm5100->pdata.hp_pol) {
2480 ret = gpio_request_one(wm5100->pdata.hp_pol,
2481 GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2482 if (ret < 0) {
2483 dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2484 wm5100->pdata.hp_pol, ret);
2485 goto err_gpio;
2486 }
2487 }
2488
2489 /* We'll get woken up again when the system has something useful
2490 * for us to do.
2491 */
2492 if (wm5100->pdata.ldo_ena)
2493 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2494 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2495 wm5100->core_supplies);
2496
2497 return 0;
2498
2499err_gpio:
6d4baf08
MB		 2500
2501 return ret;
2502}
2503
2504static int wm5100_remove(struct snd_soc_codec *codec)
2505{
2506 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2507
6d4baf08
MB		 2508 if (wm5100->pdata.hp_pol) {
2509 gpio_free(wm5100->pdata.hp_pol);
2510 }
46c1a877 2511
6d4baf08
MB		 2512 return 0;
2513}
2514
1b39bf34
MB		 2515static int wm5100_soc_volatile(struct snd_soc_codec *codec,
2516 unsigned int reg)
2517{
2518 return true;
2519}
2520
2521
6d4baf08
MB		 2522static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2523 .probe = wm5100_probe,
2524 .remove = wm5100_remove,
2525
2526 .set_sysclk = wm5100_set_sysclk,
2527 .set_pll = wm5100_set_fll,
2528 .set_bias_level = wm5100_set_bias_level,
2529 .idle_bias_off = 1,
1b39bf34
MB		 2530 .reg_cache_size = WM5100_MAX_REGISTER,
2531 .volatile_register = wm5100_soc_volatile,
6d4baf08
MB		 2532
2533 .seq_notifier = wm5100_seq_notifier,
2534 .controls = wm5100_snd_controls,
2535 .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2536 .dapm_widgets = wm5100_dapm_widgets,
2537 .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2538 .dapm_routes = wm5100_dapm_routes,
2539 .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
bd132ec5 2540};
6d4baf08 2541
bd132ec5
MB		 2542static const struct regmap_config wm5100_regmap = {
2543 .reg_bits = 16,
2544 .val_bits = 16,
6d4baf08 2545
bd132ec5
MB		 2546 .max_register = WM5100_MAX_REGISTER,
2547 .reg_defaults = wm5100_reg_defaults,
2548 .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2549 .volatile_reg = wm5100_volatile_register,
2550 .readable_reg = wm5100_readable_register,
2551 .cache_type = REGCACHE_RBTREE,
6d4baf08
MB		 2552};
2553
2554static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2555 const struct i2c_device_id *id)
2556{
2557 struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2558 struct wm5100_priv *wm5100;
588ac5e0 2559 unsigned int reg;
09452f23 2560 int ret, i, irq_flags;
6d4baf08 2561
a81b82c0
MB		 2562 wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2563 GFP_KERNEL);
6d4baf08
MB		 2564 if (wm5100 == NULL)
2565 return -ENOMEM;
2566
46c1a877
MB		 2567 wm5100->dev = &i2c->dev;
2568
bd132ec5
MB		 2569 wm5100->regmap = regmap_init_i2c(i2c, &wm5100_regmap);
2570 if (IS_ERR(wm5100->regmap)) {
2571 ret = PTR_ERR(wm5100->regmap);
2572 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2573 ret);
a81b82c0 2574 goto err;
bd132ec5
MB		 2575 }
2576
6d4baf08
MB		 2577 for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2578 init_completion(&wm5100->fll[i].lock);
2579
2580 if (pdata)
2581 wm5100->pdata = *pdata;
2582
2583 i2c_set_clientdata(i2c, wm5100);
2584
588ac5e0
MB		 2585 for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2586 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2587
2588 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm5100->core_supplies),
2589 wm5100->core_supplies);
2590 if (ret != 0) {
2591 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2592 ret);
2593 goto err_regmap;
2594 }
2595
2596 wm5100->cpvdd = regulator_get(&i2c->dev, "CPVDD");
2597 if (IS_ERR(wm5100->cpvdd)) {
2598 ret = PTR_ERR(wm5100->cpvdd);
2599 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
2600 goto err_core;
2601 }
2602
2603 wm5100->dbvdd2 = regulator_get(&i2c->dev, "DBVDD2");
2604 if (IS_ERR(wm5100->dbvdd2)) {
2605 ret = PTR_ERR(wm5100->dbvdd2);
2606 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2607 goto err_cpvdd;
2608 }
2609
2610 wm5100->dbvdd3 = regulator_get(&i2c->dev, "DBVDD3");
2611 if (IS_ERR(wm5100->dbvdd3)) {
2612 ret = PTR_ERR(wm5100->dbvdd3);
2613 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2614 goto err_dbvdd2;
2615 }
2616
2617 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2618 wm5100->core_supplies);
2619 if (ret != 0) {
2620 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2621 ret);
2622 goto err_dbvdd3;
2623 }
2624
2625 if (wm5100->pdata.ldo_ena) {
2626 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2627 GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2628 if (ret < 0) {
2629 dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2630 wm5100->pdata.ldo_ena, ret);
2631 goto err_enable;
2632 }
2633 msleep(2);
2634 }
2635
2636 if (wm5100->pdata.reset) {
2637 ret = gpio_request_one(wm5100->pdata.reset,
2638 GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2639 if (ret < 0) {
2640 dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2641 wm5100->pdata.reset, ret);
2642 goto err_ldo;
2643 }
2644 }
2645
2646 ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, &reg);
2647 if (ret < 0) {
0132615d 2648 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
588ac5e0
MB		 2649 goto err_reset;
2650 }
2651 switch (reg) {
2652 case 0x8997:
2653 case 0x5100:
2654 break;
2655
2656 default:
2657 dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2658 ret = -EINVAL;
2659 goto err_reset;
2660 }
2661
2662 ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, &reg);
2663 if (ret < 0) {
2664 dev_err(&i2c->dev, "Failed to read revision register\n");
2665 goto err_reset;
2666 }
2667 wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2668
2669 dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2670
2671 ret = wm5100_reset(wm5100);
2672 if (ret < 0) {
2673 dev_err(&i2c->dev, "Failed to issue reset\n");
2674 goto err_reset;
2675 }
2676
15b52f10
MB		 2677 switch (wm5100->rev) {
2678 case 0:
2679 ret = regmap_register_patch(wm5100->regmap,
2680 wm5100_reva_patches,
2681 ARRAY_SIZE(wm5100_reva_patches));
2682 if (ret != 0) {
2683 dev_err(&i2c->dev, "Failed to register patches: %d\n",
2684 ret);
2685 goto err_reset;
2686 }
2687 break;
2688 default:
2689 break;
2690 }
2691
2692
9db16e4c
MB		 2693 wm5100_init_gpio(i2c);
2694
d9b5e9c6
MB		 2695 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2696 if (!wm5100->pdata.gpio_defaults[i])
2697 continue;
2698
2699 regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2700 wm5100->pdata.gpio_defaults[i]);
2701 }
2702
2703 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2704 regmap_update_bits(wm5100->regmap, WM5100_IN1L_CONTROL,
2705 WM5100_IN1_MODE_MASK |
2706 WM5100_IN1_DMIC_SUP_MASK,
2707 (wm5100->pdata.in_mode[i] <<
2708 WM5100_IN1_MODE_SHIFT) |
2709 (wm5100->pdata.dmic_sup[i] <<
2710 WM5100_IN1_DMIC_SUP_SHIFT));
2711 }
2712
09452f23
MB		 2713 if (i2c->irq) {
2714 if (wm5100->pdata.irq_flags)
2715 irq_flags = wm5100->pdata.irq_flags;
2716 else
2717 irq_flags = IRQF_TRIGGER_LOW;
2718
2719 irq_flags |= IRQF_ONESHOT;
2720
2721 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2722 ret = request_threaded_irq(i2c->irq, NULL,
2723 wm5100_edge_irq, irq_flags,
2724 "wm5100", wm5100);
2725 else
2726 ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2727 irq_flags, "wm5100",
2728 wm5100);
2729
2730 if (ret != 0) {
2731 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2732 i2c->irq, ret);
2733 } else {
2734 /* Enable default interrupts */
2735 regmap_update_bits(wm5100->regmap,
2736 WM5100_INTERRUPT_STATUS_3_MASK,
2737 WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2738 WM5100_IM_SPK_SHUTDOWN_EINT |
2739 WM5100_IM_ASRC2_LOCK_EINT |
2740 WM5100_IM_ASRC1_LOCK_EINT |
2741 WM5100_IM_FLL2_LOCK_EINT |
2742 WM5100_IM_FLL1_LOCK_EINT |
2743 WM5100_CLKGEN_ERR_EINT |
2744 WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2745
2746 regmap_update_bits(wm5100->regmap,
2747 WM5100_INTERRUPT_STATUS_4_MASK,
2748 WM5100_AIF3_ERR_EINT |
2749 WM5100_AIF2_ERR_EINT |
2750 WM5100_AIF1_ERR_EINT |
2751 WM5100_CTRLIF_ERR_EINT |
2752 WM5100_ISRC2_UNDERCLOCKED_EINT |
2753 WM5100_ISRC1_UNDERCLOCKED_EINT |
2754 WM5100_FX_UNDERCLOCKED_EINT |
2755 WM5100_AIF3_UNDERCLOCKED_EINT |
2756 WM5100_AIF2_UNDERCLOCKED_EINT |
2757 WM5100_AIF1_UNDERCLOCKED_EINT |
2758 WM5100_ASRC_UNDERCLOCKED_EINT |
2759 WM5100_DAC_UNDERCLOCKED_EINT |
2760 WM5100_ADC_UNDERCLOCKED_EINT |
2761 WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2762 }
2763 }
2764
6d4baf08
MB		 2765 ret = snd_soc_register_codec(&i2c->dev,
2766 &soc_codec_dev_wm5100, wm5100_dai,
2767 ARRAY_SIZE(wm5100_dai));
2768 if (ret < 0) {
2769 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
588ac5e0 2770 goto err_reset;
6d4baf08
MB		 2771 }
2772
2773 return ret;
bd132ec5 2774
588ac5e0 2775err_reset:
09452f23
MB		 2776 if (i2c->irq)
2777 free_irq(i2c->irq, wm5100);
9db16e4c 2778 wm5100_free_gpio(i2c);
588ac5e0 2779 if (wm5100->pdata.reset) {
2688738e 2780 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
588ac5e0
MB		 2781 gpio_free(wm5100->pdata.reset);
2782 }
2783err_ldo:
2784 if (wm5100->pdata.ldo_ena) {
2785 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2786 gpio_free(wm5100->pdata.ldo_ena);
2787 }
2788err_enable:
2789 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2790 wm5100->core_supplies);
2791err_dbvdd3:
2792 regulator_put(wm5100->dbvdd3);
2793err_dbvdd2:
2794 regulator_put(wm5100->dbvdd2);
2795err_cpvdd:
2796 regulator_put(wm5100->cpvdd);
2797err_core:
2798 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2799 wm5100->core_supplies);
bd132ec5
MB		 2800err_regmap:
2801 regmap_exit(wm5100->regmap);
a81b82c0 2802err:
bd132ec5 2803 return ret;
6d4baf08
MB		 2804}
2805
09452f23 2806static __devexit int wm5100_i2c_remove(struct i2c_client *i2c)
6d4baf08 2807{
09452f23 2808 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
bd132ec5 2809
09452f23
MB		 2810 snd_soc_unregister_codec(&i2c->dev);
2811 if (i2c->irq)
2812 free_irq(i2c->irq, wm5100);
2813 wm5100_free_gpio(i2c);
588ac5e0 2814 if (wm5100->pdata.reset) {
2688738e 2815 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
588ac5e0
MB		 2816 gpio_free(wm5100->pdata.reset);
2817 }
2818 if (wm5100->pdata.ldo_ena) {
2819 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2820 gpio_free(wm5100->pdata.ldo_ena);
2821 }
2822 regulator_put(wm5100->dbvdd3);
2823 regulator_put(wm5100->dbvdd2);
2824 regulator_put(wm5100->cpvdd);
2825 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2826 wm5100->core_supplies);
bd132ec5 2827 regmap_exit(wm5100->regmap);
bd132ec5 2828
6d4baf08
MB		 2829 return 0;
2830}
2831
2832static const struct i2c_device_id wm5100_i2c_id[] = {
2833 { "wm5100", 0 },
2834 { }
2835};
2836MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2837
2838static struct i2c_driver wm5100_i2c_driver = {
2839 .driver = {
2840 .name = "wm5100",
2841 .owner = THIS_MODULE,
2842 },
2843 .probe = wm5100_i2c_probe,
2844 .remove = __devexit_p(wm5100_i2c_remove),
2845 .id_table = wm5100_i2c_id,
2846};
2847
2848static int __init wm5100_modinit(void)
2849{
2850 return i2c_add_driver(&wm5100_i2c_driver);
2851}
2852module_init(wm5100_modinit);
2853
2854static void __exit wm5100_exit(void)
2855{
2856 i2c_del_driver(&wm5100_i2c_driver);
2857}
2858module_exit(wm5100_exit);
2859
2860MODULE_DESCRIPTION("ASoC WM5100 driver");
2861MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2862MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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