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phy / PM: Replace CONFIG_PM_RUNTIME with CONFIG_PM
[deliverable/linux.git] / sound / soc / codecs / wm5100.c
CommitLineData
6d4baf08
MB		 1/*
2 * wm5100.c -- WM5100 ALSA SoC Audio driver
3 *
656baaeb 4 * Copyright 2011-2 Wolfson Microelectronics plc
6d4baf08
MB		 5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
0cf0f174 17#include <linux/export.h>
6d4baf08
MB		 18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
62c1c401 22#include <linux/pm_runtime.h>
6d4baf08
MB		 23#include <linux/regulator/consumer.h>
24#include <linux/regulator/fixed.h>
25#include <linux/slab.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
ba896ede 30#include <sound/jack.h>
6d4baf08
MB		 31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <sound/wm5100.h>
34
35#include "wm5100.h"
36
37#define WM5100_NUM_CORE_SUPPLIES 2
38static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
39 "DBVDD1",
40 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
41};
42
43#define WM5100_AIFS 3
44#define WM5100_SYNC_SRS 3
45
46struct wm5100_fll {
47 int fref;
48 int fout;
49 int src;
50 struct completion lock;
51};
52
53/* codec private data */
54struct wm5100_priv {
46c1a877 55 struct device *dev;
bd132ec5 56 struct regmap *regmap;
6d4baf08
MB		 57 struct snd_soc_codec *codec;
58
59 struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
6d4baf08
MB		 60
61 int rev;
62
63 int sysclk;
64 int asyncclk;
65
66 bool aif_async[WM5100_AIFS];
67 bool aif_symmetric[WM5100_AIFS];
68 int sr_ref[WM5100_SYNC_SRS];
69
70 bool out_ena[2];
71
ba896ede
MB		 72 struct snd_soc_jack *jack;
73 bool jack_detecting;
74 bool jack_mic;
75 int jack_mode;
2633f736 76 int jack_flips;
ba896ede 77
6d4baf08
MB		 78 struct wm5100_fll fll[2];
79
80 struct wm5100_pdata pdata;
81
82#ifdef CONFIG_GPIOLIB
83 struct gpio_chip gpio_chip;
84#endif
85};
86
87static int wm5100_sr_code[] = {
88 0,
89 12000,
90 24000,
91 48000,
92 96000,
93 192000,
94 384000,
95 768000,
96 0,
97 11025,
98 22050,
99 44100,
100 88200,
101 176400,
102 352800,
103 705600,
104 4000,
105 8000,
106 16000,
107 32000,
108 64000,
109 128000,
110 256000,
111 512000,
112};
113
114static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
115 WM5100_CLOCKING_4,
116 WM5100_CLOCKING_5,
117 WM5100_CLOCKING_6,
118};
119
120static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
121{
122 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
123 int sr_code, sr_free, i;
124
125 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
126 if (wm5100_sr_code[i] == rate)
127 break;
128 if (i == ARRAY_SIZE(wm5100_sr_code)) {
129 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
130 return -EINVAL;
131 }
132 sr_code = i;
133
134 if ((wm5100->sysclk % rate) == 0) {
135 /* Is this rate already in use? */
136 sr_free = -1;
137 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
138 if (!wm5100->sr_ref[i] && sr_free == -1) {
139 sr_free = i;
140 continue;
141 }
142 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
143 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
144 break;
145 }
146
147 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
148 wm5100->sr_ref[i]++;
149 dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
150 rate, i, wm5100->sr_ref[i]);
151 return i;
152 }
153
154 if (sr_free == -1) {
155 dev_err(codec->dev, "All SR slots already in use\n");
156 return -EBUSY;
157 }
158
159 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
160 sr_free, rate);
161 wm5100->sr_ref[sr_free]++;
162 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
163 WM5100_SAMPLE_RATE_1_MASK,
164 sr_code);
165
166 return sr_free;
167
168 } else {
169 dev_err(codec->dev,
170 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
171 rate, wm5100->sysclk, wm5100->asyncclk);
172 return -EINVAL;
173 }
174}
175
176static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
177{
178 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
179 int i, sr_code;
180
181 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
182 if (wm5100_sr_code[i] == rate)
183 break;
184 if (i == ARRAY_SIZE(wm5100_sr_code)) {
185 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
186 return;
187 }
188 sr_code = wm5100_sr_code[i];
189
190 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
191 if (!wm5100->sr_ref[i])
192 continue;
193
194 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
195 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
196 break;
197 }
198 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
199 wm5100->sr_ref[i]--;
200 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
201 rate, wm5100->sr_ref[i]);
202 } else {
203 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
204 rate);
205 }
206}
207
588ac5e0 208static int wm5100_reset(struct wm5100_priv *wm5100)
6d4baf08 209{
6d4baf08
MB		 210 if (wm5100->pdata.reset) {
211 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
212 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
213
214 return 0;
215 } else {
588ac5e0 216 return regmap_write(wm5100->regmap, WM5100_SOFTWARE_RESET, 0);
6d4baf08
MB		 217 }
218}
219
220static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
221static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
222static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
223static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
224static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
225
226static const char *wm5100_mixer_texts[] = {
227 "None",
228 "Tone Generator 1",
229 "Tone Generator 2",
230 "AEC loopback",
231 "IN1L",
232 "IN1R",
233 "IN2L",
234 "IN2R",
235 "IN3L",
236 "IN3R",
237 "IN4L",
238 "IN4R",
239 "AIF1RX1",
240 "AIF1RX2",
241 "AIF1RX3",
242 "AIF1RX4",
243 "AIF1RX5",
244 "AIF1RX6",
245 "AIF1RX7",
246 "AIF1RX8",
247 "AIF2RX1",
248 "AIF2RX2",
249 "AIF3RX1",
250 "AIF3RX2",
251 "EQ1",
252 "EQ2",
253 "EQ3",
254 "EQ4",
255 "DRC1L",
256 "DRC1R",
257 "LHPF1",
258 "LHPF2",
259 "LHPF3",
260 "LHPF4",
261 "DSP1.1",
262 "DSP1.2",
263 "DSP1.3",
264 "DSP1.4",
265 "DSP1.5",
266 "DSP1.6",
267 "DSP2.1",
268 "DSP2.2",
269 "DSP2.3",
270 "DSP2.4",
271 "DSP2.5",
272 "DSP2.6",
273 "DSP3.1",
274 "DSP3.2",
275 "DSP3.3",
276 "DSP3.4",
277 "DSP3.5",
278 "DSP3.6",
279 "ASRC1L",
280 "ASRC1R",
281 "ASRC2L",
282 "ASRC2R",
283 "ISRC1INT1",
284 "ISRC1INT2",
285 "ISRC1INT3",
286 "ISRC1INT4",
287 "ISRC2INT1",
288 "ISRC2INT2",
289 "ISRC2INT3",
290 "ISRC2INT4",
291 "ISRC1DEC1",
292 "ISRC1DEC2",
293 "ISRC1DEC3",
294 "ISRC1DEC4",
295 "ISRC2DEC1",
296 "ISRC2DEC2",
297 "ISRC2DEC3",
298 "ISRC2DEC4",
299};
300
301static int wm5100_mixer_values[] = {
302 0x00,
303 0x04, /* Tone */
304 0x05,
305 0x08, /* AEC */
306 0x10, /* Input */
307 0x11,
308 0x12,
309 0x13,
310 0x14,
311 0x15,
312 0x16,
313 0x17,
314 0x20, /* AIF */
315 0x21,
316 0x22,
317 0x23,
318 0x24,
319 0x25,
320 0x26,
321 0x27,
322 0x28,
323 0x29,
324 0x30, /* AIF3 - check */
325 0x31,
326 0x50, /* EQ */
327 0x51,
328 0x52,
329 0x53,
330 0x54,
331 0x58, /* DRC */
332 0x59,
333 0x60, /* LHPF1 */
334 0x61, /* LHPF2 */
335 0x62, /* LHPF3 */
336 0x63, /* LHPF4 */
337 0x68, /* DSP1 */
338 0x69,
339 0x6a,
340 0x6b,
341 0x6c,
342 0x6d,
343 0x70, /* DSP2 */
344 0x71,
345 0x72,
346 0x73,
347 0x74,
348 0x75,
349 0x78, /* DSP3 */
350 0x79,
351 0x7a,
352 0x7b,
353 0x7c,
354 0x7d,
355 0x90, /* ASRC1 */
356 0x91,
357 0x92, /* ASRC2 */
358 0x93,
359 0xa0, /* ISRC1DEC1 */
360 0xa1,
361 0xa2,
362 0xa3,
363 0xa4, /* ISRC1INT1 */
364 0xa5,
365 0xa6,
366 0xa7,
367 0xa8, /* ISRC2DEC1 */
368 0xa9,
369 0xaa,
370 0xab,
371 0xac, /* ISRC2INT1 */
372 0xad,
373 0xae,
374 0xaf,
375};
376
377#define WM5100_MIXER_CONTROLS(name, base) \
378 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
379 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
380 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
381 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
382 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
383 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
384 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
385 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
386
387#define WM5100_MUX_ENUM_DECL(name, reg) \
388 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
389 wm5100_mixer_texts, wm5100_mixer_values)
390
391#define WM5100_MUX_CTL_DECL(name) \
392 const struct snd_kcontrol_new name##_mux = \
cda88669 393 SOC_DAPM_ENUM("Route", name##_enum)
6d4baf08
MB		 394
395#define WM5100_MIXER_ENUMS(name, base_reg) \
396 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
397 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
398 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
399 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
400 static WM5100_MUX_CTL_DECL(name##_in1); \
401 static WM5100_MUX_CTL_DECL(name##_in2); \
402 static WM5100_MUX_CTL_DECL(name##_in3); \
403 static WM5100_MUX_CTL_DECL(name##_in4)
404
405WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
406WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
407WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
408WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
409WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
410WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
411
412WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
413WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
414WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
415WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
416WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
417WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
418
419WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
420WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
421
422WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
423WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
424WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
425WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
426WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
427WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
428WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
429WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
430
431WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
432WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
433
434WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
435WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
436
437WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
438WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
439WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
440WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
441
442WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
443WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
444
445WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
446WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
447WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
448WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
449
450#define WM5100_MUX(name, ctrl) \
cda88669 451 SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
6d4baf08
MB		 452
453#define WM5100_MIXER_WIDGETS(name, name_str) \
454 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
455 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
456 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
457 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
458 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
459
460#define WM5100_MIXER_INPUT_ROUTES(name) \
461 { name, "Tone Generator 1", "Tone Generator 1" }, \
462 { name, "Tone Generator 2", "Tone Generator 2" }, \
463 { name, "IN1L", "IN1L PGA" }, \
464 { name, "IN1R", "IN1R PGA" }, \
465 { name, "IN2L", "IN2L PGA" }, \
466 { name, "IN2R", "IN2R PGA" }, \
467 { name, "IN3L", "IN3L PGA" }, \
468 { name, "IN3R", "IN3R PGA" }, \
469 { name, "IN4L", "IN4L PGA" }, \
470 { name, "IN4R", "IN4R PGA" }, \
471 { name, "AIF1RX1", "AIF1RX1" }, \
472 { name, "AIF1RX2", "AIF1RX2" }, \
473 { name, "AIF1RX3", "AIF1RX3" }, \
474 { name, "AIF1RX4", "AIF1RX4" }, \
475 { name, "AIF1RX5", "AIF1RX5" }, \
476 { name, "AIF1RX6", "AIF1RX6" }, \
477 { name, "AIF1RX7", "AIF1RX7" }, \
478 { name, "AIF1RX8", "AIF1RX8" }, \
479 { name, "AIF2RX1", "AIF2RX1" }, \
480 { name, "AIF2RX2", "AIF2RX2" }, \
481 { name, "AIF3RX1", "AIF3RX1" }, \
482 { name, "AIF3RX2", "AIF3RX2" }, \
483 { name, "EQ1", "EQ1" }, \
484 { name, "EQ2", "EQ2" }, \
485 { name, "EQ3", "EQ3" }, \
486 { name, "EQ4", "EQ4" }, \
487 { name, "DRC1L", "DRC1L" }, \
488 { name, "DRC1R", "DRC1R" }, \
489 { name, "LHPF1", "LHPF1" }, \
490 { name, "LHPF2", "LHPF2" }, \
491 { name, "LHPF3", "LHPF3" }, \
492 { name, "LHPF4", "LHPF4" }
493
494#define WM5100_MIXER_ROUTES(widget, name) \
495 { widget, NULL, name " Mixer" }, \
496 { name " Mixer", NULL, name " Input 1" }, \
497 { name " Mixer", NULL, name " Input 2" }, \
498 { name " Mixer", NULL, name " Input 3" }, \
499 { name " Mixer", NULL, name " Input 4" }, \
500 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
501 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
502 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
503 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
504
505static const char *wm5100_lhpf_mode_text[] = {
506 "Low-pass", "High-pass"
507};
508
0224ba6a
TI		 509static SOC_ENUM_SINGLE_DECL(wm5100_lhpf1_mode,
510 WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT,
511 wm5100_lhpf_mode_text);
6d4baf08 512
0224ba6a
TI		 513static SOC_ENUM_SINGLE_DECL(wm5100_lhpf2_mode,
514 WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT,
515 wm5100_lhpf_mode_text);
6d4baf08 516
0224ba6a
TI		 517static SOC_ENUM_SINGLE_DECL(wm5100_lhpf3_mode,
518 WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT,
519 wm5100_lhpf_mode_text);
6d4baf08 520
0224ba6a
TI		 521static SOC_ENUM_SINGLE_DECL(wm5100_lhpf4_mode,
522 WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT,
523 wm5100_lhpf_mode_text);
6d4baf08
MB		 524
525static const struct snd_kcontrol_new wm5100_snd_controls[] = {
526SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
527 WM5100_IN1_OSR_SHIFT, 1, 0),
528SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
529 WM5100_IN2_OSR_SHIFT, 1, 0),
530SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
531 WM5100_IN3_OSR_SHIFT, 1, 0),
532SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
533 WM5100_IN4_OSR_SHIFT, 1, 0),
534
535/* Only applicable for analogue inputs */
536SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
537 WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
538SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
539 WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
540SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
541 WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
542SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
543 WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
544
545SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
546 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
547 0, digital_tlv),
548SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
549 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
550 0, digital_tlv),
551SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
552 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
553 0, digital_tlv),
554SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
555 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
556 0, digital_tlv),
557
558SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
559 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
560SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
561 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
562SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
563 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
564SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
565 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
566
20fc4863
MB		 567SND_SOC_BYTES_MASK("EQ1 Coefficients", WM5100_EQ1_1, 20, WM5100_EQ1_ENA),
568SND_SOC_BYTES_MASK("EQ2 Coefficients", WM5100_EQ2_1, 20, WM5100_EQ2_ENA),
569SND_SOC_BYTES_MASK("EQ3 Coefficients", WM5100_EQ3_1, 20, WM5100_EQ3_ENA),
570SND_SOC_BYTES_MASK("EQ4 Coefficients", WM5100_EQ4_1, 20, WM5100_EQ4_ENA),
571
572SND_SOC_BYTES_MASK("DRC Coefficients", WM5100_DRC1_CTRL1, 5,
573 WM5100_DRCL_ENA | WM5100_DRCR_ENA),
574
575SND_SOC_BYTES("LHPF1 Coefficeints", WM5100_HPLPF1_2, 1),
576SND_SOC_BYTES("LHPF2 Coefficeints", WM5100_HPLPF2_2, 1),
577SND_SOC_BYTES("LHPF3 Coefficeints", WM5100_HPLPF3_2, 1),
578SND_SOC_BYTES("LHPF4 Coefficeints", WM5100_HPLPF4_2, 1),
579
6d4baf08
MB		 580SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
581 WM5100_OUT1_OSR_SHIFT, 1, 0),
582SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
583 WM5100_OUT2_OSR_SHIFT, 1, 0),
584SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
585 WM5100_OUT3_OSR_SHIFT, 1, 0),
586SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
587 WM5100_OUT4_OSR_SHIFT, 1, 0),
588SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
589 WM5100_OUT5_OSR_SHIFT, 1, 0),
590SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
591 WM5100_OUT6_OSR_SHIFT, 1, 0),
592
593SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
594 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
595 digital_tlv),
596SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
597 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
598 digital_tlv),
599SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
600 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
601 digital_tlv),
602SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
603 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
604 digital_tlv),
605SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
606 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
607 digital_tlv),
608SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
609 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
610 digital_tlv),
611
612SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
613 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
614SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
615 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
616SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
617 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
618SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
619 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
620SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
621 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
622SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
623 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
624
625/* FIXME: Only valid from -12dB to 0dB (52-64) */
626SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
627 WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
628SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
629 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
630SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
631 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
632
633SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
634 WM5100_SPK1R_MUTE_SHIFT, 1, 1),
635SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
636 WM5100_SPK2R_MUTE_SHIFT, 1, 1),
637
638SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
639 24, 0, eq_tlv),
640SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
641 24, 0, eq_tlv),
642SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
643 24, 0, eq_tlv),
644SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
645 24, 0, eq_tlv),
646SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
647 24, 0, eq_tlv),
648
649SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
650 24, 0, eq_tlv),
651SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
652 24, 0, eq_tlv),
653SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
654 24, 0, eq_tlv),
655SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
656 24, 0, eq_tlv),
657SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
658 24, 0, eq_tlv),
659
660SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
661 24, 0, eq_tlv),
662SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
663 24, 0, eq_tlv),
664SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
665 24, 0, eq_tlv),
666SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
667 24, 0, eq_tlv),
668SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
669 24, 0, eq_tlv),
670
671SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
672 24, 0, eq_tlv),
673SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
674 24, 0, eq_tlv),
675SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
676 24, 0, eq_tlv),
677SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
678 24, 0, eq_tlv),
679SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
680 24, 0, eq_tlv),
681
682SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
683SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
684SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
685SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
686
687WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
688WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
689WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
690WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
691WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
692WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
693
694WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
695WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
696WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
697WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
698WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
699WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
700
701WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
702WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
703
704WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
705WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
706WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
707WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
708WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
709WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
710WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
711WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
712
713WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
714WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
715
716WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
717WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
718
719WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
720WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
721WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
722WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
723
724WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
725WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
cdaaf301
MB		 726SND_SOC_BYTES_MASK("DRC", WM5100_DRC1_CTRL1, 5,
727 WM5100_DRCL_ENA | WM5100_DRCR_ENA),
6d4baf08
MB		 728
729WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
730WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
731WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
732WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
733};
734
735static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
736 enum snd_soc_dapm_type event, int subseq)
737{
e73a2571 738 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
6d4baf08
MB		 739 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
740 u16 val, expect, i;
741
742 /* Wait for the outputs to flag themselves as enabled */
743 if (wm5100->out_ena[0]) {
744 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
745 for (i = 0; i < 200; i++) {
746 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
747 if (val == expect) {
748 wm5100->out_ena[0] = false;
749 break;
750 }
751 }
752 if (i == 200) {
753 dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
754 expect);
755 }
756 }
757
758 if (wm5100->out_ena[1]) {
759 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
760 for (i = 0; i < 200; i++) {
761 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
762 if (val == expect) {
763 wm5100->out_ena[1] = false;
764 break;
765 }
766 }
767 if (i == 200) {
768 dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
769 expect);
770 }
771 }
772}
773
774static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
775 struct snd_kcontrol *kcontrol,
776 int event)
777{
778 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec);
779
780 switch (w->reg) {
781 case WM5100_CHANNEL_ENABLES_1:
782 wm5100->out_ena[0] = true;
783 break;
784 case WM5100_OUTPUT_ENABLES_2:
785 wm5100->out_ena[0] = true;
786 break;
787 default:
788 break;
789 }
790
791 return 0;
792}
793
46c1a877 794static void wm5100_log_status3(struct wm5100_priv *wm5100, int val)
6d4baf08
MB		 795{
796 if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
46c1a877 797 dev_crit(wm5100->dev, "Speaker shutdown warning\n");
6d4baf08 798 if (val & WM5100_SPK_SHUTDOWN_EINT)
46c1a877 799 dev_crit(wm5100->dev, "Speaker shutdown\n");
6d4baf08 800 if (val & WM5100_CLKGEN_ERR_EINT)
46c1a877 801 dev_crit(wm5100->dev, "SYSCLK underclocked\n");
6d4baf08 802 if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
46c1a877 803 dev_crit(wm5100->dev, "ASYNCCLK underclocked\n");
6d4baf08
MB		 804}
805
46c1a877 806static void wm5100_log_status4(struct wm5100_priv *wm5100, int val)
6d4baf08
MB		 807{
808 if (val & WM5100_AIF3_ERR_EINT)
46c1a877 809 dev_err(wm5100->dev, "AIF3 configuration error\n");
6d4baf08 810 if (val & WM5100_AIF2_ERR_EINT)
46c1a877 811 dev_err(wm5100->dev, "AIF2 configuration error\n");
6d4baf08 812 if (val & WM5100_AIF1_ERR_EINT)
46c1a877 813 dev_err(wm5100->dev, "AIF1 configuration error\n");
6d4baf08 814 if (val & WM5100_CTRLIF_ERR_EINT)
46c1a877 815 dev_err(wm5100->dev, "Control interface error\n");
6d4baf08 816 if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
46c1a877 817 dev_err(wm5100->dev, "ISRC2 underclocked\n");
6d4baf08 818 if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
46c1a877 819 dev_err(wm5100->dev, "ISRC1 underclocked\n");
6d4baf08 820 if (val & WM5100_FX_UNDERCLOCKED_EINT)
46c1a877 821 dev_err(wm5100->dev, "FX underclocked\n");
6d4baf08 822 if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
46c1a877 823 dev_err(wm5100->dev, "AIF3 underclocked\n");
6d4baf08 824 if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
46c1a877 825 dev_err(wm5100->dev, "AIF2 underclocked\n");
6d4baf08 826 if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
46c1a877 827 dev_err(wm5100->dev, "AIF1 underclocked\n");
6d4baf08 828 if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
46c1a877 829 dev_err(wm5100->dev, "ASRC underclocked\n");
6d4baf08 830 if (val & WM5100_DAC_UNDERCLOCKED_EINT)
46c1a877 831 dev_err(wm5100->dev, "DAC underclocked\n");
6d4baf08 832 if (val & WM5100_ADC_UNDERCLOCKED_EINT)
46c1a877 833 dev_err(wm5100->dev, "ADC underclocked\n");
6d4baf08 834 if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
46c1a877 835 dev_err(wm5100->dev, "Mixer underclocked\n");
6d4baf08
MB		 836}
837
838static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
839 struct snd_kcontrol *kcontrol,
840 int event)
841{
842 struct snd_soc_codec *codec = w->codec;
46c1a877 843 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
6d4baf08
MB		 844 int ret;
845
846 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
847 ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
848 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
849 WM5100_CLKGEN_ERR_ASYNC_STS;
46c1a877 850 wm5100_log_status3(wm5100, ret);
6d4baf08
MB		 851
852 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
46c1a877 853 wm5100_log_status4(wm5100, ret);
6d4baf08
MB		 854
855 return 0;
856}
857
858static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
859SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
860 NULL, 0),
861SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
862 0, NULL, 0),
863
822b4b8d
MB		 864SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
865SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD2", 0, 0),
866SND_SOC_DAPM_REGULATOR_SUPPLY("DBVDD3", 0, 0),
1cf73356 867
6d4baf08 868SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
1cf73356 869 NULL, 0),
6d4baf08
MB		 870SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
871 NULL, 0),
872SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
1cf73356 873 WM5100_CP2_BYPASS_SHIFT, 1, NULL, 0),
6d4baf08
MB		 874
875SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
876 0, NULL, 0),
877SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
878 0, NULL, 0),
879SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
880 0, NULL, 0),
881
882SND_SOC_DAPM_INPUT("IN1L"),
883SND_SOC_DAPM_INPUT("IN1R"),
884SND_SOC_DAPM_INPUT("IN2L"),
885SND_SOC_DAPM_INPUT("IN2R"),
886SND_SOC_DAPM_INPUT("IN3L"),
887SND_SOC_DAPM_INPUT("IN3R"),
888SND_SOC_DAPM_INPUT("IN4L"),
889SND_SOC_DAPM_INPUT("IN4R"),
dea8e237 890SND_SOC_DAPM_SIGGEN("TONE"),
6d4baf08
MB		 891
892SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
893 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
894SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
895 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
896SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
897 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
898SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
899 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
900SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
901 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
902SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
903 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
904SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
905 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
906SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
907 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
908
909SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
910 WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
911SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
912 WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
913
914SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
915 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
916SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
917 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
918SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
919 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
920SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
921 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
922SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
923 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
924SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
925 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
926SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
927 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
928SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
929 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
930
931SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
932 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
933SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
934 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
935
936SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
937 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
938SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
939 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
940
941SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
942 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
943SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
944 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
945SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
946 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
947SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
948 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
949SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
950 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
951SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
952 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
953SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
954 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
955SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
956 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
957
958SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
959 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
960SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
961 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
962
963SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
964 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
965SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
966 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
967
968SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
969 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
970SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
971 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
972SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
973 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
974SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
975 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
976SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
977 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
978SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
979 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
980SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
981 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
982SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
983 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
984SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
985 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
986SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
987 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
988SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
989 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
990SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
991 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
992SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
993 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
994SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
995 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
996
997SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
998SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
999SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1000SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1001
1002SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1003 NULL, 0),
1004SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1005 NULL, 0),
1006
1007SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1008 NULL, 0),
1009SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1010 NULL, 0),
1011SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1012 NULL, 0),
1013SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1014 NULL, 0),
1015
1016WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1017WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1018WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1019WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1020
1021WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1022WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1023
1024WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1025WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1026WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1027WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1028
1029WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1030WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1031WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1032WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1033WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1034WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1035WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1036WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1037
1038WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1039WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1040
1041WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1042WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1043
1044WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1045WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1046WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1047WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1048WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1049WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1050
1051WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1052WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1053WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1054WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1055WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1056WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1057
1058WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1059WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1060
1061SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1062SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1063SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1064SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1065SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1066SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1067SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1068SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1069SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1070SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1071SND_SOC_DAPM_OUTPUT("PWM1"),
1072SND_SOC_DAPM_OUTPUT("PWM2"),
1073};
1074
1075/* We register a _POST event if we don't have IRQ support so we can
1076 * look at the error status from the CODEC - if we've got the IRQ
1077 * hooked up then we will get prompted to look by an interrupt.
1078 */
1079static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1080SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1081};
1082
1083static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1cf73356
MB		 1084 { "CP1", NULL, "CPVDD" },
1085 { "CP2 Active", NULL, "CPVDD" },
1086
6d4baf08
MB		 1087 { "IN1L", NULL, "SYSCLK" },
1088 { "IN1R", NULL, "SYSCLK" },
1089 { "IN2L", NULL, "SYSCLK" },
1090 { "IN2R", NULL, "SYSCLK" },
1091 { "IN3L", NULL, "SYSCLK" },
1092 { "IN3R", NULL, "SYSCLK" },
1093 { "IN4L", NULL, "SYSCLK" },
1094 { "IN4R", NULL, "SYSCLK" },
1095
1096 { "OUT1L", NULL, "SYSCLK" },
1097 { "OUT1R", NULL, "SYSCLK" },
1098 { "OUT2L", NULL, "SYSCLK" },
1099 { "OUT2R", NULL, "SYSCLK" },
1100 { "OUT3L", NULL, "SYSCLK" },
1101 { "OUT3R", NULL, "SYSCLK" },
1102 { "OUT4L", NULL, "SYSCLK" },
1103 { "OUT4R", NULL, "SYSCLK" },
1104 { "OUT5L", NULL, "SYSCLK" },
1105 { "OUT5R", NULL, "SYSCLK" },
1106 { "OUT6L", NULL, "SYSCLK" },
1107 { "OUT6R", NULL, "SYSCLK" },
1108
1109 { "AIF1RX1", NULL, "SYSCLK" },
1110 { "AIF1RX2", NULL, "SYSCLK" },
1111 { "AIF1RX3", NULL, "SYSCLK" },
1112 { "AIF1RX4", NULL, "SYSCLK" },
1113 { "AIF1RX5", NULL, "SYSCLK" },
1114 { "AIF1RX6", NULL, "SYSCLK" },
1115 { "AIF1RX7", NULL, "SYSCLK" },
1116 { "AIF1RX8", NULL, "SYSCLK" },
1117
1118 { "AIF2RX1", NULL, "SYSCLK" },
7aefb086 1119 { "AIF2RX1", NULL, "DBVDD2" },
6d4baf08 1120 { "AIF2RX2", NULL, "SYSCLK" },
7aefb086 1121 { "AIF2RX2", NULL, "DBVDD2" },
6d4baf08
MB		 1122
1123 { "AIF3RX1", NULL, "SYSCLK" },
7aefb086 1124 { "AIF3RX1", NULL, "DBVDD3" },
6d4baf08 1125 { "AIF3RX2", NULL, "SYSCLK" },
7aefb086 1126 { "AIF3RX2", NULL, "DBVDD3" },
6d4baf08
MB		 1127
1128 { "AIF1TX1", NULL, "SYSCLK" },
1129 { "AIF1TX2", NULL, "SYSCLK" },
1130 { "AIF1TX3", NULL, "SYSCLK" },
1131 { "AIF1TX4", NULL, "SYSCLK" },
1132 { "AIF1TX5", NULL, "SYSCLK" },
1133 { "AIF1TX6", NULL, "SYSCLK" },
1134 { "AIF1TX7", NULL, "SYSCLK" },
1135 { "AIF1TX8", NULL, "SYSCLK" },
1136
1137 { "AIF2TX1", NULL, "SYSCLK" },
7aefb086 1138 { "AIF2TX1", NULL, "DBVDD2" },
6d4baf08 1139 { "AIF2TX2", NULL, "SYSCLK" },
7aefb086 1140 { "AIF2TX2", NULL, "DBVDD2" },
6d4baf08
MB		 1141
1142 { "AIF3TX1", NULL, "SYSCLK" },
7aefb086 1143 { "AIF3TX1", NULL, "DBVDD3" },
6d4baf08 1144 { "AIF3TX2", NULL, "SYSCLK" },
7aefb086 1145 { "AIF3TX2", NULL, "DBVDD3" },
6d4baf08
MB		 1146
1147 { "MICBIAS1", NULL, "CP2" },
1148 { "MICBIAS2", NULL, "CP2" },
1149 { "MICBIAS3", NULL, "CP2" },
1150
1151 { "IN1L PGA", NULL, "CP2" },
1152 { "IN1R PGA", NULL, "CP2" },
1153 { "IN2L PGA", NULL, "CP2" },
1154 { "IN2R PGA", NULL, "CP2" },
1155 { "IN3L PGA", NULL, "CP2" },
1156 { "IN3R PGA", NULL, "CP2" },
1157 { "IN4L PGA", NULL, "CP2" },
1158 { "IN4R PGA", NULL, "CP2" },
1159
1160 { "IN1L PGA", NULL, "CP2 Active" },
1161 { "IN1R PGA", NULL, "CP2 Active" },
1162 { "IN2L PGA", NULL, "CP2 Active" },
1163 { "IN2R PGA", NULL, "CP2 Active" },
1164 { "IN3L PGA", NULL, "CP2 Active" },
1165 { "IN3R PGA", NULL, "CP2 Active" },
1166 { "IN4L PGA", NULL, "CP2 Active" },
1167 { "IN4R PGA", NULL, "CP2 Active" },
1168
1169 { "OUT1L", NULL, "CP1" },
1170 { "OUT1R", NULL, "CP1" },
1171 { "OUT2L", NULL, "CP1" },
1172 { "OUT2R", NULL, "CP1" },
1173 { "OUT3L", NULL, "CP1" },
1174 { "OUT3R", NULL, "CP1" },
1175
1176 { "Tone Generator 1", NULL, "TONE" },
1177 { "Tone Generator 2", NULL, "TONE" },
1178
1179 { "IN1L PGA", NULL, "IN1L" },
1180 { "IN1R PGA", NULL, "IN1R" },
1181 { "IN2L PGA", NULL, "IN2L" },
1182 { "IN2R PGA", NULL, "IN2R" },
1183 { "IN3L PGA", NULL, "IN3L" },
1184 { "IN3R PGA", NULL, "IN3R" },
1185 { "IN4L PGA", NULL, "IN4L" },
1186 { "IN4R PGA", NULL, "IN4R" },
1187
1188 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1189 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1190 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1191 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1192 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1193 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1194
1195 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1196 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1197 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1198 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1199 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1200 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1201
1202 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1203 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1204
1205 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1206 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1207 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1208 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1209 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1210 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1211 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1212 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1213
1214 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1215 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1216
1217 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1218 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1219
1220 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1221 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1222 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1223 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1224
1225 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1226 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1227
1228 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1229 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1230 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1231 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1232
1233 { "HPOUT1L", NULL, "OUT1L" },
1234 { "HPOUT1R", NULL, "OUT1R" },
1235 { "HPOUT2L", NULL, "OUT2L" },
1236 { "HPOUT2R", NULL, "OUT2R" },
1237 { "HPOUT3L", NULL, "OUT3L" },
1238 { "HPOUT3R", NULL, "OUT3R" },
1239 { "SPKOUTL", NULL, "OUT4L" },
1240 { "SPKOUTR", NULL, "OUT4R" },
1241 { "SPKDAT1", NULL, "OUT5L" },
1242 { "SPKDAT1", NULL, "OUT5R" },
1243 { "SPKDAT2", NULL, "OUT6L" },
1244 { "SPKDAT2", NULL, "OUT6R" },
1245 { "PWM1", NULL, "PWM1 Driver" },
1246 { "PWM2", NULL, "PWM2 Driver" },
1247};
1248
f6e65744 1249static const struct reg_default wm5100_reva_patches[] = {
6d4baf08
MB		 1250 { WM5100_AUDIO_IF_1_10, 0 },
1251 { WM5100_AUDIO_IF_1_11, 1 },
1252 { WM5100_AUDIO_IF_1_12, 2 },
1253 { WM5100_AUDIO_IF_1_13, 3 },
1254 { WM5100_AUDIO_IF_1_14, 4 },
1255 { WM5100_AUDIO_IF_1_15, 5 },
1256 { WM5100_AUDIO_IF_1_16, 6 },
1257 { WM5100_AUDIO_IF_1_17, 7 },
1258
1259 { WM5100_AUDIO_IF_1_18, 0 },
1260 { WM5100_AUDIO_IF_1_19, 1 },
1261 { WM5100_AUDIO_IF_1_20, 2 },
1262 { WM5100_AUDIO_IF_1_21, 3 },
1263 { WM5100_AUDIO_IF_1_22, 4 },
1264 { WM5100_AUDIO_IF_1_23, 5 },
1265 { WM5100_AUDIO_IF_1_24, 6 },
1266 { WM5100_AUDIO_IF_1_25, 7 },
1267
1268 { WM5100_AUDIO_IF_2_10, 0 },
1269 { WM5100_AUDIO_IF_2_11, 1 },
1270
1271 { WM5100_AUDIO_IF_2_18, 0 },
1272 { WM5100_AUDIO_IF_2_19, 1 },
1273
1274 { WM5100_AUDIO_IF_3_10, 0 },
1275 { WM5100_AUDIO_IF_3_11, 1 },
1276
1277 { WM5100_AUDIO_IF_3_18, 0 },
1278 { WM5100_AUDIO_IF_3_19, 1 },
1279};
1280
6d4baf08
MB		 1281static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1282{
1283 struct snd_soc_codec *codec = dai->codec;
1284 int lrclk, bclk, mask, base;
1285
9b523124 1286 base = dai->driver->base;
6d4baf08
MB		 1287
1288 lrclk = 0;
1289 bclk = 0;
1290
1291 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1292 case SND_SOC_DAIFMT_DSP_A:
1293 mask = 0;
1294 break;
6d4baf08
MB		 1295 case SND_SOC_DAIFMT_I2S:
1296 mask = 2;
1297 break;
6d4baf08
MB		 1298 default:
1299 dev_err(codec->dev, "Unsupported DAI format %d\n",
1300 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1301 return -EINVAL;
1302 }
1303
1304 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1305 case SND_SOC_DAIFMT_CBS_CFS:
1306 break;
1307 case SND_SOC_DAIFMT_CBS_CFM:
1308 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1309 break;
1310 case SND_SOC_DAIFMT_CBM_CFS:
1311 bclk |= WM5100_AIF1_BCLK_MSTR;
1312 break;
1313 case SND_SOC_DAIFMT_CBM_CFM:
1314 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1315 bclk |= WM5100_AIF1_BCLK_MSTR;
1316 break;
1317 default:
1318 dev_err(codec->dev, "Unsupported master mode %d\n",
1319 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1320 return -EINVAL;
1321 }
1322
1323 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1324 case SND_SOC_DAIFMT_NB_NF:
1325 break;
1326 case SND_SOC_DAIFMT_IB_IF:
1327 bclk |= WM5100_AIF1_BCLK_INV;
1328 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1329 break;
1330 case SND_SOC_DAIFMT_IB_NF:
1331 bclk |= WM5100_AIF1_BCLK_INV;
1332 break;
1333 case SND_SOC_DAIFMT_NB_IF:
1334 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1335 break;
1336 default:
1337 return -EINVAL;
1338 }
1339
1340 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1341 WM5100_AIF1_BCLK_INV, bclk);
1342 snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1343 WM5100_AIF1TX_LRCLK_INV, lrclk);
1344 snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1345 WM5100_AIF1TX_LRCLK_INV, lrclk);
1346 snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1347
1348 return 0;
1349}
1350
1351#define WM5100_NUM_BCLK_RATES 19
1352
1353static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1354 32000,
1355 48000,
1356 64000,
1357 96000,
1358 128000,
1359 192000,
d73ec75c 1360 256000,
6d4baf08
MB		 1361 384000,
1362 512000,
1363 768000,
1364 1024000,
1365 1536000,
1366 2048000,
1367 3072000,
1368 4096000,
1369 6144000,
1370 8192000,
1371 12288000,
1372 24576000,
1373};
1374
1375static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1376 29400,
1377 44100,
1378 58800,
1379 88200,
1380 117600,
1381 176400,
1382 235200,
1383 352800,
1384 470400,
1385 705600,
1386 940800,
1387 1411200,
1388 1881600,
1389 2882400,
1390 3763200,
1391 5644800,
1392 7526400,
1393 11289600,
1394 22579600,
1395};
1396
1397static int wm5100_hw_params(struct snd_pcm_substream *substream,
1398 struct snd_pcm_hw_params *params,
1399 struct snd_soc_dai *dai)
1400{
1401 struct snd_soc_codec *codec = dai->codec;
1402 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1403 bool async = wm5100->aif_async[dai->id];
1404 int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1405 int *bclk_rates;
1406
9b523124 1407 base = dai->driver->base;
6d4baf08
MB		 1408
1409 /* Data sizes if not using TDM */
1410 wl = snd_pcm_format_width(params_format(params));
1411 if (wl < 0)
1412 return wl;
1413 fl = snd_soc_params_to_frame_size(params);
1414 if (fl < 0)
1415 return fl;
1416
1417 dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1418 wl, fl);
1419
1420 /* Target BCLK rate */
1421 bclk = snd_soc_params_to_bclk(params);
1422 if (bclk < 0)
1423 return bclk;
1424
1425 /* Root for BCLK depends on SYS/ASYNCCLK */
1426 if (!async) {
1427 aif_rate = wm5100->sysclk;
1428 sr = wm5100_alloc_sr(codec, params_rate(params));
1429 if (sr < 0)
1430 return sr;
1431 } else {
1432 /* If we're in ASYNCCLK set the ASYNC sample rate */
1433 aif_rate = wm5100->asyncclk;
1434 sr = 3;
1435
1436 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1437 if (params_rate(params) == wm5100_sr_code[i])
1438 break;
1439 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1440 dev_err(codec->dev, "Invalid rate %dHzn",
1441 params_rate(params));
1442 return -EINVAL;
1443 }
1444
1445 /* TODO: We should really check for symmetry */
1446 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1447 WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1448 }
1449
1450 if (!aif_rate) {
1451 dev_err(codec->dev, "%s has no rate set\n",
1452 async ? "ASYNCCLK" : "SYSCLK");
1453 return -EINVAL;
1454 }
1455
1456 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1457 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1458
1459 if (aif_rate % 4000)
1460 bclk_rates = wm5100_bclk_rates_cd;
1461 else
1462 bclk_rates = wm5100_bclk_rates_dat;
1463
1464 for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1465 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1466 break;
1467 if (i == WM5100_NUM_BCLK_RATES) {
1468 dev_err(codec->dev,
1469 "No valid BCLK for %dHz found from %dHz %s\n",
1470 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1471 return -EINVAL;
1472 }
1473
1474 bclk = i;
1475 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1476 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1477
1478 lrclk = bclk_rates[bclk] / params_rate(params);
1479 dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1480 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1481 wm5100->aif_symmetric[dai->id])
1482 snd_soc_update_bits(codec, base + 7,
1483 WM5100_AIF1RX_BCPF_MASK, lrclk);
1484 else
1485 snd_soc_update_bits(codec, base + 6,
1486 WM5100_AIF1TX_BCPF_MASK, lrclk);
1487
1488 i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1489 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1490 snd_soc_update_bits(codec, base + 9,
1491 WM5100_AIF1RX_WL_MASK |
1492 WM5100_AIF1RX_SLOT_LEN_MASK, i);
1493 else
1494 snd_soc_update_bits(codec, base + 8,
1495 WM5100_AIF1TX_WL_MASK |
1496 WM5100_AIF1TX_SLOT_LEN_MASK, i);
1497
1498 snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1499
1500 return 0;
1501}
1502
85e7652d 1503static const struct snd_soc_dai_ops wm5100_dai_ops = {
6d4baf08
MB		 1504 .set_fmt = wm5100_set_fmt,
1505 .hw_params = wm5100_hw_params,
1506};
1507
1508static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1509 int source, unsigned int freq, int dir)
1510{
1511 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1512 int *rate_store;
1513 int fval, audio_rate, ret, reg;
1514
1515 switch (clk_id) {
1516 case WM5100_CLK_SYSCLK:
1517 reg = WM5100_CLOCKING_3;
1518 rate_store = &wm5100->sysclk;
1519 break;
1520 case WM5100_CLK_ASYNCCLK:
1521 reg = WM5100_CLOCKING_7;
1522 rate_store = &wm5100->asyncclk;
1523 break;
1524 case WM5100_CLK_32KHZ:
1525 /* The 32kHz clock is slightly different to the others */
1526 switch (source) {
1527 case WM5100_CLKSRC_MCLK1:
1528 case WM5100_CLKSRC_MCLK2:
1529 case WM5100_CLKSRC_SYSCLK:
1530 snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1531 WM5100_CLK_32K_SRC_MASK,
1532 source);
1533 break;
1534 default:
1535 return -EINVAL;
1536 }
1537 return 0;
1538
1539 case WM5100_CLK_AIF1:
1540 case WM5100_CLK_AIF2:
1541 case WM5100_CLK_AIF3:
1542 /* Not real clocks, record which clock domain they're in */
1543 switch (source) {
1544 case WM5100_CLKSRC_SYSCLK:
1545 wm5100->aif_async[clk_id - 1] = false;
1546 break;
1547 case WM5100_CLKSRC_ASYNCCLK:
1548 wm5100->aif_async[clk_id - 1] = true;
1549 break;
1550 default:
1551 dev_err(codec->dev, "Invalid source %d\n", source);
1552 return -EINVAL;
1553 }
1554 return 0;
1555
1556 case WM5100_CLK_OPCLK:
1557 switch (freq) {
1558 case 5644800:
1559 case 6144000:
1560 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1561 WM5100_OPCLK_SEL_MASK, 0);
1562 break;
1563 case 11289600:
1564 case 12288000:
1565 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1566 WM5100_OPCLK_SEL_MASK, 0);
1567 break;
1568 case 22579200:
1569 case 24576000:
1570 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1571 WM5100_OPCLK_SEL_MASK, 0);
1572 break;
1573 default:
1574 dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1575 freq);
1576 return -EINVAL;
1577 }
1578 return 0;
1579
1580 default:
1581 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1582 return -EINVAL;
1583 }
1584
1585 switch (source) {
1586 case WM5100_CLKSRC_SYSCLK:
1587 case WM5100_CLKSRC_ASYNCCLK:
1588 dev_err(codec->dev, "Invalid source %d\n", source);
1589 return -EINVAL;
1590 }
1591
1592 switch (freq) {
1593 case 5644800:
1594 case 6144000:
1595 fval = 0;
1596 break;
1597 case 11289600:
1598 case 12288000:
1599 fval = 1;
1600 break;
1601 case 22579200:
11c2b5f2 1602 case 24576000:
6d4baf08
MB		 1603 fval = 2;
1604 break;
1605 default:
1606 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1607 return -EINVAL;
1608 }
1609
1610 switch (freq) {
1611 case 5644800:
1612 case 11289600:
1613 case 22579200:
1614 audio_rate = 44100;
1615 break;
1616
1617 case 6144000:
1618 case 12288000:
11c2b5f2 1619 case 24576000:
6d4baf08
MB		 1620 audio_rate = 48000;
1621 break;
1622
1623 default:
1624 BUG();
1625 audio_rate = 0;
1626 break;
1627 }
1628
1629 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1630 * match.
1631 */
1632
1633 snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1634 WM5100_SYSCLK_SRC_MASK,
1635 fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1636
1637 /* If this is SYSCLK then configure the clock rate for the
1638 * internal audio functions to the natural sample rate for
1639 * this clock rate.
1640 */
1641 if (clk_id == WM5100_CLK_SYSCLK) {
1642 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1643 audio_rate);
1644 if (0 && *rate_store)
1645 wm5100_free_sr(codec, audio_rate);
1646 ret = wm5100_alloc_sr(codec, audio_rate);
1647 if (ret != 0)
1648 dev_warn(codec->dev, "Primary audio slot is %d\n",
1649 ret);
1650 }
1651
1652 *rate_store = freq;
1653
1654 return 0;
1655}
1656
1657struct _fll_div {
1658 u16 fll_fratio;
1659 u16 fll_outdiv;
1660 u16 fll_refclk_div;
1661 u16 n;
1662 u16 theta;
1663 u16 lambda;
1664};
1665
1666static struct {
1667 unsigned int min;
1668 unsigned int max;
1669 u16 fll_fratio;
1670 int ratio;
1671} fll_fratios[] = {
1672 { 0, 64000, 4, 16 },
1673 { 64000, 128000, 3, 8 },
1674 { 128000, 256000, 2, 4 },
1675 { 256000, 1000000, 1, 2 },
1676 { 1000000, 13500000, 0, 1 },
1677};
1678
1679static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1680 unsigned int Fout)
1681{
1682 unsigned int target;
1683 unsigned int div;
1684 unsigned int fratio, gcd_fll;
1685 int i;
1686
1687 /* Fref must be <=13.5MHz */
1688 div = 1;
1689 fll_div->fll_refclk_div = 0;
1690 while ((Fref / div) > 13500000) {
1691 div *= 2;
1692 fll_div->fll_refclk_div++;
1693
1694 if (div > 8) {
1695 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1696 Fref);
1697 return -EINVAL;
1698 }
1699 }
1700
1701 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1702
1703 /* Apply the division for our remaining calculations */
1704 Fref /= div;
1705
1706 /* Fvco should be 90-100MHz; don't check the upper bound */
1707 div = 2;
1708 while (Fout * div < 90000000) {
1709 div++;
1710 if (div > 64) {
1711 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1712 Fout);
1713 return -EINVAL;
1714 }
1715 }
1716 target = Fout * div;
1717 fll_div->fll_outdiv = div - 1;
1718
1719 pr_debug("FLL Fvco=%dHz\n", target);
1720
1721 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1722 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1723 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1724 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1725 fratio = fll_fratios[i].ratio;
1726 break;
1727 }
1728 }
1729 if (i == ARRAY_SIZE(fll_fratios)) {
1730 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1731 return -EINVAL;
1732 }
1733
1734 fll_div->n = target / (fratio * Fref);
1735
1736 if (target % Fref == 0) {
1737 fll_div->theta = 0;
1738 fll_div->lambda = 0;
1739 } else {
1740 gcd_fll = gcd(target, fratio * Fref);
1741
1742 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1743 / gcd_fll;
1744 fll_div->lambda = (fratio * Fref) / gcd_fll;
1745 }
1746
1747 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1748 fll_div->n, fll_div->theta, fll_div->lambda);
1749 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1750 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1751 fll_div->fll_refclk_div);
1752
1753 return 0;
1754}
1755
1756static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1757 unsigned int Fref, unsigned int Fout)
1758{
1759 struct i2c_client *i2c = to_i2c_client(codec->dev);
1760 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1761 struct _fll_div factors;
1762 struct wm5100_fll *fll;
1763 int ret, base, lock, i, timeout;
1764
1765 switch (fll_id) {
1766 case WM5100_FLL1:
1767 fll = &wm5100->fll[0];
1768 base = WM5100_FLL1_CONTROL_1 - 1;
1769 lock = WM5100_FLL1_LOCK_STS;
1770 break;
1771 case WM5100_FLL2:
1772 fll = &wm5100->fll[1];
1773 base = WM5100_FLL2_CONTROL_2 - 1;
1774 lock = WM5100_FLL2_LOCK_STS;
1775 break;
1776 default:
1777 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1778 return -EINVAL;
1779 }
1780
1781 if (!Fout) {
1782 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
62c1c401
MB		 1783 if (fll->fout)
1784 pm_runtime_put(codec->dev);
6d4baf08
MB		 1785 fll->fout = 0;
1786 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1787 return 0;
1788 }
1789
1790 switch (source) {
1791 case WM5100_FLL_SRC_MCLK1:
1792 case WM5100_FLL_SRC_MCLK2:
1793 case WM5100_FLL_SRC_FLL1:
1794 case WM5100_FLL_SRC_FLL2:
1795 case WM5100_FLL_SRC_AIF1BCLK:
1796 case WM5100_FLL_SRC_AIF2BCLK:
1797 case WM5100_FLL_SRC_AIF3BCLK:
1798 break;
1799 default:
1800 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1801 return -EINVAL;
1802 }
1803
1804 ret = fll_factors(&factors, Fref, Fout);
1805 if (ret < 0)
1806 return ret;
1807
1808 /* Disable the FLL while we reconfigure */
1809 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1810
1811 snd_soc_update_bits(codec, base + 2,
1812 WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1813 (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1814 factors.fll_fratio);
1815 snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1816 factors.theta);
1817 snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1818 snd_soc_update_bits(codec, base + 6,
1819 WM5100_FLL1_REFCLK_DIV_MASK |
1820 WM5100_FLL1_REFCLK_SRC_MASK,
1821 (factors.fll_refclk_div
1822 << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1823 snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1824 factors.lambda);
1825
1826 /* Clear any pending completions */
1827 try_wait_for_completion(&fll->lock);
1828
62c1c401
MB		 1829 pm_runtime_get_sync(codec->dev);
1830
6d4baf08
MB		 1831 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1832
1833 if (i2c->irq)
1834 timeout = 2;
1835 else
1836 timeout = 50;
1837
bd132ec5
MB		 1838 snd_soc_update_bits(codec, WM5100_CLOCKING_3, WM5100_SYSCLK_ENA,
1839 WM5100_SYSCLK_ENA);
1840
6d4baf08
MB		 1841 /* Poll for the lock; will use interrupt when we can test */
1842 for (i = 0; i < timeout; i++) {
1843 if (i2c->irq) {
1844 ret = wait_for_completion_timeout(&fll->lock,
1845 msecs_to_jiffies(25));
1846 if (ret > 0)
1847 break;
1848 } else {
1849 msleep(1);
1850 }
1851
1852 ret = snd_soc_read(codec,
1853 WM5100_INTERRUPT_RAW_STATUS_3);
1854 if (ret < 0) {
1855 dev_err(codec->dev,
1856 "Failed to read FLL status: %d\n",
1857 ret);
1858 continue;
1859 }
1860 if (ret & lock)
1861 break;
1862 }
1863 if (i == timeout) {
1864 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
62c1c401 1865 pm_runtime_put(codec->dev);
6d4baf08
MB		 1866 return -ETIMEDOUT;
1867 }
1868
1869 fll->src = source;
1870 fll->fref = Fref;
1871 fll->fout = Fout;
1872
1873 dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
1874 Fref, Fout);
1875
1876 return 0;
1877}
1878
1879/* Actually go much higher */
1880#define WM5100_RATES SNDRV_PCM_RATE_8000_192000
1881
1882#define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1883 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1884
1885static struct snd_soc_dai_driver wm5100_dai[] = {
1886 {
1887 .name = "wm5100-aif1",
9b523124 1888 .base = WM5100_AUDIO_IF_1_1 - 1,
6d4baf08
MB		 1889 .playback = {
1890 .stream_name = "AIF1 Playback",
1891 .channels_min = 2,
1892 .channels_max = 2,
1893 .rates = WM5100_RATES,
1894 .formats = WM5100_FORMATS,
1895 },
1896 .capture = {
1897 .stream_name = "AIF1 Capture",
1898 .channels_min = 2,
1899 .channels_max = 2,
1900 .rates = WM5100_RATES,
1901 .formats = WM5100_FORMATS,
1902 },
1903 .ops = &wm5100_dai_ops,
1904 },
1905 {
1906 .name = "wm5100-aif2",
1907 .id = 1,
9b523124 1908 .base = WM5100_AUDIO_IF_2_1 - 1,
6d4baf08
MB		 1909 .playback = {
1910 .stream_name = "AIF2 Playback",
1911 .channels_min = 2,
1912 .channels_max = 2,
1913 .rates = WM5100_RATES,
1914 .formats = WM5100_FORMATS,
1915 },
1916 .capture = {
1917 .stream_name = "AIF2 Capture",
1918 .channels_min = 2,
1919 .channels_max = 2,
1920 .rates = WM5100_RATES,
1921 .formats = WM5100_FORMATS,
1922 },
1923 .ops = &wm5100_dai_ops,
1924 },
1925 {
1926 .name = "wm5100-aif3",
1927 .id = 2,
9b523124 1928 .base = WM5100_AUDIO_IF_3_1 - 1,
6d4baf08
MB		 1929 .playback = {
1930 .stream_name = "AIF3 Playback",
1931 .channels_min = 2,
1932 .channels_max = 2,
1933 .rates = WM5100_RATES,
1934 .formats = WM5100_FORMATS,
1935 },
1936 .capture = {
1937 .stream_name = "AIF3 Capture",
1938 .channels_min = 2,
1939 .channels_max = 2,
1940 .rates = WM5100_RATES,
1941 .formats = WM5100_FORMATS,
1942 },
1943 .ops = &wm5100_dai_ops,
1944 },
1945};
1946
1947static int wm5100_dig_vu[] = {
1948 WM5100_ADC_DIGITAL_VOLUME_1L,
1949 WM5100_ADC_DIGITAL_VOLUME_1R,
1950 WM5100_ADC_DIGITAL_VOLUME_2L,
1951 WM5100_ADC_DIGITAL_VOLUME_2R,
1952 WM5100_ADC_DIGITAL_VOLUME_3L,
1953 WM5100_ADC_DIGITAL_VOLUME_3R,
1954 WM5100_ADC_DIGITAL_VOLUME_4L,
1955 WM5100_ADC_DIGITAL_VOLUME_4R,
1956
1957 WM5100_DAC_DIGITAL_VOLUME_1L,
1958 WM5100_DAC_DIGITAL_VOLUME_1R,
1959 WM5100_DAC_DIGITAL_VOLUME_2L,
1960 WM5100_DAC_DIGITAL_VOLUME_2R,
1961 WM5100_DAC_DIGITAL_VOLUME_3L,
1962 WM5100_DAC_DIGITAL_VOLUME_3R,
1963 WM5100_DAC_DIGITAL_VOLUME_4L,
1964 WM5100_DAC_DIGITAL_VOLUME_4R,
1965 WM5100_DAC_DIGITAL_VOLUME_5L,
1966 WM5100_DAC_DIGITAL_VOLUME_5R,
1967 WM5100_DAC_DIGITAL_VOLUME_6L,
1968 WM5100_DAC_DIGITAL_VOLUME_6R,
1969};
1970
46c1a877 1971static void wm5100_set_detect_mode(struct wm5100_priv *wm5100, int the_mode)
ba896ede 1972{
ba896ede
MB		 1973 struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
1974
95ff71e9
TI		 1975 if (WARN_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes)))
1976 return;
ba896ede
MB		 1977
1978 gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
46c1a877
MB		 1979 regmap_update_bits(wm5100->regmap, WM5100_ACCESSORY_DETECT_MODE_1,
1980 WM5100_ACCDET_BIAS_SRC_MASK |
1981 WM5100_ACCDET_SRC,
1982 (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
1983 mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
1984 regmap_update_bits(wm5100->regmap, WM5100_MISC_CONTROL,
1985 WM5100_HPCOM_SRC,
1986 mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
ba896ede
MB		 1987
1988 wm5100->jack_mode = the_mode;
1989
46c1a877 1990 dev_dbg(wm5100->dev, "Set microphone polarity to %d\n",
ba896ede
MB		 1991 wm5100->jack_mode);
1992}
1993
2633f736
MB		 1994static void wm5100_report_headphone(struct wm5100_priv *wm5100)
1995{
1996 dev_dbg(wm5100->dev, "Headphone detected\n");
1997 wm5100->jack_detecting = false;
1998 snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
1999 SND_JACK_HEADPHONE);
2000
2001 /* Increase the detection rate a bit for responsiveness. */
2002 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2003 WM5100_ACCDET_RATE_MASK,
2004 7 << WM5100_ACCDET_RATE_SHIFT);
2005}
2006
46c1a877 2007static void wm5100_micd_irq(struct wm5100_priv *wm5100)
ba896ede 2008{
46c1a877
MB		 2009 unsigned int val;
2010 int ret;
ba896ede 2011
46c1a877
MB		 2012 ret = regmap_read(wm5100->regmap, WM5100_MIC_DETECT_3, &val);
2013 if (ret != 0) {
2014 dev_err(wm5100->dev, "Failed to read micropone status: %d\n",
2015 ret);
2016 return;
2017 }
ba896ede 2018
46c1a877 2019 dev_dbg(wm5100->dev, "Microphone event: %x\n", val);
ba896ede
MB		 2020
2021 if (!(val & WM5100_ACCDET_VALID)) {
46c1a877 2022 dev_warn(wm5100->dev, "Microphone detection state invalid\n");
ba896ede
MB		 2023 return;
2024 }
2025
2026 /* No accessory, reset everything and report removal */
2027 if (!(val & WM5100_ACCDET_STS)) {
46c1a877 2028 dev_dbg(wm5100->dev, "Jack removal detected\n");
ba896ede
MB		 2029 wm5100->jack_mic = false;
2030 wm5100->jack_detecting = true;
2633f736 2031 wm5100->jack_flips = 0;
ba896ede
MB		 2032 snd_soc_jack_report(wm5100->jack, 0,
2033 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2034 SND_JACK_BTN_0);
2035
46c1a877
MB		 2036 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2037 WM5100_ACCDET_RATE_MASK,
2038 WM5100_ACCDET_RATE_MASK);
ba896ede
MB		 2039 return;
2040 }
2041
2042 /* If the measurement is very high we've got a microphone,
2043 * either we just detected one or if we already reported then
2044 * we've got a button release event.
2045 */
2046 if (val & 0x400) {
2047 if (wm5100->jack_detecting) {
46c1a877 2048 dev_dbg(wm5100->dev, "Microphone detected\n");
ba896ede 2049 wm5100->jack_mic = true;
9fb83526 2050 wm5100->jack_detecting = false;
ba896ede
MB		 2051 snd_soc_jack_report(wm5100->jack,
2052 SND_JACK_HEADSET,
2053 SND_JACK_HEADSET | SND_JACK_BTN_0);
2054
2055 /* Increase poll rate to give better responsiveness
2056 * for buttons */
46c1a877
MB		 2057 regmap_update_bits(wm5100->regmap, WM5100_MIC_DETECT_1,
2058 WM5100_ACCDET_RATE_MASK,
2059 5 << WM5100_ACCDET_RATE_SHIFT);
ba896ede 2060 } else {
46c1a877 2061 dev_dbg(wm5100->dev, "Mic button up\n");
ba896ede
MB		 2062 snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2063 }
2064
2065 return;
2066 }
2067
2068 /* If we detected a lower impedence during initial startup
2069 * then we probably have the wrong polarity, flip it. Don't
2070 * do this for the lowest impedences to speed up detection of
2633f736
MB		 2071 * plain headphones and give up if neither polarity looks
2072 * sensible.
ba896ede
MB		 2073 */
2074 if (wm5100->jack_detecting && (val & 0x3f8)) {
2633f736
MB		 2075 wm5100->jack_flips++;
2076
2077 if (wm5100->jack_flips > 1)
2078 wm5100_report_headphone(wm5100);
2079 else
2080 wm5100_set_detect_mode(wm5100, !wm5100->jack_mode);
ba896ede
MB		 2081
2082 return;
2083 }
2084
2085 /* Don't distinguish between buttons, just report any low
2086 * impedence as BTN_0.
2087 */
2088 if (val & 0x3fc) {
2089 if (wm5100->jack_mic) {
46c1a877 2090 dev_dbg(wm5100->dev, "Mic button detected\n");
ba896ede
MB		 2091 snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2092 SND_JACK_BTN_0);
2093 } else if (wm5100->jack_detecting) {
2633f736 2094 wm5100_report_headphone(wm5100);
ba896ede
MB		 2095 }
2096 }
2097}
2098
2099int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2100{
2101 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
e951f267 2102 struct snd_soc_dapm_context *dapm = &codec->dapm;
ba896ede
MB		 2103
2104 if (jack) {
2105 wm5100->jack = jack;
2106 wm5100->jack_detecting = true;
2633f736 2107 wm5100->jack_flips = 0;
ba896ede 2108
46c1a877 2109 wm5100_set_detect_mode(wm5100, 0);
ba896ede
MB		 2110
2111 /* Slowest detection rate, gives debounce for initial
2112 * detection */
2113 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2114 WM5100_ACCDET_BIAS_STARTTIME_MASK |
2115 WM5100_ACCDET_RATE_MASK,
2116 (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2117 WM5100_ACCDET_RATE_MASK);
2118
2119 /* We need the charge pump to power MICBIAS */
e951f267
CK		 2120 snd_soc_dapm_mutex_lock(dapm);
2121
2122 snd_soc_dapm_force_enable_pin_unlocked(dapm, "CP2");
2123 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
2124
2125 snd_soc_dapm_sync_unlocked(dapm);
2126
2127 snd_soc_dapm_mutex_unlock(dapm);
ba896ede
MB		 2128
2129 /* We start off just enabling microphone detection - even a
2130 * plain headphone will trigger detection.
2131 */
2132 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2133 WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2134
2135 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2136 WM5100_IM_ACCDET_EINT, 0);
2137 } else {
2138 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2139 WM5100_IM_HPDET_EINT |
2140 WM5100_IM_ACCDET_EINT,
2141 WM5100_IM_HPDET_EINT |
2142 WM5100_IM_ACCDET_EINT);
2143 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2144 WM5100_ACCDET_ENA, 0);
2145 wm5100->jack = NULL;
2146 }
2147
2148 return 0;
2149}
0cf0f174 2150EXPORT_SYMBOL_GPL(wm5100_detect);
ba896ede 2151
6d4baf08
MB		 2152static irqreturn_t wm5100_irq(int irq, void *data)
2153{
46c1a877 2154 struct wm5100_priv *wm5100 = data;
6d4baf08 2155 irqreturn_t status = IRQ_NONE;
46c1a877
MB		 2156 unsigned int irq_val, mask_val;
2157 int ret;
6d4baf08 2158
46c1a877
MB		 2159 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, &irq_val);
2160 if (ret < 0) {
2161 dev_err(wm5100->dev, "Failed to read IRQ status 3: %d\n",
2162 ret);
6d4baf08
MB		 2163 irq_val = 0;
2164 }
6d4baf08 2165
46c1a877
MB		 2166 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_3_MASK,
2167 &mask_val);
2168 if (ret < 0) {
2169 dev_err(wm5100->dev, "Failed to read IRQ mask 3: %d\n",
2170 ret);
2171 mask_val = 0xffff;
2172 }
2173
2174 irq_val &= ~mask_val;
2175
2176 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_3, irq_val);
6d4baf08
MB		 2177
2178 if (irq_val)
2179 status = IRQ_HANDLED;
2180
46c1a877 2181 wm5100_log_status3(wm5100, irq_val);
6d4baf08
MB		 2182
2183 if (irq_val & WM5100_FLL1_LOCK_EINT) {
46c1a877 2184 dev_dbg(wm5100->dev, "FLL1 locked\n");
6d4baf08
MB		 2185 complete(&wm5100->fll[0].lock);
2186 }
2187 if (irq_val & WM5100_FLL2_LOCK_EINT) {
46c1a877 2188 dev_dbg(wm5100->dev, "FLL2 locked\n");
6d4baf08
MB		 2189 complete(&wm5100->fll[1].lock);
2190 }
2191
ba896ede 2192 if (irq_val & WM5100_ACCDET_EINT)
46c1a877 2193 wm5100_micd_irq(wm5100);
ba896ede 2194
46c1a877
MB		 2195 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, &irq_val);
2196 if (ret < 0) {
2197 dev_err(wm5100->dev, "Failed to read IRQ status 4: %d\n",
2198 ret);
6d4baf08
MB		 2199 irq_val = 0;
2200 }
46c1a877
MB		 2201
2202 ret = regmap_read(wm5100->regmap, WM5100_INTERRUPT_STATUS_4_MASK,
2203 &mask_val);
2204 if (ret < 0) {
2205 dev_err(wm5100->dev, "Failed to read IRQ mask 4: %d\n",
2206 ret);
2207 mask_val = 0xffff;
2208 }
2209
2210 irq_val &= ~mask_val;
6d4baf08
MB		 2211
2212 if (irq_val)
2213 status = IRQ_HANDLED;
2214
46c1a877 2215 regmap_write(wm5100->regmap, WM5100_INTERRUPT_STATUS_4, irq_val);
6d4baf08 2216
46c1a877 2217 wm5100_log_status4(wm5100, irq_val);
6d4baf08
MB		 2218
2219 return status;
2220}
2221
2222static irqreturn_t wm5100_edge_irq(int irq, void *data)
2223{
2224 irqreturn_t ret = IRQ_NONE;
2225 irqreturn_t val;
2226
2227 do {
2228 val = wm5100_irq(irq, data);
2229 if (val != IRQ_NONE)
2230 ret = val;
2231 } while (val != IRQ_NONE);
2232
2233 return ret;
2234}
2235
2236#ifdef CONFIG_GPIOLIB
2237static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2238{
2239 return container_of(chip, struct wm5100_priv, gpio_chip);
2240}
2241
2242static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2243{
2244 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
6d4baf08 2245
9db16e4c
MB		 2246 regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2247 WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
6d4baf08
MB		 2248}
2249
2250static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2251 unsigned offset, int value)
2252{
2253 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
64964e82 2254 int val, ret;
6d4baf08
MB		 2255
2256 val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2257
9db16e4c
MB		 2258 ret = regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2259 WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2260 WM5100_GP1_LVL, val);
64964e82
MB		 2261 if (ret < 0)
2262 return ret;
2263 else
2264 return 0;
6d4baf08
MB		 2265}
2266
2267static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2268{
2269 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
9db16e4c 2270 unsigned int reg;
6d4baf08
MB		 2271 int ret;
2272
9db16e4c 2273 ret = regmap_read(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset, &reg);
6d4baf08
MB		 2274 if (ret < 0)
2275 return ret;
2276
9db16e4c 2277 return (reg & WM5100_GP1_LVL) != 0;
6d4baf08
MB		 2278}
2279
2280static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2281{
2282 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
6d4baf08 2283
9db16e4c
MB		 2284 return regmap_update_bits(wm5100->regmap, WM5100_GPIO_CTRL_1 + offset,
2285 WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2286 (1 << WM5100_GP1_FN_SHIFT) |
2287 (1 << WM5100_GP1_DIR_SHIFT));
6d4baf08
MB		 2288}
2289
2290static struct gpio_chip wm5100_template_chip = {
2291 .label = "wm5100",
2292 .owner = THIS_MODULE,
2293 .direction_output = wm5100_gpio_direction_out,
2294 .set = wm5100_gpio_set,
2295 .direction_input = wm5100_gpio_direction_in,
2296 .get = wm5100_gpio_get,
2297 .can_sleep = 1,
2298};
2299
9db16e4c 2300static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08 2301{
9db16e4c 2302 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08
MB		 2303 int ret;
2304
2305 wm5100->gpio_chip = wm5100_template_chip;
2306 wm5100->gpio_chip.ngpio = 6;
9db16e4c 2307 wm5100->gpio_chip.dev = &i2c->dev;
6d4baf08
MB		 2308
2309 if (wm5100->pdata.gpio_base)
2310 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2311 else
2312 wm5100->gpio_chip.base = -1;
2313
2314 ret = gpiochip_add(&wm5100->gpio_chip);
2315 if (ret != 0)
9db16e4c 2316 dev_err(&i2c->dev, "Failed to add GPIOs: %d\n", ret);
6d4baf08
MB		 2317}
2318
9db16e4c 2319static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08 2320{
9db16e4c 2321 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
6d4baf08 2322
88d5e520 2323 gpiochip_remove(&wm5100->gpio_chip);
6d4baf08
MB		 2324}
2325#else
9db16e4c 2326static void wm5100_init_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2327{
2328}
2329
9db16e4c 2330static void wm5100_free_gpio(struct i2c_client *i2c)
6d4baf08
MB		 2331{
2332}
2333#endif
2334
2335static int wm5100_probe(struct snd_soc_codec *codec)
2336{
2337 struct i2c_client *i2c = to_i2c_client(codec->dev);
2338 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
09452f23 2339 int ret, i;
6d4baf08
MB		 2340
2341 wm5100->codec = codec;
6d4baf08 2342
6d4baf08
MB		 2343 for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2344 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2345 WM5100_OUT_VU);
2346
6d4baf08
MB		 2347 /* Don't debounce interrupts to support use of SYSCLK only */
2348 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2349 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2350
2351 /* TODO: check if we're symmetric */
2352
09452f23 2353 if (i2c->irq)
6d4baf08
MB		 2354 snd_soc_dapm_new_controls(&codec->dapm,
2355 wm5100_dapm_widgets_noirq,
2356 ARRAY_SIZE(wm5100_dapm_widgets_noirq));
6d4baf08
MB		 2357
2358 if (wm5100->pdata.hp_pol) {
2359 ret = gpio_request_one(wm5100->pdata.hp_pol,
2360 GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2361 if (ret < 0) {
2362 dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2363 wm5100->pdata.hp_pol, ret);
2364 goto err_gpio;
2365 }
2366 }
2367
6d4baf08
MB		 2368 return 0;
2369
2370err_gpio:
6d4baf08
MB		 2371
2372 return ret;
2373}
2374
2375static int wm5100_remove(struct snd_soc_codec *codec)
2376{
2377 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2378
6d4baf08
MB		 2379 if (wm5100->pdata.hp_pol) {
2380 gpio_free(wm5100->pdata.hp_pol);
2381 }
46c1a877 2382
6d4baf08
MB		 2383 return 0;
2384}
2385
2386static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2387 .probe = wm5100_probe,
2388 .remove = wm5100_remove,
2389
2390 .set_sysclk = wm5100_set_sysclk,
2391 .set_pll = wm5100_set_fll,
6d4baf08
MB		 2392 .idle_bias_off = 1,
2393
2394 .seq_notifier = wm5100_seq_notifier,
2395 .controls = wm5100_snd_controls,
2396 .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2397 .dapm_widgets = wm5100_dapm_widgets,
2398 .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2399 .dapm_routes = wm5100_dapm_routes,
2400 .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
bd132ec5 2401};
6d4baf08 2402
bd132ec5
MB		 2403static const struct regmap_config wm5100_regmap = {
2404 .reg_bits = 16,
2405 .val_bits = 16,
6d4baf08 2406
bd132ec5
MB		 2407 .max_register = WM5100_MAX_REGISTER,
2408 .reg_defaults = wm5100_reg_defaults,
2409 .num_reg_defaults = ARRAY_SIZE(wm5100_reg_defaults),
2410 .volatile_reg = wm5100_volatile_register,
2411 .readable_reg = wm5100_readable_register,
2412 .cache_type = REGCACHE_RBTREE,
6d4baf08
MB		 2413};
2414
a188fcba
MB		 2415static const unsigned int wm5100_mic_ctrl_reg[] = {
2416 WM5100_IN1L_CONTROL,
2417 WM5100_IN2L_CONTROL,
2418 WM5100_IN3L_CONTROL,
2419 WM5100_IN4L_CONTROL,
2420};
2421
7a79e94e
BP		 2422static int wm5100_i2c_probe(struct i2c_client *i2c,
2423 const struct i2c_device_id *id)
6d4baf08
MB		 2424{
2425 struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2426 struct wm5100_priv *wm5100;
588ac5e0 2427 unsigned int reg;
09452f23 2428 int ret, i, irq_flags;
6d4baf08 2429
a81b82c0
MB		 2430 wm5100 = devm_kzalloc(&i2c->dev, sizeof(struct wm5100_priv),
2431 GFP_KERNEL);
6d4baf08
MB		 2432 if (wm5100 == NULL)
2433 return -ENOMEM;
2434
46c1a877
MB		 2435 wm5100->dev = &i2c->dev;
2436
77caabaa 2437 wm5100->regmap = devm_regmap_init_i2c(i2c, &wm5100_regmap);
bd132ec5
MB		 2438 if (IS_ERR(wm5100->regmap)) {
2439 ret = PTR_ERR(wm5100->regmap);
2440 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2441 ret);
a81b82c0 2442 goto err;
bd132ec5
MB		 2443 }
2444
6d4baf08
MB		 2445 for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2446 init_completion(&wm5100->fll[i].lock);
2447
2448 if (pdata)
2449 wm5100->pdata = *pdata;
2450
2451 i2c_set_clientdata(i2c, wm5100);
2452
588ac5e0
MB		 2453 for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2454 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2455
17e3e57b
MB		 2456 ret = devm_regulator_bulk_get(&i2c->dev,
2457 ARRAY_SIZE(wm5100->core_supplies),
2458 wm5100->core_supplies);
588ac5e0
MB		 2459 if (ret != 0) {
2460 dev_err(&i2c->dev, "Failed to request core supplies: %d\n",
2461 ret);
77caabaa 2462 goto err;
588ac5e0
MB		 2463 }
2464
588ac5e0
MB		 2465 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2466 wm5100->core_supplies);
2467 if (ret != 0) {
2468 dev_err(&i2c->dev, "Failed to enable core supplies: %d\n",
2469 ret);
77caabaa 2470 goto err;
588ac5e0
MB		 2471 }
2472
2473 if (wm5100->pdata.ldo_ena) {
2474 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2475 GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2476 if (ret < 0) {
2477 dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2478 wm5100->pdata.ldo_ena, ret);
2479 goto err_enable;
2480 }
2481 msleep(2);
2482 }
2483
2484 if (wm5100->pdata.reset) {
2485 ret = gpio_request_one(wm5100->pdata.reset,
2486 GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2487 if (ret < 0) {
2488 dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2489 wm5100->pdata.reset, ret);
2490 goto err_ldo;
2491 }
2492 }
2493
2494 ret = regmap_read(wm5100->regmap, WM5100_SOFTWARE_RESET, &reg);
2495 if (ret < 0) {
0132615d 2496 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
588ac5e0
MB		 2497 goto err_reset;
2498 }
2499 switch (reg) {
2500 case 0x8997:
2501 case 0x5100:
2502 break;
2503
2504 default:
2505 dev_err(&i2c->dev, "Device is not a WM5100, ID is %x\n", reg);
2506 ret = -EINVAL;
2507 goto err_reset;
2508 }
2509
2510 ret = regmap_read(wm5100->regmap, WM5100_DEVICE_REVISION, &reg);
2511 if (ret < 0) {
2512 dev_err(&i2c->dev, "Failed to read revision register\n");
2513 goto err_reset;
2514 }
2515 wm5100->rev = reg & WM5100_DEVICE_REVISION_MASK;
2516
2517 dev_info(&i2c->dev, "revision %c\n", wm5100->rev + 'A');
2518
2519 ret = wm5100_reset(wm5100);
2520 if (ret < 0) {
2521 dev_err(&i2c->dev, "Failed to issue reset\n");
2522 goto err_reset;
2523 }
2524
15b52f10
MB		 2525 switch (wm5100->rev) {
2526 case 0:
2527 ret = regmap_register_patch(wm5100->regmap,
2528 wm5100_reva_patches,
2529 ARRAY_SIZE(wm5100_reva_patches));
2530 if (ret != 0) {
2531 dev_err(&i2c->dev, "Failed to register patches: %d\n",
2532 ret);
2533 goto err_reset;
2534 }
2535 break;
2536 default:
2537 break;
2538 }
2539
2540
9db16e4c
MB		 2541 wm5100_init_gpio(i2c);
2542
d9b5e9c6
MB		 2543 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2544 if (!wm5100->pdata.gpio_defaults[i])
2545 continue;
2546
2547 regmap_write(wm5100->regmap, WM5100_GPIO_CTRL_1 + i,
2548 wm5100->pdata.gpio_defaults[i]);
2549 }
2550
2551 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
a188fcba 2552 regmap_update_bits(wm5100->regmap, wm5100_mic_ctrl_reg[i],
d9b5e9c6
MB		 2553 WM5100_IN1_MODE_MASK |
2554 WM5100_IN1_DMIC_SUP_MASK,
2555 (wm5100->pdata.in_mode[i] <<
2556 WM5100_IN1_MODE_SHIFT) |
2557 (wm5100->pdata.dmic_sup[i] <<
2558 WM5100_IN1_DMIC_SUP_SHIFT));
2559 }
2560
09452f23
MB		 2561 if (i2c->irq) {
2562 if (wm5100->pdata.irq_flags)
2563 irq_flags = wm5100->pdata.irq_flags;
2564 else
2565 irq_flags = IRQF_TRIGGER_LOW;
2566
2567 irq_flags |= IRQF_ONESHOT;
2568
2569 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2570 ret = request_threaded_irq(i2c->irq, NULL,
2571 wm5100_edge_irq, irq_flags,
2572 "wm5100", wm5100);
2573 else
2574 ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2575 irq_flags, "wm5100",
2576 wm5100);
2577
2578 if (ret != 0) {
2579 dev_err(&i2c->dev, "Failed to request IRQ %d: %d\n",
2580 i2c->irq, ret);
2581 } else {
2582 /* Enable default interrupts */
2583 regmap_update_bits(wm5100->regmap,
2584 WM5100_INTERRUPT_STATUS_3_MASK,
2585 WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2586 WM5100_IM_SPK_SHUTDOWN_EINT |
2587 WM5100_IM_ASRC2_LOCK_EINT |
2588 WM5100_IM_ASRC1_LOCK_EINT |
2589 WM5100_IM_FLL2_LOCK_EINT |
2590 WM5100_IM_FLL1_LOCK_EINT |
2591 WM5100_CLKGEN_ERR_EINT |
2592 WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2593
2594 regmap_update_bits(wm5100->regmap,
2595 WM5100_INTERRUPT_STATUS_4_MASK,
2596 WM5100_AIF3_ERR_EINT |
2597 WM5100_AIF2_ERR_EINT |
2598 WM5100_AIF1_ERR_EINT |
2599 WM5100_CTRLIF_ERR_EINT |
2600 WM5100_ISRC2_UNDERCLOCKED_EINT |
2601 WM5100_ISRC1_UNDERCLOCKED_EINT |
2602 WM5100_FX_UNDERCLOCKED_EINT |
2603 WM5100_AIF3_UNDERCLOCKED_EINT |
2604 WM5100_AIF2_UNDERCLOCKED_EINT |
2605 WM5100_AIF1_UNDERCLOCKED_EINT |
2606 WM5100_ASRC_UNDERCLOCKED_EINT |
2607 WM5100_DAC_UNDERCLOCKED_EINT |
2608 WM5100_ADC_UNDERCLOCKED_EINT |
2609 WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2610 }
2611 }
2612
62c1c401
MB		 2613 pm_runtime_set_active(&i2c->dev);
2614 pm_runtime_enable(&i2c->dev);
2615 pm_request_idle(&i2c->dev);
2616
6d4baf08
MB		 2617 ret = snd_soc_register_codec(&i2c->dev,
2618 &soc_codec_dev_wm5100, wm5100_dai,
2619 ARRAY_SIZE(wm5100_dai));
2620 if (ret < 0) {
2621 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
588ac5e0 2622 goto err_reset;
6d4baf08
MB		 2623 }
2624
2625 return ret;
bd132ec5 2626
588ac5e0 2627err_reset:
09452f23
MB		 2628 if (i2c->irq)
2629 free_irq(i2c->irq, wm5100);
9db16e4c 2630 wm5100_free_gpio(i2c);
588ac5e0 2631 if (wm5100->pdata.reset) {
2688738e 2632 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
588ac5e0
MB		 2633 gpio_free(wm5100->pdata.reset);
2634 }
2635err_ldo:
2636 if (wm5100->pdata.ldo_ena) {
2637 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2638 gpio_free(wm5100->pdata.ldo_ena);
2639 }
2640err_enable:
2641 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2642 wm5100->core_supplies);
a81b82c0 2643err:
bd132ec5 2644 return ret;
6d4baf08
MB		 2645}
2646
7a79e94e 2647static int wm5100_i2c_remove(struct i2c_client *i2c)
6d4baf08 2648{
09452f23 2649 struct wm5100_priv *wm5100 = i2c_get_clientdata(i2c);
bd132ec5 2650
09452f23
MB		 2651 snd_soc_unregister_codec(&i2c->dev);
2652 if (i2c->irq)
2653 free_irq(i2c->irq, wm5100);
2654 wm5100_free_gpio(i2c);
588ac5e0 2655 if (wm5100->pdata.reset) {
2688738e 2656 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
588ac5e0
MB		 2657 gpio_free(wm5100->pdata.reset);
2658 }
2659 if (wm5100->pdata.ldo_ena) {
2660 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2661 gpio_free(wm5100->pdata.ldo_ena);
2662 }
bd132ec5 2663
6d4baf08
MB		 2664 return 0;
2665}
2666
62c1c401
MB		 2667#ifdef CONFIG_PM_RUNTIME
2668static int wm5100_runtime_suspend(struct device *dev)
2669{
2670 struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2671
2672 regcache_cache_only(wm5100->regmap, true);
2673 regcache_mark_dirty(wm5100->regmap);
2674 if (wm5100->pdata.ldo_ena)
2675 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2676 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2677 wm5100->core_supplies);
2678
2679 return 0;
2680}
2681
2682static int wm5100_runtime_resume(struct device *dev)
2683{
2684 struct wm5100_priv *wm5100 = dev_get_drvdata(dev);
2685 int ret;
2686
2687 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2688 wm5100->core_supplies);
2689 if (ret != 0) {
2690 dev_err(dev, "Failed to enable supplies: %d\n",
2691 ret);
2692 return ret;
2693 }
2694
2695 if (wm5100->pdata.ldo_ena) {
2696 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 1);
2697 msleep(2);
2698 }
2699
2700 regcache_cache_only(wm5100->regmap, false);
2701 regcache_sync(wm5100->regmap);
2702
2703 return 0;
2704}
2705#endif
2706
2707static struct dev_pm_ops wm5100_pm = {
2708 SET_RUNTIME_PM_OPS(wm5100_runtime_suspend, wm5100_runtime_resume,
2709 NULL)
2710};
2711
6d4baf08
MB		 2712static const struct i2c_device_id wm5100_i2c_id[] = {
2713 { "wm5100", 0 },
2714 { }
2715};
2716MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2717
2718static struct i2c_driver wm5100_i2c_driver = {
2719 .driver = {
2720 .name = "wm5100",
2721 .owner = THIS_MODULE,
62c1c401 2722 .pm = &wm5100_pm,
6d4baf08
MB		 2723 },
2724 .probe = wm5100_i2c_probe,
7a79e94e 2725 .remove = wm5100_i2c_remove,
6d4baf08
MB		 2726 .id_table = wm5100_i2c_id,
2727};
2728
d5644076 2729module_i2c_driver(wm5100_i2c_driver);
6d4baf08
MB		 2730
2731MODULE_DESCRIPTION("ASoC WM5100 driver");
2732MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2733MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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