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ASoC: wm8350: Remove check for clocks in trigger()
[deliverable/linux.git] / sound / soc / codecs / wm8350.c
CommitLineData
40aa4a30
MB		 1/*
2 * wm8350.c -- WM8350 ALSA SoC audio driver
3 *
4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
5 *
64ca0404 6 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
40aa4a30
MB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
5a0e3ad6 16#include <linux/slab.h>
40aa4a30
MB		 17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/platform_device.h>
20#include <linux/mfd/wm8350/audio.h>
21#include <linux/mfd/wm8350/core.h>
22#include <linux/regulator/consumer.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
40aa4a30
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
2bbb5d66 29#include <trace/events/asoc.h>
40aa4a30
MB		 30
31#include "wm8350.h"
32
33#define WM8350_OUTn_0dB 0x39
34
35#define WM8350_RAMP_NONE 0
36#define WM8350_RAMP_UP 1
37#define WM8350_RAMP_DOWN 2
38
39/* We only include the analogue supplies here; the digital supplies
40 * need to be available well before this driver can be probed.
41 */
42static const char *supply_names[] = {
43 "AVDD",
44 "HPVDD",
45};
46
47struct wm8350_output {
48 u16 active;
49 u16 left_vol;
50 u16 right_vol;
51 u16 ramp;
52 u16 mute;
53};
54
a6ba2b2d
MB		 55struct wm8350_jack_data {
56 struct snd_soc_jack *jack;
6d3c26bc 57 struct delayed_work work;
a6ba2b2d 58 int report;
2a0761a3 59 int short_report;
a6ba2b2d
MB		 60};
61
40aa4a30
MB		 62struct wm8350_data {
63 struct snd_soc_codec codec;
64 struct wm8350_output out1;
65 struct wm8350_output out2;
a6ba2b2d
MB		 66 struct wm8350_jack_data hpl;
67 struct wm8350_jack_data hpr;
2a0761a3 68 struct wm8350_jack_data mic;
40aa4a30 69 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
f1e887de
MB		 70 int fll_freq_out;
71 int fll_freq_in;
40aa4a30
MB		 72};
73
40aa4a30
MB		 74static unsigned int wm8350_codec_read(struct snd_soc_codec *codec,
75 unsigned int reg)
76{
77 struct wm8350 *wm8350 = codec->control_data;
78 return wm8350_reg_read(wm8350, reg);
79}
80
81static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg,
82 unsigned int value)
83{
84 struct wm8350 *wm8350 = codec->control_data;
85 return wm8350_reg_write(wm8350, reg, value);
86}
87
88/*
89 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
90 */
91static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec)
92{
b2c812e2 93 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 94 struct wm8350_output *out1 = &wm8350_data->out1;
95 struct wm8350 *wm8350 = codec->control_data;
96 int left_complete = 0, right_complete = 0;
97 u16 reg, val;
98
99 /* left channel */
100 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
101 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
102
103 if (out1->ramp == WM8350_RAMP_UP) {
104 /* ramp step up */
105 if (val < out1->left_vol) {
106 val++;
107 reg &= ~WM8350_OUT1L_VOL_MASK;
108 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
109 reg | (val << WM8350_OUT1L_VOL_SHIFT));
110 } else
111 left_complete = 1;
112 } else if (out1->ramp == WM8350_RAMP_DOWN) {
113 /* ramp step down */
114 if (val > 0) {
115 val--;
116 reg &= ~WM8350_OUT1L_VOL_MASK;
117 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
118 reg | (val << WM8350_OUT1L_VOL_SHIFT));
119 } else
120 left_complete = 1;
121 } else
122 return 1;
123
124 /* right channel */
125 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
126 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
127 if (out1->ramp == WM8350_RAMP_UP) {
128 /* ramp step up */
129 if (val < out1->right_vol) {
130 val++;
131 reg &= ~WM8350_OUT1R_VOL_MASK;
132 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
133 reg | (val << WM8350_OUT1R_VOL_SHIFT));
134 } else
135 right_complete = 1;
136 } else if (out1->ramp == WM8350_RAMP_DOWN) {
137 /* ramp step down */
138 if (val > 0) {
139 val--;
140 reg &= ~WM8350_OUT1R_VOL_MASK;
141 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
142 reg | (val << WM8350_OUT1R_VOL_SHIFT));
143 } else
144 right_complete = 1;
145 }
146
147 /* only hit the update bit if either volume has changed this step */
148 if (!left_complete || !right_complete)
149 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
150
151 return left_complete & right_complete;
152}
153
154/*
155 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
156 */
157static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
158{
b2c812e2 159 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 160 struct wm8350_output *out2 = &wm8350_data->out2;
161 struct wm8350 *wm8350 = codec->control_data;
162 int left_complete = 0, right_complete = 0;
163 u16 reg, val;
164
165 /* left channel */
166 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
167 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
168 if (out2->ramp == WM8350_RAMP_UP) {
169 /* ramp step up */
170 if (val < out2->left_vol) {
171 val++;
172 reg &= ~WM8350_OUT2L_VOL_MASK;
173 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
174 reg | (val << WM8350_OUT1L_VOL_SHIFT));
175 } else
176 left_complete = 1;
177 } else if (out2->ramp == WM8350_RAMP_DOWN) {
178 /* ramp step down */
179 if (val > 0) {
180 val--;
181 reg &= ~WM8350_OUT2L_VOL_MASK;
182 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
183 reg | (val << WM8350_OUT1L_VOL_SHIFT));
184 } else
185 left_complete = 1;
186 } else
187 return 1;
188
189 /* right channel */
190 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
191 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
192 if (out2->ramp == WM8350_RAMP_UP) {
193 /* ramp step up */
194 if (val < out2->right_vol) {
195 val++;
196 reg &= ~WM8350_OUT2R_VOL_MASK;
197 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
198 reg | (val << WM8350_OUT1R_VOL_SHIFT));
199 } else
200 right_complete = 1;
201 } else if (out2->ramp == WM8350_RAMP_DOWN) {
202 /* ramp step down */
203 if (val > 0) {
204 val--;
205 reg &= ~WM8350_OUT2R_VOL_MASK;
206 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
207 reg | (val << WM8350_OUT1R_VOL_SHIFT));
208 } else
209 right_complete = 1;
210 }
211
212 /* only hit the update bit if either volume has changed this step */
213 if (!left_complete || !right_complete)
214 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
215
216 return left_complete & right_complete;
217}
218
219/*
220 * This work ramps both output PGAs at stream start/stop time to
221 * minimise pop associated with DAPM power switching.
222 * It's best to enable Zero Cross when ramping occurs to minimise any
223 * zipper noises.
224 */
225static void wm8350_pga_work(struct work_struct *work)
226{
ce6120cc
LG		 227 struct snd_soc_dapm_context *dapm =
228 container_of(work, struct snd_soc_dapm_context, delayed_work.work);
229 struct snd_soc_codec *codec = dapm->codec;
b2c812e2 230 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 231 struct wm8350_output *out1 = &wm8350_data->out1,
232 *out2 = &wm8350_data->out2;
233 int i, out1_complete, out2_complete;
234
235 /* do we need to ramp at all ? */
236 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
237 return;
238
239 /* PGA volumes have 6 bits of resolution to ramp */
240 for (i = 0; i <= 63; i++) {
241 out1_complete = 1, out2_complete = 1;
242 if (out1->ramp != WM8350_RAMP_NONE)
243 out1_complete = wm8350_out1_ramp_step(codec);
244 if (out2->ramp != WM8350_RAMP_NONE)
245 out2_complete = wm8350_out2_ramp_step(codec);
246
247 /* ramp finished ? */
248 if (out1_complete && out2_complete)
249 break;
250
251 /* we need to delay longer on the up ramp */
252 if (out1->ramp == WM8350_RAMP_UP ||
253 out2->ramp == WM8350_RAMP_UP) {
254 /* delay is longer over 0dB as increases are larger */
255 if (i >= WM8350_OUTn_0dB)
256 schedule_timeout_interruptible(msecs_to_jiffies
257 (2));
258 else
259 schedule_timeout_interruptible(msecs_to_jiffies
260 (1));
261 } else
262 udelay(50); /* doesn't matter if we delay longer */
263 }
264
265 out1->ramp = WM8350_RAMP_NONE;
266 out2->ramp = WM8350_RAMP_NONE;
267}
268
269/*
270 * WM8350 Controls
271 */
272
273static int pga_event(struct snd_soc_dapm_widget *w,
274 struct snd_kcontrol *kcontrol, int event)
275{
276 struct snd_soc_codec *codec = w->codec;
b2c812e2 277 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 278 struct wm8350_output *out;
279
280 switch (w->shift) {
281 case 0:
282 case 1:
283 out = &wm8350_data->out1;
284 break;
285 case 2:
286 case 3:
287 out = &wm8350_data->out2;
288 break;
289
290 default:
291 BUG();
292 return -1;
293 }
294
295 switch (event) {
296 case SND_SOC_DAPM_POST_PMU:
297 out->ramp = WM8350_RAMP_UP;
298 out->active = 1;
299
ce6120cc
LG		 300 if (!delayed_work_pending(&codec->dapm.delayed_work))
301 schedule_delayed_work(&codec->dapm.delayed_work,
40aa4a30
MB		 302 msecs_to_jiffies(1));
303 break;
304
305 case SND_SOC_DAPM_PRE_PMD:
306 out->ramp = WM8350_RAMP_DOWN;
307 out->active = 0;
308
ce6120cc
LG		 309 if (!delayed_work_pending(&codec->dapm.delayed_work))
310 schedule_delayed_work(&codec->dapm.delayed_work,
40aa4a30
MB		 311 msecs_to_jiffies(1));
312 break;
313 }
314
315 return 0;
316}
317
318static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
319 struct snd_ctl_elem_value *ucontrol)
320{
321 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 322 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 323 struct wm8350_output *out = NULL;
324 struct soc_mixer_control *mc =
325 (struct soc_mixer_control *)kcontrol->private_value;
326 int ret;
327 unsigned int reg = mc->reg;
328 u16 val;
329
330 /* For OUT1 and OUT2 we shadow the values and only actually write
331 * them out when active in order to ensure the amplifier comes on
332 * as quietly as possible. */
333 switch (reg) {
334 case WM8350_LOUT1_VOLUME:
335 out = &wm8350_priv->out1;
336 break;
337 case WM8350_LOUT2_VOLUME:
338 out = &wm8350_priv->out2;
339 break;
340 default:
341 break;
342 }
343
344 if (out) {
345 out->left_vol = ucontrol->value.integer.value[0];
346 out->right_vol = ucontrol->value.integer.value[1];
347 if (!out->active)
348 return 1;
349 }
350
c4671a95 351 ret = snd_soc_put_volsw(kcontrol, ucontrol);
40aa4a30
MB		 352 if (ret < 0)
353 return ret;
354
355 /* now hit the volume update bits (always bit 8) */
356 val = wm8350_codec_read(codec, reg);
357 wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU);
358 return 1;
359}
360
361static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
362 struct snd_ctl_elem_value *ucontrol)
363{
364 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 365 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 366 struct wm8350_output *out1 = &wm8350_priv->out1;
367 struct wm8350_output *out2 = &wm8350_priv->out2;
368 struct soc_mixer_control *mc =
369 (struct soc_mixer_control *)kcontrol->private_value;
370 unsigned int reg = mc->reg;
371
372 /* If these are cached registers use the cache */
373 switch (reg) {
374 case WM8350_LOUT1_VOLUME:
375 ucontrol->value.integer.value[0] = out1->left_vol;
376 ucontrol->value.integer.value[1] = out1->right_vol;
377 return 0;
378
379 case WM8350_LOUT2_VOLUME:
380 ucontrol->value.integer.value[0] = out2->left_vol;
381 ucontrol->value.integer.value[1] = out2->right_vol;
382 return 0;
383
384 default:
385 break;
386 }
387
c4671a95 388 return snd_soc_get_volsw(kcontrol, ucontrol);
40aa4a30
MB		 389}
390
40aa4a30
MB		 391static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
392static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
393static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
394static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
40aa4a30
MB		 395static const char *wm8350_adcfilter[] = { "None", "High Pass" };
396static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
397static const char *wm8350_lr[] = { "Left", "Right" };
398
399static const struct soc_enum wm8350_enum[] = {
400 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
401 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
402 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
403 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
40aa4a30
MB		 404 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
405 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
406 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
407 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
408};
409
e6a08c5a
MB		 410static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
411static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
40aa4a30
MB		 412static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
413static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
414static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
415
416static const unsigned int capture_sd_tlv[] = {
417 TLV_DB_RANGE_HEAD(2),
418 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
419 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
420};
421
422static const struct snd_kcontrol_new wm8350_snd_controls[] = {
423 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
424 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
0f9887d1 425 SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
40aa4a30
MB		 426 WM8350_DAC_DIGITAL_VOLUME_L,
427 WM8350_DAC_DIGITAL_VOLUME_R,
0f9887d1
PU		 428 0, 255, 0, wm8350_get_volsw_2r,
429 wm8350_put_volsw_2r_vu, dac_pcm_tlv),
40aa4a30
MB		 430 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
431 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
61943999
MB		 432 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
433 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
434 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
0f9887d1 435 SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
40aa4a30
MB		 436 WM8350_ADC_DIGITAL_VOLUME_L,
437 WM8350_ADC_DIGITAL_VOLUME_R,
0f9887d1
PU		 438 0, 255, 0, wm8350_get_volsw_2r,
439 wm8350_put_volsw_2r_vu, adc_pcm_tlv),
40aa4a30
MB		 440 SOC_DOUBLE_TLV("Capture Sidetone Volume",
441 WM8350_ADC_DIVIDER,
442 8, 4, 15, 1, capture_sd_tlv),
0f9887d1 443 SOC_DOUBLE_R_EXT_TLV("Capture Volume",
40aa4a30
MB		 444 WM8350_LEFT_INPUT_VOLUME,
445 WM8350_RIGHT_INPUT_VOLUME,
0f9887d1
PU		 446 2, 63, 0, wm8350_get_volsw_2r,
447 wm8350_put_volsw_2r_vu, pre_amp_tlv),
40aa4a30
MB		 448 SOC_DOUBLE_R("Capture ZC Switch",
449 WM8350_LEFT_INPUT_VOLUME,
450 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
451 SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
452 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
453 SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
454 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
455 5, 7, 0, out_mix_tlv),
456 SOC_SINGLE_TLV("Left Input Bypass Volume",
457 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
458 9, 7, 0, out_mix_tlv),
459 SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
460 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
461 1, 7, 0, out_mix_tlv),
462 SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
463 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
464 5, 7, 0, out_mix_tlv),
465 SOC_SINGLE_TLV("Right Input Bypass Volume",
466 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
467 13, 7, 0, out_mix_tlv),
468 SOC_SINGLE("Left Input Mixer +20dB Switch",
469 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
470 SOC_SINGLE("Right Input Mixer +20dB Switch",
471 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
472 SOC_SINGLE_TLV("Out4 Capture Volume",
473 WM8350_INPUT_MIXER_VOLUME,
474 1, 7, 0, out_mix_tlv),
0f9887d1 475 SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
40aa4a30
MB		 476 WM8350_LOUT1_VOLUME,
477 WM8350_ROUT1_VOLUME,
0f9887d1
PU		 478 2, 63, 0, wm8350_get_volsw_2r,
479 wm8350_put_volsw_2r_vu, out_pga_tlv),
40aa4a30
MB		 480 SOC_DOUBLE_R("Out1 Playback ZC Switch",
481 WM8350_LOUT1_VOLUME,
482 WM8350_ROUT1_VOLUME, 13, 1, 0),
0f9887d1 483 SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
40aa4a30
MB		 484 WM8350_LOUT2_VOLUME,
485 WM8350_ROUT2_VOLUME,
0f9887d1
PU		 486 2, 63, 0, wm8350_get_volsw_2r,
487 wm8350_put_volsw_2r_vu, out_pga_tlv),
40aa4a30
MB		 488 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
489 WM8350_ROUT2_VOLUME, 13, 1, 0),
490 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
491 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
492 5, 7, 0, out_mix_tlv),
493
494 SOC_DOUBLE_R("Out1 Playback Switch",
495 WM8350_LOUT1_VOLUME,
496 WM8350_ROUT1_VOLUME,
497 14, 1, 1),
498 SOC_DOUBLE_R("Out2 Playback Switch",
499 WM8350_LOUT2_VOLUME,
500 WM8350_ROUT2_VOLUME,
501 14, 1, 1),
502};
503
504/*
505 * DAPM Controls
506 */
507
508/* Left Playback Mixer */
509static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
510 SOC_DAPM_SINGLE("Playback Switch",
511 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
512 SOC_DAPM_SINGLE("Left Bypass Switch",
513 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
514 SOC_DAPM_SINGLE("Right Playback Switch",
515 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
516 SOC_DAPM_SINGLE("Left Sidetone Switch",
517 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
518 SOC_DAPM_SINGLE("Right Sidetone Switch",
519 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
520};
521
522/* Right Playback Mixer */
523static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
524 SOC_DAPM_SINGLE("Playback Switch",
525 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
526 SOC_DAPM_SINGLE("Right Bypass Switch",
527 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
528 SOC_DAPM_SINGLE("Left Playback Switch",
529 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
530 SOC_DAPM_SINGLE("Left Sidetone Switch",
531 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
532 SOC_DAPM_SINGLE("Right Sidetone Switch",
533 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
534};
535
536/* Out4 Mixer */
537static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
538 SOC_DAPM_SINGLE("Right Playback Switch",
539 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
540 SOC_DAPM_SINGLE("Left Playback Switch",
541 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
542 SOC_DAPM_SINGLE("Right Capture Switch",
543 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
544 SOC_DAPM_SINGLE("Out3 Playback Switch",
545 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
546 SOC_DAPM_SINGLE("Right Mixer Switch",
547 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
548 SOC_DAPM_SINGLE("Left Mixer Switch",
549 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
550};
551
552/* Out3 Mixer */
553static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
554 SOC_DAPM_SINGLE("Left Playback Switch",
555 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
556 SOC_DAPM_SINGLE("Left Capture Switch",
557 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
558 SOC_DAPM_SINGLE("Out4 Playback Switch",
559 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
560 SOC_DAPM_SINGLE("Left Mixer Switch",
561 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
562};
563
564/* Left Input Mixer */
565static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
566 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
567 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
568 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
569 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
570 SOC_DAPM_SINGLE("PGA Capture Switch",
5b7dde34 571 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
40aa4a30
MB		 572};
573
574/* Right Input Mixer */
575static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
576 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
577 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
578 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
579 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
580 SOC_DAPM_SINGLE("PGA Capture Switch",
5b7dde34 581 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
40aa4a30
MB		 582};
583
584/* Left Mic Mixer */
585static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
586 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
587 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
588 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
589};
590
591/* Right Mic Mixer */
592static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
593 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
594 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
595 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
596};
597
598/* Beep Switch */
599static const struct snd_kcontrol_new wm8350_beep_switch_controls =
600SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
601
602/* Out4 Capture Mux */
603static const struct snd_kcontrol_new wm8350_out4_capture_controls =
87831cb6 604SOC_DAPM_ENUM("Route", wm8350_enum[7]);
40aa4a30
MB		 605
606static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
607
608 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
609 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
610 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
611 0, pga_event,
612 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
613 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
614 pga_event,
615 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
616 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
617 0, pga_event,
618 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
619 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
620 pga_event,
621 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
622
623 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
624 7, 0, &wm8350_right_capt_mixer_controls[0],
625 ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
626
627 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
628 6, 0, &wm8350_left_capt_mixer_controls[0],
629 ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
630
631 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
632 &wm8350_out4_mixer_controls[0],
633 ARRAY_SIZE(wm8350_out4_mixer_controls)),
634
635 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
636 &wm8350_out3_mixer_controls[0],
637 ARRAY_SIZE(wm8350_out3_mixer_controls)),
638
639 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
640 &wm8350_right_play_mixer_controls[0],
641 ARRAY_SIZE(wm8350_right_play_mixer_controls)),
642
643 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
644 &wm8350_left_play_mixer_controls[0],
645 ARRAY_SIZE(wm8350_left_play_mixer_controls)),
646
647 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
648 &wm8350_left_mic_mixer_controls[0],
649 ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
650
651 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
652 &wm8350_right_mic_mixer_controls[0],
653 ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
654
655 /* virtual mixer for Beep and Out2R */
656 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
657
658 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
659 &wm8350_beep_switch_controls),
660
661 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
662 WM8350_POWER_MGMT_4, 3, 0),
663 SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
664 WM8350_POWER_MGMT_4, 2, 0),
665 SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
666 WM8350_POWER_MGMT_4, 5, 0),
667 SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
668 WM8350_POWER_MGMT_4, 4, 0),
669
670 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
671
672 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
673 &wm8350_out4_capture_controls),
674
675 SND_SOC_DAPM_OUTPUT("OUT1R"),
676 SND_SOC_DAPM_OUTPUT("OUT1L"),
677 SND_SOC_DAPM_OUTPUT("OUT2R"),
678 SND_SOC_DAPM_OUTPUT("OUT2L"),
679 SND_SOC_DAPM_OUTPUT("OUT3"),
680 SND_SOC_DAPM_OUTPUT("OUT4"),
681
682 SND_SOC_DAPM_INPUT("IN1RN"),
683 SND_SOC_DAPM_INPUT("IN1RP"),
684 SND_SOC_DAPM_INPUT("IN2R"),
685 SND_SOC_DAPM_INPUT("IN1LP"),
686 SND_SOC_DAPM_INPUT("IN1LN"),
687 SND_SOC_DAPM_INPUT("IN2L"),
688 SND_SOC_DAPM_INPUT("IN3R"),
689 SND_SOC_DAPM_INPUT("IN3L"),
690};
691
e6c94e9f 692static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
40aa4a30
MB		 693
694 /* left playback mixer */
695 {"Left Playback Mixer", "Playback Switch", "Left DAC"},
696 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
697 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
698 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
699 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
700
701 /* right playback mixer */
702 {"Right Playback Mixer", "Playback Switch", "Right DAC"},
703 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
704 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
705 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
706 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
707
708 /* out4 playback mixer */
709 {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
710 {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
711 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
712 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
713 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
714 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
715 {"OUT4", NULL, "Out4 Mixer"},
716
717 /* out3 playback mixer */
718 {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
719 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
720 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
721 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
722 {"OUT3", NULL, "Out3 Mixer"},
723
724 /* out2 */
725 {"Right Out2 PGA", NULL, "Right Playback Mixer"},
726 {"Left Out2 PGA", NULL, "Left Playback Mixer"},
727 {"OUT2L", NULL, "Left Out2 PGA"},
728 {"OUT2R", NULL, "Right Out2 PGA"},
729
730 /* out1 */
731 {"Right Out1 PGA", NULL, "Right Playback Mixer"},
732 {"Left Out1 PGA", NULL, "Left Playback Mixer"},
733 {"OUT1L", NULL, "Left Out1 PGA"},
734 {"OUT1R", NULL, "Right Out1 PGA"},
735
736 /* ADCs */
737 {"Left ADC", NULL, "Left Capture Mixer"},
738 {"Right ADC", NULL, "Right Capture Mixer"},
739
740 /* Left capture mixer */
741 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
742 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
743 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
744 {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
745
746 /* Right capture mixer */
747 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
748 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
749 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
750 {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
751
752 /* L3 Inputs */
753 {"IN3L PGA", NULL, "IN3L"},
754 {"IN3R PGA", NULL, "IN3R"},
755
756 /* Left Mic mixer */
757 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
758 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
759 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
760
761 /* Right Mic mixer */
762 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
763 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
764 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
765
766 /* out 4 capture */
767 {"Out4 Capture Channel", NULL, "Out4 Mixer"},
768
769 /* Beep */
770 {"Beep", NULL, "IN3R PGA"},
771};
772
40aa4a30
MB		 773static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
774 int clk_id, unsigned int freq, int dir)
775{
776 struct snd_soc_codec *codec = codec_dai->codec;
777 struct wm8350 *wm8350 = codec->control_data;
778 u16 fll_4;
779
780 switch (clk_id) {
781 case WM8350_MCLK_SEL_MCLK:
782 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
783 WM8350_MCLK_SEL);
784 break;
785 case WM8350_MCLK_SEL_PLL_MCLK:
786 case WM8350_MCLK_SEL_PLL_DAC:
787 case WM8350_MCLK_SEL_PLL_ADC:
788 case WM8350_MCLK_SEL_PLL_32K:
789 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
790 WM8350_MCLK_SEL);
791 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
792 ~WM8350_FLL_CLK_SRC_MASK;
793 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
794 break;
795 }
796
797 /* MCLK direction */
c28a9926 798 if (dir == SND_SOC_CLOCK_OUT)
40aa4a30
MB		 799 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
800 WM8350_MCLK_DIR);
801 else
802 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
803 WM8350_MCLK_DIR);
804
805 return 0;
806}
807
808static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
809{
810 struct snd_soc_codec *codec = codec_dai->codec;
811 u16 val;
812
813 switch (div_id) {
814 case WM8350_ADC_CLKDIV:
815 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) &
816 ~WM8350_ADC_CLKDIV_MASK;
817 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div);
818 break;
819 case WM8350_DAC_CLKDIV:
820 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) &
821 ~WM8350_DAC_CLKDIV_MASK;
822 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
823 break;
824 case WM8350_BCLK_CLKDIV:
825 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
826 ~WM8350_BCLK_DIV_MASK;
827 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
828 break;
829 case WM8350_OPCLK_CLKDIV:
830 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
831 ~WM8350_OPCLK_DIV_MASK;
832 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
833 break;
834 case WM8350_SYS_CLKDIV:
835 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
836 ~WM8350_MCLK_DIV_MASK;
837 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
838 break;
839 case WM8350_DACLR_CLKDIV:
840 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
841 ~WM8350_DACLRC_RATE_MASK;
842 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div);
843 break;
844 case WM8350_ADCLR_CLKDIV:
845 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
846 ~WM8350_ADCLRC_RATE_MASK;
847 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div);
848 break;
849 default:
850 return -EINVAL;
851 }
852
853 return 0;
854}
855
856static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
857{
858 struct snd_soc_codec *codec = codec_dai->codec;
859 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
860 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
861 u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) &
862 ~WM8350_BCLK_MSTR;
863 u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
864 ~WM8350_DACLRC_ENA;
865 u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
866 ~WM8350_ADCLRC_ENA;
867
868 /* set master/slave audio interface */
869 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
870 case SND_SOC_DAIFMT_CBM_CFM:
871 master |= WM8350_BCLK_MSTR;
872 dac_lrc |= WM8350_DACLRC_ENA;
873 adc_lrc |= WM8350_ADCLRC_ENA;
874 break;
875 case SND_SOC_DAIFMT_CBS_CFS:
876 break;
877 default:
878 return -EINVAL;
879 }
880
881 /* interface format */
882 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
883 case SND_SOC_DAIFMT_I2S:
884 iface |= 0x2 << 8;
885 break;
886 case SND_SOC_DAIFMT_RIGHT_J:
887 break;
888 case SND_SOC_DAIFMT_LEFT_J:
889 iface |= 0x1 << 8;
890 break;
891 case SND_SOC_DAIFMT_DSP_A:
892 iface |= 0x3 << 8;
893 break;
894 case SND_SOC_DAIFMT_DSP_B:
5ee518ec 895 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
40aa4a30
MB		 896 break;
897 default:
898 return -EINVAL;
899 }
900
901 /* clock inversion */
902 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
903 case SND_SOC_DAIFMT_NB_NF:
904 break;
905 case SND_SOC_DAIFMT_IB_IF:
906 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
907 break;
908 case SND_SOC_DAIFMT_IB_NF:
909 iface |= WM8350_AIF_BCLK_INV;
910 break;
911 case SND_SOC_DAIFMT_NB_IF:
912 iface |= WM8350_AIF_LRCLK_INV;
913 break;
914 default:
915 return -EINVAL;
916 }
917
918 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
919 wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master);
920 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
921 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
922 return 0;
923}
924
40aa4a30
MB		 925static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
926 struct snd_pcm_hw_params *params,
927 struct snd_soc_dai *codec_dai)
928{
929 struct snd_soc_codec *codec = codec_dai->codec;
61943999 930 struct wm8350 *wm8350 = codec->control_data;
40aa4a30
MB		 931 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
932 ~WM8350_AIF_WL_MASK;
933
934 /* bit size */
935 switch (params_format(params)) {
936 case SNDRV_PCM_FORMAT_S16_LE:
937 break;
938 case SNDRV_PCM_FORMAT_S20_3LE:
939 iface |= 0x1 << 10;
940 break;
941 case SNDRV_PCM_FORMAT_S24_LE:
942 iface |= 0x2 << 10;
943 break;
944 case SNDRV_PCM_FORMAT_S32_LE:
945 iface |= 0x3 << 10;
946 break;
947 }
948
949 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
61943999
MB		 950
951 /* The sloping stopband filter is recommended for use with
952 * lower sample rates to improve performance.
953 */
954 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
955 if (params_rate(params) < 24000)
956 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
957 WM8350_DAC_SB_FILT);
958 else
959 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
960 WM8350_DAC_SB_FILT);
961 }
962
40aa4a30
MB		 963 return 0;
964}
965
966static int wm8350_mute(struct snd_soc_dai *dai, int mute)
967{
968 struct snd_soc_codec *codec = dai->codec;
969 struct wm8350 *wm8350 = codec->control_data;
970
971 if (mute)
972 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
973 else
974 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
975 return 0;
976}
977
978/* FLL divisors */
979struct _fll_div {
980 int div; /* FLL_OUTDIV */
981 int n;
982 int k;
983 int ratio; /* FLL_FRATIO */
984};
985
986/* The size in bits of the fll divide multiplied by 10
987 * to allow rounding later */
988#define FIXED_FLL_SIZE ((1 << 16) * 10)
989
990static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
991 unsigned int output)
992{
993 u64 Kpart;
994 unsigned int t1, t2, K, Nmod;
995
996 if (output >= 2815250 && output <= 3125000)
997 fll_div->div = 0x4;
998 else if (output >= 5625000 && output <= 6250000)
999 fll_div->div = 0x3;
1000 else if (output >= 11250000 && output <= 12500000)
1001 fll_div->div = 0x2;
1002 else if (output >= 22500000 && output <= 25000000)
1003 fll_div->div = 0x1;
1004 else {
1005 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
1006 return -EINVAL;
1007 }
1008
1009 if (input > 48000)
1010 fll_div->ratio = 1;
1011 else
1012 fll_div->ratio = 8;
1013
1014 t1 = output * (1 << (fll_div->div + 1));
1015 t2 = input * fll_div->ratio;
1016
1017 fll_div->n = t1 / t2;
1018 Nmod = t1 % t2;
1019
1020 if (Nmod) {
1021 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1022 do_div(Kpart, t2);
1023 K = Kpart & 0xFFFFFFFF;
1024
1025 /* Check if we need to round */
1026 if ((K % 10) >= 5)
1027 K += 5;
1028
1029 /* Move down to proper range now rounding is done */
1030 K /= 10;
1031 fll_div->k = K;
1032 } else
1033 fll_div->k = 0;
1034
1035 return 0;
1036}
1037
1038static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
85488037 1039 int pll_id, int source, unsigned int freq_in,
40aa4a30
MB		 1040 unsigned int freq_out)
1041{
1042 struct snd_soc_codec *codec = codec_dai->codec;
1043 struct wm8350 *wm8350 = codec->control_data;
b2c812e2 1044 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 1045 struct _fll_div fll_div;
1046 int ret = 0;
1047 u16 fll_1, fll_4;
1048
f1e887de
MB		 1049 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1050 return 0;
1051
40aa4a30
MB		 1052 /* power down FLL - we need to do this for reconfiguration */
1053 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1054 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1055
1056 if (freq_out == 0 || freq_in == 0)
1057 return ret;
1058
1059 ret = fll_factors(&fll_div, freq_in, freq_out);
1060 if (ret < 0)
1061 return ret;
1062 dev_dbg(wm8350->dev,
449bd54d 1063 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
40aa4a30
MB		 1064 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1065 fll_div.ratio);
1066
1067 /* set up N.K & dividers */
1068 fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) &
1069 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1070 wm8350_codec_write(codec, WM8350_FLL_CONTROL_1,
1071 fll_1 | (fll_div.div << 8) | 0x50);
1072 wm8350_codec_write(codec, WM8350_FLL_CONTROL_2,
1073 (fll_div.ratio << 11) | (fll_div.
1074 n & WM8350_FLL_N_MASK));
1075 wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1076 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
1077 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1078 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4,
1079 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1080 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1081
1082 /* power FLL on */
1083 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1084 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1085
f1e887de
MB		 1086 priv->fll_freq_out = freq_out;
1087 priv->fll_freq_in = freq_in;
1088
40aa4a30
MB		 1089 return 0;
1090}
1091
1092static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1093 enum snd_soc_bias_level level)
1094{
1095 struct wm8350 *wm8350 = codec->control_data;
b2c812e2 1096 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 1097 struct wm8350_audio_platform_data *platform =
1098 wm8350->codec.platform_data;
1099 u16 pm1;
1100 int ret;
1101
1102 switch (level) {
1103 case SND_SOC_BIAS_ON:
1104 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1105 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1106 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1107 pm1 | WM8350_VMID_50K |
1108 platform->codec_current_on << 14);
1109 break;
1110
1111 case SND_SOC_BIAS_PREPARE:
1112 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1113 pm1 &= ~WM8350_VMID_MASK;
1114 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1115 pm1 | WM8350_VMID_50K);
1116 break;
1117
1118 case SND_SOC_BIAS_STANDBY:
ce6120cc 1119 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
40aa4a30
MB		 1120 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1121 priv->supplies);
1122 if (ret != 0)
1123 return ret;
1124
1125 /* Enable the system clock */
1126 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1127 WM8350_SYSCLK_ENA);
1128
1129 /* mute DAC & outputs */
1130 wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1131 WM8350_DAC_MUTE_ENA);
1132
1133 /* discharge cap memory */
1134 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1135 platform->dis_out1 |
1136 (platform->dis_out2 << 2) |
1137 (platform->dis_out3 << 4) |
1138 (platform->dis_out4 << 6));
1139
1140 /* wait for discharge */
1141 schedule_timeout_interruptible(msecs_to_jiffies
1142 (platform->
1143 cap_discharge_msecs));
1144
1145 /* enable antipop */
1146 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1147 (platform->vmid_s_curve << 8));
1148
1149 /* ramp up vmid */
1150 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1151 (platform->
1152 codec_current_charge << 14) |
1153 WM8350_VMID_5K | WM8350_VMIDEN |
1154 WM8350_VBUFEN);
1155
1156 /* wait for vmid */
1157 schedule_timeout_interruptible(msecs_to_jiffies
1158 (platform->
1159 vmid_charge_msecs));
1160
1161 /* turn on vmid 300k */
1162 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1163 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1164 pm1 |= WM8350_VMID_300K |
1165 (platform->codec_current_standby << 14);
1166 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1167 pm1);
1168
1169
1170 /* enable analogue bias */
1171 pm1 |= WM8350_BIASEN;
1172 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1173
1174 /* disable antipop */
1175 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1176
1177 } else {
1178 /* turn on vmid 300k and reduce current */
1179 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1180 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1181 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1182 pm1 | WM8350_VMID_300K |
1183 (platform->
1184 codec_current_standby << 14));
1185
1186 }
1187 break;
1188
1189 case SND_SOC_BIAS_OFF:
1190
1191 /* mute DAC & enable outputs */
1192 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1193
1194 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1195 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1196 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1197
1198 /* enable anti pop S curve */
1199 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1200 (platform->vmid_s_curve << 8));
1201
1202 /* turn off vmid */
1203 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1204 ~WM8350_VMIDEN;
1205 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1206
1207 /* wait */
1208 schedule_timeout_interruptible(msecs_to_jiffies
1209 (platform->
1210 vmid_discharge_msecs));
1211
1212 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1213 (platform->vmid_s_curve << 8) |
1214 platform->dis_out1 |
1215 (platform->dis_out2 << 2) |
1216 (platform->dis_out3 << 4) |
1217 (platform->dis_out4 << 6));
1218
1219 /* turn off VBuf and drain */
1220 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1221 ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1222 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1223 pm1 | WM8350_OUTPUT_DRAIN_EN);
1224
1225 /* wait */
1226 schedule_timeout_interruptible(msecs_to_jiffies
1227 (platform->drain_msecs));
1228
1229 pm1 &= ~WM8350_BIASEN;
1230 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1231
1232 /* disable anti-pop */
1233 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1234
1235 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1236 WM8350_OUT1L_ENA);
1237 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1238 WM8350_OUT1R_ENA);
1239 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1240 WM8350_OUT2L_ENA);
1241 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1242 WM8350_OUT2R_ENA);
1243
1244 /* disable clock gen */
1245 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1246 WM8350_SYSCLK_ENA);
1247
1248 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1249 priv->supplies);
1250 break;
1251 }
ce6120cc 1252 codec->dapm.bias_level = level;
40aa4a30
MB		 1253 return 0;
1254}
1255
84b315ee 1256static int wm8350_suspend(struct snd_soc_codec *codec)
40aa4a30 1257{
40aa4a30
MB		 1258 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1259 return 0;
1260}
1261
f0fba2ad 1262static int wm8350_resume(struct snd_soc_codec *codec)
40aa4a30 1263{
40aa4a30
MB		 1264 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1265
40aa4a30
MB		 1266 return 0;
1267}
1268
6d3c26bc
MB		 1269static void wm8350_hp_work(struct wm8350_data *priv,
1270 struct wm8350_jack_data *jack,
1271 u16 mask)
a6ba2b2d 1272{
5a65edbc 1273 struct wm8350 *wm8350 = priv->codec.control_data;
a6ba2b2d
MB		 1274 u16 reg;
1275 int report;
6d3c26bc
MB		 1276
1277 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1278 if (reg & mask)
1279 report = jack->report;
1280 else
1281 report = 0;
1282
1283 snd_soc_jack_report(jack->jack, report, jack->report);
1284
1285}
1286
1287static void wm8350_hpl_work(struct work_struct *work)
1288{
1289 struct wm8350_data *priv =
1290 container_of(work, struct wm8350_data, hpl.work.work);
1291
1292 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1293}
1294
1295static void wm8350_hpr_work(struct work_struct *work)
1296{
1297 struct wm8350_data *priv =
1298 container_of(work, struct wm8350_data, hpr.work.work);
1299
1300 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1301}
1302
1303static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
1304{
1305 struct wm8350_data *priv = data;
1306 struct wm8350 *wm8350 = priv->codec.control_data;
a6ba2b2d
MB		 1307 struct wm8350_jack_data *jack = NULL;
1308
59f25070 1309 switch (irq - wm8350->irq_base) {
a6ba2b2d 1310 case WM8350_IRQ_CODEC_JCK_DET_L:
1435b940 1311#ifndef CONFIG_SND_SOC_WM8350_MODULE
2bbb5d66 1312 trace_snd_soc_jack_irq("WM8350 HPL");
1435b940 1313#endif
a6ba2b2d 1314 jack = &priv->hpl;
a6ba2b2d
MB		 1315 break;
1316
1317 case WM8350_IRQ_CODEC_JCK_DET_R:
1435b940 1318#ifndef CONFIG_SND_SOC_WM8350_MODULE
2bbb5d66 1319 trace_snd_soc_jack_irq("WM8350 HPR");
1435b940 1320#endif
a6ba2b2d 1321 jack = &priv->hpr;
a6ba2b2d
MB		 1322 break;
1323
1324 default:
1325 BUG();
1326 }
1327
6d3c26bc
MB		 1328 if (device_may_wakeup(wm8350->dev))
1329 pm_wakeup_event(wm8350->dev, 250);
a6ba2b2d 1330
6d3c26bc 1331 schedule_delayed_work(&jack->work, 200);
5a65edbc
MB		 1332
1333 return IRQ_HANDLED;
a6ba2b2d
MB		 1334}
1335
1336/**
1337 * wm8350_hp_jack_detect - Enable headphone jack detection.
1338 *
1339 * @codec: WM8350 codec
1340 * @which: left or right jack detect signal
1341 * @jack: jack to report detection events on
1342 * @report: value to report
1343 *
f06bce9c
MB		 1344 * Enables the headphone jack detection of the WM8350. If no report
1345 * is specified then detection is disabled.
a6ba2b2d
MB		 1346 */
1347int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1348 struct snd_soc_jack *jack, int report)
1349{
b2c812e2 1350 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
a6ba2b2d
MB		 1351 struct wm8350 *wm8350 = codec->control_data;
1352 int irq;
1353 int ena;
1354
1355 switch (which) {
1356 case WM8350_JDL:
1357 priv->hpl.jack = jack;
1358 priv->hpl.report = report;
1359 irq = WM8350_IRQ_CODEC_JCK_DET_L;
1360 ena = WM8350_JDL_ENA;
1361 break;
1362
1363 case WM8350_JDR:
1364 priv->hpr.jack = jack;
1365 priv->hpr.report = report;
1366 irq = WM8350_IRQ_CODEC_JCK_DET_R;
1367 ena = WM8350_JDR_ENA;
1368 break;
1369
1370 default:
1371 return -EINVAL;
1372 }
1373
f06bce9c
MB		 1374 if (report) {
1375 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1376 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1377 } else {
1378 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1379 }
a6ba2b2d
MB		 1380
1381 /* Sync status */
59f25070 1382 wm8350_hp_jack_handler(irq + wm8350->irq_base, priv);
a6ba2b2d 1383
a6ba2b2d
MB		 1384 return 0;
1385}
1386EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1387
2a0761a3
MB		 1388static irqreturn_t wm8350_mic_handler(int irq, void *data)
1389{
1390 struct wm8350_data *priv = data;
1391 struct wm8350 *wm8350 = priv->codec.control_data;
1392 u16 reg;
1393 int report = 0;
1394
7116f452 1395#ifndef CONFIG_SND_SOC_WM8350_MODULE
2bbb5d66 1396 trace_snd_soc_jack_irq("WM8350 mic");
7116f452 1397#endif
2bbb5d66 1398
2a0761a3
MB		 1399 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1400 if (reg & WM8350_JACK_MICSCD_LVL)
1401 report |= priv->mic.short_report;
1402 if (reg & WM8350_JACK_MICSD_LVL)
1403 report |= priv->mic.report;
1404
1405 snd_soc_jack_report(priv->mic.jack, report,
1406 priv->mic.report | priv->mic.short_report);
1407
1408 return IRQ_HANDLED;
1409}
1410
1411/**
1412 * wm8350_mic_jack_detect - Enable microphone jack detection.
1413 *
1414 * @codec: WM8350 codec
1415 * @jack: jack to report detection events on
1416 * @detect_report: value to report when presence detected
1417 * @short_report: value to report when microphone short detected
1418 *
f06bce9c
MB		 1419 * Enables the microphone jack detection of the WM8350. If both reports
1420 * are specified as zero then detection is disabled.
2a0761a3
MB		 1421 */
1422int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1423 struct snd_soc_jack *jack,
1424 int detect_report, int short_report)
1425{
b2c812e2 1426 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
2a0761a3
MB		 1427 struct wm8350 *wm8350 = codec->control_data;
1428
1429 priv->mic.jack = jack;
1430 priv->mic.report = detect_report;
1431 priv->mic.short_report = short_report;
1432
f06bce9c
MB		 1433 if (detect_report || short_report) {
1434 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1435 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1436 WM8350_MIC_DET_ENA);
1437 } else {
1438 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1439 WM8350_MIC_DET_ENA);
1440 }
2a0761a3 1441
2a0761a3
MB		 1442 return 0;
1443}
1444EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1445
f0fba2ad
LG		 1446#define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1447
1448#define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1449 SNDRV_PCM_FMTBIT_S20_3LE |\
1450 SNDRV_PCM_FMTBIT_S24_LE)
1451
85e7652d 1452static const struct snd_soc_dai_ops wm8350_dai_ops = {
f0fba2ad
LG		 1453 .hw_params = wm8350_pcm_hw_params,
1454 .digital_mute = wm8350_mute,
f0fba2ad
LG		 1455 .set_fmt = wm8350_set_dai_fmt,
1456 .set_sysclk = wm8350_set_dai_sysclk,
1457 .set_pll = wm8350_set_fll,
1458 .set_clkdiv = wm8350_set_clkdiv,
1459};
1460
1461static struct snd_soc_dai_driver wm8350_dai = {
1462 .name = "wm8350-hifi",
1463 .playback = {
1464 .stream_name = "Playback",
1465 .channels_min = 1,
1466 .channels_max = 2,
1467 .rates = WM8350_RATES,
1468 .formats = WM8350_FORMATS,
1469 },
1470 .capture = {
1471 .stream_name = "Capture",
1472 .channels_min = 1,
1473 .channels_max = 2,
1474 .rates = WM8350_RATES,
1475 .formats = WM8350_FORMATS,
1476 },
1477 .ops = &wm8350_dai_ops,
1478};
40aa4a30 1479
f0fba2ad 1480static int wm8350_codec_probe(struct snd_soc_codec *codec)
40aa4a30 1481{
f0fba2ad 1482 struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
40aa4a30 1483 struct wm8350_data *priv;
40aa4a30
MB		 1484 struct wm8350_output *out1;
1485 struct wm8350_output *out2;
f0fba2ad 1486 int ret, i;
40aa4a30 1487
f0fba2ad
LG		 1488 if (wm8350->codec.platform_data == NULL) {
1489 dev_err(codec->dev, "No audio platform data supplied\n");
1490 return -EINVAL;
1491 }
1492
0d1fe0d4
MB		 1493 priv = devm_kzalloc(codec->dev, sizeof(struct wm8350_data),
1494 GFP_KERNEL);
f0fba2ad
LG		 1495 if (priv == NULL)
1496 return -ENOMEM;
1497 snd_soc_codec_set_drvdata(codec, priv);
1498
1499 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1500 priv->supplies[i].supply = supply_names[i];
1501
1502 ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1503 priv->supplies);
1504 if (ret != 0)
0d1fe0d4 1505 return ret;
f0fba2ad
LG		 1506
1507 wm8350->codec.codec = codec;
1508 codec->control_data = wm8350;
40aa4a30 1509
f0fba2ad
LG		 1510 /* Put the codec into reset if it wasn't already */
1511 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1512
ce6120cc 1513 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work);
6d3c26bc
MB		 1514 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1515 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
40aa4a30
MB		 1516
1517 /* Enable the codec */
1518 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1519
1520 /* Enable robust clocking mode in ADC */
1521 wm8350_codec_write(codec, WM8350_SECURITY, 0xa7);
1522 wm8350_codec_write(codec, 0xde, 0x13);
1523 wm8350_codec_write(codec, WM8350_SECURITY, 0);
1524
1525 /* read OUT1 & OUT2 volumes */
1526 out1 = &priv->out1;
1527 out2 = &priv->out2;
1528 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1529 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1530 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1531 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1532 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1533 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1534 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1535 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1536 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1537 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1538 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1539 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1540
1541 /* Latch VU bits & mute */
1542 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1543 WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1544 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1545 WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1546 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1547 WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1548 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1549 WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1550
0049317e
MB		 1551 /* Make sure AIF tristating is disabled by default */
1552 wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1553
1554 /* Make sure we've got a sane companding setup too */
1555 wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1556 WM8350_DAC_COMP | WM8350_LOOPBACK);
1557
6a612746
MB		 1558 /* Make sure jack detect is disabled to start off with */
1559 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1560 WM8350_JDL_ENA | WM8350_JDR_ENA);
1561
a6ba2b2d 1562 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
5a65edbc
MB		 1563 wm8350_hp_jack_handler, 0, "Left jack detect",
1564 priv);
a6ba2b2d 1565 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
5a65edbc
MB		 1566 wm8350_hp_jack_handler, 0, "Right jack detect",
1567 priv);
2a0761a3
MB		 1568 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1569 wm8350_mic_handler, 0, "Microphone short", priv);
1570 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1571 wm8350_mic_handler, 0, "Microphone detect", priv);
a6ba2b2d 1572
40aa4a30 1573
40aa4a30
MB		 1574 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1575
40aa4a30 1576 return 0;
40aa4a30
MB		 1577}
1578
f0fba2ad 1579static int wm8350_codec_remove(struct snd_soc_codec *codec)
40aa4a30 1580{
b2c812e2 1581 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
f0fba2ad 1582 struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
40aa4a30 1583
a6ba2b2d
MB		 1584 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1585 WM8350_JDL_ENA | WM8350_JDR_ENA);
1586 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1587
2a0761a3
MB		 1588 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1589 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
f99344fc
MB		 1590 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1591 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
a6ba2b2d
MB		 1592
1593 priv->hpl.jack = NULL;
1594 priv->hpr.jack = NULL;
2a0761a3 1595 priv->mic.jack = NULL;
a6ba2b2d 1596
6d3c26bc
MB		 1597 cancel_delayed_work_sync(&priv->hpl.work);
1598 cancel_delayed_work_sync(&priv->hpr.work);
1599
40aa4a30
MB		 1600 /* if there was any work waiting then we run it now and
1601 * wait for its completion */
fdea0571 1602 flush_delayed_work_sync(&codec->dapm.delayed_work);
40aa4a30
MB		 1603
1604 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1605
1606 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1607
f0fba2ad 1608 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
0d1fe0d4 1609
40aa4a30
MB		 1610 return 0;
1611}
1612
f0fba2ad
LG		 1613static struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
1614 .probe = wm8350_codec_probe,
1615 .remove = wm8350_codec_remove,
40aa4a30
MB		 1616 .suspend = wm8350_suspend,
1617 .resume = wm8350_resume,
f0fba2ad
LG		 1618 .read = wm8350_codec_read,
1619 .write = wm8350_codec_write,
1620 .set_bias_level = wm8350_set_bias_level,
e6c94e9f
MB		 1621
1622 .controls = wm8350_snd_controls,
1623 .num_controls = ARRAY_SIZE(wm8350_snd_controls),
1624 .dapm_widgets = wm8350_dapm_widgets,
1625 .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets),
1626 .dapm_routes = wm8350_dapm_routes,
1627 .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes),
40aa4a30 1628};
40aa4a30 1629
f0fba2ad 1630static int __devinit wm8350_probe(struct platform_device *pdev)
40aa4a30 1631{
f0fba2ad
LG		 1632 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350,
1633 &wm8350_dai, 1);
40aa4a30
MB		 1634}
1635
f0fba2ad 1636static int __devexit wm8350_remove(struct platform_device *pdev)
40aa4a30 1637{
f0fba2ad 1638 snd_soc_unregister_codec(&pdev->dev);
40aa4a30
MB		 1639 return 0;
1640}
1641
1642static struct platform_driver wm8350_codec_driver = {
1643 .driver = {
1644 .name = "wm8350-codec",
1645 .owner = THIS_MODULE,
1646 },
f0fba2ad
LG		 1647 .probe = wm8350_probe,
1648 .remove = __devexit_p(wm8350_remove),
40aa4a30
MB		 1649};
1650
5bbcc3c0 1651module_platform_driver(wm8350_codec_driver);
40aa4a30
MB		 1652
1653MODULE_DESCRIPTION("ASoC WM8350 driver");
1654MODULE_AUTHOR("Liam Girdwood");
1655MODULE_LICENSE("GPL");
1656MODULE_ALIAS("platform:wm8350-codec");
Linux kernel - Deliverables
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