projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: uda1380: Replace TLV_DB_RANGE_HEAD with DECLARE_TLV_DB_RANGE
[deliverable/linux.git] / sound / soc / codecs / wm8350.c
CommitLineData
40aa4a30
MB		 1/*
2 * wm8350.c -- WM8350 ALSA SoC audio driver
3 *
656baaeb 4 * Copyright (C) 2007-12 Wolfson Microelectronics PLC.
40aa4a30 5 *
64ca0404 6 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
40aa4a30
MB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
5a0e3ad6 16#include <linux/slab.h>
40aa4a30
MB		 17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/platform_device.h>
20#include <linux/mfd/wm8350/audio.h>
21#include <linux/mfd/wm8350/core.h>
22#include <linux/regulator/consumer.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
40aa4a30
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
2bbb5d66 29#include <trace/events/asoc.h>
40aa4a30
MB		 30
31#include "wm8350.h"
32
33#define WM8350_OUTn_0dB 0x39
34
35#define WM8350_RAMP_NONE 0
36#define WM8350_RAMP_UP 1
37#define WM8350_RAMP_DOWN 2
38
39/* We only include the analogue supplies here; the digital supplies
40 * need to be available well before this driver can be probed.
41 */
42static const char *supply_names[] = {
43 "AVDD",
44 "HPVDD",
45};
46
47struct wm8350_output {
48 u16 active;
49 u16 left_vol;
50 u16 right_vol;
51 u16 ramp;
52 u16 mute;
53};
54
a6ba2b2d
MB		 55struct wm8350_jack_data {
56 struct snd_soc_jack *jack;
6d3c26bc 57 struct delayed_work work;
a6ba2b2d 58 int report;
2a0761a3 59 int short_report;
a6ba2b2d
MB		 60};
61
40aa4a30 62struct wm8350_data {
30facd4d 63 struct wm8350 *wm8350;
40aa4a30
MB		 64 struct wm8350_output out1;
65 struct wm8350_output out2;
a6ba2b2d
MB		 66 struct wm8350_jack_data hpl;
67 struct wm8350_jack_data hpr;
2a0761a3 68 struct wm8350_jack_data mic;
40aa4a30 69 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
f1e887de
MB		 70 int fll_freq_out;
71 int fll_freq_in;
cd5d8226 72 struct delayed_work pga_work;
40aa4a30
MB		 73};
74
40aa4a30
MB		 75/*
76 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
77 */
cd5d8226 78static inline int wm8350_out1_ramp_step(struct wm8350_data *wm8350_data)
40aa4a30 79{
40aa4a30 80 struct wm8350_output *out1 = &wm8350_data->out1;
018a455a 81 struct wm8350 *wm8350 = wm8350_data->wm8350;
40aa4a30
MB		 82 int left_complete = 0, right_complete = 0;
83 u16 reg, val;
84
85 /* left channel */
86 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
87 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
88
89 if (out1->ramp == WM8350_RAMP_UP) {
90 /* ramp step up */
91 if (val < out1->left_vol) {
92 val++;
93 reg &= ~WM8350_OUT1L_VOL_MASK;
94 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
95 reg | (val << WM8350_OUT1L_VOL_SHIFT));
96 } else
97 left_complete = 1;
98 } else if (out1->ramp == WM8350_RAMP_DOWN) {
99 /* ramp step down */
100 if (val > 0) {
101 val--;
102 reg &= ~WM8350_OUT1L_VOL_MASK;
103 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
104 reg | (val << WM8350_OUT1L_VOL_SHIFT));
105 } else
106 left_complete = 1;
107 } else
108 return 1;
109
110 /* right channel */
111 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
112 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
113 if (out1->ramp == WM8350_RAMP_UP) {
114 /* ramp step up */
115 if (val < out1->right_vol) {
116 val++;
117 reg &= ~WM8350_OUT1R_VOL_MASK;
118 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
119 reg | (val << WM8350_OUT1R_VOL_SHIFT));
120 } else
121 right_complete = 1;
122 } else if (out1->ramp == WM8350_RAMP_DOWN) {
123 /* ramp step down */
124 if (val > 0) {
125 val--;
126 reg &= ~WM8350_OUT1R_VOL_MASK;
127 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
128 reg | (val << WM8350_OUT1R_VOL_SHIFT));
129 } else
130 right_complete = 1;
131 }
132
133 /* only hit the update bit if either volume has changed this step */
134 if (!left_complete || !right_complete)
135 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
136
137 return left_complete & right_complete;
138}
139
140/*
141 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
142 */
cd5d8226 143static inline int wm8350_out2_ramp_step(struct wm8350_data *wm8350_data)
40aa4a30 144{
40aa4a30 145 struct wm8350_output *out2 = &wm8350_data->out2;
018a455a 146 struct wm8350 *wm8350 = wm8350_data->wm8350;
40aa4a30
MB		 147 int left_complete = 0, right_complete = 0;
148 u16 reg, val;
149
150 /* left channel */
151 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
152 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
153 if (out2->ramp == WM8350_RAMP_UP) {
154 /* ramp step up */
155 if (val < out2->left_vol) {
156 val++;
157 reg &= ~WM8350_OUT2L_VOL_MASK;
158 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
159 reg | (val << WM8350_OUT1L_VOL_SHIFT));
160 } else
161 left_complete = 1;
162 } else if (out2->ramp == WM8350_RAMP_DOWN) {
163 /* ramp step down */
164 if (val > 0) {
165 val--;
166 reg &= ~WM8350_OUT2L_VOL_MASK;
167 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
168 reg | (val << WM8350_OUT1L_VOL_SHIFT));
169 } else
170 left_complete = 1;
171 } else
172 return 1;
173
174 /* right channel */
175 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
176 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
177 if (out2->ramp == WM8350_RAMP_UP) {
178 /* ramp step up */
179 if (val < out2->right_vol) {
180 val++;
181 reg &= ~WM8350_OUT2R_VOL_MASK;
182 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
183 reg | (val << WM8350_OUT1R_VOL_SHIFT));
184 } else
185 right_complete = 1;
186 } else if (out2->ramp == WM8350_RAMP_DOWN) {
187 /* ramp step down */
188 if (val > 0) {
189 val--;
190 reg &= ~WM8350_OUT2R_VOL_MASK;
191 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
192 reg | (val << WM8350_OUT1R_VOL_SHIFT));
193 } else
194 right_complete = 1;
195 }
196
197 /* only hit the update bit if either volume has changed this step */
198 if (!left_complete || !right_complete)
199 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
200
201 return left_complete & right_complete;
202}
203
204/*
205 * This work ramps both output PGAs at stream start/stop time to
206 * minimise pop associated with DAPM power switching.
207 * It's best to enable Zero Cross when ramping occurs to minimise any
208 * zipper noises.
209 */
210static void wm8350_pga_work(struct work_struct *work)
211{
cd5d8226
LPC		 212 struct wm8350_data *wm8350_data =
213 container_of(work, struct wm8350_data, pga_work.work);
40aa4a30
MB		 214 struct wm8350_output *out1 = &wm8350_data->out1,
215 *out2 = &wm8350_data->out2;
216 int i, out1_complete, out2_complete;
217
218 /* do we need to ramp at all ? */
219 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
220 return;
221
222 /* PGA volumes have 6 bits of resolution to ramp */
223 for (i = 0; i <= 63; i++) {
224 out1_complete = 1, out2_complete = 1;
225 if (out1->ramp != WM8350_RAMP_NONE)
cd5d8226 226 out1_complete = wm8350_out1_ramp_step(wm8350_data);
40aa4a30 227 if (out2->ramp != WM8350_RAMP_NONE)
cd5d8226 228 out2_complete = wm8350_out2_ramp_step(wm8350_data);
40aa4a30
MB		 229
230 /* ramp finished ? */
231 if (out1_complete && out2_complete)
232 break;
233
234 /* we need to delay longer on the up ramp */
235 if (out1->ramp == WM8350_RAMP_UP ||
236 out2->ramp == WM8350_RAMP_UP) {
237 /* delay is longer over 0dB as increases are larger */
238 if (i >= WM8350_OUTn_0dB)
239 schedule_timeout_interruptible(msecs_to_jiffies
240 (2));
241 else
242 schedule_timeout_interruptible(msecs_to_jiffies
243 (1));
244 } else
245 udelay(50); /* doesn't matter if we delay longer */
246 }
247
248 out1->ramp = WM8350_RAMP_NONE;
249 out2->ramp = WM8350_RAMP_NONE;
250}
251
252/*
253 * WM8350 Controls
254 */
255
256static int pga_event(struct snd_soc_dapm_widget *w,
257 struct snd_kcontrol *kcontrol, int event)
258{
83f132c5 259 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
b2c812e2 260 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 261 struct wm8350_output *out;
262
263 switch (w->shift) {
264 case 0:
265 case 1:
266 out = &wm8350_data->out1;
267 break;
268 case 2:
269 case 3:
270 out = &wm8350_data->out2;
271 break;
272
273 default:
a361f452 274 WARN(1, "Invalid shift %d\n", w->shift);
40aa4a30
MB		 275 return -1;
276 }
277
278 switch (event) {
279 case SND_SOC_DAPM_POST_PMU:
280 out->ramp = WM8350_RAMP_UP;
281 out->active = 1;
282
cd5d8226 283 schedule_delayed_work(&wm8350_data->pga_work,
8a47ca95 284 msecs_to_jiffies(1));
40aa4a30
MB		 285 break;
286
287 case SND_SOC_DAPM_PRE_PMD:
288 out->ramp = WM8350_RAMP_DOWN;
289 out->active = 0;
290
cd5d8226 291 schedule_delayed_work(&wm8350_data->pga_work,
8a47ca95 292 msecs_to_jiffies(1));
40aa4a30
MB		 293 break;
294 }
295
296 return 0;
297}
298
299static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
300 struct snd_ctl_elem_value *ucontrol)
301{
ea53bf77 302 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b2c812e2 303 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 304 struct wm8350_output *out = NULL;
305 struct soc_mixer_control *mc =
306 (struct soc_mixer_control *)kcontrol->private_value;
307 int ret;
308 unsigned int reg = mc->reg;
309 u16 val;
310
311 /* For OUT1 and OUT2 we shadow the values and only actually write
312 * them out when active in order to ensure the amplifier comes on
313 * as quietly as possible. */
314 switch (reg) {
315 case WM8350_LOUT1_VOLUME:
316 out = &wm8350_priv->out1;
317 break;
318 case WM8350_LOUT2_VOLUME:
319 out = &wm8350_priv->out2;
320 break;
321 default:
322 break;
323 }
324
325 if (out) {
326 out->left_vol = ucontrol->value.integer.value[0];
327 out->right_vol = ucontrol->value.integer.value[1];
328 if (!out->active)
329 return 1;
330 }
331
c4671a95 332 ret = snd_soc_put_volsw(kcontrol, ucontrol);
40aa4a30
MB		 333 if (ret < 0)
334 return ret;
335
336 /* now hit the volume update bits (always bit 8) */
3a96c77e
MB		 337 val = snd_soc_read(codec, reg);
338 snd_soc_write(codec, reg, val | WM8350_OUT1_VU);
40aa4a30
MB		 339 return 1;
340}
341
342static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
343 struct snd_ctl_elem_value *ucontrol)
344{
ea53bf77 345 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
b2c812e2 346 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 347 struct wm8350_output *out1 = &wm8350_priv->out1;
348 struct wm8350_output *out2 = &wm8350_priv->out2;
349 struct soc_mixer_control *mc =
350 (struct soc_mixer_control *)kcontrol->private_value;
351 unsigned int reg = mc->reg;
352
353 /* If these are cached registers use the cache */
354 switch (reg) {
355 case WM8350_LOUT1_VOLUME:
356 ucontrol->value.integer.value[0] = out1->left_vol;
357 ucontrol->value.integer.value[1] = out1->right_vol;
358 return 0;
359
360 case WM8350_LOUT2_VOLUME:
361 ucontrol->value.integer.value[0] = out2->left_vol;
362 ucontrol->value.integer.value[1] = out2->right_vol;
363 return 0;
364
365 default:
366 break;
367 }
368
c4671a95 369 return snd_soc_get_volsw(kcontrol, ucontrol);
40aa4a30
MB		 370}
371
40aa4a30
MB		 372static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
373static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
374static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
375static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
40aa4a30
MB		 376static const char *wm8350_adcfilter[] = { "None", "High Pass" };
377static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
378static const char *wm8350_lr[] = { "Left", "Right" };
379
380static const struct soc_enum wm8350_enum[] = {
381 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
382 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
383 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
384 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
40aa4a30
MB		 385 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
386 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
387 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
388 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
389};
390
e6a08c5a
MB		 391static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
392static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
40aa4a30
MB		 393static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
394static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
395static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
396
397static const unsigned int capture_sd_tlv[] = {
398 TLV_DB_RANGE_HEAD(2),
399 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
400 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
401};
402
403static const struct snd_kcontrol_new wm8350_snd_controls[] = {
404 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
405 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
0f9887d1 406 SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
40aa4a30
MB		 407 WM8350_DAC_DIGITAL_VOLUME_L,
408 WM8350_DAC_DIGITAL_VOLUME_R,
0f9887d1
PU		 409 0, 255, 0, wm8350_get_volsw_2r,
410 wm8350_put_volsw_2r_vu, dac_pcm_tlv),
40aa4a30
MB		 411 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
412 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
61943999
MB		 413 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
414 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
415 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
0f9887d1 416 SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
40aa4a30
MB		 417 WM8350_ADC_DIGITAL_VOLUME_L,
418 WM8350_ADC_DIGITAL_VOLUME_R,
0f9887d1
PU		 419 0, 255, 0, wm8350_get_volsw_2r,
420 wm8350_put_volsw_2r_vu, adc_pcm_tlv),
40aa4a30
MB		 421 SOC_DOUBLE_TLV("Capture Sidetone Volume",
422 WM8350_ADC_DIVIDER,
423 8, 4, 15, 1, capture_sd_tlv),
0f9887d1 424 SOC_DOUBLE_R_EXT_TLV("Capture Volume",
40aa4a30
MB		 425 WM8350_LEFT_INPUT_VOLUME,
426 WM8350_RIGHT_INPUT_VOLUME,
0f9887d1
PU		 427 2, 63, 0, wm8350_get_volsw_2r,
428 wm8350_put_volsw_2r_vu, pre_amp_tlv),
40aa4a30
MB		 429 SOC_DOUBLE_R("Capture ZC Switch",
430 WM8350_LEFT_INPUT_VOLUME,
431 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
432 SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
433 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
434 SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
435 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
436 5, 7, 0, out_mix_tlv),
437 SOC_SINGLE_TLV("Left Input Bypass Volume",
438 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
439 9, 7, 0, out_mix_tlv),
440 SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
441 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
442 1, 7, 0, out_mix_tlv),
443 SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
444 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
445 5, 7, 0, out_mix_tlv),
446 SOC_SINGLE_TLV("Right Input Bypass Volume",
447 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
448 13, 7, 0, out_mix_tlv),
449 SOC_SINGLE("Left Input Mixer +20dB Switch",
450 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
451 SOC_SINGLE("Right Input Mixer +20dB Switch",
452 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
453 SOC_SINGLE_TLV("Out4 Capture Volume",
454 WM8350_INPUT_MIXER_VOLUME,
455 1, 7, 0, out_mix_tlv),
0f9887d1 456 SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
40aa4a30
MB		 457 WM8350_LOUT1_VOLUME,
458 WM8350_ROUT1_VOLUME,
0f9887d1
PU		 459 2, 63, 0, wm8350_get_volsw_2r,
460 wm8350_put_volsw_2r_vu, out_pga_tlv),
40aa4a30
MB		 461 SOC_DOUBLE_R("Out1 Playback ZC Switch",
462 WM8350_LOUT1_VOLUME,
463 WM8350_ROUT1_VOLUME, 13, 1, 0),
0f9887d1 464 SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
40aa4a30
MB		 465 WM8350_LOUT2_VOLUME,
466 WM8350_ROUT2_VOLUME,
0f9887d1
PU		 467 2, 63, 0, wm8350_get_volsw_2r,
468 wm8350_put_volsw_2r_vu, out_pga_tlv),
40aa4a30
MB		 469 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
470 WM8350_ROUT2_VOLUME, 13, 1, 0),
471 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
472 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
473 5, 7, 0, out_mix_tlv),
474
475 SOC_DOUBLE_R("Out1 Playback Switch",
476 WM8350_LOUT1_VOLUME,
477 WM8350_ROUT1_VOLUME,
478 14, 1, 1),
479 SOC_DOUBLE_R("Out2 Playback Switch",
480 WM8350_LOUT2_VOLUME,
481 WM8350_ROUT2_VOLUME,
482 14, 1, 1),
483};
484
485/*
486 * DAPM Controls
487 */
488
489/* Left Playback Mixer */
490static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
491 SOC_DAPM_SINGLE("Playback Switch",
492 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
493 SOC_DAPM_SINGLE("Left Bypass Switch",
494 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
495 SOC_DAPM_SINGLE("Right Playback Switch",
496 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
497 SOC_DAPM_SINGLE("Left Sidetone Switch",
498 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
499 SOC_DAPM_SINGLE("Right Sidetone Switch",
500 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
501};
502
503/* Right Playback Mixer */
504static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
505 SOC_DAPM_SINGLE("Playback Switch",
506 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
507 SOC_DAPM_SINGLE("Right Bypass Switch",
508 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
509 SOC_DAPM_SINGLE("Left Playback Switch",
510 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
511 SOC_DAPM_SINGLE("Left Sidetone Switch",
512 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
513 SOC_DAPM_SINGLE("Right Sidetone Switch",
514 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
515};
516
517/* Out4 Mixer */
518static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
519 SOC_DAPM_SINGLE("Right Playback Switch",
520 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
521 SOC_DAPM_SINGLE("Left Playback Switch",
522 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
523 SOC_DAPM_SINGLE("Right Capture Switch",
524 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
525 SOC_DAPM_SINGLE("Out3 Playback Switch",
526 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
527 SOC_DAPM_SINGLE("Right Mixer Switch",
528 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
529 SOC_DAPM_SINGLE("Left Mixer Switch",
530 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
531};
532
533/* Out3 Mixer */
534static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
535 SOC_DAPM_SINGLE("Left Playback Switch",
536 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
537 SOC_DAPM_SINGLE("Left Capture Switch",
538 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
539 SOC_DAPM_SINGLE("Out4 Playback Switch",
540 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
541 SOC_DAPM_SINGLE("Left Mixer Switch",
542 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
543};
544
545/* Left Input Mixer */
546static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
547 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
548 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
549 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
550 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
551 SOC_DAPM_SINGLE("PGA Capture Switch",
5b7dde34 552 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
40aa4a30
MB		 553};
554
555/* Right Input Mixer */
556static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
557 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
558 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
559 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
560 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
561 SOC_DAPM_SINGLE("PGA Capture Switch",
5b7dde34 562 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
40aa4a30
MB		 563};
564
565/* Left Mic Mixer */
566static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
567 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
568 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
569 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
570};
571
572/* Right Mic Mixer */
573static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
574 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
575 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
576 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
577};
578
579/* Beep Switch */
580static const struct snd_kcontrol_new wm8350_beep_switch_controls =
581SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
582
583/* Out4 Capture Mux */
584static const struct snd_kcontrol_new wm8350_out4_capture_controls =
87831cb6 585SOC_DAPM_ENUM("Route", wm8350_enum[7]);
40aa4a30
MB		 586
587static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
588
589 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
590 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
591 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
592 0, pga_event,
593 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
594 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
595 pga_event,
596 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
597 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
598 0, pga_event,
599 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
600 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
601 pga_event,
602 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
603
604 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
605 7, 0, &wm8350_right_capt_mixer_controls[0],
606 ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
607
608 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
609 6, 0, &wm8350_left_capt_mixer_controls[0],
610 ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
611
612 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
613 &wm8350_out4_mixer_controls[0],
614 ARRAY_SIZE(wm8350_out4_mixer_controls)),
615
616 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
617 &wm8350_out3_mixer_controls[0],
618 ARRAY_SIZE(wm8350_out3_mixer_controls)),
619
620 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
621 &wm8350_right_play_mixer_controls[0],
622 ARRAY_SIZE(wm8350_right_play_mixer_controls)),
623
624 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
625 &wm8350_left_play_mixer_controls[0],
626 ARRAY_SIZE(wm8350_left_play_mixer_controls)),
627
628 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
629 &wm8350_left_mic_mixer_controls[0],
630 ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
631
632 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
633 &wm8350_right_mic_mixer_controls[0],
634 ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
635
636 /* virtual mixer for Beep and Out2R */
637 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
638
639 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
640 &wm8350_beep_switch_controls),
641
642 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
643 WM8350_POWER_MGMT_4, 3, 0),
644 SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
645 WM8350_POWER_MGMT_4, 2, 0),
646 SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
647 WM8350_POWER_MGMT_4, 5, 0),
648 SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
649 WM8350_POWER_MGMT_4, 4, 0),
650
651 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
652
653 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
654 &wm8350_out4_capture_controls),
655
656 SND_SOC_DAPM_OUTPUT("OUT1R"),
657 SND_SOC_DAPM_OUTPUT("OUT1L"),
658 SND_SOC_DAPM_OUTPUT("OUT2R"),
659 SND_SOC_DAPM_OUTPUT("OUT2L"),
660 SND_SOC_DAPM_OUTPUT("OUT3"),
661 SND_SOC_DAPM_OUTPUT("OUT4"),
662
663 SND_SOC_DAPM_INPUT("IN1RN"),
664 SND_SOC_DAPM_INPUT("IN1RP"),
665 SND_SOC_DAPM_INPUT("IN2R"),
666 SND_SOC_DAPM_INPUT("IN1LP"),
667 SND_SOC_DAPM_INPUT("IN1LN"),
668 SND_SOC_DAPM_INPUT("IN2L"),
669 SND_SOC_DAPM_INPUT("IN3R"),
670 SND_SOC_DAPM_INPUT("IN3L"),
671};
672
e6c94e9f 673static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
40aa4a30
MB		 674
675 /* left playback mixer */
676 {"Left Playback Mixer", "Playback Switch", "Left DAC"},
677 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
678 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
679 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
680 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
681
682 /* right playback mixer */
683 {"Right Playback Mixer", "Playback Switch", "Right DAC"},
684 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
685 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
686 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
687 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
688
689 /* out4 playback mixer */
690 {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
691 {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
692 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
693 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
694 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
695 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
696 {"OUT4", NULL, "Out4 Mixer"},
697
698 /* out3 playback mixer */
699 {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
700 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
701 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
702 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
703 {"OUT3", NULL, "Out3 Mixer"},
704
705 /* out2 */
706 {"Right Out2 PGA", NULL, "Right Playback Mixer"},
707 {"Left Out2 PGA", NULL, "Left Playback Mixer"},
708 {"OUT2L", NULL, "Left Out2 PGA"},
709 {"OUT2R", NULL, "Right Out2 PGA"},
710
711 /* out1 */
712 {"Right Out1 PGA", NULL, "Right Playback Mixer"},
713 {"Left Out1 PGA", NULL, "Left Playback Mixer"},
714 {"OUT1L", NULL, "Left Out1 PGA"},
715 {"OUT1R", NULL, "Right Out1 PGA"},
716
717 /* ADCs */
718 {"Left ADC", NULL, "Left Capture Mixer"},
719 {"Right ADC", NULL, "Right Capture Mixer"},
720
721 /* Left capture mixer */
722 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
723 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
724 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
725 {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
726
727 /* Right capture mixer */
728 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
729 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
730 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
731 {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
732
733 /* L3 Inputs */
734 {"IN3L PGA", NULL, "IN3L"},
735 {"IN3R PGA", NULL, "IN3R"},
736
737 /* Left Mic mixer */
738 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
739 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
740 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
741
742 /* Right Mic mixer */
743 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
744 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
745 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
746
747 /* out 4 capture */
748 {"Out4 Capture Channel", NULL, "Out4 Mixer"},
749
750 /* Beep */
751 {"Beep", NULL, "IN3R PGA"},
752};
753
40aa4a30
MB		 754static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
755 int clk_id, unsigned int freq, int dir)
756{
757 struct snd_soc_codec *codec = codec_dai->codec;
018a455a
MB		 758 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
759 struct wm8350 *wm8350 = wm8350_data->wm8350;
40aa4a30
MB		 760 u16 fll_4;
761
762 switch (clk_id) {
763 case WM8350_MCLK_SEL_MCLK:
764 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
765 WM8350_MCLK_SEL);
766 break;
767 case WM8350_MCLK_SEL_PLL_MCLK:
768 case WM8350_MCLK_SEL_PLL_DAC:
769 case WM8350_MCLK_SEL_PLL_ADC:
770 case WM8350_MCLK_SEL_PLL_32K:
771 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
772 WM8350_MCLK_SEL);
3a96c77e 773 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
40aa4a30 774 ~WM8350_FLL_CLK_SRC_MASK;
3a96c77e 775 snd_soc_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
40aa4a30
MB		 776 break;
777 }
778
779 /* MCLK direction */
c28a9926 780 if (dir == SND_SOC_CLOCK_OUT)
40aa4a30
MB		 781 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
782 WM8350_MCLK_DIR);
783 else
784 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
785 WM8350_MCLK_DIR);
786
787 return 0;
788}
789
790static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
791{
792 struct snd_soc_codec *codec = codec_dai->codec;
793 u16 val;
794
795 switch (div_id) {
796 case WM8350_ADC_CLKDIV:
3a96c77e 797 val = snd_soc_read(codec, WM8350_ADC_DIVIDER) &
40aa4a30 798 ~WM8350_ADC_CLKDIV_MASK;
3a96c77e 799 snd_soc_write(codec, WM8350_ADC_DIVIDER, val | div);
40aa4a30
MB		 800 break;
801 case WM8350_DAC_CLKDIV:
3a96c77e 802 val = snd_soc_read(codec, WM8350_DAC_CLOCK_CONTROL) &
40aa4a30 803 ~WM8350_DAC_CLKDIV_MASK;
3a96c77e 804 snd_soc_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
40aa4a30
MB		 805 break;
806 case WM8350_BCLK_CLKDIV:
3a96c77e 807 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
40aa4a30 808 ~WM8350_BCLK_DIV_MASK;
3a96c77e 809 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
40aa4a30
MB		 810 break;
811 case WM8350_OPCLK_CLKDIV:
3a96c77e 812 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
40aa4a30 813 ~WM8350_OPCLK_DIV_MASK;
3a96c77e 814 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
40aa4a30
MB		 815 break;
816 case WM8350_SYS_CLKDIV:
3a96c77e 817 val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
40aa4a30 818 ~WM8350_MCLK_DIV_MASK;
3a96c77e 819 snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
40aa4a30
MB		 820 break;
821 case WM8350_DACLR_CLKDIV:
3a96c77e 822 val = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
40aa4a30 823 ~WM8350_DACLRC_RATE_MASK;
3a96c77e 824 snd_soc_write(codec, WM8350_DAC_LR_RATE, val | div);
40aa4a30
MB		 825 break;
826 case WM8350_ADCLR_CLKDIV:
3a96c77e 827 val = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
40aa4a30 828 ~WM8350_ADCLRC_RATE_MASK;
3a96c77e 829 snd_soc_write(codec, WM8350_ADC_LR_RATE, val | div);
40aa4a30
MB		 830 break;
831 default:
832 return -EINVAL;
833 }
834
835 return 0;
836}
837
838static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
839{
840 struct snd_soc_codec *codec = codec_dai->codec;
3a96c77e 841 u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
40aa4a30 842 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
3a96c77e 843 u16 master = snd_soc_read(codec, WM8350_AI_DAC_CONTROL) &
40aa4a30 844 ~WM8350_BCLK_MSTR;
3a96c77e 845 u16 dac_lrc = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
40aa4a30 846 ~WM8350_DACLRC_ENA;
3a96c77e 847 u16 adc_lrc = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
40aa4a30
MB		 848 ~WM8350_ADCLRC_ENA;
849
850 /* set master/slave audio interface */
851 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
852 case SND_SOC_DAIFMT_CBM_CFM:
853 master |= WM8350_BCLK_MSTR;
854 dac_lrc |= WM8350_DACLRC_ENA;
855 adc_lrc |= WM8350_ADCLRC_ENA;
856 break;
857 case SND_SOC_DAIFMT_CBS_CFS:
858 break;
859 default:
860 return -EINVAL;
861 }
862
863 /* interface format */
864 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
865 case SND_SOC_DAIFMT_I2S:
866 iface |= 0x2 << 8;
867 break;
868 case SND_SOC_DAIFMT_RIGHT_J:
869 break;
870 case SND_SOC_DAIFMT_LEFT_J:
871 iface |= 0x1 << 8;
872 break;
873 case SND_SOC_DAIFMT_DSP_A:
874 iface |= 0x3 << 8;
875 break;
876 case SND_SOC_DAIFMT_DSP_B:
5ee518ec 877 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
40aa4a30
MB		 878 break;
879 default:
880 return -EINVAL;
881 }
882
883 /* clock inversion */
884 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
885 case SND_SOC_DAIFMT_NB_NF:
886 break;
887 case SND_SOC_DAIFMT_IB_IF:
888 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
889 break;
890 case SND_SOC_DAIFMT_IB_NF:
891 iface |= WM8350_AIF_BCLK_INV;
892 break;
893 case SND_SOC_DAIFMT_NB_IF:
894 iface |= WM8350_AIF_LRCLK_INV;
895 break;
896 default:
897 return -EINVAL;
898 }
899
3a96c77e
MB		 900 snd_soc_write(codec, WM8350_AI_FORMATING, iface);
901 snd_soc_write(codec, WM8350_AI_DAC_CONTROL, master);
902 snd_soc_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
903 snd_soc_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
40aa4a30
MB		 904 return 0;
905}
906
40aa4a30
MB		 907static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
908 struct snd_pcm_hw_params *params,
909 struct snd_soc_dai *codec_dai)
910{
911 struct snd_soc_codec *codec = codec_dai->codec;
018a455a
MB		 912 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
913 struct wm8350 *wm8350 = wm8350_data->wm8350;
3a96c77e 914 u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
40aa4a30
MB		 915 ~WM8350_AIF_WL_MASK;
916
917 /* bit size */
1e6453ac
MB		 918 switch (params_width(params)) {
919 case 16:
40aa4a30 920 break;
1e6453ac 921 case 20:
40aa4a30
MB		 922 iface |= 0x1 << 10;
923 break;
1e6453ac 924 case 24:
40aa4a30
MB		 925 iface |= 0x2 << 10;
926 break;
1e6453ac 927 case 32:
40aa4a30
MB		 928 iface |= 0x3 << 10;
929 break;
930 }
931
3a96c77e 932 snd_soc_write(codec, WM8350_AI_FORMATING, iface);
61943999
MB		 933
934 /* The sloping stopband filter is recommended for use with
935 * lower sample rates to improve performance.
936 */
937 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
938 if (params_rate(params) < 24000)
939 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
940 WM8350_DAC_SB_FILT);
941 else
942 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
943 WM8350_DAC_SB_FILT);
944 }
945
40aa4a30
MB		 946 return 0;
947}
948
949static int wm8350_mute(struct snd_soc_dai *dai, int mute)
950{
951 struct snd_soc_codec *codec = dai->codec;
018a455a 952 unsigned int val;
40aa4a30
MB		 953
954 if (mute)
018a455a 955 val = WM8350_DAC_MUTE_ENA;
40aa4a30 956 else
018a455a
MB		 957 val = 0;
958
959 snd_soc_update_bits(codec, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
960
40aa4a30
MB		 961 return 0;
962}
963
964/* FLL divisors */
965struct _fll_div {
966 int div; /* FLL_OUTDIV */
967 int n;
968 int k;
969 int ratio; /* FLL_FRATIO */
970};
971
972/* The size in bits of the fll divide multiplied by 10
973 * to allow rounding later */
974#define FIXED_FLL_SIZE ((1 << 16) * 10)
975
976static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
977 unsigned int output)
978{
979 u64 Kpart;
980 unsigned int t1, t2, K, Nmod;
981
982 if (output >= 2815250 && output <= 3125000)
983 fll_div->div = 0x4;
984 else if (output >= 5625000 && output <= 6250000)
985 fll_div->div = 0x3;
986 else if (output >= 11250000 && output <= 12500000)
987 fll_div->div = 0x2;
988 else if (output >= 22500000 && output <= 25000000)
989 fll_div->div = 0x1;
990 else {
991 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
992 return -EINVAL;
993 }
994
995 if (input > 48000)
996 fll_div->ratio = 1;
997 else
998 fll_div->ratio = 8;
999
1000 t1 = output * (1 << (fll_div->div + 1));
1001 t2 = input * fll_div->ratio;
1002
1003 fll_div->n = t1 / t2;
1004 Nmod = t1 % t2;
1005
1006 if (Nmod) {
1007 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1008 do_div(Kpart, t2);
1009 K = Kpart & 0xFFFFFFFF;
1010
1011 /* Check if we need to round */
1012 if ((K % 10) >= 5)
1013 K += 5;
1014
1015 /* Move down to proper range now rounding is done */
1016 K /= 10;
1017 fll_div->k = K;
1018 } else
1019 fll_div->k = 0;
1020
1021 return 0;
1022}
1023
1024static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
85488037 1025 int pll_id, int source, unsigned int freq_in,
40aa4a30
MB		 1026 unsigned int freq_out)
1027{
1028 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1029 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
018a455a 1030 struct wm8350 *wm8350 = priv->wm8350;
40aa4a30
MB		 1031 struct _fll_div fll_div;
1032 int ret = 0;
1033 u16 fll_1, fll_4;
1034
f1e887de
MB		 1035 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1036 return 0;
1037
40aa4a30
MB		 1038 /* power down FLL - we need to do this for reconfiguration */
1039 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1040 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1041
1042 if (freq_out == 0 || freq_in == 0)
1043 return ret;
1044
1045 ret = fll_factors(&fll_div, freq_in, freq_out);
1046 if (ret < 0)
1047 return ret;
1048 dev_dbg(wm8350->dev,
449bd54d 1049 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
40aa4a30
MB		 1050 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1051 fll_div.ratio);
1052
1053 /* set up N.K & dividers */
3a96c77e 1054 fll_1 = snd_soc_read(codec, WM8350_FLL_CONTROL_1) &
40aa4a30 1055 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
3a96c77e 1056 snd_soc_write(codec, WM8350_FLL_CONTROL_1,
40aa4a30 1057 fll_1 | (fll_div.div << 8) | 0x50);
3a96c77e 1058 snd_soc_write(codec, WM8350_FLL_CONTROL_2,
40aa4a30
MB		 1059 (fll_div.ratio << 11) | (fll_div.
1060 n & WM8350_FLL_N_MASK));
3a96c77e
MB		 1061 snd_soc_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1062 fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
40aa4a30 1063 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
3a96c77e 1064 snd_soc_write(codec, WM8350_FLL_CONTROL_4,
40aa4a30
MB		 1065 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1066 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1067
1068 /* power FLL on */
1069 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1070 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1071
f1e887de
MB		 1072 priv->fll_freq_out = freq_out;
1073 priv->fll_freq_in = freq_in;
1074
40aa4a30
MB		 1075 return 0;
1076}
1077
1078static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1079 enum snd_soc_bias_level level)
1080{
b2c812e2 1081 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
018a455a 1082 struct wm8350 *wm8350 = priv->wm8350;
40aa4a30
MB		 1083 struct wm8350_audio_platform_data *platform =
1084 wm8350->codec.platform_data;
1085 u16 pm1;
1086 int ret;
1087
1088 switch (level) {
1089 case SND_SOC_BIAS_ON:
1090 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1091 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1092 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1093 pm1 | WM8350_VMID_50K |
1094 platform->codec_current_on << 14);
1095 break;
1096
1097 case SND_SOC_BIAS_PREPARE:
1098 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1099 pm1 &= ~WM8350_VMID_MASK;
1100 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1101 pm1 | WM8350_VMID_50K);
1102 break;
1103
1104 case SND_SOC_BIAS_STANDBY:
9b142894 1105 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
40aa4a30
MB		 1106 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1107 priv->supplies);
1108 if (ret != 0)
1109 return ret;
1110
1111 /* Enable the system clock */
1112 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1113 WM8350_SYSCLK_ENA);
1114
1115 /* mute DAC & outputs */
1116 wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1117 WM8350_DAC_MUTE_ENA);
1118
1119 /* discharge cap memory */
1120 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1121 platform->dis_out1 |
1122 (platform->dis_out2 << 2) |
1123 (platform->dis_out3 << 4) |
1124 (platform->dis_out4 << 6));
1125
1126 /* wait for discharge */
1127 schedule_timeout_interruptible(msecs_to_jiffies
1128 (platform->
1129 cap_discharge_msecs));
1130
1131 /* enable antipop */
1132 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1133 (platform->vmid_s_curve << 8));
1134
1135 /* ramp up vmid */
1136 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1137 (platform->
1138 codec_current_charge << 14) |
1139 WM8350_VMID_5K | WM8350_VMIDEN |
1140 WM8350_VBUFEN);
1141
1142 /* wait for vmid */
1143 schedule_timeout_interruptible(msecs_to_jiffies
1144 (platform->
1145 vmid_charge_msecs));
1146
1147 /* turn on vmid 300k */
1148 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1149 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1150 pm1 |= WM8350_VMID_300K |
1151 (platform->codec_current_standby << 14);
1152 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1153 pm1);
1154
1155
1156 /* enable analogue bias */
1157 pm1 |= WM8350_BIASEN;
1158 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1159
1160 /* disable antipop */
1161 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1162
1163 } else {
1164 /* turn on vmid 300k and reduce current */
1165 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1166 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1167 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1168 pm1 | WM8350_VMID_300K |
1169 (platform->
1170 codec_current_standby << 14));
1171
1172 }
1173 break;
1174
1175 case SND_SOC_BIAS_OFF:
1176
1177 /* mute DAC & enable outputs */
1178 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1179
1180 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1181 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1182 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1183
1184 /* enable anti pop S curve */
1185 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1186 (platform->vmid_s_curve << 8));
1187
1188 /* turn off vmid */
1189 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1190 ~WM8350_VMIDEN;
1191 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1192
1193 /* wait */
1194 schedule_timeout_interruptible(msecs_to_jiffies
1195 (platform->
1196 vmid_discharge_msecs));
1197
1198 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1199 (platform->vmid_s_curve << 8) |
1200 platform->dis_out1 |
1201 (platform->dis_out2 << 2) |
1202 (platform->dis_out3 << 4) |
1203 (platform->dis_out4 << 6));
1204
1205 /* turn off VBuf and drain */
1206 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1207 ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1208 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1209 pm1 | WM8350_OUTPUT_DRAIN_EN);
1210
1211 /* wait */
1212 schedule_timeout_interruptible(msecs_to_jiffies
1213 (platform->drain_msecs));
1214
1215 pm1 &= ~WM8350_BIASEN;
1216 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1217
1218 /* disable anti-pop */
1219 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1220
1221 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1222 WM8350_OUT1L_ENA);
1223 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1224 WM8350_OUT1R_ENA);
1225 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1226 WM8350_OUT2L_ENA);
1227 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1228 WM8350_OUT2R_ENA);
1229
1230 /* disable clock gen */
1231 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1232 WM8350_SYSCLK_ENA);
1233
1234 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1235 priv->supplies);
1236 break;
1237 }
40aa4a30
MB		 1238 return 0;
1239}
1240
6d3c26bc
MB		 1241static void wm8350_hp_work(struct wm8350_data *priv,
1242 struct wm8350_jack_data *jack,
1243 u16 mask)
a6ba2b2d 1244{
30facd4d 1245 struct wm8350 *wm8350 = priv->wm8350;
a6ba2b2d
MB		 1246 u16 reg;
1247 int report;
6d3c26bc
MB		 1248
1249 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1250 if (reg & mask)
1251 report = jack->report;
1252 else
1253 report = 0;
1254
1255 snd_soc_jack_report(jack->jack, report, jack->report);
1256
1257}
1258
1259static void wm8350_hpl_work(struct work_struct *work)
1260{
1261 struct wm8350_data *priv =
1262 container_of(work, struct wm8350_data, hpl.work.work);
1263
1264 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1265}
1266
1267static void wm8350_hpr_work(struct work_struct *work)
1268{
1269 struct wm8350_data *priv =
1270 container_of(work, struct wm8350_data, hpr.work.work);
1271
1272 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1273}
1274
f43f2db7 1275static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
6d3c26bc
MB		 1276{
1277 struct wm8350_data *priv = data;
30facd4d 1278 struct wm8350 *wm8350 = priv->wm8350;
a6ba2b2d 1279
1435b940 1280#ifndef CONFIG_SND_SOC_WM8350_MODULE
f43f2db7 1281 trace_snd_soc_jack_irq("WM8350 HPL");
1435b940 1282#endif
a6ba2b2d 1283
f43f2db7
MB		 1284 if (device_may_wakeup(wm8350->dev))
1285 pm_wakeup_event(wm8350->dev, 250);
1286
2c5920a7
MB		 1287 queue_delayed_work(system_power_efficient_wq,
1288 &priv->hpl.work, msecs_to_jiffies(200));
f43f2db7
MB		 1289
1290 return IRQ_HANDLED;
1291}
1292
1293static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
1294{
1295 struct wm8350_data *priv = data;
1296 struct wm8350 *wm8350 = priv->wm8350;
1297
1435b940 1298#ifndef CONFIG_SND_SOC_WM8350_MODULE
f43f2db7 1299 trace_snd_soc_jack_irq("WM8350 HPR");
1435b940 1300#endif
a6ba2b2d 1301
6d3c26bc
MB		 1302 if (device_may_wakeup(wm8350->dev))
1303 pm_wakeup_event(wm8350->dev, 250);
a6ba2b2d 1304
2c5920a7
MB		 1305 queue_delayed_work(system_power_efficient_wq,
1306 &priv->hpr.work, msecs_to_jiffies(200));
5a65edbc
MB		 1307
1308 return IRQ_HANDLED;
a6ba2b2d
MB		 1309}
1310
1311/**
1312 * wm8350_hp_jack_detect - Enable headphone jack detection.
1313 *
1314 * @codec: WM8350 codec
1315 * @which: left or right jack detect signal
1316 * @jack: jack to report detection events on
1317 * @report: value to report
1318 *
f06bce9c
MB		 1319 * Enables the headphone jack detection of the WM8350. If no report
1320 * is specified then detection is disabled.
a6ba2b2d
MB		 1321 */
1322int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1323 struct snd_soc_jack *jack, int report)
1324{
b2c812e2 1325 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
018a455a 1326 struct wm8350 *wm8350 = priv->wm8350;
a6ba2b2d
MB		 1327 int ena;
1328
1329 switch (which) {
1330 case WM8350_JDL:
1331 priv->hpl.jack = jack;
1332 priv->hpl.report = report;
a6ba2b2d
MB		 1333 ena = WM8350_JDL_ENA;
1334 break;
1335
1336 case WM8350_JDR:
1337 priv->hpr.jack = jack;
1338 priv->hpr.report = report;
a6ba2b2d
MB		 1339 ena = WM8350_JDR_ENA;
1340 break;
1341
1342 default:
1343 return -EINVAL;
1344 }
1345
f06bce9c
MB		 1346 if (report) {
1347 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1348 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1349 } else {
1350 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1351 }
a6ba2b2d
MB		 1352
1353 /* Sync status */
f43f2db7
MB		 1354 switch (which) {
1355 case WM8350_JDL:
1356 wm8350_hpl_jack_handler(0, priv);
1357 break;
1358 case WM8350_JDR:
1359 wm8350_hpr_jack_handler(0, priv);
1360 break;
1361 }
a6ba2b2d 1362
a6ba2b2d
MB		 1363 return 0;
1364}
1365EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1366
2a0761a3
MB		 1367static irqreturn_t wm8350_mic_handler(int irq, void *data)
1368{
1369 struct wm8350_data *priv = data;
30facd4d 1370 struct wm8350 *wm8350 = priv->wm8350;
2a0761a3
MB		 1371 u16 reg;
1372 int report = 0;
1373
7116f452 1374#ifndef CONFIG_SND_SOC_WM8350_MODULE
2bbb5d66 1375 trace_snd_soc_jack_irq("WM8350 mic");
7116f452 1376#endif
2bbb5d66 1377
2a0761a3
MB		 1378 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1379 if (reg & WM8350_JACK_MICSCD_LVL)
1380 report |= priv->mic.short_report;
1381 if (reg & WM8350_JACK_MICSD_LVL)
1382 report |= priv->mic.report;
1383
1384 snd_soc_jack_report(priv->mic.jack, report,
1385 priv->mic.report | priv->mic.short_report);
1386
1387 return IRQ_HANDLED;
1388}
1389
1390/**
1391 * wm8350_mic_jack_detect - Enable microphone jack detection.
1392 *
1393 * @codec: WM8350 codec
1394 * @jack: jack to report detection events on
1395 * @detect_report: value to report when presence detected
1396 * @short_report: value to report when microphone short detected
1397 *
f06bce9c
MB		 1398 * Enables the microphone jack detection of the WM8350. If both reports
1399 * are specified as zero then detection is disabled.
2a0761a3
MB		 1400 */
1401int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1402 struct snd_soc_jack *jack,
1403 int detect_report, int short_report)
1404{
b2c812e2 1405 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
018a455a 1406 struct wm8350 *wm8350 = priv->wm8350;
2a0761a3
MB		 1407
1408 priv->mic.jack = jack;
1409 priv->mic.report = detect_report;
1410 priv->mic.short_report = short_report;
1411
f06bce9c
MB		 1412 if (detect_report || short_report) {
1413 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1414 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1415 WM8350_MIC_DET_ENA);
1416 } else {
1417 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1418 WM8350_MIC_DET_ENA);
1419 }
2a0761a3 1420
2a0761a3
MB		 1421 return 0;
1422}
1423EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1424
f0fba2ad
LG		 1425#define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1426
1427#define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1428 SNDRV_PCM_FMTBIT_S20_3LE |\
1429 SNDRV_PCM_FMTBIT_S24_LE)
1430
85e7652d 1431static const struct snd_soc_dai_ops wm8350_dai_ops = {
f0fba2ad
LG		 1432 .hw_params = wm8350_pcm_hw_params,
1433 .digital_mute = wm8350_mute,
f0fba2ad
LG		 1434 .set_fmt = wm8350_set_dai_fmt,
1435 .set_sysclk = wm8350_set_dai_sysclk,
1436 .set_pll = wm8350_set_fll,
1437 .set_clkdiv = wm8350_set_clkdiv,
1438};
1439
1440static struct snd_soc_dai_driver wm8350_dai = {
1441 .name = "wm8350-hifi",
1442 .playback = {
1443 .stream_name = "Playback",
1444 .channels_min = 1,
1445 .channels_max = 2,
1446 .rates = WM8350_RATES,
1447 .formats = WM8350_FORMATS,
1448 },
1449 .capture = {
1450 .stream_name = "Capture",
1451 .channels_min = 1,
1452 .channels_max = 2,
1453 .rates = WM8350_RATES,
1454 .formats = WM8350_FORMATS,
1455 },
1456 .ops = &wm8350_dai_ops,
1457};
40aa4a30 1458
f0fba2ad 1459static int wm8350_codec_probe(struct snd_soc_codec *codec)
40aa4a30 1460{
f0fba2ad 1461 struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
40aa4a30 1462 struct wm8350_data *priv;
40aa4a30
MB		 1463 struct wm8350_output *out1;
1464 struct wm8350_output *out2;
f0fba2ad 1465 int ret, i;
40aa4a30 1466
f0fba2ad
LG		 1467 if (wm8350->codec.platform_data == NULL) {
1468 dev_err(codec->dev, "No audio platform data supplied\n");
1469 return -EINVAL;
1470 }
1471
0d1fe0d4
MB		 1472 priv = devm_kzalloc(codec->dev, sizeof(struct wm8350_data),
1473 GFP_KERNEL);
f0fba2ad
LG		 1474 if (priv == NULL)
1475 return -ENOMEM;
1476 snd_soc_codec_set_drvdata(codec, priv);
1477
30facd4d
MB		 1478 priv->wm8350 = wm8350;
1479
f0fba2ad
LG		 1480 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1481 priv->supplies[i].supply = supply_names[i];
1482
5851e9b8 1483 ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
f0fba2ad
LG		 1484 priv->supplies);
1485 if (ret != 0)
0d1fe0d4 1486 return ret;
f0fba2ad 1487
f0fba2ad
LG		 1488 /* Put the codec into reset if it wasn't already */
1489 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1490
cd5d8226 1491 INIT_DELAYED_WORK(&priv->pga_work, wm8350_pga_work);
6d3c26bc
MB		 1492 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1493 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
40aa4a30
MB		 1494
1495 /* Enable the codec */
1496 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1497
1498 /* Enable robust clocking mode in ADC */
3a96c77e
MB		 1499 snd_soc_write(codec, WM8350_SECURITY, 0xa7);
1500 snd_soc_write(codec, 0xde, 0x13);
1501 snd_soc_write(codec, WM8350_SECURITY, 0);
40aa4a30
MB		 1502
1503 /* read OUT1 & OUT2 volumes */
1504 out1 = &priv->out1;
1505 out2 = &priv->out2;
1506 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1507 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1508 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1509 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1510 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1511 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1512 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1513 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1514 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1515 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1516 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1517 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1518
1519 /* Latch VU bits & mute */
1520 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1521 WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1522 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1523 WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1524 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1525 WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1526 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1527 WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1528
0049317e
MB		 1529 /* Make sure AIF tristating is disabled by default */
1530 wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1531
1532 /* Make sure we've got a sane companding setup too */
1533 wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1534 WM8350_DAC_COMP | WM8350_LOOPBACK);
1535
6a612746
MB		 1536 /* Make sure jack detect is disabled to start off with */
1537 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1538 WM8350_JDL_ENA | WM8350_JDR_ENA);
1539
a6ba2b2d 1540 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
f43f2db7 1541 wm8350_hpl_jack_handler, 0, "Left jack detect",
5a65edbc 1542 priv);
a6ba2b2d 1543 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
f43f2db7 1544 wm8350_hpr_jack_handler, 0, "Right jack detect",
5a65edbc 1545 priv);
2a0761a3
MB		 1546 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1547 wm8350_mic_handler, 0, "Microphone short", priv);
1548 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1549 wm8350_mic_handler, 0, "Microphone detect", priv);
a6ba2b2d 1550
40aa4a30 1551 return 0;
40aa4a30
MB		 1552}
1553
f0fba2ad 1554static int wm8350_codec_remove(struct snd_soc_codec *codec)
40aa4a30 1555{
b2c812e2 1556 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
f0fba2ad 1557 struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
40aa4a30 1558
a6ba2b2d
MB		 1559 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1560 WM8350_JDL_ENA | WM8350_JDR_ENA);
1561 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1562
2a0761a3
MB		 1563 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1564 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
f99344fc
MB		 1565 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1566 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
a6ba2b2d
MB		 1567
1568 priv->hpl.jack = NULL;
1569 priv->hpr.jack = NULL;
2a0761a3 1570 priv->mic.jack = NULL;
a6ba2b2d 1571
6d3c26bc
MB		 1572 cancel_delayed_work_sync(&priv->hpl.work);
1573 cancel_delayed_work_sync(&priv->hpr.work);
1574
40aa4a30
MB		 1575 /* if there was any work waiting then we run it now and
1576 * wait for its completion */
cd5d8226 1577 flush_delayed_work(&priv->pga_work);
40aa4a30 1578
40aa4a30
MB		 1579 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1580
1581 return 0;
1582}
1583
7a34b1c1 1584static struct regmap *wm8350_get_regmap(struct device *dev)
aec0eb50
XL		 1585{
1586 struct wm8350 *wm8350 = dev_get_platdata(dev);
1587
1588 return wm8350->regmap;
1589}
1590
f0fba2ad
LG		 1591static struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
1592 .probe = wm8350_codec_probe,
1593 .remove = wm8350_codec_remove,
aec0eb50 1594 .get_regmap = wm8350_get_regmap,
f0fba2ad 1595 .set_bias_level = wm8350_set_bias_level,
21a942fd 1596 .suspend_bias_off = true,
e6c94e9f
MB		 1597
1598 .controls = wm8350_snd_controls,
1599 .num_controls = ARRAY_SIZE(wm8350_snd_controls),
1600 .dapm_widgets = wm8350_dapm_widgets,
1601 .num_dapm_widgets = ARRAY_SIZE(wm8350_dapm_widgets),
1602 .dapm_routes = wm8350_dapm_routes,
1603 .num_dapm_routes = ARRAY_SIZE(wm8350_dapm_routes),
40aa4a30 1604};
40aa4a30 1605
7a79e94e 1606static int wm8350_probe(struct platform_device *pdev)
40aa4a30 1607{
f0fba2ad
LG		 1608 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350,
1609 &wm8350_dai, 1);
40aa4a30
MB		 1610}
1611
7a79e94e 1612static int wm8350_remove(struct platform_device *pdev)
40aa4a30 1613{
f0fba2ad 1614 snd_soc_unregister_codec(&pdev->dev);
40aa4a30
MB		 1615 return 0;
1616}
1617
1618static struct platform_driver wm8350_codec_driver = {
1619 .driver = {
1620 .name = "wm8350-codec",
40aa4a30 1621 },
f0fba2ad 1622 .probe = wm8350_probe,
7a79e94e 1623 .remove = wm8350_remove,
40aa4a30
MB		 1624};
1625
5bbcc3c0 1626module_platform_driver(wm8350_codec_driver);
40aa4a30
MB		 1627
1628MODULE_DESCRIPTION("ASoC WM8350 driver");
1629MODULE_AUTHOR("Liam Girdwood");
1630MODULE_LICENSE("GPL");
1631MODULE_ALIAS("platform:wm8350-codec");
Linux kernel - Deliverables
This page took 0.364996 seconds and 5 git commands to generate.