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ASoC: Use dapm_mark_dirty() for new DAPM widgets for consistency
[deliverable/linux.git] / sound / soc / codecs / wm8350.c
CommitLineData
40aa4a30
MB		 1/*
2 * wm8350.c -- WM8350 ALSA SoC audio driver
3 *
4 * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC.
5 *
64ca0404 6 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
40aa4a30
MB		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
5a0e3ad6 16#include <linux/slab.h>
40aa4a30
MB		 17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/platform_device.h>
20#include <linux/mfd/wm8350/audio.h>
21#include <linux/mfd/wm8350/core.h>
22#include <linux/regulator/consumer.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
40aa4a30
MB		 27#include <sound/initval.h>
28#include <sound/tlv.h>
2bbb5d66 29#include <trace/events/asoc.h>
40aa4a30
MB		 30
31#include "wm8350.h"
32
33#define WM8350_OUTn_0dB 0x39
34
35#define WM8350_RAMP_NONE 0
36#define WM8350_RAMP_UP 1
37#define WM8350_RAMP_DOWN 2
38
39/* We only include the analogue supplies here; the digital supplies
40 * need to be available well before this driver can be probed.
41 */
42static const char *supply_names[] = {
43 "AVDD",
44 "HPVDD",
45};
46
47struct wm8350_output {
48 u16 active;
49 u16 left_vol;
50 u16 right_vol;
51 u16 ramp;
52 u16 mute;
53};
54
a6ba2b2d
MB		 55struct wm8350_jack_data {
56 struct snd_soc_jack *jack;
6d3c26bc 57 struct delayed_work work;
a6ba2b2d 58 int report;
2a0761a3 59 int short_report;
a6ba2b2d
MB		 60};
61
40aa4a30
MB		 62struct wm8350_data {
63 struct snd_soc_codec codec;
64 struct wm8350_output out1;
65 struct wm8350_output out2;
a6ba2b2d
MB		 66 struct wm8350_jack_data hpl;
67 struct wm8350_jack_data hpr;
2a0761a3 68 struct wm8350_jack_data mic;
40aa4a30 69 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
f1e887de
MB		 70 int fll_freq_out;
71 int fll_freq_in;
40aa4a30
MB		 72};
73
74static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec,
75 unsigned int reg)
76{
77 struct wm8350 *wm8350 = codec->control_data;
78 return wm8350->reg_cache[reg];
79}
80
81static unsigned int wm8350_codec_read(struct snd_soc_codec *codec,
82 unsigned int reg)
83{
84 struct wm8350 *wm8350 = codec->control_data;
85 return wm8350_reg_read(wm8350, reg);
86}
87
88static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg,
89 unsigned int value)
90{
91 struct wm8350 *wm8350 = codec->control_data;
92 return wm8350_reg_write(wm8350, reg, value);
93}
94
95/*
96 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
97 */
98static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec)
99{
b2c812e2 100 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 101 struct wm8350_output *out1 = &wm8350_data->out1;
102 struct wm8350 *wm8350 = codec->control_data;
103 int left_complete = 0, right_complete = 0;
104 u16 reg, val;
105
106 /* left channel */
107 reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
108 val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
109
110 if (out1->ramp == WM8350_RAMP_UP) {
111 /* ramp step up */
112 if (val < out1->left_vol) {
113 val++;
114 reg &= ~WM8350_OUT1L_VOL_MASK;
115 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
116 reg | (val << WM8350_OUT1L_VOL_SHIFT));
117 } else
118 left_complete = 1;
119 } else if (out1->ramp == WM8350_RAMP_DOWN) {
120 /* ramp step down */
121 if (val > 0) {
122 val--;
123 reg &= ~WM8350_OUT1L_VOL_MASK;
124 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
125 reg | (val << WM8350_OUT1L_VOL_SHIFT));
126 } else
127 left_complete = 1;
128 } else
129 return 1;
130
131 /* right channel */
132 reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
133 val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
134 if (out1->ramp == WM8350_RAMP_UP) {
135 /* ramp step up */
136 if (val < out1->right_vol) {
137 val++;
138 reg &= ~WM8350_OUT1R_VOL_MASK;
139 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
140 reg | (val << WM8350_OUT1R_VOL_SHIFT));
141 } else
142 right_complete = 1;
143 } else if (out1->ramp == WM8350_RAMP_DOWN) {
144 /* ramp step down */
145 if (val > 0) {
146 val--;
147 reg &= ~WM8350_OUT1R_VOL_MASK;
148 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
149 reg | (val << WM8350_OUT1R_VOL_SHIFT));
150 } else
151 right_complete = 1;
152 }
153
154 /* only hit the update bit if either volume has changed this step */
155 if (!left_complete || !right_complete)
156 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
157
158 return left_complete & right_complete;
159}
160
161/*
162 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
163 */
164static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec)
165{
b2c812e2 166 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 167 struct wm8350_output *out2 = &wm8350_data->out2;
168 struct wm8350 *wm8350 = codec->control_data;
169 int left_complete = 0, right_complete = 0;
170 u16 reg, val;
171
172 /* left channel */
173 reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
174 val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
175 if (out2->ramp == WM8350_RAMP_UP) {
176 /* ramp step up */
177 if (val < out2->left_vol) {
178 val++;
179 reg &= ~WM8350_OUT2L_VOL_MASK;
180 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
181 reg | (val << WM8350_OUT1L_VOL_SHIFT));
182 } else
183 left_complete = 1;
184 } else if (out2->ramp == WM8350_RAMP_DOWN) {
185 /* ramp step down */
186 if (val > 0) {
187 val--;
188 reg &= ~WM8350_OUT2L_VOL_MASK;
189 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
190 reg | (val << WM8350_OUT1L_VOL_SHIFT));
191 } else
192 left_complete = 1;
193 } else
194 return 1;
195
196 /* right channel */
197 reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
198 val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
199 if (out2->ramp == WM8350_RAMP_UP) {
200 /* ramp step up */
201 if (val < out2->right_vol) {
202 val++;
203 reg &= ~WM8350_OUT2R_VOL_MASK;
204 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
205 reg | (val << WM8350_OUT1R_VOL_SHIFT));
206 } else
207 right_complete = 1;
208 } else if (out2->ramp == WM8350_RAMP_DOWN) {
209 /* ramp step down */
210 if (val > 0) {
211 val--;
212 reg &= ~WM8350_OUT2R_VOL_MASK;
213 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
214 reg | (val << WM8350_OUT1R_VOL_SHIFT));
215 } else
216 right_complete = 1;
217 }
218
219 /* only hit the update bit if either volume has changed this step */
220 if (!left_complete || !right_complete)
221 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
222
223 return left_complete & right_complete;
224}
225
226/*
227 * This work ramps both output PGAs at stream start/stop time to
228 * minimise pop associated with DAPM power switching.
229 * It's best to enable Zero Cross when ramping occurs to minimise any
230 * zipper noises.
231 */
232static void wm8350_pga_work(struct work_struct *work)
233{
ce6120cc
LG		 234 struct snd_soc_dapm_context *dapm =
235 container_of(work, struct snd_soc_dapm_context, delayed_work.work);
236 struct snd_soc_codec *codec = dapm->codec;
b2c812e2 237 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 238 struct wm8350_output *out1 = &wm8350_data->out1,
239 *out2 = &wm8350_data->out2;
240 int i, out1_complete, out2_complete;
241
242 /* do we need to ramp at all ? */
243 if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
244 return;
245
246 /* PGA volumes have 6 bits of resolution to ramp */
247 for (i = 0; i <= 63; i++) {
248 out1_complete = 1, out2_complete = 1;
249 if (out1->ramp != WM8350_RAMP_NONE)
250 out1_complete = wm8350_out1_ramp_step(codec);
251 if (out2->ramp != WM8350_RAMP_NONE)
252 out2_complete = wm8350_out2_ramp_step(codec);
253
254 /* ramp finished ? */
255 if (out1_complete && out2_complete)
256 break;
257
258 /* we need to delay longer on the up ramp */
259 if (out1->ramp == WM8350_RAMP_UP ||
260 out2->ramp == WM8350_RAMP_UP) {
261 /* delay is longer over 0dB as increases are larger */
262 if (i >= WM8350_OUTn_0dB)
263 schedule_timeout_interruptible(msecs_to_jiffies
264 (2));
265 else
266 schedule_timeout_interruptible(msecs_to_jiffies
267 (1));
268 } else
269 udelay(50); /* doesn't matter if we delay longer */
270 }
271
272 out1->ramp = WM8350_RAMP_NONE;
273 out2->ramp = WM8350_RAMP_NONE;
274}
275
276/*
277 * WM8350 Controls
278 */
279
280static int pga_event(struct snd_soc_dapm_widget *w,
281 struct snd_kcontrol *kcontrol, int event)
282{
283 struct snd_soc_codec *codec = w->codec;
b2c812e2 284 struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 285 struct wm8350_output *out;
286
287 switch (w->shift) {
288 case 0:
289 case 1:
290 out = &wm8350_data->out1;
291 break;
292 case 2:
293 case 3:
294 out = &wm8350_data->out2;
295 break;
296
297 default:
298 BUG();
299 return -1;
300 }
301
302 switch (event) {
303 case SND_SOC_DAPM_POST_PMU:
304 out->ramp = WM8350_RAMP_UP;
305 out->active = 1;
306
ce6120cc
LG		 307 if (!delayed_work_pending(&codec->dapm.delayed_work))
308 schedule_delayed_work(&codec->dapm.delayed_work,
40aa4a30
MB		 309 msecs_to_jiffies(1));
310 break;
311
312 case SND_SOC_DAPM_PRE_PMD:
313 out->ramp = WM8350_RAMP_DOWN;
314 out->active = 0;
315
ce6120cc
LG		 316 if (!delayed_work_pending(&codec->dapm.delayed_work))
317 schedule_delayed_work(&codec->dapm.delayed_work,
40aa4a30
MB		 318 msecs_to_jiffies(1));
319 break;
320 }
321
322 return 0;
323}
324
325static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
326 struct snd_ctl_elem_value *ucontrol)
327{
328 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 329 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 330 struct wm8350_output *out = NULL;
331 struct soc_mixer_control *mc =
332 (struct soc_mixer_control *)kcontrol->private_value;
333 int ret;
334 unsigned int reg = mc->reg;
335 u16 val;
336
337 /* For OUT1 and OUT2 we shadow the values and only actually write
338 * them out when active in order to ensure the amplifier comes on
339 * as quietly as possible. */
340 switch (reg) {
341 case WM8350_LOUT1_VOLUME:
342 out = &wm8350_priv->out1;
343 break;
344 case WM8350_LOUT2_VOLUME:
345 out = &wm8350_priv->out2;
346 break;
347 default:
348 break;
349 }
350
351 if (out) {
352 out->left_vol = ucontrol->value.integer.value[0];
353 out->right_vol = ucontrol->value.integer.value[1];
354 if (!out->active)
355 return 1;
356 }
357
358 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
359 if (ret < 0)
360 return ret;
361
362 /* now hit the volume update bits (always bit 8) */
363 val = wm8350_codec_read(codec, reg);
364 wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU);
365 return 1;
366}
367
368static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
369 struct snd_ctl_elem_value *ucontrol)
370{
371 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
b2c812e2 372 struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 373 struct wm8350_output *out1 = &wm8350_priv->out1;
374 struct wm8350_output *out2 = &wm8350_priv->out2;
375 struct soc_mixer_control *mc =
376 (struct soc_mixer_control *)kcontrol->private_value;
377 unsigned int reg = mc->reg;
378
379 /* If these are cached registers use the cache */
380 switch (reg) {
381 case WM8350_LOUT1_VOLUME:
382 ucontrol->value.integer.value[0] = out1->left_vol;
383 ucontrol->value.integer.value[1] = out1->right_vol;
384 return 0;
385
386 case WM8350_LOUT2_VOLUME:
387 ucontrol->value.integer.value[0] = out2->left_vol;
388 ucontrol->value.integer.value[1] = out2->right_vol;
389 return 0;
390
391 default:
392 break;
393 }
394
395 return snd_soc_get_volsw_2r(kcontrol, ucontrol);
396}
397
398/* double control with volume update */
399#define SOC_WM8350_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
400 xinvert, tlv_array) \
401{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
402 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
403 SNDRV_CTL_ELEM_ACCESS_READWRITE | \
404 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
405 .tlv.p = (tlv_array), \
406 .info = snd_soc_info_volsw_2r, \
407 .get = wm8350_get_volsw_2r, .put = wm8350_put_volsw_2r_vu, \
408 .private_value = (unsigned long)&(struct soc_mixer_control) \
409 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
410 .rshift = xshift, .max = xmax, .invert = xinvert}, }
411
412static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
413static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
414static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
415static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
40aa4a30
MB		 416static const char *wm8350_adcfilter[] = { "None", "High Pass" };
417static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
418static const char *wm8350_lr[] = { "Left", "Right" };
419
420static const struct soc_enum wm8350_enum[] = {
421 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
422 SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
423 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
424 SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
40aa4a30
MB		 425 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
426 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
427 SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
428 SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
429};
430
e6a08c5a
MB		 431static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
432static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
40aa4a30
MB		 433static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
434static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
435static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
436
437static const unsigned int capture_sd_tlv[] = {
438 TLV_DB_RANGE_HEAD(2),
439 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
440 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0),
441};
442
443static const struct snd_kcontrol_new wm8350_snd_controls[] = {
444 SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
445 SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
446 SOC_WM8350_DOUBLE_R_TLV("Playback PCM Volume",
447 WM8350_DAC_DIGITAL_VOLUME_L,
448 WM8350_DAC_DIGITAL_VOLUME_R,
449 0, 255, 0, dac_pcm_tlv),
450 SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
451 SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
61943999
MB		 452 SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
453 SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
454 SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
40aa4a30
MB		 455 SOC_WM8350_DOUBLE_R_TLV("Capture PCM Volume",
456 WM8350_ADC_DIGITAL_VOLUME_L,
457 WM8350_ADC_DIGITAL_VOLUME_R,
458 0, 255, 0, adc_pcm_tlv),
459 SOC_DOUBLE_TLV("Capture Sidetone Volume",
460 WM8350_ADC_DIVIDER,
461 8, 4, 15, 1, capture_sd_tlv),
462 SOC_WM8350_DOUBLE_R_TLV("Capture Volume",
463 WM8350_LEFT_INPUT_VOLUME,
464 WM8350_RIGHT_INPUT_VOLUME,
465 2, 63, 0, pre_amp_tlv),
466 SOC_DOUBLE_R("Capture ZC Switch",
467 WM8350_LEFT_INPUT_VOLUME,
468 WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
469 SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
470 WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
471 SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
472 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
473 5, 7, 0, out_mix_tlv),
474 SOC_SINGLE_TLV("Left Input Bypass Volume",
475 WM8350_OUTPUT_LEFT_MIXER_VOLUME,
476 9, 7, 0, out_mix_tlv),
477 SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
478 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
479 1, 7, 0, out_mix_tlv),
480 SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
481 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
482 5, 7, 0, out_mix_tlv),
483 SOC_SINGLE_TLV("Right Input Bypass Volume",
484 WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
485 13, 7, 0, out_mix_tlv),
486 SOC_SINGLE("Left Input Mixer +20dB Switch",
487 WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
488 SOC_SINGLE("Right Input Mixer +20dB Switch",
489 WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
490 SOC_SINGLE_TLV("Out4 Capture Volume",
491 WM8350_INPUT_MIXER_VOLUME,
492 1, 7, 0, out_mix_tlv),
493 SOC_WM8350_DOUBLE_R_TLV("Out1 Playback Volume",
494 WM8350_LOUT1_VOLUME,
495 WM8350_ROUT1_VOLUME,
496 2, 63, 0, out_pga_tlv),
497 SOC_DOUBLE_R("Out1 Playback ZC Switch",
498 WM8350_LOUT1_VOLUME,
499 WM8350_ROUT1_VOLUME, 13, 1, 0),
500 SOC_WM8350_DOUBLE_R_TLV("Out2 Playback Volume",
501 WM8350_LOUT2_VOLUME,
502 WM8350_ROUT2_VOLUME,
503 2, 63, 0, out_pga_tlv),
504 SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
505 WM8350_ROUT2_VOLUME, 13, 1, 0),
506 SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
507 SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
508 5, 7, 0, out_mix_tlv),
509
510 SOC_DOUBLE_R("Out1 Playback Switch",
511 WM8350_LOUT1_VOLUME,
512 WM8350_ROUT1_VOLUME,
513 14, 1, 1),
514 SOC_DOUBLE_R("Out2 Playback Switch",
515 WM8350_LOUT2_VOLUME,
516 WM8350_ROUT2_VOLUME,
517 14, 1, 1),
518};
519
520/*
521 * DAPM Controls
522 */
523
524/* Left Playback Mixer */
525static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
526 SOC_DAPM_SINGLE("Playback Switch",
527 WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
528 SOC_DAPM_SINGLE("Left Bypass Switch",
529 WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
530 SOC_DAPM_SINGLE("Right Playback Switch",
531 WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
532 SOC_DAPM_SINGLE("Left Sidetone Switch",
533 WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
534 SOC_DAPM_SINGLE("Right Sidetone Switch",
535 WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
536};
537
538/* Right Playback Mixer */
539static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
540 SOC_DAPM_SINGLE("Playback Switch",
541 WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
542 SOC_DAPM_SINGLE("Right Bypass Switch",
543 WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
544 SOC_DAPM_SINGLE("Left Playback Switch",
545 WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
546 SOC_DAPM_SINGLE("Left Sidetone Switch",
547 WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
548 SOC_DAPM_SINGLE("Right Sidetone Switch",
549 WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
550};
551
552/* Out4 Mixer */
553static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
554 SOC_DAPM_SINGLE("Right Playback Switch",
555 WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
556 SOC_DAPM_SINGLE("Left Playback Switch",
557 WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
558 SOC_DAPM_SINGLE("Right Capture Switch",
559 WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
560 SOC_DAPM_SINGLE("Out3 Playback Switch",
561 WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
562 SOC_DAPM_SINGLE("Right Mixer Switch",
563 WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
564 SOC_DAPM_SINGLE("Left Mixer Switch",
565 WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
566};
567
568/* Out3 Mixer */
569static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
570 SOC_DAPM_SINGLE("Left Playback Switch",
571 WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
572 SOC_DAPM_SINGLE("Left Capture Switch",
573 WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
574 SOC_DAPM_SINGLE("Out4 Playback Switch",
575 WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
576 SOC_DAPM_SINGLE("Left Mixer Switch",
577 WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
578};
579
580/* Left Input Mixer */
581static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
582 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
583 WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
584 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
585 WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
586 SOC_DAPM_SINGLE("PGA Capture Switch",
5b7dde34 587 WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
40aa4a30
MB		 588};
589
590/* Right Input Mixer */
591static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
592 SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
593 WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
594 SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
595 WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
596 SOC_DAPM_SINGLE("PGA Capture Switch",
5b7dde34 597 WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
40aa4a30
MB		 598};
599
600/* Left Mic Mixer */
601static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
602 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
603 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
604 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
605};
606
607/* Right Mic Mixer */
608static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
609 SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
610 SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
611 SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
612};
613
614/* Beep Switch */
615static const struct snd_kcontrol_new wm8350_beep_switch_controls =
616SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
617
618/* Out4 Capture Mux */
619static const struct snd_kcontrol_new wm8350_out4_capture_controls =
87831cb6 620SOC_DAPM_ENUM("Route", wm8350_enum[7]);
40aa4a30
MB		 621
622static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
623
624 SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
625 SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
626 SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
627 0, pga_event,
628 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
629 SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
630 pga_event,
631 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
632 SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
633 0, pga_event,
634 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
635 SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
636 pga_event,
637 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
638
639 SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
640 7, 0, &wm8350_right_capt_mixer_controls[0],
641 ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
642
643 SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
644 6, 0, &wm8350_left_capt_mixer_controls[0],
645 ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
646
647 SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
648 &wm8350_out4_mixer_controls[0],
649 ARRAY_SIZE(wm8350_out4_mixer_controls)),
650
651 SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
652 &wm8350_out3_mixer_controls[0],
653 ARRAY_SIZE(wm8350_out3_mixer_controls)),
654
655 SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
656 &wm8350_right_play_mixer_controls[0],
657 ARRAY_SIZE(wm8350_right_play_mixer_controls)),
658
659 SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
660 &wm8350_left_play_mixer_controls[0],
661 ARRAY_SIZE(wm8350_left_play_mixer_controls)),
662
663 SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
664 &wm8350_left_mic_mixer_controls[0],
665 ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
666
667 SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
668 &wm8350_right_mic_mixer_controls[0],
669 ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
670
671 /* virtual mixer for Beep and Out2R */
672 SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
673
674 SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
675 &wm8350_beep_switch_controls),
676
677 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
678 WM8350_POWER_MGMT_4, 3, 0),
679 SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
680 WM8350_POWER_MGMT_4, 2, 0),
681 SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
682 WM8350_POWER_MGMT_4, 5, 0),
683 SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
684 WM8350_POWER_MGMT_4, 4, 0),
685
686 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
687
688 SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
689 &wm8350_out4_capture_controls),
690
691 SND_SOC_DAPM_OUTPUT("OUT1R"),
692 SND_SOC_DAPM_OUTPUT("OUT1L"),
693 SND_SOC_DAPM_OUTPUT("OUT2R"),
694 SND_SOC_DAPM_OUTPUT("OUT2L"),
695 SND_SOC_DAPM_OUTPUT("OUT3"),
696 SND_SOC_DAPM_OUTPUT("OUT4"),
697
698 SND_SOC_DAPM_INPUT("IN1RN"),
699 SND_SOC_DAPM_INPUT("IN1RP"),
700 SND_SOC_DAPM_INPUT("IN2R"),
701 SND_SOC_DAPM_INPUT("IN1LP"),
702 SND_SOC_DAPM_INPUT("IN1LN"),
703 SND_SOC_DAPM_INPUT("IN2L"),
704 SND_SOC_DAPM_INPUT("IN3R"),
705 SND_SOC_DAPM_INPUT("IN3L"),
706};
707
708static const struct snd_soc_dapm_route audio_map[] = {
709
710 /* left playback mixer */
711 {"Left Playback Mixer", "Playback Switch", "Left DAC"},
712 {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
713 {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
714 {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
715 {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
716
717 /* right playback mixer */
718 {"Right Playback Mixer", "Playback Switch", "Right DAC"},
719 {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
720 {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
721 {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
722 {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
723
724 /* out4 playback mixer */
725 {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
726 {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
727 {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
728 {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
729 {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
730 {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
731 {"OUT4", NULL, "Out4 Mixer"},
732
733 /* out3 playback mixer */
734 {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
735 {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
736 {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
737 {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
738 {"OUT3", NULL, "Out3 Mixer"},
739
740 /* out2 */
741 {"Right Out2 PGA", NULL, "Right Playback Mixer"},
742 {"Left Out2 PGA", NULL, "Left Playback Mixer"},
743 {"OUT2L", NULL, "Left Out2 PGA"},
744 {"OUT2R", NULL, "Right Out2 PGA"},
745
746 /* out1 */
747 {"Right Out1 PGA", NULL, "Right Playback Mixer"},
748 {"Left Out1 PGA", NULL, "Left Playback Mixer"},
749 {"OUT1L", NULL, "Left Out1 PGA"},
750 {"OUT1R", NULL, "Right Out1 PGA"},
751
752 /* ADCs */
753 {"Left ADC", NULL, "Left Capture Mixer"},
754 {"Right ADC", NULL, "Right Capture Mixer"},
755
756 /* Left capture mixer */
757 {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
758 {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
759 {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
760 {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
761
762 /* Right capture mixer */
763 {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
764 {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
765 {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
766 {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
767
768 /* L3 Inputs */
769 {"IN3L PGA", NULL, "IN3L"},
770 {"IN3R PGA", NULL, "IN3R"},
771
772 /* Left Mic mixer */
773 {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
774 {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
775 {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
776
777 /* Right Mic mixer */
778 {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
779 {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
780 {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
781
782 /* out 4 capture */
783 {"Out4 Capture Channel", NULL, "Out4 Mixer"},
784
785 /* Beep */
786 {"Beep", NULL, "IN3R PGA"},
787};
788
40aa4a30
MB		 789static int wm8350_add_widgets(struct snd_soc_codec *codec)
790{
ce6120cc 791 struct snd_soc_dapm_context *dapm = &codec->dapm;
40aa4a30
MB		 792 int ret;
793
ce6120cc 794 ret = snd_soc_dapm_new_controls(dapm,
40aa4a30
MB		 795 wm8350_dapm_widgets,
796 ARRAY_SIZE(wm8350_dapm_widgets));
797 if (ret != 0) {
798 dev_err(codec->dev, "dapm control register failed\n");
799 return ret;
800 }
801
802 /* set up audio paths */
ce6120cc 803 ret = snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
40aa4a30
MB		 804 if (ret != 0) {
805 dev_err(codec->dev, "DAPM route register failed\n");
806 return ret;
807 }
808
0a3f5e35 809 return 0;
40aa4a30
MB		 810}
811
812static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
813 int clk_id, unsigned int freq, int dir)
814{
815 struct snd_soc_codec *codec = codec_dai->codec;
816 struct wm8350 *wm8350 = codec->control_data;
817 u16 fll_4;
818
819 switch (clk_id) {
820 case WM8350_MCLK_SEL_MCLK:
821 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
822 WM8350_MCLK_SEL);
823 break;
824 case WM8350_MCLK_SEL_PLL_MCLK:
825 case WM8350_MCLK_SEL_PLL_DAC:
826 case WM8350_MCLK_SEL_PLL_ADC:
827 case WM8350_MCLK_SEL_PLL_32K:
828 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
829 WM8350_MCLK_SEL);
830 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
831 ~WM8350_FLL_CLK_SRC_MASK;
832 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
833 break;
834 }
835
836 /* MCLK direction */
c28a9926 837 if (dir == SND_SOC_CLOCK_OUT)
40aa4a30
MB		 838 wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
839 WM8350_MCLK_DIR);
840 else
841 wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
842 WM8350_MCLK_DIR);
843
844 return 0;
845}
846
847static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
848{
849 struct snd_soc_codec *codec = codec_dai->codec;
850 u16 val;
851
852 switch (div_id) {
853 case WM8350_ADC_CLKDIV:
854 val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) &
855 ~WM8350_ADC_CLKDIV_MASK;
856 wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div);
857 break;
858 case WM8350_DAC_CLKDIV:
859 val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) &
860 ~WM8350_DAC_CLKDIV_MASK;
861 wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
862 break;
863 case WM8350_BCLK_CLKDIV:
864 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
865 ~WM8350_BCLK_DIV_MASK;
866 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
867 break;
868 case WM8350_OPCLK_CLKDIV:
869 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
870 ~WM8350_OPCLK_DIV_MASK;
871 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
872 break;
873 case WM8350_SYS_CLKDIV:
874 val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) &
875 ~WM8350_MCLK_DIV_MASK;
876 wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
877 break;
878 case WM8350_DACLR_CLKDIV:
879 val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
880 ~WM8350_DACLRC_RATE_MASK;
881 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div);
882 break;
883 case WM8350_ADCLR_CLKDIV:
884 val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
885 ~WM8350_ADCLRC_RATE_MASK;
886 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div);
887 break;
888 default:
889 return -EINVAL;
890 }
891
892 return 0;
893}
894
895static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
896{
897 struct snd_soc_codec *codec = codec_dai->codec;
898 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
899 ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
900 u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) &
901 ~WM8350_BCLK_MSTR;
902 u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) &
903 ~WM8350_DACLRC_ENA;
904 u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) &
905 ~WM8350_ADCLRC_ENA;
906
907 /* set master/slave audio interface */
908 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
909 case SND_SOC_DAIFMT_CBM_CFM:
910 master |= WM8350_BCLK_MSTR;
911 dac_lrc |= WM8350_DACLRC_ENA;
912 adc_lrc |= WM8350_ADCLRC_ENA;
913 break;
914 case SND_SOC_DAIFMT_CBS_CFS:
915 break;
916 default:
917 return -EINVAL;
918 }
919
920 /* interface format */
921 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
922 case SND_SOC_DAIFMT_I2S:
923 iface |= 0x2 << 8;
924 break;
925 case SND_SOC_DAIFMT_RIGHT_J:
926 break;
927 case SND_SOC_DAIFMT_LEFT_J:
928 iface |= 0x1 << 8;
929 break;
930 case SND_SOC_DAIFMT_DSP_A:
931 iface |= 0x3 << 8;
932 break;
933 case SND_SOC_DAIFMT_DSP_B:
5ee518ec 934 iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
40aa4a30
MB		 935 break;
936 default:
937 return -EINVAL;
938 }
939
940 /* clock inversion */
941 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
942 case SND_SOC_DAIFMT_NB_NF:
943 break;
944 case SND_SOC_DAIFMT_IB_IF:
945 iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
946 break;
947 case SND_SOC_DAIFMT_IB_NF:
948 iface |= WM8350_AIF_BCLK_INV;
949 break;
950 case SND_SOC_DAIFMT_NB_IF:
951 iface |= WM8350_AIF_LRCLK_INV;
952 break;
953 default:
954 return -EINVAL;
955 }
956
957 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
958 wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master);
959 wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
960 wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
961 return 0;
962}
963
964static int wm8350_pcm_trigger(struct snd_pcm_substream *substream,
965 int cmd, struct snd_soc_dai *codec_dai)
966{
967 struct snd_soc_codec *codec = codec_dai->codec;
968 int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) &
969 WM8350_BCLK_MSTR;
970 int enabled = 0;
971
972 /* Check that the DACs or ADCs are enabled since they are
973 * required for LRC in master mode. The DACs or ADCs need a
974 * valid audio path i.e. pin -> ADC or DAC -> pin before
975 * the LRC will be enabled in master mode. */
5e42336a 976 if (!master || cmd != SNDRV_PCM_TRIGGER_START)
40aa4a30
MB		 977 return 0;
978
979 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
980 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
981 (WM8350_ADCR_ENA | WM8350_ADCL_ENA);
982 } else {
983 enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) &
984 (WM8350_DACR_ENA | WM8350_DACL_ENA);
985 }
986
987 if (!enabled) {
988 dev_err(codec->dev,
989 "%s: invalid audio path - no clocks available\n",
990 __func__);
991 return -EINVAL;
992 }
993 return 0;
994}
995
996static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
997 struct snd_pcm_hw_params *params,
998 struct snd_soc_dai *codec_dai)
999{
1000 struct snd_soc_codec *codec = codec_dai->codec;
61943999 1001 struct wm8350 *wm8350 = codec->control_data;
40aa4a30
MB		 1002 u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) &
1003 ~WM8350_AIF_WL_MASK;
1004
1005 /* bit size */
1006 switch (params_format(params)) {
1007 case SNDRV_PCM_FORMAT_S16_LE:
1008 break;
1009 case SNDRV_PCM_FORMAT_S20_3LE:
1010 iface |= 0x1 << 10;
1011 break;
1012 case SNDRV_PCM_FORMAT_S24_LE:
1013 iface |= 0x2 << 10;
1014 break;
1015 case SNDRV_PCM_FORMAT_S32_LE:
1016 iface |= 0x3 << 10;
1017 break;
1018 }
1019
1020 wm8350_codec_write(codec, WM8350_AI_FORMATING, iface);
61943999
MB		 1021
1022 /* The sloping stopband filter is recommended for use with
1023 * lower sample rates to improve performance.
1024 */
1025 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1026 if (params_rate(params) < 24000)
1027 wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1028 WM8350_DAC_SB_FILT);
1029 else
1030 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
1031 WM8350_DAC_SB_FILT);
1032 }
1033
40aa4a30
MB		 1034 return 0;
1035}
1036
1037static int wm8350_mute(struct snd_soc_dai *dai, int mute)
1038{
1039 struct snd_soc_codec *codec = dai->codec;
1040 struct wm8350 *wm8350 = codec->control_data;
1041
1042 if (mute)
1043 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1044 else
1045 wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1046 return 0;
1047}
1048
1049/* FLL divisors */
1050struct _fll_div {
1051 int div; /* FLL_OUTDIV */
1052 int n;
1053 int k;
1054 int ratio; /* FLL_FRATIO */
1055};
1056
1057/* The size in bits of the fll divide multiplied by 10
1058 * to allow rounding later */
1059#define FIXED_FLL_SIZE ((1 << 16) * 10)
1060
1061static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
1062 unsigned int output)
1063{
1064 u64 Kpart;
1065 unsigned int t1, t2, K, Nmod;
1066
1067 if (output >= 2815250 && output <= 3125000)
1068 fll_div->div = 0x4;
1069 else if (output >= 5625000 && output <= 6250000)
1070 fll_div->div = 0x3;
1071 else if (output >= 11250000 && output <= 12500000)
1072 fll_div->div = 0x2;
1073 else if (output >= 22500000 && output <= 25000000)
1074 fll_div->div = 0x1;
1075 else {
1076 printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
1077 return -EINVAL;
1078 }
1079
1080 if (input > 48000)
1081 fll_div->ratio = 1;
1082 else
1083 fll_div->ratio = 8;
1084
1085 t1 = output * (1 << (fll_div->div + 1));
1086 t2 = input * fll_div->ratio;
1087
1088 fll_div->n = t1 / t2;
1089 Nmod = t1 % t2;
1090
1091 if (Nmod) {
1092 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1093 do_div(Kpart, t2);
1094 K = Kpart & 0xFFFFFFFF;
1095
1096 /* Check if we need to round */
1097 if ((K % 10) >= 5)
1098 K += 5;
1099
1100 /* Move down to proper range now rounding is done */
1101 K /= 10;
1102 fll_div->k = K;
1103 } else
1104 fll_div->k = 0;
1105
1106 return 0;
1107}
1108
1109static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
85488037 1110 int pll_id, int source, unsigned int freq_in,
40aa4a30
MB		 1111 unsigned int freq_out)
1112{
1113 struct snd_soc_codec *codec = codec_dai->codec;
1114 struct wm8350 *wm8350 = codec->control_data;
b2c812e2 1115 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 1116 struct _fll_div fll_div;
1117 int ret = 0;
1118 u16 fll_1, fll_4;
1119
f1e887de
MB		 1120 if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1121 return 0;
1122
40aa4a30
MB		 1123 /* power down FLL - we need to do this for reconfiguration */
1124 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1125 WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1126
1127 if (freq_out == 0 || freq_in == 0)
1128 return ret;
1129
1130 ret = fll_factors(&fll_div, freq_in, freq_out);
1131 if (ret < 0)
1132 return ret;
1133 dev_dbg(wm8350->dev,
449bd54d 1134 "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
40aa4a30
MB		 1135 freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1136 fll_div.ratio);
1137
1138 /* set up N.K & dividers */
1139 fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) &
1140 ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1141 wm8350_codec_write(codec, WM8350_FLL_CONTROL_1,
1142 fll_1 | (fll_div.div << 8) | 0x50);
1143 wm8350_codec_write(codec, WM8350_FLL_CONTROL_2,
1144 (fll_div.ratio << 11) | (fll_div.
1145 n & WM8350_FLL_N_MASK));
1146 wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1147 fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) &
1148 ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1149 wm8350_codec_write(codec, WM8350_FLL_CONTROL_4,
1150 fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1151 (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1152
1153 /* power FLL on */
1154 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1155 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1156
f1e887de
MB		 1157 priv->fll_freq_out = freq_out;
1158 priv->fll_freq_in = freq_in;
1159
40aa4a30
MB		 1160 return 0;
1161}
1162
1163static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1164 enum snd_soc_bias_level level)
1165{
1166 struct wm8350 *wm8350 = codec->control_data;
b2c812e2 1167 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
40aa4a30
MB		 1168 struct wm8350_audio_platform_data *platform =
1169 wm8350->codec.platform_data;
1170 u16 pm1;
1171 int ret;
1172
1173 switch (level) {
1174 case SND_SOC_BIAS_ON:
1175 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1176 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1177 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1178 pm1 | WM8350_VMID_50K |
1179 platform->codec_current_on << 14);
1180 break;
1181
1182 case SND_SOC_BIAS_PREPARE:
1183 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1184 pm1 &= ~WM8350_VMID_MASK;
1185 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1186 pm1 | WM8350_VMID_50K);
1187 break;
1188
1189 case SND_SOC_BIAS_STANDBY:
ce6120cc 1190 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
40aa4a30
MB		 1191 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1192 priv->supplies);
1193 if (ret != 0)
1194 return ret;
1195
1196 /* Enable the system clock */
1197 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1198 WM8350_SYSCLK_ENA);
1199
1200 /* mute DAC & outputs */
1201 wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1202 WM8350_DAC_MUTE_ENA);
1203
1204 /* discharge cap memory */
1205 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1206 platform->dis_out1 |
1207 (platform->dis_out2 << 2) |
1208 (platform->dis_out3 << 4) |
1209 (platform->dis_out4 << 6));
1210
1211 /* wait for discharge */
1212 schedule_timeout_interruptible(msecs_to_jiffies
1213 (platform->
1214 cap_discharge_msecs));
1215
1216 /* enable antipop */
1217 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1218 (platform->vmid_s_curve << 8));
1219
1220 /* ramp up vmid */
1221 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1222 (platform->
1223 codec_current_charge << 14) |
1224 WM8350_VMID_5K | WM8350_VMIDEN |
1225 WM8350_VBUFEN);
1226
1227 /* wait for vmid */
1228 schedule_timeout_interruptible(msecs_to_jiffies
1229 (platform->
1230 vmid_charge_msecs));
1231
1232 /* turn on vmid 300k */
1233 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1234 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1235 pm1 |= WM8350_VMID_300K |
1236 (platform->codec_current_standby << 14);
1237 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1238 pm1);
1239
1240
1241 /* enable analogue bias */
1242 pm1 |= WM8350_BIASEN;
1243 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1244
1245 /* disable antipop */
1246 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1247
1248 } else {
1249 /* turn on vmid 300k and reduce current */
1250 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1251 ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1252 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1253 pm1 | WM8350_VMID_300K |
1254 (platform->
1255 codec_current_standby << 14));
1256
1257 }
1258 break;
1259
1260 case SND_SOC_BIAS_OFF:
1261
1262 /* mute DAC & enable outputs */
1263 wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1264
1265 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1266 WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1267 WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1268
1269 /* enable anti pop S curve */
1270 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1271 (platform->vmid_s_curve << 8));
1272
1273 /* turn off vmid */
1274 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1275 ~WM8350_VMIDEN;
1276 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1277
1278 /* wait */
1279 schedule_timeout_interruptible(msecs_to_jiffies
1280 (platform->
1281 vmid_discharge_msecs));
1282
1283 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1284 (platform->vmid_s_curve << 8) |
1285 platform->dis_out1 |
1286 (platform->dis_out2 << 2) |
1287 (platform->dis_out3 << 4) |
1288 (platform->dis_out4 << 6));
1289
1290 /* turn off VBuf and drain */
1291 pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1292 ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1293 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1294 pm1 | WM8350_OUTPUT_DRAIN_EN);
1295
1296 /* wait */
1297 schedule_timeout_interruptible(msecs_to_jiffies
1298 (platform->drain_msecs));
1299
1300 pm1 &= ~WM8350_BIASEN;
1301 wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1302
1303 /* disable anti-pop */
1304 wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1305
1306 wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1307 WM8350_OUT1L_ENA);
1308 wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1309 WM8350_OUT1R_ENA);
1310 wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1311 WM8350_OUT2L_ENA);
1312 wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1313 WM8350_OUT2R_ENA);
1314
1315 /* disable clock gen */
1316 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1317 WM8350_SYSCLK_ENA);
1318
1319 regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1320 priv->supplies);
1321 break;
1322 }
ce6120cc 1323 codec->dapm.bias_level = level;
40aa4a30
MB		 1324 return 0;
1325}
1326
f0fba2ad 1327static int wm8350_suspend(struct snd_soc_codec *codec, pm_message_t state)
40aa4a30 1328{
40aa4a30
MB		 1329 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1330 return 0;
1331}
1332
f0fba2ad 1333static int wm8350_resume(struct snd_soc_codec *codec)
40aa4a30 1334{
40aa4a30
MB		 1335 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1336
40aa4a30
MB		 1337 return 0;
1338}
1339
6d3c26bc
MB		 1340static void wm8350_hp_work(struct wm8350_data *priv,
1341 struct wm8350_jack_data *jack,
1342 u16 mask)
a6ba2b2d 1343{
5a65edbc 1344 struct wm8350 *wm8350 = priv->codec.control_data;
a6ba2b2d
MB		 1345 u16 reg;
1346 int report;
6d3c26bc
MB		 1347
1348 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1349 if (reg & mask)
1350 report = jack->report;
1351 else
1352 report = 0;
1353
1354 snd_soc_jack_report(jack->jack, report, jack->report);
1355
1356}
1357
1358static void wm8350_hpl_work(struct work_struct *work)
1359{
1360 struct wm8350_data *priv =
1361 container_of(work, struct wm8350_data, hpl.work.work);
1362
1363 wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1364}
1365
1366static void wm8350_hpr_work(struct work_struct *work)
1367{
1368 struct wm8350_data *priv =
1369 container_of(work, struct wm8350_data, hpr.work.work);
1370
1371 wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1372}
1373
1374static irqreturn_t wm8350_hp_jack_handler(int irq, void *data)
1375{
1376 struct wm8350_data *priv = data;
1377 struct wm8350 *wm8350 = priv->codec.control_data;
a6ba2b2d
MB		 1378 struct wm8350_jack_data *jack = NULL;
1379
59f25070 1380 switch (irq - wm8350->irq_base) {
a6ba2b2d 1381 case WM8350_IRQ_CODEC_JCK_DET_L:
1435b940 1382#ifndef CONFIG_SND_SOC_WM8350_MODULE
2bbb5d66 1383 trace_snd_soc_jack_irq("WM8350 HPL");
1435b940 1384#endif
a6ba2b2d 1385 jack = &priv->hpl;
a6ba2b2d
MB		 1386 break;
1387
1388 case WM8350_IRQ_CODEC_JCK_DET_R:
1435b940 1389#ifndef CONFIG_SND_SOC_WM8350_MODULE
2bbb5d66 1390 trace_snd_soc_jack_irq("WM8350 HPR");
1435b940 1391#endif
a6ba2b2d 1392 jack = &priv->hpr;
a6ba2b2d
MB		 1393 break;
1394
1395 default:
1396 BUG();
1397 }
1398
6d3c26bc
MB		 1399 if (device_may_wakeup(wm8350->dev))
1400 pm_wakeup_event(wm8350->dev, 250);
a6ba2b2d 1401
6d3c26bc 1402 schedule_delayed_work(&jack->work, 200);
5a65edbc
MB		 1403
1404 return IRQ_HANDLED;
a6ba2b2d
MB		 1405}
1406
1407/**
1408 * wm8350_hp_jack_detect - Enable headphone jack detection.
1409 *
1410 * @codec: WM8350 codec
1411 * @which: left or right jack detect signal
1412 * @jack: jack to report detection events on
1413 * @report: value to report
1414 *
f06bce9c
MB		 1415 * Enables the headphone jack detection of the WM8350. If no report
1416 * is specified then detection is disabled.
a6ba2b2d
MB		 1417 */
1418int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1419 struct snd_soc_jack *jack, int report)
1420{
b2c812e2 1421 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
a6ba2b2d
MB		 1422 struct wm8350 *wm8350 = codec->control_data;
1423 int irq;
1424 int ena;
1425
1426 switch (which) {
1427 case WM8350_JDL:
1428 priv->hpl.jack = jack;
1429 priv->hpl.report = report;
1430 irq = WM8350_IRQ_CODEC_JCK_DET_L;
1431 ena = WM8350_JDL_ENA;
1432 break;
1433
1434 case WM8350_JDR:
1435 priv->hpr.jack = jack;
1436 priv->hpr.report = report;
1437 irq = WM8350_IRQ_CODEC_JCK_DET_R;
1438 ena = WM8350_JDR_ENA;
1439 break;
1440
1441 default:
1442 return -EINVAL;
1443 }
1444
f06bce9c
MB		 1445 if (report) {
1446 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1447 wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1448 } else {
1449 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1450 }
a6ba2b2d
MB		 1451
1452 /* Sync status */
59f25070 1453 wm8350_hp_jack_handler(irq + wm8350->irq_base, priv);
a6ba2b2d 1454
a6ba2b2d
MB		 1455 return 0;
1456}
1457EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1458
2a0761a3
MB		 1459static irqreturn_t wm8350_mic_handler(int irq, void *data)
1460{
1461 struct wm8350_data *priv = data;
1462 struct wm8350 *wm8350 = priv->codec.control_data;
1463 u16 reg;
1464 int report = 0;
1465
7116f452 1466#ifndef CONFIG_SND_SOC_WM8350_MODULE
2bbb5d66 1467 trace_snd_soc_jack_irq("WM8350 mic");
7116f452 1468#endif
2bbb5d66 1469
2a0761a3
MB		 1470 reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1471 if (reg & WM8350_JACK_MICSCD_LVL)
1472 report |= priv->mic.short_report;
1473 if (reg & WM8350_JACK_MICSD_LVL)
1474 report |= priv->mic.report;
1475
1476 snd_soc_jack_report(priv->mic.jack, report,
1477 priv->mic.report | priv->mic.short_report);
1478
1479 return IRQ_HANDLED;
1480}
1481
1482/**
1483 * wm8350_mic_jack_detect - Enable microphone jack detection.
1484 *
1485 * @codec: WM8350 codec
1486 * @jack: jack to report detection events on
1487 * @detect_report: value to report when presence detected
1488 * @short_report: value to report when microphone short detected
1489 *
f06bce9c
MB		 1490 * Enables the microphone jack detection of the WM8350. If both reports
1491 * are specified as zero then detection is disabled.
2a0761a3
MB		 1492 */
1493int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1494 struct snd_soc_jack *jack,
1495 int detect_report, int short_report)
1496{
b2c812e2 1497 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
2a0761a3
MB		 1498 struct wm8350 *wm8350 = codec->control_data;
1499
1500 priv->mic.jack = jack;
1501 priv->mic.report = detect_report;
1502 priv->mic.short_report = short_report;
1503
f06bce9c
MB		 1504 if (detect_report || short_report) {
1505 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1506 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1507 WM8350_MIC_DET_ENA);
1508 } else {
1509 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1510 WM8350_MIC_DET_ENA);
1511 }
2a0761a3 1512
2a0761a3
MB		 1513 return 0;
1514}
1515EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1516
f0fba2ad
LG		 1517#define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1518
1519#define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1520 SNDRV_PCM_FMTBIT_S20_3LE |\
1521 SNDRV_PCM_FMTBIT_S24_LE)
1522
1523static struct snd_soc_dai_ops wm8350_dai_ops = {
1524 .hw_params = wm8350_pcm_hw_params,
1525 .digital_mute = wm8350_mute,
1526 .trigger = wm8350_pcm_trigger,
1527 .set_fmt = wm8350_set_dai_fmt,
1528 .set_sysclk = wm8350_set_dai_sysclk,
1529 .set_pll = wm8350_set_fll,
1530 .set_clkdiv = wm8350_set_clkdiv,
1531};
1532
1533static struct snd_soc_dai_driver wm8350_dai = {
1534 .name = "wm8350-hifi",
1535 .playback = {
1536 .stream_name = "Playback",
1537 .channels_min = 1,
1538 .channels_max = 2,
1539 .rates = WM8350_RATES,
1540 .formats = WM8350_FORMATS,
1541 },
1542 .capture = {
1543 .stream_name = "Capture",
1544 .channels_min = 1,
1545 .channels_max = 2,
1546 .rates = WM8350_RATES,
1547 .formats = WM8350_FORMATS,
1548 },
1549 .ops = &wm8350_dai_ops,
1550};
40aa4a30 1551
f0fba2ad 1552static int wm8350_codec_probe(struct snd_soc_codec *codec)
40aa4a30 1553{
f0fba2ad 1554 struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
40aa4a30 1555 struct wm8350_data *priv;
40aa4a30
MB		 1556 struct wm8350_output *out1;
1557 struct wm8350_output *out2;
f0fba2ad 1558 int ret, i;
40aa4a30 1559
f0fba2ad
LG		 1560 if (wm8350->codec.platform_data == NULL) {
1561 dev_err(codec->dev, "No audio platform data supplied\n");
1562 return -EINVAL;
1563 }
1564
1565 priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL);
1566 if (priv == NULL)
1567 return -ENOMEM;
1568 snd_soc_codec_set_drvdata(codec, priv);
1569
1570 for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1571 priv->supplies[i].supply = supply_names[i];
1572
1573 ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1574 priv->supplies);
1575 if (ret != 0)
1576 goto err_priv;
1577
1578 wm8350->codec.codec = codec;
1579 codec->control_data = wm8350;
40aa4a30 1580
f0fba2ad
LG		 1581 /* Put the codec into reset if it wasn't already */
1582 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1583
ce6120cc 1584 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8350_pga_work);
6d3c26bc
MB		 1585 INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1586 INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
40aa4a30
MB		 1587
1588 /* Enable the codec */
1589 wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1590
1591 /* Enable robust clocking mode in ADC */
1592 wm8350_codec_write(codec, WM8350_SECURITY, 0xa7);
1593 wm8350_codec_write(codec, 0xde, 0x13);
1594 wm8350_codec_write(codec, WM8350_SECURITY, 0);
1595
1596 /* read OUT1 & OUT2 volumes */
1597 out1 = &priv->out1;
1598 out2 = &priv->out2;
1599 out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1600 WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1601 out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1602 WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1603 out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1604 WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1605 out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1606 WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1607 wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1608 wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1609 wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1610 wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1611
1612 /* Latch VU bits & mute */
1613 wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1614 WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1615 wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1616 WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1617 wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1618 WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1619 wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1620 WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1621
0049317e
MB		 1622 /* Make sure AIF tristating is disabled by default */
1623 wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1624
1625 /* Make sure we've got a sane companding setup too */
1626 wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1627 WM8350_DAC_COMP | WM8350_LOOPBACK);
1628
6a612746
MB		 1629 /* Make sure jack detect is disabled to start off with */
1630 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1631 WM8350_JDL_ENA | WM8350_JDR_ENA);
1632
a6ba2b2d 1633 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
5a65edbc
MB		 1634 wm8350_hp_jack_handler, 0, "Left jack detect",
1635 priv);
a6ba2b2d 1636 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
5a65edbc
MB		 1637 wm8350_hp_jack_handler, 0, "Right jack detect",
1638 priv);
2a0761a3
MB		 1639 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1640 wm8350_mic_handler, 0, "Microphone short", priv);
1641 wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1642 wm8350_mic_handler, 0, "Microphone detect", priv);
a6ba2b2d 1643
40aa4a30 1644
3e8e1952
IM		 1645 snd_soc_add_controls(codec, wm8350_snd_controls,
1646 ARRAY_SIZE(wm8350_snd_controls));
40aa4a30
MB		 1647 wm8350_add_widgets(codec);
1648
1649 wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1650
40aa4a30 1651 return 0;
f0fba2ad
LG		 1652
1653err_priv:
1654 kfree(priv);
1655 return ret;
40aa4a30
MB		 1656}
1657
f0fba2ad 1658static int wm8350_codec_remove(struct snd_soc_codec *codec)
40aa4a30 1659{
b2c812e2 1660 struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
f0fba2ad 1661 struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
40aa4a30 1662
a6ba2b2d
MB		 1663 wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1664 WM8350_JDL_ENA | WM8350_JDR_ENA);
1665 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1666
2a0761a3
MB		 1667 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1668 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
f99344fc
MB		 1669 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1670 wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
a6ba2b2d
MB		 1671
1672 priv->hpl.jack = NULL;
1673 priv->hpr.jack = NULL;
2a0761a3 1674 priv->mic.jack = NULL;
a6ba2b2d 1675
6d3c26bc
MB		 1676 cancel_delayed_work_sync(&priv->hpl.work);
1677 cancel_delayed_work_sync(&priv->hpr.work);
1678
40aa4a30
MB		 1679 /* if there was any work waiting then we run it now and
1680 * wait for its completion */
fdea0571 1681 flush_delayed_work_sync(&codec->dapm.delayed_work);
40aa4a30
MB		 1682
1683 wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF);
1684
1685 wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1686
f0fba2ad
LG		 1687 regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies);
1688 kfree(priv);
40aa4a30
MB		 1689 return 0;
1690}
1691
f0fba2ad
LG		 1692static struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
1693 .probe = wm8350_codec_probe,
1694 .remove = wm8350_codec_remove,
40aa4a30
MB		 1695 .suspend = wm8350_suspend,
1696 .resume = wm8350_resume,
f0fba2ad
LG		 1697 .read = wm8350_codec_read,
1698 .write = wm8350_codec_write,
1699 .set_bias_level = wm8350_set_bias_level,
40aa4a30 1700};
40aa4a30 1701
f0fba2ad 1702static int __devinit wm8350_probe(struct platform_device *pdev)
40aa4a30 1703{
f0fba2ad
LG		 1704 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350,
1705 &wm8350_dai, 1);
40aa4a30
MB		 1706}
1707
f0fba2ad 1708static int __devexit wm8350_remove(struct platform_device *pdev)
40aa4a30 1709{
f0fba2ad 1710 snd_soc_unregister_codec(&pdev->dev);
40aa4a30
MB		 1711 return 0;
1712}
1713
1714static struct platform_driver wm8350_codec_driver = {
1715 .driver = {
1716 .name = "wm8350-codec",
1717 .owner = THIS_MODULE,
1718 },
f0fba2ad
LG		 1719 .probe = wm8350_probe,
1720 .remove = __devexit_p(wm8350_remove),
40aa4a30
MB		 1721};
1722
1723static __init int wm8350_init(void)
1724{
1725 return platform_driver_register(&wm8350_codec_driver);
1726}
1727module_init(wm8350_init);
1728
1729static __exit void wm8350_exit(void)
1730{
1731 platform_driver_unregister(&wm8350_codec_driver);
1732}
1733module_exit(wm8350_exit);
1734
1735MODULE_DESCRIPTION("ASoC WM8350 driver");
1736MODULE_AUTHOR("Liam Girdwood");
1737MODULE_LICENSE("GPL");
1738MODULE_ALIAS("platform:wm8350-codec");
Linux kernel - Deliverables
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