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1 | /* |
2 | * wm8350.c -- WM8350 ALSA SoC audio driver | |
3 | * | |
4 | * Copyright (C) 2007, 2008 Wolfson Microelectronics PLC. | |
5 | * | |
64ca0404 | 6 | * Author: Liam Girdwood <lrg@slimlogic.co.uk> |
40aa4a30 MB |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/moduleparam.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/pm.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/mfd/wm8350/audio.h> | |
20 | #include <linux/mfd/wm8350/core.h> | |
21 | #include <linux/regulator/consumer.h> | |
22 | #include <sound/core.h> | |
23 | #include <sound/pcm.h> | |
24 | #include <sound/pcm_params.h> | |
25 | #include <sound/soc.h> | |
26 | #include <sound/soc-dapm.h> | |
27 | #include <sound/initval.h> | |
28 | #include <sound/tlv.h> | |
29 | ||
30 | #include "wm8350.h" | |
31 | ||
32 | #define WM8350_OUTn_0dB 0x39 | |
33 | ||
34 | #define WM8350_RAMP_NONE 0 | |
35 | #define WM8350_RAMP_UP 1 | |
36 | #define WM8350_RAMP_DOWN 2 | |
37 | ||
38 | /* We only include the analogue supplies here; the digital supplies | |
39 | * need to be available well before this driver can be probed. | |
40 | */ | |
41 | static const char *supply_names[] = { | |
42 | "AVDD", | |
43 | "HPVDD", | |
44 | }; | |
45 | ||
46 | struct wm8350_output { | |
47 | u16 active; | |
48 | u16 left_vol; | |
49 | u16 right_vol; | |
50 | u16 ramp; | |
51 | u16 mute; | |
52 | }; | |
53 | ||
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54 | struct wm8350_jack_data { |
55 | struct snd_soc_jack *jack; | |
56 | int report; | |
57 | }; | |
58 | ||
40aa4a30 MB |
59 | struct wm8350_data { |
60 | struct snd_soc_codec codec; | |
61 | struct wm8350_output out1; | |
62 | struct wm8350_output out2; | |
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63 | struct wm8350_jack_data hpl; |
64 | struct wm8350_jack_data hpr; | |
40aa4a30 MB |
65 | struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; |
66 | }; | |
67 | ||
68 | static unsigned int wm8350_codec_cache_read(struct snd_soc_codec *codec, | |
69 | unsigned int reg) | |
70 | { | |
71 | struct wm8350 *wm8350 = codec->control_data; | |
72 | return wm8350->reg_cache[reg]; | |
73 | } | |
74 | ||
75 | static unsigned int wm8350_codec_read(struct snd_soc_codec *codec, | |
76 | unsigned int reg) | |
77 | { | |
78 | struct wm8350 *wm8350 = codec->control_data; | |
79 | return wm8350_reg_read(wm8350, reg); | |
80 | } | |
81 | ||
82 | static int wm8350_codec_write(struct snd_soc_codec *codec, unsigned int reg, | |
83 | unsigned int value) | |
84 | { | |
85 | struct wm8350 *wm8350 = codec->control_data; | |
86 | return wm8350_reg_write(wm8350, reg, value); | |
87 | } | |
88 | ||
89 | /* | |
90 | * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown. | |
91 | */ | |
92 | static inline int wm8350_out1_ramp_step(struct snd_soc_codec *codec) | |
93 | { | |
94 | struct wm8350_data *wm8350_data = codec->private_data; | |
95 | struct wm8350_output *out1 = &wm8350_data->out1; | |
96 | struct wm8350 *wm8350 = codec->control_data; | |
97 | int left_complete = 0, right_complete = 0; | |
98 | u16 reg, val; | |
99 | ||
100 | /* left channel */ | |
101 | reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME); | |
102 | val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; | |
103 | ||
104 | if (out1->ramp == WM8350_RAMP_UP) { | |
105 | /* ramp step up */ | |
106 | if (val < out1->left_vol) { | |
107 | val++; | |
108 | reg &= ~WM8350_OUT1L_VOL_MASK; | |
109 | wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, | |
110 | reg | (val << WM8350_OUT1L_VOL_SHIFT)); | |
111 | } else | |
112 | left_complete = 1; | |
113 | } else if (out1->ramp == WM8350_RAMP_DOWN) { | |
114 | /* ramp step down */ | |
115 | if (val > 0) { | |
116 | val--; | |
117 | reg &= ~WM8350_OUT1L_VOL_MASK; | |
118 | wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, | |
119 | reg | (val << WM8350_OUT1L_VOL_SHIFT)); | |
120 | } else | |
121 | left_complete = 1; | |
122 | } else | |
123 | return 1; | |
124 | ||
125 | /* right channel */ | |
126 | reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME); | |
127 | val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; | |
128 | if (out1->ramp == WM8350_RAMP_UP) { | |
129 | /* ramp step up */ | |
130 | if (val < out1->right_vol) { | |
131 | val++; | |
132 | reg &= ~WM8350_OUT1R_VOL_MASK; | |
133 | wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, | |
134 | reg | (val << WM8350_OUT1R_VOL_SHIFT)); | |
135 | } else | |
136 | right_complete = 1; | |
137 | } else if (out1->ramp == WM8350_RAMP_DOWN) { | |
138 | /* ramp step down */ | |
139 | if (val > 0) { | |
140 | val--; | |
141 | reg &= ~WM8350_OUT1R_VOL_MASK; | |
142 | wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, | |
143 | reg | (val << WM8350_OUT1R_VOL_SHIFT)); | |
144 | } else | |
145 | right_complete = 1; | |
146 | } | |
147 | ||
148 | /* only hit the update bit if either volume has changed this step */ | |
149 | if (!left_complete || !right_complete) | |
150 | wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU); | |
151 | ||
152 | return left_complete & right_complete; | |
153 | } | |
154 | ||
155 | /* | |
156 | * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown. | |
157 | */ | |
158 | static inline int wm8350_out2_ramp_step(struct snd_soc_codec *codec) | |
159 | { | |
160 | struct wm8350_data *wm8350_data = codec->private_data; | |
161 | struct wm8350_output *out2 = &wm8350_data->out2; | |
162 | struct wm8350 *wm8350 = codec->control_data; | |
163 | int left_complete = 0, right_complete = 0; | |
164 | u16 reg, val; | |
165 | ||
166 | /* left channel */ | |
167 | reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME); | |
168 | val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; | |
169 | if (out2->ramp == WM8350_RAMP_UP) { | |
170 | /* ramp step up */ | |
171 | if (val < out2->left_vol) { | |
172 | val++; | |
173 | reg &= ~WM8350_OUT2L_VOL_MASK; | |
174 | wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, | |
175 | reg | (val << WM8350_OUT1L_VOL_SHIFT)); | |
176 | } else | |
177 | left_complete = 1; | |
178 | } else if (out2->ramp == WM8350_RAMP_DOWN) { | |
179 | /* ramp step down */ | |
180 | if (val > 0) { | |
181 | val--; | |
182 | reg &= ~WM8350_OUT2L_VOL_MASK; | |
183 | wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, | |
184 | reg | (val << WM8350_OUT1L_VOL_SHIFT)); | |
185 | } else | |
186 | left_complete = 1; | |
187 | } else | |
188 | return 1; | |
189 | ||
190 | /* right channel */ | |
191 | reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME); | |
192 | val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; | |
193 | if (out2->ramp == WM8350_RAMP_UP) { | |
194 | /* ramp step up */ | |
195 | if (val < out2->right_vol) { | |
196 | val++; | |
197 | reg &= ~WM8350_OUT2R_VOL_MASK; | |
198 | wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, | |
199 | reg | (val << WM8350_OUT1R_VOL_SHIFT)); | |
200 | } else | |
201 | right_complete = 1; | |
202 | } else if (out2->ramp == WM8350_RAMP_DOWN) { | |
203 | /* ramp step down */ | |
204 | if (val > 0) { | |
205 | val--; | |
206 | reg &= ~WM8350_OUT2R_VOL_MASK; | |
207 | wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, | |
208 | reg | (val << WM8350_OUT1R_VOL_SHIFT)); | |
209 | } else | |
210 | right_complete = 1; | |
211 | } | |
212 | ||
213 | /* only hit the update bit if either volume has changed this step */ | |
214 | if (!left_complete || !right_complete) | |
215 | wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU); | |
216 | ||
217 | return left_complete & right_complete; | |
218 | } | |
219 | ||
220 | /* | |
221 | * This work ramps both output PGAs at stream start/stop time to | |
222 | * minimise pop associated with DAPM power switching. | |
223 | * It's best to enable Zero Cross when ramping occurs to minimise any | |
224 | * zipper noises. | |
225 | */ | |
226 | static void wm8350_pga_work(struct work_struct *work) | |
227 | { | |
228 | struct snd_soc_codec *codec = | |
229 | container_of(work, struct snd_soc_codec, delayed_work.work); | |
230 | struct wm8350_data *wm8350_data = codec->private_data; | |
231 | struct wm8350_output *out1 = &wm8350_data->out1, | |
232 | *out2 = &wm8350_data->out2; | |
233 | int i, out1_complete, out2_complete; | |
234 | ||
235 | /* do we need to ramp at all ? */ | |
236 | if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE) | |
237 | return; | |
238 | ||
239 | /* PGA volumes have 6 bits of resolution to ramp */ | |
240 | for (i = 0; i <= 63; i++) { | |
241 | out1_complete = 1, out2_complete = 1; | |
242 | if (out1->ramp != WM8350_RAMP_NONE) | |
243 | out1_complete = wm8350_out1_ramp_step(codec); | |
244 | if (out2->ramp != WM8350_RAMP_NONE) | |
245 | out2_complete = wm8350_out2_ramp_step(codec); | |
246 | ||
247 | /* ramp finished ? */ | |
248 | if (out1_complete && out2_complete) | |
249 | break; | |
250 | ||
251 | /* we need to delay longer on the up ramp */ | |
252 | if (out1->ramp == WM8350_RAMP_UP || | |
253 | out2->ramp == WM8350_RAMP_UP) { | |
254 | /* delay is longer over 0dB as increases are larger */ | |
255 | if (i >= WM8350_OUTn_0dB) | |
256 | schedule_timeout_interruptible(msecs_to_jiffies | |
257 | (2)); | |
258 | else | |
259 | schedule_timeout_interruptible(msecs_to_jiffies | |
260 | (1)); | |
261 | } else | |
262 | udelay(50); /* doesn't matter if we delay longer */ | |
263 | } | |
264 | ||
265 | out1->ramp = WM8350_RAMP_NONE; | |
266 | out2->ramp = WM8350_RAMP_NONE; | |
267 | } | |
268 | ||
269 | /* | |
270 | * WM8350 Controls | |
271 | */ | |
272 | ||
273 | static int pga_event(struct snd_soc_dapm_widget *w, | |
274 | struct snd_kcontrol *kcontrol, int event) | |
275 | { | |
276 | struct snd_soc_codec *codec = w->codec; | |
277 | struct wm8350_data *wm8350_data = codec->private_data; | |
278 | struct wm8350_output *out; | |
279 | ||
280 | switch (w->shift) { | |
281 | case 0: | |
282 | case 1: | |
283 | out = &wm8350_data->out1; | |
284 | break; | |
285 | case 2: | |
286 | case 3: | |
287 | out = &wm8350_data->out2; | |
288 | break; | |
289 | ||
290 | default: | |
291 | BUG(); | |
292 | return -1; | |
293 | } | |
294 | ||
295 | switch (event) { | |
296 | case SND_SOC_DAPM_POST_PMU: | |
297 | out->ramp = WM8350_RAMP_UP; | |
298 | out->active = 1; | |
299 | ||
300 | if (!delayed_work_pending(&codec->delayed_work)) | |
301 | schedule_delayed_work(&codec->delayed_work, | |
302 | msecs_to_jiffies(1)); | |
303 | break; | |
304 | ||
305 | case SND_SOC_DAPM_PRE_PMD: | |
306 | out->ramp = WM8350_RAMP_DOWN; | |
307 | out->active = 0; | |
308 | ||
309 | if (!delayed_work_pending(&codec->delayed_work)) | |
310 | schedule_delayed_work(&codec->delayed_work, | |
311 | msecs_to_jiffies(1)); | |
312 | break; | |
313 | } | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol, | |
319 | struct snd_ctl_elem_value *ucontrol) | |
320 | { | |
321 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
322 | struct wm8350_data *wm8350_priv = codec->private_data; | |
323 | struct wm8350_output *out = NULL; | |
324 | struct soc_mixer_control *mc = | |
325 | (struct soc_mixer_control *)kcontrol->private_value; | |
326 | int ret; | |
327 | unsigned int reg = mc->reg; | |
328 | u16 val; | |
329 | ||
330 | /* For OUT1 and OUT2 we shadow the values and only actually write | |
331 | * them out when active in order to ensure the amplifier comes on | |
332 | * as quietly as possible. */ | |
333 | switch (reg) { | |
334 | case WM8350_LOUT1_VOLUME: | |
335 | out = &wm8350_priv->out1; | |
336 | break; | |
337 | case WM8350_LOUT2_VOLUME: | |
338 | out = &wm8350_priv->out2; | |
339 | break; | |
340 | default: | |
341 | break; | |
342 | } | |
343 | ||
344 | if (out) { | |
345 | out->left_vol = ucontrol->value.integer.value[0]; | |
346 | out->right_vol = ucontrol->value.integer.value[1]; | |
347 | if (!out->active) | |
348 | return 1; | |
349 | } | |
350 | ||
351 | ret = snd_soc_put_volsw_2r(kcontrol, ucontrol); | |
352 | if (ret < 0) | |
353 | return ret; | |
354 | ||
355 | /* now hit the volume update bits (always bit 8) */ | |
356 | val = wm8350_codec_read(codec, reg); | |
357 | wm8350_codec_write(codec, reg, val | WM8350_OUT1_VU); | |
358 | return 1; | |
359 | } | |
360 | ||
361 | static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol, | |
362 | struct snd_ctl_elem_value *ucontrol) | |
363 | { | |
364 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
365 | struct wm8350_data *wm8350_priv = codec->private_data; | |
366 | struct wm8350_output *out1 = &wm8350_priv->out1; | |
367 | struct wm8350_output *out2 = &wm8350_priv->out2; | |
368 | struct soc_mixer_control *mc = | |
369 | (struct soc_mixer_control *)kcontrol->private_value; | |
370 | unsigned int reg = mc->reg; | |
371 | ||
372 | /* If these are cached registers use the cache */ | |
373 | switch (reg) { | |
374 | case WM8350_LOUT1_VOLUME: | |
375 | ucontrol->value.integer.value[0] = out1->left_vol; | |
376 | ucontrol->value.integer.value[1] = out1->right_vol; | |
377 | return 0; | |
378 | ||
379 | case WM8350_LOUT2_VOLUME: | |
380 | ucontrol->value.integer.value[0] = out2->left_vol; | |
381 | ucontrol->value.integer.value[1] = out2->right_vol; | |
382 | return 0; | |
383 | ||
384 | default: | |
385 | break; | |
386 | } | |
387 | ||
388 | return snd_soc_get_volsw_2r(kcontrol, ucontrol); | |
389 | } | |
390 | ||
391 | /* double control with volume update */ | |
392 | #define SOC_WM8350_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \ | |
393 | xinvert, tlv_array) \ | |
394 | { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ | |
395 | .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ | |
396 | SNDRV_CTL_ELEM_ACCESS_READWRITE | \ | |
397 | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ | |
398 | .tlv.p = (tlv_array), \ | |
399 | .info = snd_soc_info_volsw_2r, \ | |
400 | .get = wm8350_get_volsw_2r, .put = wm8350_put_volsw_2r_vu, \ | |
401 | .private_value = (unsigned long)&(struct soc_mixer_control) \ | |
402 | {.reg = reg_left, .rreg = reg_right, .shift = xshift, \ | |
403 | .rshift = xshift, .max = xmax, .invert = xinvert}, } | |
404 | ||
405 | static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" }; | |
406 | static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" }; | |
407 | static const char *wm8350_dacmutem[] = { "Normal", "Soft" }; | |
408 | static const char *wm8350_dacmutes[] = { "Fast", "Slow" }; | |
409 | static const char *wm8350_dacfilter[] = { "Normal", "Sloping" }; | |
410 | static const char *wm8350_adcfilter[] = { "None", "High Pass" }; | |
411 | static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" }; | |
412 | static const char *wm8350_lr[] = { "Left", "Right" }; | |
413 | ||
414 | static const struct soc_enum wm8350_enum[] = { | |
415 | SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp), | |
416 | SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol), | |
417 | SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem), | |
418 | SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes), | |
419 | SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 12, 2, wm8350_dacfilter), | |
420 | SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter), | |
421 | SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp), | |
422 | SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol), | |
423 | SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr), | |
424 | }; | |
425 | ||
426 | static DECLARE_TLV_DB_LINEAR(pre_amp_tlv, -1200, 3525); | |
427 | static DECLARE_TLV_DB_LINEAR(out_pga_tlv, -5700, 600); | |
428 | static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1); | |
429 | static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1); | |
430 | static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1); | |
431 | ||
432 | static const unsigned int capture_sd_tlv[] = { | |
433 | TLV_DB_RANGE_HEAD(2), | |
434 | 0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1), | |
435 | 13, 15, TLV_DB_SCALE_ITEM(0, 0, 0), | |
436 | }; | |
437 | ||
438 | static const struct snd_kcontrol_new wm8350_snd_controls[] = { | |
439 | SOC_ENUM("Playback Deemphasis", wm8350_enum[0]), | |
440 | SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]), | |
441 | SOC_WM8350_DOUBLE_R_TLV("Playback PCM Volume", | |
442 | WM8350_DAC_DIGITAL_VOLUME_L, | |
443 | WM8350_DAC_DIGITAL_VOLUME_R, | |
444 | 0, 255, 0, dac_pcm_tlv), | |
445 | SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]), | |
446 | SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]), | |
447 | SOC_ENUM("Playback PCM Filter", wm8350_enum[4]), | |
448 | SOC_ENUM("Capture PCM Filter", wm8350_enum[5]), | |
449 | SOC_ENUM("Capture PCM HP Filter", wm8350_enum[6]), | |
450 | SOC_ENUM("Capture ADC Inversion", wm8350_enum[7]), | |
451 | SOC_WM8350_DOUBLE_R_TLV("Capture PCM Volume", | |
452 | WM8350_ADC_DIGITAL_VOLUME_L, | |
453 | WM8350_ADC_DIGITAL_VOLUME_R, | |
454 | 0, 255, 0, adc_pcm_tlv), | |
455 | SOC_DOUBLE_TLV("Capture Sidetone Volume", | |
456 | WM8350_ADC_DIVIDER, | |
457 | 8, 4, 15, 1, capture_sd_tlv), | |
458 | SOC_WM8350_DOUBLE_R_TLV("Capture Volume", | |
459 | WM8350_LEFT_INPUT_VOLUME, | |
460 | WM8350_RIGHT_INPUT_VOLUME, | |
461 | 2, 63, 0, pre_amp_tlv), | |
462 | SOC_DOUBLE_R("Capture ZC Switch", | |
463 | WM8350_LEFT_INPUT_VOLUME, | |
464 | WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0), | |
465 | SOC_SINGLE_TLV("Left Input Left Sidetone Volume", | |
466 | WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv), | |
467 | SOC_SINGLE_TLV("Left Input Right Sidetone Volume", | |
468 | WM8350_OUTPUT_LEFT_MIXER_VOLUME, | |
469 | 5, 7, 0, out_mix_tlv), | |
470 | SOC_SINGLE_TLV("Left Input Bypass Volume", | |
471 | WM8350_OUTPUT_LEFT_MIXER_VOLUME, | |
472 | 9, 7, 0, out_mix_tlv), | |
473 | SOC_SINGLE_TLV("Right Input Left Sidetone Volume", | |
474 | WM8350_OUTPUT_RIGHT_MIXER_VOLUME, | |
475 | 1, 7, 0, out_mix_tlv), | |
476 | SOC_SINGLE_TLV("Right Input Right Sidetone Volume", | |
477 | WM8350_OUTPUT_RIGHT_MIXER_VOLUME, | |
478 | 5, 7, 0, out_mix_tlv), | |
479 | SOC_SINGLE_TLV("Right Input Bypass Volume", | |
480 | WM8350_OUTPUT_RIGHT_MIXER_VOLUME, | |
481 | 13, 7, 0, out_mix_tlv), | |
482 | SOC_SINGLE("Left Input Mixer +20dB Switch", | |
483 | WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0), | |
484 | SOC_SINGLE("Right Input Mixer +20dB Switch", | |
485 | WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0), | |
486 | SOC_SINGLE_TLV("Out4 Capture Volume", | |
487 | WM8350_INPUT_MIXER_VOLUME, | |
488 | 1, 7, 0, out_mix_tlv), | |
489 | SOC_WM8350_DOUBLE_R_TLV("Out1 Playback Volume", | |
490 | WM8350_LOUT1_VOLUME, | |
491 | WM8350_ROUT1_VOLUME, | |
492 | 2, 63, 0, out_pga_tlv), | |
493 | SOC_DOUBLE_R("Out1 Playback ZC Switch", | |
494 | WM8350_LOUT1_VOLUME, | |
495 | WM8350_ROUT1_VOLUME, 13, 1, 0), | |
496 | SOC_WM8350_DOUBLE_R_TLV("Out2 Playback Volume", | |
497 | WM8350_LOUT2_VOLUME, | |
498 | WM8350_ROUT2_VOLUME, | |
499 | 2, 63, 0, out_pga_tlv), | |
500 | SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME, | |
501 | WM8350_ROUT2_VOLUME, 13, 1, 0), | |
502 | SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0), | |
503 | SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME, | |
504 | 5, 7, 0, out_mix_tlv), | |
505 | ||
506 | SOC_DOUBLE_R("Out1 Playback Switch", | |
507 | WM8350_LOUT1_VOLUME, | |
508 | WM8350_ROUT1_VOLUME, | |
509 | 14, 1, 1), | |
510 | SOC_DOUBLE_R("Out2 Playback Switch", | |
511 | WM8350_LOUT2_VOLUME, | |
512 | WM8350_ROUT2_VOLUME, | |
513 | 14, 1, 1), | |
514 | }; | |
515 | ||
516 | /* | |
517 | * DAPM Controls | |
518 | */ | |
519 | ||
520 | /* Left Playback Mixer */ | |
521 | static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = { | |
522 | SOC_DAPM_SINGLE("Playback Switch", | |
523 | WM8350_LEFT_MIXER_CONTROL, 11, 1, 0), | |
524 | SOC_DAPM_SINGLE("Left Bypass Switch", | |
525 | WM8350_LEFT_MIXER_CONTROL, 2, 1, 0), | |
526 | SOC_DAPM_SINGLE("Right Playback Switch", | |
527 | WM8350_LEFT_MIXER_CONTROL, 12, 1, 0), | |
528 | SOC_DAPM_SINGLE("Left Sidetone Switch", | |
529 | WM8350_LEFT_MIXER_CONTROL, 0, 1, 0), | |
530 | SOC_DAPM_SINGLE("Right Sidetone Switch", | |
531 | WM8350_LEFT_MIXER_CONTROL, 1, 1, 0), | |
532 | }; | |
533 | ||
534 | /* Right Playback Mixer */ | |
535 | static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = { | |
536 | SOC_DAPM_SINGLE("Playback Switch", | |
537 | WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0), | |
538 | SOC_DAPM_SINGLE("Right Bypass Switch", | |
539 | WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0), | |
540 | SOC_DAPM_SINGLE("Left Playback Switch", | |
541 | WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0), | |
542 | SOC_DAPM_SINGLE("Left Sidetone Switch", | |
543 | WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0), | |
544 | SOC_DAPM_SINGLE("Right Sidetone Switch", | |
545 | WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0), | |
546 | }; | |
547 | ||
548 | /* Out4 Mixer */ | |
549 | static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = { | |
550 | SOC_DAPM_SINGLE("Right Playback Switch", | |
551 | WM8350_OUT4_MIXER_CONTROL, 12, 1, 0), | |
552 | SOC_DAPM_SINGLE("Left Playback Switch", | |
553 | WM8350_OUT4_MIXER_CONTROL, 11, 1, 0), | |
554 | SOC_DAPM_SINGLE("Right Capture Switch", | |
555 | WM8350_OUT4_MIXER_CONTROL, 9, 1, 0), | |
556 | SOC_DAPM_SINGLE("Out3 Playback Switch", | |
557 | WM8350_OUT4_MIXER_CONTROL, 2, 1, 0), | |
558 | SOC_DAPM_SINGLE("Right Mixer Switch", | |
559 | WM8350_OUT4_MIXER_CONTROL, 1, 1, 0), | |
560 | SOC_DAPM_SINGLE("Left Mixer Switch", | |
561 | WM8350_OUT4_MIXER_CONTROL, 0, 1, 0), | |
562 | }; | |
563 | ||
564 | /* Out3 Mixer */ | |
565 | static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = { | |
566 | SOC_DAPM_SINGLE("Left Playback Switch", | |
567 | WM8350_OUT3_MIXER_CONTROL, 11, 1, 0), | |
568 | SOC_DAPM_SINGLE("Left Capture Switch", | |
569 | WM8350_OUT3_MIXER_CONTROL, 8, 1, 0), | |
570 | SOC_DAPM_SINGLE("Out4 Playback Switch", | |
571 | WM8350_OUT3_MIXER_CONTROL, 3, 1, 0), | |
572 | SOC_DAPM_SINGLE("Left Mixer Switch", | |
573 | WM8350_OUT3_MIXER_CONTROL, 0, 1, 0), | |
574 | }; | |
575 | ||
576 | /* Left Input Mixer */ | |
577 | static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = { | |
578 | SOC_DAPM_SINGLE_TLV("L2 Capture Volume", | |
579 | WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv), | |
580 | SOC_DAPM_SINGLE_TLV("L3 Capture Volume", | |
581 | WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv), | |
582 | SOC_DAPM_SINGLE("PGA Capture Switch", | |
583 | WM8350_LEFT_INPUT_VOLUME, 14, 1, 0), | |
584 | }; | |
585 | ||
586 | /* Right Input Mixer */ | |
587 | static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = { | |
588 | SOC_DAPM_SINGLE_TLV("L2 Capture Volume", | |
589 | WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv), | |
590 | SOC_DAPM_SINGLE_TLV("L3 Capture Volume", | |
591 | WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv), | |
592 | SOC_DAPM_SINGLE("PGA Capture Switch", | |
593 | WM8350_RIGHT_INPUT_VOLUME, 14, 1, 0), | |
594 | }; | |
595 | ||
596 | /* Left Mic Mixer */ | |
597 | static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = { | |
598 | SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0), | |
599 | SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0), | |
600 | SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0), | |
601 | }; | |
602 | ||
603 | /* Right Mic Mixer */ | |
604 | static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = { | |
605 | SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0), | |
606 | SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0), | |
607 | SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0), | |
608 | }; | |
609 | ||
610 | /* Beep Switch */ | |
611 | static const struct snd_kcontrol_new wm8350_beep_switch_controls = | |
612 | SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1); | |
613 | ||
614 | /* Out4 Capture Mux */ | |
615 | static const struct snd_kcontrol_new wm8350_out4_capture_controls = | |
616 | SOC_DAPM_ENUM("Route", wm8350_enum[8]); | |
617 | ||
618 | static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = { | |
619 | ||
620 | SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0), | |
621 | SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0), | |
622 | SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL, | |
623 | 0, pga_event, | |
624 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
625 | SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0, | |
626 | pga_event, | |
627 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
628 | SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL, | |
629 | 0, pga_event, | |
630 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
631 | SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0, | |
632 | pga_event, | |
633 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), | |
634 | ||
635 | SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2, | |
636 | 7, 0, &wm8350_right_capt_mixer_controls[0], | |
637 | ARRAY_SIZE(wm8350_right_capt_mixer_controls)), | |
638 | ||
639 | SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2, | |
640 | 6, 0, &wm8350_left_capt_mixer_controls[0], | |
641 | ARRAY_SIZE(wm8350_left_capt_mixer_controls)), | |
642 | ||
643 | SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0, | |
644 | &wm8350_out4_mixer_controls[0], | |
645 | ARRAY_SIZE(wm8350_out4_mixer_controls)), | |
646 | ||
647 | SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0, | |
648 | &wm8350_out3_mixer_controls[0], | |
649 | ARRAY_SIZE(wm8350_out3_mixer_controls)), | |
650 | ||
651 | SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0, | |
652 | &wm8350_right_play_mixer_controls[0], | |
653 | ARRAY_SIZE(wm8350_right_play_mixer_controls)), | |
654 | ||
655 | SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0, | |
656 | &wm8350_left_play_mixer_controls[0], | |
657 | ARRAY_SIZE(wm8350_left_play_mixer_controls)), | |
658 | ||
659 | SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0, | |
660 | &wm8350_left_mic_mixer_controls[0], | |
661 | ARRAY_SIZE(wm8350_left_mic_mixer_controls)), | |
662 | ||
663 | SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0, | |
664 | &wm8350_right_mic_mixer_controls[0], | |
665 | ARRAY_SIZE(wm8350_right_mic_mixer_controls)), | |
666 | ||
667 | /* virtual mixer for Beep and Out2R */ | |
668 | SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0), | |
669 | ||
670 | SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0, | |
671 | &wm8350_beep_switch_controls), | |
672 | ||
673 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", | |
674 | WM8350_POWER_MGMT_4, 3, 0), | |
675 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", | |
676 | WM8350_POWER_MGMT_4, 2, 0), | |
677 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", | |
678 | WM8350_POWER_MGMT_4, 5, 0), | |
679 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", | |
680 | WM8350_POWER_MGMT_4, 4, 0), | |
681 | ||
682 | SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0), | |
683 | ||
684 | SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0, | |
685 | &wm8350_out4_capture_controls), | |
686 | ||
687 | SND_SOC_DAPM_OUTPUT("OUT1R"), | |
688 | SND_SOC_DAPM_OUTPUT("OUT1L"), | |
689 | SND_SOC_DAPM_OUTPUT("OUT2R"), | |
690 | SND_SOC_DAPM_OUTPUT("OUT2L"), | |
691 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
692 | SND_SOC_DAPM_OUTPUT("OUT4"), | |
693 | ||
694 | SND_SOC_DAPM_INPUT("IN1RN"), | |
695 | SND_SOC_DAPM_INPUT("IN1RP"), | |
696 | SND_SOC_DAPM_INPUT("IN2R"), | |
697 | SND_SOC_DAPM_INPUT("IN1LP"), | |
698 | SND_SOC_DAPM_INPUT("IN1LN"), | |
699 | SND_SOC_DAPM_INPUT("IN2L"), | |
700 | SND_SOC_DAPM_INPUT("IN3R"), | |
701 | SND_SOC_DAPM_INPUT("IN3L"), | |
702 | }; | |
703 | ||
704 | static const struct snd_soc_dapm_route audio_map[] = { | |
705 | ||
706 | /* left playback mixer */ | |
707 | {"Left Playback Mixer", "Playback Switch", "Left DAC"}, | |
708 | {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"}, | |
709 | {"Left Playback Mixer", "Right Playback Switch", "Right DAC"}, | |
710 | {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, | |
711 | {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, | |
712 | ||
713 | /* right playback mixer */ | |
714 | {"Right Playback Mixer", "Playback Switch", "Right DAC"}, | |
715 | {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"}, | |
716 | {"Right Playback Mixer", "Left Playback Switch", "Left DAC"}, | |
717 | {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"}, | |
718 | {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"}, | |
719 | ||
720 | /* out4 playback mixer */ | |
721 | {"Out4 Mixer", "Right Playback Switch", "Right DAC"}, | |
722 | {"Out4 Mixer", "Left Playback Switch", "Left DAC"}, | |
723 | {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"}, | |
724 | {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"}, | |
725 | {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"}, | |
726 | {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, | |
727 | {"OUT4", NULL, "Out4 Mixer"}, | |
728 | ||
729 | /* out3 playback mixer */ | |
730 | {"Out3 Mixer", "Left Playback Switch", "Left DAC"}, | |
731 | {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"}, | |
732 | {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"}, | |
733 | {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"}, | |
734 | {"OUT3", NULL, "Out3 Mixer"}, | |
735 | ||
736 | /* out2 */ | |
737 | {"Right Out2 PGA", NULL, "Right Playback Mixer"}, | |
738 | {"Left Out2 PGA", NULL, "Left Playback Mixer"}, | |
739 | {"OUT2L", NULL, "Left Out2 PGA"}, | |
740 | {"OUT2R", NULL, "Right Out2 PGA"}, | |
741 | ||
742 | /* out1 */ | |
743 | {"Right Out1 PGA", NULL, "Right Playback Mixer"}, | |
744 | {"Left Out1 PGA", NULL, "Left Playback Mixer"}, | |
745 | {"OUT1L", NULL, "Left Out1 PGA"}, | |
746 | {"OUT1R", NULL, "Right Out1 PGA"}, | |
747 | ||
748 | /* ADCs */ | |
749 | {"Left ADC", NULL, "Left Capture Mixer"}, | |
750 | {"Right ADC", NULL, "Right Capture Mixer"}, | |
751 | ||
752 | /* Left capture mixer */ | |
753 | {"Left Capture Mixer", "L2 Capture Volume", "IN2L"}, | |
754 | {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"}, | |
755 | {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"}, | |
756 | {"Left Capture Mixer", NULL, "Out4 Capture Channel"}, | |
757 | ||
758 | /* Right capture mixer */ | |
759 | {"Right Capture Mixer", "L2 Capture Volume", "IN2R"}, | |
760 | {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"}, | |
761 | {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"}, | |
762 | {"Right Capture Mixer", NULL, "Out4 Capture Channel"}, | |
763 | ||
764 | /* L3 Inputs */ | |
765 | {"IN3L PGA", NULL, "IN3L"}, | |
766 | {"IN3R PGA", NULL, "IN3R"}, | |
767 | ||
768 | /* Left Mic mixer */ | |
769 | {"Left Mic Mixer", "INN Capture Switch", "IN1LN"}, | |
770 | {"Left Mic Mixer", "INP Capture Switch", "IN1LP"}, | |
771 | {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"}, | |
772 | ||
773 | /* Right Mic mixer */ | |
774 | {"Right Mic Mixer", "INN Capture Switch", "IN1RN"}, | |
775 | {"Right Mic Mixer", "INP Capture Switch", "IN1RP"}, | |
776 | {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"}, | |
777 | ||
778 | /* out 4 capture */ | |
779 | {"Out4 Capture Channel", NULL, "Out4 Mixer"}, | |
780 | ||
781 | /* Beep */ | |
782 | {"Beep", NULL, "IN3R PGA"}, | |
783 | }; | |
784 | ||
40aa4a30 MB |
785 | static int wm8350_add_widgets(struct snd_soc_codec *codec) |
786 | { | |
787 | int ret; | |
788 | ||
789 | ret = snd_soc_dapm_new_controls(codec, | |
790 | wm8350_dapm_widgets, | |
791 | ARRAY_SIZE(wm8350_dapm_widgets)); | |
792 | if (ret != 0) { | |
793 | dev_err(codec->dev, "dapm control register failed\n"); | |
794 | return ret; | |
795 | } | |
796 | ||
797 | /* set up audio paths */ | |
798 | ret = snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map)); | |
799 | if (ret != 0) { | |
800 | dev_err(codec->dev, "DAPM route register failed\n"); | |
801 | return ret; | |
802 | } | |
803 | ||
804 | return snd_soc_dapm_new_widgets(codec); | |
805 | } | |
806 | ||
807 | static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
808 | int clk_id, unsigned int freq, int dir) | |
809 | { | |
810 | struct snd_soc_codec *codec = codec_dai->codec; | |
811 | struct wm8350 *wm8350 = codec->control_data; | |
812 | u16 fll_4; | |
813 | ||
814 | switch (clk_id) { | |
815 | case WM8350_MCLK_SEL_MCLK: | |
816 | wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1, | |
817 | WM8350_MCLK_SEL); | |
818 | break; | |
819 | case WM8350_MCLK_SEL_PLL_MCLK: | |
820 | case WM8350_MCLK_SEL_PLL_DAC: | |
821 | case WM8350_MCLK_SEL_PLL_ADC: | |
822 | case WM8350_MCLK_SEL_PLL_32K: | |
823 | wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1, | |
824 | WM8350_MCLK_SEL); | |
825 | fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & | |
826 | ~WM8350_FLL_CLK_SRC_MASK; | |
827 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id); | |
828 | break; | |
829 | } | |
830 | ||
831 | /* MCLK direction */ | |
832 | if (dir == WM8350_MCLK_DIR_OUT) | |
833 | wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2, | |
834 | WM8350_MCLK_DIR); | |
835 | else | |
836 | wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2, | |
837 | WM8350_MCLK_DIR); | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
842 | static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div) | |
843 | { | |
844 | struct snd_soc_codec *codec = codec_dai->codec; | |
845 | u16 val; | |
846 | ||
847 | switch (div_id) { | |
848 | case WM8350_ADC_CLKDIV: | |
849 | val = wm8350_codec_read(codec, WM8350_ADC_DIVIDER) & | |
850 | ~WM8350_ADC_CLKDIV_MASK; | |
851 | wm8350_codec_write(codec, WM8350_ADC_DIVIDER, val | div); | |
852 | break; | |
853 | case WM8350_DAC_CLKDIV: | |
854 | val = wm8350_codec_read(codec, WM8350_DAC_CLOCK_CONTROL) & | |
855 | ~WM8350_DAC_CLKDIV_MASK; | |
856 | wm8350_codec_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div); | |
857 | break; | |
858 | case WM8350_BCLK_CLKDIV: | |
859 | val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & | |
860 | ~WM8350_BCLK_DIV_MASK; | |
861 | wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); | |
862 | break; | |
863 | case WM8350_OPCLK_CLKDIV: | |
864 | val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & | |
865 | ~WM8350_OPCLK_DIV_MASK; | |
866 | wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); | |
867 | break; | |
868 | case WM8350_SYS_CLKDIV: | |
869 | val = wm8350_codec_read(codec, WM8350_CLOCK_CONTROL_1) & | |
870 | ~WM8350_MCLK_DIV_MASK; | |
871 | wm8350_codec_write(codec, WM8350_CLOCK_CONTROL_1, val | div); | |
872 | break; | |
873 | case WM8350_DACLR_CLKDIV: | |
874 | val = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & | |
875 | ~WM8350_DACLRC_RATE_MASK; | |
876 | wm8350_codec_write(codec, WM8350_DAC_LR_RATE, val | div); | |
877 | break; | |
878 | case WM8350_ADCLR_CLKDIV: | |
879 | val = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & | |
880 | ~WM8350_ADCLRC_RATE_MASK; | |
881 | wm8350_codec_write(codec, WM8350_ADC_LR_RATE, val | div); | |
882 | break; | |
883 | default: | |
884 | return -EINVAL; | |
885 | } | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
890 | static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) | |
891 | { | |
892 | struct snd_soc_codec *codec = codec_dai->codec; | |
893 | u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & | |
894 | ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK); | |
895 | u16 master = wm8350_codec_read(codec, WM8350_AI_DAC_CONTROL) & | |
896 | ~WM8350_BCLK_MSTR; | |
897 | u16 dac_lrc = wm8350_codec_read(codec, WM8350_DAC_LR_RATE) & | |
898 | ~WM8350_DACLRC_ENA; | |
899 | u16 adc_lrc = wm8350_codec_read(codec, WM8350_ADC_LR_RATE) & | |
900 | ~WM8350_ADCLRC_ENA; | |
901 | ||
902 | /* set master/slave audio interface */ | |
903 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
904 | case SND_SOC_DAIFMT_CBM_CFM: | |
905 | master |= WM8350_BCLK_MSTR; | |
906 | dac_lrc |= WM8350_DACLRC_ENA; | |
907 | adc_lrc |= WM8350_ADCLRC_ENA; | |
908 | break; | |
909 | case SND_SOC_DAIFMT_CBS_CFS: | |
910 | break; | |
911 | default: | |
912 | return -EINVAL; | |
913 | } | |
914 | ||
915 | /* interface format */ | |
916 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
917 | case SND_SOC_DAIFMT_I2S: | |
918 | iface |= 0x2 << 8; | |
919 | break; | |
920 | case SND_SOC_DAIFMT_RIGHT_J: | |
921 | break; | |
922 | case SND_SOC_DAIFMT_LEFT_J: | |
923 | iface |= 0x1 << 8; | |
924 | break; | |
925 | case SND_SOC_DAIFMT_DSP_A: | |
926 | iface |= 0x3 << 8; | |
927 | break; | |
928 | case SND_SOC_DAIFMT_DSP_B: | |
929 | iface |= 0x3 << 8; /* lg not sure which mode */ | |
930 | break; | |
931 | default: | |
932 | return -EINVAL; | |
933 | } | |
934 | ||
935 | /* clock inversion */ | |
936 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
937 | case SND_SOC_DAIFMT_NB_NF: | |
938 | break; | |
939 | case SND_SOC_DAIFMT_IB_IF: | |
940 | iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV; | |
941 | break; | |
942 | case SND_SOC_DAIFMT_IB_NF: | |
943 | iface |= WM8350_AIF_BCLK_INV; | |
944 | break; | |
945 | case SND_SOC_DAIFMT_NB_IF: | |
946 | iface |= WM8350_AIF_LRCLK_INV; | |
947 | break; | |
948 | default: | |
949 | return -EINVAL; | |
950 | } | |
951 | ||
952 | wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); | |
953 | wm8350_codec_write(codec, WM8350_AI_DAC_CONTROL, master); | |
954 | wm8350_codec_write(codec, WM8350_DAC_LR_RATE, dac_lrc); | |
955 | wm8350_codec_write(codec, WM8350_ADC_LR_RATE, adc_lrc); | |
956 | return 0; | |
957 | } | |
958 | ||
959 | static int wm8350_pcm_trigger(struct snd_pcm_substream *substream, | |
960 | int cmd, struct snd_soc_dai *codec_dai) | |
961 | { | |
962 | struct snd_soc_codec *codec = codec_dai->codec; | |
963 | int master = wm8350_codec_cache_read(codec, WM8350_AI_DAC_CONTROL) & | |
964 | WM8350_BCLK_MSTR; | |
965 | int enabled = 0; | |
966 | ||
967 | /* Check that the DACs or ADCs are enabled since they are | |
968 | * required for LRC in master mode. The DACs or ADCs need a | |
969 | * valid audio path i.e. pin -> ADC or DAC -> pin before | |
970 | * the LRC will be enabled in master mode. */ | |
971 | if (!master && cmd != SNDRV_PCM_TRIGGER_START) | |
972 | return 0; | |
973 | ||
974 | if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { | |
975 | enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) & | |
976 | (WM8350_ADCR_ENA | WM8350_ADCL_ENA); | |
977 | } else { | |
978 | enabled = wm8350_codec_cache_read(codec, WM8350_POWER_MGMT_4) & | |
979 | (WM8350_DACR_ENA | WM8350_DACL_ENA); | |
980 | } | |
981 | ||
982 | if (!enabled) { | |
983 | dev_err(codec->dev, | |
984 | "%s: invalid audio path - no clocks available\n", | |
985 | __func__); | |
986 | return -EINVAL; | |
987 | } | |
988 | return 0; | |
989 | } | |
990 | ||
991 | static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream, | |
992 | struct snd_pcm_hw_params *params, | |
993 | struct snd_soc_dai *codec_dai) | |
994 | { | |
995 | struct snd_soc_codec *codec = codec_dai->codec; | |
996 | u16 iface = wm8350_codec_read(codec, WM8350_AI_FORMATING) & | |
997 | ~WM8350_AIF_WL_MASK; | |
998 | ||
999 | /* bit size */ | |
1000 | switch (params_format(params)) { | |
1001 | case SNDRV_PCM_FORMAT_S16_LE: | |
1002 | break; | |
1003 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1004 | iface |= 0x1 << 10; | |
1005 | break; | |
1006 | case SNDRV_PCM_FORMAT_S24_LE: | |
1007 | iface |= 0x2 << 10; | |
1008 | break; | |
1009 | case SNDRV_PCM_FORMAT_S32_LE: | |
1010 | iface |= 0x3 << 10; | |
1011 | break; | |
1012 | } | |
1013 | ||
1014 | wm8350_codec_write(codec, WM8350_AI_FORMATING, iface); | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | static int wm8350_mute(struct snd_soc_dai *dai, int mute) | |
1019 | { | |
1020 | struct snd_soc_codec *codec = dai->codec; | |
1021 | struct wm8350 *wm8350 = codec->control_data; | |
1022 | ||
1023 | if (mute) | |
1024 | wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); | |
1025 | else | |
1026 | wm8350_clear_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); | |
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | /* FLL divisors */ | |
1031 | struct _fll_div { | |
1032 | int div; /* FLL_OUTDIV */ | |
1033 | int n; | |
1034 | int k; | |
1035 | int ratio; /* FLL_FRATIO */ | |
1036 | }; | |
1037 | ||
1038 | /* The size in bits of the fll divide multiplied by 10 | |
1039 | * to allow rounding later */ | |
1040 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
1041 | ||
1042 | static inline int fll_factors(struct _fll_div *fll_div, unsigned int input, | |
1043 | unsigned int output) | |
1044 | { | |
1045 | u64 Kpart; | |
1046 | unsigned int t1, t2, K, Nmod; | |
1047 | ||
1048 | if (output >= 2815250 && output <= 3125000) | |
1049 | fll_div->div = 0x4; | |
1050 | else if (output >= 5625000 && output <= 6250000) | |
1051 | fll_div->div = 0x3; | |
1052 | else if (output >= 11250000 && output <= 12500000) | |
1053 | fll_div->div = 0x2; | |
1054 | else if (output >= 22500000 && output <= 25000000) | |
1055 | fll_div->div = 0x1; | |
1056 | else { | |
1057 | printk(KERN_ERR "wm8350: fll freq %d out of range\n", output); | |
1058 | return -EINVAL; | |
1059 | } | |
1060 | ||
1061 | if (input > 48000) | |
1062 | fll_div->ratio = 1; | |
1063 | else | |
1064 | fll_div->ratio = 8; | |
1065 | ||
1066 | t1 = output * (1 << (fll_div->div + 1)); | |
1067 | t2 = input * fll_div->ratio; | |
1068 | ||
1069 | fll_div->n = t1 / t2; | |
1070 | Nmod = t1 % t2; | |
1071 | ||
1072 | if (Nmod) { | |
1073 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
1074 | do_div(Kpart, t2); | |
1075 | K = Kpart & 0xFFFFFFFF; | |
1076 | ||
1077 | /* Check if we need to round */ | |
1078 | if ((K % 10) >= 5) | |
1079 | K += 5; | |
1080 | ||
1081 | /* Move down to proper range now rounding is done */ | |
1082 | K /= 10; | |
1083 | fll_div->k = K; | |
1084 | } else | |
1085 | fll_div->k = 0; | |
1086 | ||
1087 | return 0; | |
1088 | } | |
1089 | ||
1090 | static int wm8350_set_fll(struct snd_soc_dai *codec_dai, | |
1091 | int pll_id, unsigned int freq_in, | |
1092 | unsigned int freq_out) | |
1093 | { | |
1094 | struct snd_soc_codec *codec = codec_dai->codec; | |
1095 | struct wm8350 *wm8350 = codec->control_data; | |
1096 | struct _fll_div fll_div; | |
1097 | int ret = 0; | |
1098 | u16 fll_1, fll_4; | |
1099 | ||
1100 | /* power down FLL - we need to do this for reconfiguration */ | |
1101 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, | |
1102 | WM8350_FLL_ENA | WM8350_FLL_OSC_ENA); | |
1103 | ||
1104 | if (freq_out == 0 || freq_in == 0) | |
1105 | return ret; | |
1106 | ||
1107 | ret = fll_factors(&fll_div, freq_in, freq_out); | |
1108 | if (ret < 0) | |
1109 | return ret; | |
1110 | dev_dbg(wm8350->dev, | |
1111 | "FLL in %d FLL out %d N 0x%x K 0x%x div %d ratio %d", | |
1112 | freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div, | |
1113 | fll_div.ratio); | |
1114 | ||
1115 | /* set up N.K & dividers */ | |
1116 | fll_1 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_1) & | |
1117 | ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000); | |
1118 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_1, | |
1119 | fll_1 | (fll_div.div << 8) | 0x50); | |
1120 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_2, | |
1121 | (fll_div.ratio << 11) | (fll_div. | |
1122 | n & WM8350_FLL_N_MASK)); | |
1123 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_3, fll_div.k); | |
1124 | fll_4 = wm8350_codec_read(codec, WM8350_FLL_CONTROL_4) & | |
1125 | ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF); | |
1126 | wm8350_codec_write(codec, WM8350_FLL_CONTROL_4, | |
1127 | fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) | | |
1128 | (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0)); | |
1129 | ||
1130 | /* power FLL on */ | |
1131 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA); | |
1132 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA); | |
1133 | ||
1134 | return 0; | |
1135 | } | |
1136 | ||
1137 | static int wm8350_set_bias_level(struct snd_soc_codec *codec, | |
1138 | enum snd_soc_bias_level level) | |
1139 | { | |
1140 | struct wm8350 *wm8350 = codec->control_data; | |
1141 | struct wm8350_data *priv = codec->private_data; | |
1142 | struct wm8350_audio_platform_data *platform = | |
1143 | wm8350->codec.platform_data; | |
1144 | u16 pm1; | |
1145 | int ret; | |
1146 | ||
1147 | switch (level) { | |
1148 | case SND_SOC_BIAS_ON: | |
1149 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1150 | ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); | |
1151 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1152 | pm1 | WM8350_VMID_50K | | |
1153 | platform->codec_current_on << 14); | |
1154 | break; | |
1155 | ||
1156 | case SND_SOC_BIAS_PREPARE: | |
1157 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1); | |
1158 | pm1 &= ~WM8350_VMID_MASK; | |
1159 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1160 | pm1 | WM8350_VMID_50K); | |
1161 | break; | |
1162 | ||
1163 | case SND_SOC_BIAS_STANDBY: | |
1164 | if (codec->bias_level == SND_SOC_BIAS_OFF) { | |
1165 | ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), | |
1166 | priv->supplies); | |
1167 | if (ret != 0) | |
1168 | return ret; | |
1169 | ||
1170 | /* Enable the system clock */ | |
1171 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, | |
1172 | WM8350_SYSCLK_ENA); | |
1173 | ||
1174 | /* mute DAC & outputs */ | |
1175 | wm8350_set_bits(wm8350, WM8350_DAC_MUTE, | |
1176 | WM8350_DAC_MUTE_ENA); | |
1177 | ||
1178 | /* discharge cap memory */ | |
1179 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, | |
1180 | platform->dis_out1 | | |
1181 | (platform->dis_out2 << 2) | | |
1182 | (platform->dis_out3 << 4) | | |
1183 | (platform->dis_out4 << 6)); | |
1184 | ||
1185 | /* wait for discharge */ | |
1186 | schedule_timeout_interruptible(msecs_to_jiffies | |
1187 | (platform-> | |
1188 | cap_discharge_msecs)); | |
1189 | ||
1190 | /* enable antipop */ | |
1191 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, | |
1192 | (platform->vmid_s_curve << 8)); | |
1193 | ||
1194 | /* ramp up vmid */ | |
1195 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1196 | (platform-> | |
1197 | codec_current_charge << 14) | | |
1198 | WM8350_VMID_5K | WM8350_VMIDEN | | |
1199 | WM8350_VBUFEN); | |
1200 | ||
1201 | /* wait for vmid */ | |
1202 | schedule_timeout_interruptible(msecs_to_jiffies | |
1203 | (platform-> | |
1204 | vmid_charge_msecs)); | |
1205 | ||
1206 | /* turn on vmid 300k */ | |
1207 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1208 | ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); | |
1209 | pm1 |= WM8350_VMID_300K | | |
1210 | (platform->codec_current_standby << 14); | |
1211 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1212 | pm1); | |
1213 | ||
1214 | ||
1215 | /* enable analogue bias */ | |
1216 | pm1 |= WM8350_BIASEN; | |
1217 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); | |
1218 | ||
1219 | /* disable antipop */ | |
1220 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); | |
1221 | ||
1222 | } else { | |
1223 | /* turn on vmid 300k and reduce current */ | |
1224 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1225 | ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK); | |
1226 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1227 | pm1 | WM8350_VMID_300K | | |
1228 | (platform-> | |
1229 | codec_current_standby << 14)); | |
1230 | ||
1231 | } | |
1232 | break; | |
1233 | ||
1234 | case SND_SOC_BIAS_OFF: | |
1235 | ||
1236 | /* mute DAC & enable outputs */ | |
1237 | wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA); | |
1238 | ||
1239 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3, | |
1240 | WM8350_OUT1L_ENA | WM8350_OUT1R_ENA | | |
1241 | WM8350_OUT2L_ENA | WM8350_OUT2R_ENA); | |
1242 | ||
1243 | /* enable anti pop S curve */ | |
1244 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, | |
1245 | (platform->vmid_s_curve << 8)); | |
1246 | ||
1247 | /* turn off vmid */ | |
1248 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1249 | ~WM8350_VMIDEN; | |
1250 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); | |
1251 | ||
1252 | /* wait */ | |
1253 | schedule_timeout_interruptible(msecs_to_jiffies | |
1254 | (platform-> | |
1255 | vmid_discharge_msecs)); | |
1256 | ||
1257 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, | |
1258 | (platform->vmid_s_curve << 8) | | |
1259 | platform->dis_out1 | | |
1260 | (platform->dis_out2 << 2) | | |
1261 | (platform->dis_out3 << 4) | | |
1262 | (platform->dis_out4 << 6)); | |
1263 | ||
1264 | /* turn off VBuf and drain */ | |
1265 | pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) & | |
1266 | ~(WM8350_VBUFEN | WM8350_VMID_MASK); | |
1267 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, | |
1268 | pm1 | WM8350_OUTPUT_DRAIN_EN); | |
1269 | ||
1270 | /* wait */ | |
1271 | schedule_timeout_interruptible(msecs_to_jiffies | |
1272 | (platform->drain_msecs)); | |
1273 | ||
1274 | pm1 &= ~WM8350_BIASEN; | |
1275 | wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1); | |
1276 | ||
1277 | /* disable anti-pop */ | |
1278 | wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0); | |
1279 | ||
1280 | wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME, | |
1281 | WM8350_OUT1L_ENA); | |
1282 | wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME, | |
1283 | WM8350_OUT1R_ENA); | |
1284 | wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME, | |
1285 | WM8350_OUT2L_ENA); | |
1286 | wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME, | |
1287 | WM8350_OUT2R_ENA); | |
1288 | ||
1289 | /* disable clock gen */ | |
1290 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, | |
1291 | WM8350_SYSCLK_ENA); | |
1292 | ||
1293 | regulator_bulk_disable(ARRAY_SIZE(priv->supplies), | |
1294 | priv->supplies); | |
1295 | break; | |
1296 | } | |
1297 | codec->bias_level = level; | |
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | static int wm8350_suspend(struct platform_device *pdev, pm_message_t state) | |
1302 | { | |
1303 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1304 | struct snd_soc_codec *codec = socdev->card->codec; |
40aa4a30 MB |
1305 | |
1306 | wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1307 | return 0; | |
1308 | } | |
1309 | ||
1310 | static int wm8350_resume(struct platform_device *pdev) | |
1311 | { | |
1312 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1313 | struct snd_soc_codec *codec = socdev->card->codec; |
40aa4a30 MB |
1314 | |
1315 | wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1316 | ||
1317 | if (codec->suspend_bias_level == SND_SOC_BIAS_ON) | |
1318 | wm8350_set_bias_level(codec, SND_SOC_BIAS_ON); | |
1319 | ||
1320 | return 0; | |
1321 | } | |
1322 | ||
a6ba2b2d MB |
1323 | static void wm8350_hp_jack_handler(struct wm8350 *wm8350, int irq, void *data) |
1324 | { | |
1325 | struct wm8350_data *priv = data; | |
1326 | u16 reg; | |
1327 | int report; | |
1328 | int mask; | |
1329 | struct wm8350_jack_data *jack = NULL; | |
1330 | ||
1331 | switch (irq) { | |
1332 | case WM8350_IRQ_CODEC_JCK_DET_L: | |
1333 | jack = &priv->hpl; | |
1334 | mask = WM8350_JACK_L_LVL; | |
1335 | break; | |
1336 | ||
1337 | case WM8350_IRQ_CODEC_JCK_DET_R: | |
1338 | jack = &priv->hpr; | |
1339 | mask = WM8350_JACK_R_LVL; | |
1340 | break; | |
1341 | ||
1342 | default: | |
1343 | BUG(); | |
1344 | } | |
1345 | ||
1346 | if (!jack->jack) { | |
1347 | dev_warn(wm8350->dev, "Jack interrupt called with no jack\n"); | |
1348 | return; | |
1349 | } | |
1350 | ||
1351 | /* Debounce */ | |
1352 | msleep(200); | |
1353 | ||
1354 | reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS); | |
1355 | if (reg & mask) | |
1356 | report = jack->report; | |
1357 | else | |
1358 | report = 0; | |
1359 | ||
1360 | snd_soc_jack_report(jack->jack, report, jack->report); | |
1361 | } | |
1362 | ||
1363 | /** | |
1364 | * wm8350_hp_jack_detect - Enable headphone jack detection. | |
1365 | * | |
1366 | * @codec: WM8350 codec | |
1367 | * @which: left or right jack detect signal | |
1368 | * @jack: jack to report detection events on | |
1369 | * @report: value to report | |
1370 | * | |
1371 | * Enables the headphone jack detection of the WM8350. | |
1372 | */ | |
1373 | int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which, | |
1374 | struct snd_soc_jack *jack, int report) | |
1375 | { | |
1376 | struct wm8350_data *priv = codec->private_data; | |
1377 | struct wm8350 *wm8350 = codec->control_data; | |
1378 | int irq; | |
1379 | int ena; | |
1380 | ||
1381 | switch (which) { | |
1382 | case WM8350_JDL: | |
1383 | priv->hpl.jack = jack; | |
1384 | priv->hpl.report = report; | |
1385 | irq = WM8350_IRQ_CODEC_JCK_DET_L; | |
1386 | ena = WM8350_JDL_ENA; | |
1387 | break; | |
1388 | ||
1389 | case WM8350_JDR: | |
1390 | priv->hpr.jack = jack; | |
1391 | priv->hpr.report = report; | |
1392 | irq = WM8350_IRQ_CODEC_JCK_DET_R; | |
1393 | ena = WM8350_JDR_ENA; | |
1394 | break; | |
1395 | ||
1396 | default: | |
1397 | return -EINVAL; | |
1398 | } | |
1399 | ||
1400 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); | |
1401 | wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena); | |
1402 | ||
1403 | /* Sync status */ | |
1404 | wm8350_hp_jack_handler(wm8350, irq, priv); | |
1405 | ||
1406 | wm8350_unmask_irq(wm8350, irq); | |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect); | |
1411 | ||
40aa4a30 MB |
1412 | static struct snd_soc_codec *wm8350_codec; |
1413 | ||
1414 | static int wm8350_probe(struct platform_device *pdev) | |
1415 | { | |
1416 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
1417 | struct snd_soc_codec *codec; | |
1418 | struct wm8350 *wm8350; | |
1419 | struct wm8350_data *priv; | |
1420 | int ret; | |
1421 | struct wm8350_output *out1; | |
1422 | struct wm8350_output *out2; | |
1423 | ||
1424 | BUG_ON(!wm8350_codec); | |
1425 | ||
6627a653 MB |
1426 | socdev->card->codec = wm8350_codec; |
1427 | codec = socdev->card->codec; | |
40aa4a30 MB |
1428 | wm8350 = codec->control_data; |
1429 | priv = codec->private_data; | |
1430 | ||
1431 | /* Enable the codec */ | |
1432 | wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); | |
1433 | ||
1434 | /* Enable robust clocking mode in ADC */ | |
1435 | wm8350_codec_write(codec, WM8350_SECURITY, 0xa7); | |
1436 | wm8350_codec_write(codec, 0xde, 0x13); | |
1437 | wm8350_codec_write(codec, WM8350_SECURITY, 0); | |
1438 | ||
1439 | /* read OUT1 & OUT2 volumes */ | |
1440 | out1 = &priv->out1; | |
1441 | out2 = &priv->out2; | |
1442 | out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) & | |
1443 | WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; | |
1444 | out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) & | |
1445 | WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; | |
1446 | out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) & | |
1447 | WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT; | |
1448 | out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) & | |
1449 | WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT; | |
1450 | wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0); | |
1451 | wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0); | |
1452 | wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0); | |
1453 | wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0); | |
1454 | ||
1455 | /* Latch VU bits & mute */ | |
1456 | wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, | |
1457 | WM8350_OUT1_VU | WM8350_OUT1L_MUTE); | |
1458 | wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, | |
1459 | WM8350_OUT2_VU | WM8350_OUT2L_MUTE); | |
1460 | wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME, | |
1461 | WM8350_OUT1_VU | WM8350_OUT1R_MUTE); | |
1462 | wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME, | |
1463 | WM8350_OUT2_VU | WM8350_OUT2R_MUTE); | |
1464 | ||
a6ba2b2d MB |
1465 | wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L); |
1466 | wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); | |
1467 | wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, | |
1468 | wm8350_hp_jack_handler, priv); | |
1469 | wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, | |
1470 | wm8350_hp_jack_handler, priv); | |
1471 | ||
40aa4a30 MB |
1472 | ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1); |
1473 | if (ret < 0) { | |
1474 | dev_err(&pdev->dev, "failed to create pcms\n"); | |
1475 | return ret; | |
1476 | } | |
1477 | ||
3e8e1952 IM |
1478 | snd_soc_add_controls(codec, wm8350_snd_controls, |
1479 | ARRAY_SIZE(wm8350_snd_controls)); | |
40aa4a30 MB |
1480 | wm8350_add_widgets(codec); |
1481 | ||
1482 | wm8350_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
1483 | ||
1484 | ret = snd_soc_init_card(socdev); | |
1485 | if (ret < 0) { | |
1486 | dev_err(&pdev->dev, "failed to register card\n"); | |
1487 | goto card_err; | |
1488 | } | |
1489 | ||
1490 | return 0; | |
1491 | ||
1492 | card_err: | |
1493 | snd_soc_free_pcms(socdev); | |
1494 | snd_soc_dapm_free(socdev); | |
1495 | return ret; | |
1496 | } | |
1497 | ||
1498 | static int wm8350_remove(struct platform_device *pdev) | |
1499 | { | |
1500 | struct snd_soc_device *socdev = platform_get_drvdata(pdev); | |
6627a653 | 1501 | struct snd_soc_codec *codec = socdev->card->codec; |
40aa4a30 | 1502 | struct wm8350 *wm8350 = codec->control_data; |
a6ba2b2d | 1503 | struct wm8350_data *priv = codec->private_data; |
40aa4a30 MB |
1504 | int ret; |
1505 | ||
a6ba2b2d MB |
1506 | wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, |
1507 | WM8350_JDL_ENA | WM8350_JDR_ENA); | |
1508 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA); | |
1509 | ||
1510 | wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L); | |
1511 | wm8350_mask_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); | |
1512 | wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L); | |
1513 | wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R); | |
1514 | ||
1515 | priv->hpl.jack = NULL; | |
1516 | priv->hpr.jack = NULL; | |
1517 | ||
40aa4a30 MB |
1518 | /* cancel any work waiting to be queued. */ |
1519 | ret = cancel_delayed_work(&codec->delayed_work); | |
1520 | ||
1521 | /* if there was any work waiting then we run it now and | |
1522 | * wait for its completion */ | |
1523 | if (ret) { | |
1524 | schedule_delayed_work(&codec->delayed_work, 0); | |
1525 | flush_scheduled_work(); | |
1526 | } | |
1527 | ||
1528 | wm8350_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
1529 | ||
1530 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); | |
1531 | ||
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | #define WM8350_RATES (SNDRV_PCM_RATE_8000_96000) | |
1536 | ||
1537 | #define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ | |
1538 | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1539 | SNDRV_PCM_FMTBIT_S24_LE) | |
1540 | ||
1541 | struct snd_soc_dai wm8350_dai = { | |
1542 | .name = "WM8350", | |
1543 | .playback = { | |
1544 | .stream_name = "Playback", | |
1545 | .channels_min = 1, | |
1546 | .channels_max = 2, | |
1547 | .rates = WM8350_RATES, | |
1548 | .formats = WM8350_FORMATS, | |
1549 | }, | |
1550 | .capture = { | |
1551 | .stream_name = "Capture", | |
1552 | .channels_min = 1, | |
1553 | .channels_max = 2, | |
1554 | .rates = WM8350_RATES, | |
1555 | .formats = WM8350_FORMATS, | |
1556 | }, | |
1557 | .ops = { | |
1558 | .hw_params = wm8350_pcm_hw_params, | |
1559 | .digital_mute = wm8350_mute, | |
1560 | .trigger = wm8350_pcm_trigger, | |
1561 | .set_fmt = wm8350_set_dai_fmt, | |
1562 | .set_sysclk = wm8350_set_dai_sysclk, | |
1563 | .set_pll = wm8350_set_fll, | |
1564 | .set_clkdiv = wm8350_set_clkdiv, | |
1565 | }, | |
1566 | }; | |
1567 | EXPORT_SYMBOL_GPL(wm8350_dai); | |
1568 | ||
1569 | struct snd_soc_codec_device soc_codec_dev_wm8350 = { | |
1570 | .probe = wm8350_probe, | |
1571 | .remove = wm8350_remove, | |
1572 | .suspend = wm8350_suspend, | |
1573 | .resume = wm8350_resume, | |
1574 | }; | |
1575 | EXPORT_SYMBOL_GPL(soc_codec_dev_wm8350); | |
1576 | ||
1577 | static int wm8350_codec_probe(struct platform_device *pdev) | |
1578 | { | |
1579 | struct wm8350 *wm8350 = platform_get_drvdata(pdev); | |
1580 | struct wm8350_data *priv; | |
1581 | struct snd_soc_codec *codec; | |
1582 | int ret, i; | |
1583 | ||
1584 | if (wm8350->codec.platform_data == NULL) { | |
1585 | dev_err(&pdev->dev, "No audio platform data supplied\n"); | |
1586 | return -EINVAL; | |
1587 | } | |
1588 | ||
1589 | priv = kzalloc(sizeof(struct wm8350_data), GFP_KERNEL); | |
1590 | if (priv == NULL) | |
1591 | return -ENOMEM; | |
1592 | ||
1593 | for (i = 0; i < ARRAY_SIZE(supply_names); i++) | |
1594 | priv->supplies[i].supply = supply_names[i]; | |
1595 | ||
1596 | ret = regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies), | |
1597 | priv->supplies); | |
1598 | if (ret != 0) | |
1599 | goto err_priv; | |
1600 | ||
1601 | codec = &priv->codec; | |
1602 | wm8350->codec.codec = codec; | |
1603 | ||
1604 | wm8350_dai.dev = &pdev->dev; | |
1605 | ||
1606 | mutex_init(&codec->mutex); | |
1607 | INIT_LIST_HEAD(&codec->dapm_widgets); | |
1608 | INIT_LIST_HEAD(&codec->dapm_paths); | |
1609 | codec->dev = &pdev->dev; | |
1610 | codec->name = "WM8350"; | |
1611 | codec->owner = THIS_MODULE; | |
1612 | codec->read = wm8350_codec_read; | |
1613 | codec->write = wm8350_codec_write; | |
1614 | codec->bias_level = SND_SOC_BIAS_OFF; | |
1615 | codec->set_bias_level = wm8350_set_bias_level; | |
1616 | codec->dai = &wm8350_dai; | |
1617 | codec->num_dai = 1; | |
1618 | codec->reg_cache_size = WM8350_MAX_REGISTER; | |
1619 | codec->private_data = priv; | |
1620 | codec->control_data = wm8350; | |
1621 | ||
1622 | /* Put the codec into reset if it wasn't already */ | |
1623 | wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA); | |
1624 | ||
1625 | INIT_DELAYED_WORK(&codec->delayed_work, wm8350_pga_work); | |
1626 | ret = snd_soc_register_codec(codec); | |
1627 | if (ret != 0) | |
1628 | goto err_supply; | |
1629 | ||
1630 | wm8350_codec = codec; | |
1631 | ||
1632 | ret = snd_soc_register_dai(&wm8350_dai); | |
1633 | if (ret != 0) | |
1634 | goto err_codec; | |
1635 | return 0; | |
1636 | ||
1637 | err_codec: | |
1638 | snd_soc_unregister_codec(codec); | |
1639 | err_supply: | |
1640 | regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies); | |
1641 | err_priv: | |
1642 | kfree(priv); | |
1643 | wm8350_codec = NULL; | |
1644 | return ret; | |
1645 | } | |
1646 | ||
a31501d1 | 1647 | static int __devexit wm8350_codec_remove(struct platform_device *pdev) |
40aa4a30 MB |
1648 | { |
1649 | struct wm8350 *wm8350 = platform_get_drvdata(pdev); | |
1650 | struct snd_soc_codec *codec = wm8350->codec.codec; | |
1651 | struct wm8350_data *priv = codec->private_data; | |
1652 | ||
1653 | snd_soc_unregister_dai(&wm8350_dai); | |
1654 | snd_soc_unregister_codec(codec); | |
1655 | regulator_bulk_free(ARRAY_SIZE(priv->supplies), priv->supplies); | |
1656 | kfree(priv); | |
1657 | wm8350_codec = NULL; | |
1658 | return 0; | |
1659 | } | |
1660 | ||
1661 | static struct platform_driver wm8350_codec_driver = { | |
1662 | .driver = { | |
1663 | .name = "wm8350-codec", | |
1664 | .owner = THIS_MODULE, | |
1665 | }, | |
1666 | .probe = wm8350_codec_probe, | |
1667 | .remove = __devexit_p(wm8350_codec_remove), | |
1668 | }; | |
1669 | ||
1670 | static __init int wm8350_init(void) | |
1671 | { | |
1672 | return platform_driver_register(&wm8350_codec_driver); | |
1673 | } | |
1674 | module_init(wm8350_init); | |
1675 | ||
1676 | static __exit void wm8350_exit(void) | |
1677 | { | |
1678 | platform_driver_unregister(&wm8350_codec_driver); | |
1679 | } | |
1680 | module_exit(wm8350_exit); | |
1681 | ||
1682 | MODULE_DESCRIPTION("ASoC WM8350 driver"); | |
1683 | MODULE_AUTHOR("Liam Girdwood"); | |
1684 | MODULE_LICENSE("GPL"); | |
1685 | MODULE_ALIAS("platform:wm8350-codec"); |