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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux...
[deliverable/linux.git] / sound / soc / codecs / wm8400.c
CommitLineData
aaf1e176
MB		 1/*
2 * wm8400.c -- WM8400 ALSA Soc Audio driver
3 *
656baaeb 4 * Copyright 2008-11 Wolfson Microelectronics PLC.
aaf1e176
MB		 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/kernel.h>
5a0e3ad6 17#include <linux/slab.h>
aaf1e176
MB		 18#include <linux/init.h>
19#include <linux/delay.h>
20#include <linux/pm.h>
21#include <linux/platform_device.h>
22#include <linux/regulator/consumer.h>
23#include <linux/mfd/wm8400-audio.h>
24#include <linux/mfd/wm8400-private.h>
dab1547a 25#include <linux/mfd/core.h>
aaf1e176
MB		 26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
aaf1e176
MB		 30#include <sound/initval.h>
31#include <sound/tlv.h>
32
33#include "wm8400.h"
34
aaf1e176
MB		 35static struct regulator_bulk_data power[] = {
36 {
37 .supply = "I2S1VDD",
38 },
39 {
40 .supply = "I2S2VDD",
41 },
42 {
43 .supply = "DCVDD",
44 },
24a51029
MB		 45 {
46 .supply = "AVDD",
47 },
aaf1e176
MB		 48 {
49 .supply = "FLLVDD",
50 },
51 {
52 .supply = "HPVDD",
53 },
54 {
55 .supply = "SPKVDD",
56 },
57};
58
59/* codec private data */
60struct wm8400_priv {
f0fba2ad 61 struct snd_soc_codec *codec;
aaf1e176
MB		 62 struct wm8400 *wm8400;
63 u16 fake_register;
64 unsigned int sysclk;
65 unsigned int pcmclk;
66 struct work_struct work;
e8523b64 67 int fll_in, fll_out;
aaf1e176
MB		 68};
69
aaf1e176
MB		 70static void wm8400_codec_reset(struct snd_soc_codec *codec)
71{
b2c812e2 72 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
aaf1e176
MB		 73
74 wm8400_reset_codec_reg_cache(wm8400->wm8400);
75}
76
3351e9fb 77static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
aaf1e176 78
3351e9fb 79static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
aaf1e176 80
3351e9fb 81static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
aaf1e176 82
3351e9fb 83static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
aaf1e176 84
3351e9fb 85static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
aaf1e176 86
3351e9fb 87static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
aaf1e176 88
3351e9fb 89static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
aaf1e176 90
3351e9fb 91static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
aaf1e176
MB		 92
93static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
94 struct snd_ctl_elem_value *ucontrol)
95{
96 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
97 struct soc_mixer_control *mc =
98 (struct soc_mixer_control *)kcontrol->private_value;
99 int reg = mc->reg;
100 int ret;
101 u16 val;
102
103 ret = snd_soc_put_volsw(kcontrol, ucontrol);
104 if (ret < 0)
105 return ret;
106
107 /* now hit the volume update bits (always bit 8) */
5fa87d34
MB		 108 val = snd_soc_read(codec, reg);
109 return snd_soc_write(codec, reg, val | 0x0100);
aaf1e176
MB		 110}
111
112#define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
a44b5177
LPC		 113 SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \
114 snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array)
aaf1e176
MB		 115
116
117static const char *wm8400_digital_sidetone[] =
118 {"None", "Left ADC", "Right ADC", "Reserved"};
119
898b48eb
TI		 120static SOC_ENUM_SINGLE_DECL(wm8400_left_digital_sidetone_enum,
121 WM8400_DIGITAL_SIDE_TONE,
122 WM8400_ADC_TO_DACL_SHIFT,
123 wm8400_digital_sidetone);
aaf1e176 124
898b48eb
TI		 125static SOC_ENUM_SINGLE_DECL(wm8400_right_digital_sidetone_enum,
126 WM8400_DIGITAL_SIDE_TONE,
127 WM8400_ADC_TO_DACR_SHIFT,
128 wm8400_digital_sidetone);
aaf1e176
MB		 129
130static const char *wm8400_adcmode[] =
131 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
132
898b48eb
TI		 133static SOC_ENUM_SINGLE_DECL(wm8400_right_adcmode_enum,
134 WM8400_ADC_CTRL,
135 WM8400_ADC_HPF_CUT_SHIFT,
136 wm8400_adcmode);
aaf1e176
MB		 137
138static const struct snd_kcontrol_new wm8400_snd_controls[] = {
139/* INMIXL */
140SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
141 1, 0),
142SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
143 1, 0),
144/* INMIXR */
145SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
146 1, 0),
147SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
148 1, 0),
149
150/* LOMIX */
151SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
152 WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
153SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
154 WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
155SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
156 WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
157SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
158 WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
159SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
160 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
161SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
162 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
163
164/* ROMIX */
165SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
166 WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
167SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
168 WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
169SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
170 WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
171SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
172 WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
173SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
174 WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
175SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
176 WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
177
178/* LOUT */
179WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
180 WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
181SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
182
183/* ROUT */
184WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
185 WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
186SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
187
188/* LOPGA */
189WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
190 WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
191SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
192 WM8400_LOPGAZC_SHIFT, 1, 0),
193
194/* ROPGA */
195WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
196 WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
197SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
198 WM8400_ROPGAZC_SHIFT, 1, 0),
199
200SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
201 WM8400_LONMUTE_SHIFT, 1, 0),
202SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
203 WM8400_LOPMUTE_SHIFT, 1, 0),
204SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
205 WM8400_LOATTN_SHIFT, 1, 0),
206SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
207 WM8400_RONMUTE_SHIFT, 1, 0),
208SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
209 WM8400_ROPMUTE_SHIFT, 1, 0),
210SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
211 WM8400_ROATTN_SHIFT, 1, 0),
212
213SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
214 WM8400_OUT3MUTE_SHIFT, 1, 0),
215SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
216 WM8400_OUT3ATTN_SHIFT, 1, 0),
217
218SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
219 WM8400_OUT4MUTE_SHIFT, 1, 0),
220SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
221 WM8400_OUT4ATTN_SHIFT, 1, 0),
222
223SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
224 WM8400_CDMODE_SHIFT, 1, 0),
225
226SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
227 WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
228SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
229 WM8400_DCGAIN_SHIFT, 6, 0),
230SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
231 WM8400_ACGAIN_SHIFT, 6, 0),
232
233WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
234 WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
235 127, 0, out_dac_tlv),
236
237WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
238 WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
239 127, 0, out_dac_tlv),
240
241SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
242SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
243
244SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
245 WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
246SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
247 WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
248
249SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
250 WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
251
252SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
253
254WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
255 WM8400_LEFT_ADC_DIGITAL_VOLUME,
256 WM8400_ADCL_VOL_SHIFT,
257 WM8400_ADCL_VOL_MASK,
258 0,
259 in_adc_tlv),
260
261WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
262 WM8400_RIGHT_ADC_DIGITAL_VOLUME,
263 WM8400_ADCR_VOL_SHIFT,
264 WM8400_ADCR_VOL_MASK,
265 0,
266 in_adc_tlv),
267
268WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
269 WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
270 WM8400_LIN12VOL_SHIFT,
271 WM8400_LIN12VOL_MASK,
272 0,
273 in_pga_tlv),
274
275SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
276 WM8400_LI12ZC_SHIFT, 1, 0),
277
278SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
279 WM8400_LI12MUTE_SHIFT, 1, 0),
280
281WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
282 WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
283 WM8400_LIN34VOL_SHIFT,
284 WM8400_LIN34VOL_MASK,
285 0,
286 in_pga_tlv),
287
288SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
289 WM8400_LI34ZC_SHIFT, 1, 0),
290
291SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
292 WM8400_LI34MUTE_SHIFT, 1, 0),
293
294WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
295 WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
296 WM8400_RIN12VOL_SHIFT,
297 WM8400_RIN12VOL_MASK,
298 0,
299 in_pga_tlv),
300
301SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
302 WM8400_RI12ZC_SHIFT, 1, 0),
303
304SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
305 WM8400_RI12MUTE_SHIFT, 1, 0),
306
307WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
308 WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
309 WM8400_RIN34VOL_SHIFT,
310 WM8400_RIN34VOL_MASK,
311 0,
312 in_pga_tlv),
313
314SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
315 WM8400_RI34ZC_SHIFT, 1, 0),
316
317SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
318 WM8400_RI34MUTE_SHIFT, 1, 0),
319
320};
321
aaf1e176
MB		 322/*
323 * _DAPM_ Controls
324 */
325
aaf1e176
MB		 326static int outmixer_event (struct snd_soc_dapm_widget *w,
327 struct snd_kcontrol * kcontrol, int event)
328{
329 struct soc_mixer_control *mc =
330 (struct soc_mixer_control *)kcontrol->private_value;
331 u32 reg_shift = mc->shift;
332 int ret = 0;
333 u16 reg;
334
335 switch (reg_shift) {
336 case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
5fa87d34 337 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER1);
aaf1e176
MB		 338 if (reg & WM8400_LDLO) {
339 printk(KERN_WARNING
340 "Cannot set as Output Mixer 1 LDLO Set\n");
341 ret = -1;
342 }
343 break;
344 case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
5fa87d34 345 reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER2);
aaf1e176
MB		 346 if (reg & WM8400_RDRO) {
347 printk(KERN_WARNING
348 "Cannot set as Output Mixer 2 RDRO Set\n");
349 ret = -1;
350 }
351 break;
352 case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
5fa87d34 353 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER);
aaf1e176
MB		 354 if (reg & WM8400_LDSPK) {
355 printk(KERN_WARNING
356 "Cannot set as Speaker Mixer LDSPK Set\n");
357 ret = -1;
358 }
359 break;
360 case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
5fa87d34 361 reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER);
aaf1e176
MB		 362 if (reg & WM8400_RDSPK) {
363 printk(KERN_WARNING
364 "Cannot set as Speaker Mixer RDSPK Set\n");
365 ret = -1;
366 }
367 break;
368 }
369
370 return ret;
371}
372
373/* INMIX dB values */
374static const unsigned int in_mix_tlv[] = {
375 TLV_DB_RANGE_HEAD(1),
3351e9fb 376 0,7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
aaf1e176
MB		 377};
378
379/* Left In PGA Connections */
380static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
381SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
382SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
383};
384
385static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
386SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
387SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
388};
389
390/* Right In PGA Connections */
391static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
392SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
393SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
394};
395
396static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
397SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
398SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
399};
400
401/* INMIXL */
402static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
403SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
404 WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
405SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
406 7, 0, in_mix_tlv),
407SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
408 1, 0),
409SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
410 1, 0),
411};
412
413/* INMIXR */
414static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
415SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
416 WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
417SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
418 7, 0, in_mix_tlv),
419SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
420 1, 0),
421SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
422 1, 0),
423};
424
425/* AINLMUX */
426static const char *wm8400_ainlmux[] =
427 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
428
898b48eb
TI		 429static SOC_ENUM_SINGLE_DECL(wm8400_ainlmux_enum,
430 WM8400_INPUT_MIXER1,
431 WM8400_AINLMODE_SHIFT,
432 wm8400_ainlmux);
aaf1e176
MB		 433
434static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
435SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
436
437/* DIFFINL */
438
439/* AINRMUX */
440static const char *wm8400_ainrmux[] =
441 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
442
898b48eb
TI		 443static SOC_ENUM_SINGLE_DECL(wm8400_ainrmux_enum,
444 WM8400_INPUT_MIXER1,
445 WM8400_AINRMODE_SHIFT,
446 wm8400_ainrmux);
aaf1e176
MB		 447
448static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
449SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
450
451/* RXVOICE */
452static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = {
453SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT,
454 WM8400_LR4BVOL_MASK, 0, in_mix_tlv),
455SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT,
456 WM8400_RL4BVOL_MASK, 0, in_mix_tlv),
457};
458
459/* LOMIX */
460static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
461SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
462 WM8400_LRBLO_SHIFT, 1, 0),
463SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
464 WM8400_LLBLO_SHIFT, 1, 0),
465SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
466 WM8400_LRI3LO_SHIFT, 1, 0),
467SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
468 WM8400_LLI3LO_SHIFT, 1, 0),
469SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
470 WM8400_LR12LO_SHIFT, 1, 0),
471SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
472 WM8400_LL12LO_SHIFT, 1, 0),
473SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
474 WM8400_LDLO_SHIFT, 1, 0),
475};
476
477/* ROMIX */
478static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
479SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
480 WM8400_RLBRO_SHIFT, 1, 0),
481SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
482 WM8400_RRBRO_SHIFT, 1, 0),
483SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
484 WM8400_RLI3RO_SHIFT, 1, 0),
485SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
486 WM8400_RRI3RO_SHIFT, 1, 0),
487SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
488 WM8400_RL12RO_SHIFT, 1, 0),
489SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
490 WM8400_RR12RO_SHIFT, 1, 0),
491SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
492 WM8400_RDRO_SHIFT, 1, 0),
493};
494
495/* LONMIX */
496static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
497SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
498 WM8400_LLOPGALON_SHIFT, 1, 0),
499SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
500 WM8400_LROPGALON_SHIFT, 1, 0),
501SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
502 WM8400_LOPLON_SHIFT, 1, 0),
503};
504
505/* LOPMIX */
506static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
507SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
508 WM8400_LR12LOP_SHIFT, 1, 0),
509SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
510 WM8400_LL12LOP_SHIFT, 1, 0),
511SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
512 WM8400_LLOPGALOP_SHIFT, 1, 0),
513};
514
515/* RONMIX */
516static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
517SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
518 WM8400_RROPGARON_SHIFT, 1, 0),
519SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
520 WM8400_RLOPGARON_SHIFT, 1, 0),
521SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
522 WM8400_ROPRON_SHIFT, 1, 0),
523};
524
525/* ROPMIX */
526static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
527SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
528 WM8400_RL12ROP_SHIFT, 1, 0),
529SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
530 WM8400_RR12ROP_SHIFT, 1, 0),
531SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
532 WM8400_RROPGAROP_SHIFT, 1, 0),
533};
534
535/* OUT3MIX */
536static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
537SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
538 WM8400_LI4O3_SHIFT, 1, 0),
539SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
540 WM8400_LPGAO3_SHIFT, 1, 0),
541};
542
543/* OUT4MIX */
544static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
545SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
546 WM8400_RPGAO4_SHIFT, 1, 0),
547SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
548 WM8400_RI4O4_SHIFT, 1, 0),
549};
550
551/* SPKMIX */
552static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
553SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
554 WM8400_LI2SPK_SHIFT, 1, 0),
555SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
556 WM8400_LB2SPK_SHIFT, 1, 0),
557SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
558 WM8400_LOPGASPK_SHIFT, 1, 0),
559SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
560 WM8400_LDSPK_SHIFT, 1, 0),
561SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
562 WM8400_RDSPK_SHIFT, 1, 0),
563SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
564 WM8400_ROPGASPK_SHIFT, 1, 0),
565SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
566 WM8400_RL12ROP_SHIFT, 1, 0),
567SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
568 WM8400_RI2SPK_SHIFT, 1, 0),
569};
570
571static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
572/* Input Side */
573/* Input Lines */
574SND_SOC_DAPM_INPUT("LIN1"),
575SND_SOC_DAPM_INPUT("LIN2"),
576SND_SOC_DAPM_INPUT("LIN3"),
577SND_SOC_DAPM_INPUT("LIN4/RXN"),
578SND_SOC_DAPM_INPUT("RIN3"),
579SND_SOC_DAPM_INPUT("RIN4/RXP"),
580SND_SOC_DAPM_INPUT("RIN1"),
581SND_SOC_DAPM_INPUT("RIN2"),
582SND_SOC_DAPM_INPUT("Internal ADC Source"),
583
584/* DACs */
585SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
586 WM8400_ADCL_ENA_SHIFT, 0),
587SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
588 WM8400_ADCR_ENA_SHIFT, 0),
589
590/* Input PGAs */
591SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
592 WM8400_LIN12_ENA_SHIFT,
593 0, &wm8400_dapm_lin12_pga_controls[0],
594 ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
595SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
596 WM8400_LIN34_ENA_SHIFT,
597 0, &wm8400_dapm_lin34_pga_controls[0],
598 ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
599SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
600 WM8400_RIN12_ENA_SHIFT,
601 0, &wm8400_dapm_rin12_pga_controls[0],
602 ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
603SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
604 WM8400_RIN34_ENA_SHIFT,
605 0, &wm8400_dapm_rin34_pga_controls[0],
606 ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
607
37c83edf
MB		 608SND_SOC_DAPM_SUPPLY("INL", WM8400_POWER_MANAGEMENT_2, WM8400_AINL_ENA_SHIFT,
609 0, NULL, 0),
610SND_SOC_DAPM_SUPPLY("INR", WM8400_POWER_MANAGEMENT_2, WM8400_AINR_ENA_SHIFT,
611 0, NULL, 0),
612
aaf1e176 613/* INMIXL */
37c83edf 614SND_SOC_DAPM_MIXER("INMIXL", SND_SOC_NOPM, 0, 0,
aaf1e176 615 &wm8400_dapm_inmixl_controls[0],
37c83edf 616 ARRAY_SIZE(wm8400_dapm_inmixl_controls)),
aaf1e176
MB		 617
618/* AINLMUX */
37c83edf 619SND_SOC_DAPM_MUX("AILNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainlmux_controls),
aaf1e176
MB		 620
621/* INMIXR */
37c83edf 622SND_SOC_DAPM_MIXER("INMIXR", SND_SOC_NOPM, 0, 0,
aaf1e176 623 &wm8400_dapm_inmixr_controls[0],
37c83edf 624 ARRAY_SIZE(wm8400_dapm_inmixr_controls)),
aaf1e176
MB		 625
626/* AINRMUX */
37c83edf 627SND_SOC_DAPM_MUX("AIRNMUX", SND_SOC_NOPM, 0, 0, &wm8400_dapm_ainrmux_controls),
aaf1e176
MB		 628
629/* Output Side */
630/* DACs */
631SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
632 WM8400_DACL_ENA_SHIFT, 0),
633SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
634 WM8400_DACR_ENA_SHIFT, 0),
635
636/* LOMIX */
637SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
638 WM8400_LOMIX_ENA_SHIFT,
639 0, &wm8400_dapm_lomix_controls[0],
640 ARRAY_SIZE(wm8400_dapm_lomix_controls),
641 outmixer_event, SND_SOC_DAPM_PRE_REG),
642
643/* LONMIX */
644SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
645 0, &wm8400_dapm_lonmix_controls[0],
646 ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
647
648/* LOPMIX */
649SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
650 0, &wm8400_dapm_lopmix_controls[0],
651 ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
652
653/* OUT3MIX */
654SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
655 0, &wm8400_dapm_out3mix_controls[0],
656 ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
657
658/* SPKMIX */
659SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
660 0, &wm8400_dapm_spkmix_controls[0],
661 ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
662 SND_SOC_DAPM_PRE_REG),
663
664/* OUT4MIX */
665SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
666 0, &wm8400_dapm_out4mix_controls[0],
667 ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
668
669/* ROPMIX */
670SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
671 0, &wm8400_dapm_ropmix_controls[0],
672 ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
673
674/* RONMIX */
675SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
676 0, &wm8400_dapm_ronmix_controls[0],
677 ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
678
679/* ROMIX */
680SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
681 WM8400_ROMIX_ENA_SHIFT,
682 0, &wm8400_dapm_romix_controls[0],
683 ARRAY_SIZE(wm8400_dapm_romix_controls),
684 outmixer_event, SND_SOC_DAPM_PRE_REG),
685
686/* LOUT PGA */
687SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
688 0, NULL, 0),
689
690/* ROUT PGA */
691SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
692 0, NULL, 0),
693
694/* LOPGA */
695SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
696 NULL, 0),
697
698/* ROPGA */
699SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
700 NULL, 0),
701
702/* MICBIAS */
3ff51c85
MB		 703SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1,
704 WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0),
aaf1e176
MB		 705
706SND_SOC_DAPM_OUTPUT("LON"),
707SND_SOC_DAPM_OUTPUT("LOP"),
708SND_SOC_DAPM_OUTPUT("OUT3"),
709SND_SOC_DAPM_OUTPUT("LOUT"),
710SND_SOC_DAPM_OUTPUT("SPKN"),
711SND_SOC_DAPM_OUTPUT("SPKP"),
712SND_SOC_DAPM_OUTPUT("ROUT"),
713SND_SOC_DAPM_OUTPUT("OUT4"),
714SND_SOC_DAPM_OUTPUT("ROP"),
715SND_SOC_DAPM_OUTPUT("RON"),
716
717SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
718};
719
b4505ab1 720static const struct snd_soc_dapm_route wm8400_dapm_routes[] = {
aaf1e176
MB		 721 /* Make DACs turn on when playing even if not mixed into any outputs */
722 {"Internal DAC Sink", NULL, "Left DAC"},
723 {"Internal DAC Sink", NULL, "Right DAC"},
724
725 /* Make ADCs turn on when recording
726 * even if not mixed from any inputs */
727 {"Left ADC", NULL, "Internal ADC Source"},
728 {"Right ADC", NULL, "Internal ADC Source"},
729
730 /* Input Side */
731 /* LIN12 PGA */
732 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
733 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
734 /* LIN34 PGA */
735 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
736 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
737 /* INMIXL */
37c83edf 738 {"INMIXL", NULL, "INL"},
aaf1e176
MB		 739 {"INMIXL", "Record Left Volume", "LOMIX"},
740 {"INMIXL", "LIN2 Volume", "LIN2"},
741 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
742 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
743 /* AILNMUX */
37c83edf 744 {"AILNMUX", NULL, "INL"},
aaf1e176
MB		 745 {"AILNMUX", "INMIXL Mix", "INMIXL"},
746 {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
747 {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
748 {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
749 {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
750 /* ADC */
751 {"Left ADC", NULL, "AILNMUX"},
752
753 /* RIN12 PGA */
754 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
755 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
756 /* RIN34 PGA */
757 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
758 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
37c83edf
MB		 759 /* INMIXR */
760 {"INMIXR", NULL, "INR"},
aaf1e176
MB		 761 {"INMIXR", "Record Right Volume", "ROMIX"},
762 {"INMIXR", "RIN2 Volume", "RIN2"},
763 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
764 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
765 /* AIRNMUX */
37c83edf 766 {"AIRNMUX", NULL, "INR"},
aaf1e176
MB		 767 {"AIRNMUX", "INMIXR Mix", "INMIXR"},
768 {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
769 {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
770 {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
771 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
772 /* ADC */
773 {"Right ADC", NULL, "AIRNMUX"},
774
775 /* LOMIX */
776 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
777 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
778 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
779 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
780 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
781 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
782 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
783
784 /* ROMIX */
785 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
786 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
787 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
788 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
789 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
790 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
791 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
792
793 /* SPKMIX */
794 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
795 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
796 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
797 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
798 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
799 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
800 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
801 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
802
803 /* LONMIX */
804 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
805 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
806 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
807
808 /* LOPMIX */
809 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
810 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
811 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
812
813 /* OUT3MIX */
814 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
815 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
816
817 /* OUT4MIX */
818 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
819 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
820
821 /* RONMIX */
822 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
823 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
824 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
825
826 /* ROPMIX */
827 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
828 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
829 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
830
831 /* Out Mixer PGAs */
832 {"LOPGA", NULL, "LOMIX"},
833 {"ROPGA", NULL, "ROMIX"},
834
835 {"LOUT PGA", NULL, "LOMIX"},
836 {"ROUT PGA", NULL, "ROMIX"},
837
838 /* Output Pins */
839 {"LON", NULL, "LONMIX"},
840 {"LOP", NULL, "LOPMIX"},
841 {"OUT3", NULL, "OUT3MIX"},
842 {"LOUT", NULL, "LOUT PGA"},
843 {"SPKN", NULL, "SPKMIX"},
844 {"ROUT", NULL, "ROUT PGA"},
845 {"OUT4", NULL, "OUT4MIX"},
846 {"ROP", NULL, "ROPMIX"},
847 {"RON", NULL, "RONMIX"},
848};
849
aaf1e176
MB		 850/*
851 * Clock after FLL and dividers
852 */
853static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
854 int clk_id, unsigned int freq, int dir)
855{
856 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 857 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
aaf1e176
MB		 858
859 wm8400->sysclk = freq;
860 return 0;
861}
862
e8523b64
MB		 863struct fll_factors {
864 u16 n;
865 u16 k;
866 u16 outdiv;
867 u16 fratio;
868 u16 freq_ref;
869};
870
871#define FIXED_FLL_SIZE ((1 << 16) * 10)
872
873static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
874 unsigned int Fref, unsigned int Fout)
875{
876 u64 Kpart;
877 unsigned int K, Nmod, target;
878
879 factors->outdiv = 2;
880 while (Fout * factors->outdiv < 90000000 ||
881 Fout * factors->outdiv > 100000000) {
882 factors->outdiv *= 2;
883 if (factors->outdiv > 32) {
884 dev_err(wm8400->wm8400->dev,
449bd54d 885 "Unsupported FLL output frequency %uHz\n",
e8523b64
MB		 886 Fout);
887 return -EINVAL;
888 }
889 }
890 target = Fout * factors->outdiv;
891 factors->outdiv = factors->outdiv >> 2;
892
893 if (Fref < 48000)
894 factors->freq_ref = 1;
895 else
896 factors->freq_ref = 0;
897
898 if (Fref < 1000000)
899 factors->fratio = 9;
900 else
901 factors->fratio = 0;
902
903 /* Ensure we have a fractional part */
904 do {
905 if (Fref < 1000000)
906 factors->fratio--;
907 else
908 factors->fratio++;
909
910 if (factors->fratio < 1 || factors->fratio > 8) {
911 dev_err(wm8400->wm8400->dev,
912 "Unable to calculate FRATIO\n");
913 return -EINVAL;
914 }
915
916 factors->n = target / (Fref * factors->fratio);
917 Nmod = target % (Fref * factors->fratio);
918 } while (Nmod == 0);
919
920 /* Calculate fractional part - scale up so we can round. */
921 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
922
923 do_div(Kpart, (Fref * factors->fratio));
924
925 K = Kpart & 0xFFFFFFFF;
926
927 if ((K % 10) >= 5)
928 K += 5;
929
930 /* Move down to proper range now rounding is done */
931 factors->k = K / 10;
932
933 dev_dbg(wm8400->wm8400->dev,
449bd54d 934 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
e8523b64
MB		 935 Fref, Fout,
936 factors->n, factors->k, factors->fratio, factors->outdiv);
937
938 return 0;
939}
940
941static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
85488037
MB		 942 int source, unsigned int freq_in,
943 unsigned int freq_out)
e8523b64
MB		 944{
945 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 946 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
e8523b64
MB		 947 struct fll_factors factors;
948 int ret;
949 u16 reg;
950
951 if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
952 return 0;
953
8aa2df53 954 if (freq_out) {
e8523b64
MB		 955 ret = fll_factors(wm8400, &factors, freq_in, freq_out);
956 if (ret != 0)
957 return ret;
8aa2df53
MB		 958 } else {
959 /* Bodge GCC 4.4.0 uninitialised variable warning - it
960 * doesn't seem capable of working out that we exit if
961 * freq_out is 0 before any of the uses. */
962 memset(&factors, 0, sizeof(factors));
e8523b64
MB		 963 }
964
965 wm8400->fll_out = freq_out;
966 wm8400->fll_in = freq_in;
967
968 /* We *must* disable the FLL before any changes */
5fa87d34 969 reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_2);
e8523b64 970 reg &= ~WM8400_FLL_ENA;
5fa87d34 971 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_2, reg);
e8523b64 972
5fa87d34 973 reg = snd_soc_read(codec, WM8400_FLL_CONTROL_1);
e8523b64 974 reg &= ~WM8400_FLL_OSC_ENA;
5fa87d34 975 snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
e8523b64 976
8aa2df53 977 if (!freq_out)
e8523b64
MB		 978 return 0;
979
980 reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
981 reg |= WM8400_FLL_FRAC | factors.fratio;
982 reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
5fa87d34 983 snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg);
e8523b64 984
5fa87d34
MB		 985 snd_soc_write(codec, WM8400_FLL_CONTROL_2, factors.k);
986 snd_soc_write(codec, WM8400_FLL_CONTROL_3, factors.n);
e8523b64 987
5fa87d34 988 reg = snd_soc_read(codec, WM8400_FLL_CONTROL_4);
1d533de9 989 reg &= ~WM8400_FLL_OUTDIV_MASK;
e8523b64 990 reg |= factors.outdiv;
5fa87d34 991 snd_soc_write(codec, WM8400_FLL_CONTROL_4, reg);
e8523b64
MB		 992
993 return 0;
994}
995
aaf1e176
MB		 996/*
997 * Sets ADC and Voice DAC format.
998 */
999static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
1000 unsigned int fmt)
1001{
1002 struct snd_soc_codec *codec = codec_dai->codec;
1003 u16 audio1, audio3;
1004
5fa87d34
MB		 1005 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
1006 audio3 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_3);
aaf1e176
MB		 1007
1008 /* set master/slave audio interface */
1009 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1010 case SND_SOC_DAIFMT_CBS_CFS:
1011 audio3 &= ~WM8400_AIF_MSTR1;
1012 break;
1013 case SND_SOC_DAIFMT_CBM_CFM:
1014 audio3 |= WM8400_AIF_MSTR1;
1015 break;
1016 default:
1017 return -EINVAL;
1018 }
1019
1020 audio1 &= ~WM8400_AIF_FMT_MASK;
1021
1022 /* interface format */
1023 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1024 case SND_SOC_DAIFMT_I2S:
1025 audio1 |= WM8400_AIF_FMT_I2S;
1026 audio1 &= ~WM8400_AIF_LRCLK_INV;
1027 break;
1028 case SND_SOC_DAIFMT_RIGHT_J:
1029 audio1 |= WM8400_AIF_FMT_RIGHTJ;
1030 audio1 &= ~WM8400_AIF_LRCLK_INV;
1031 break;
1032 case SND_SOC_DAIFMT_LEFT_J:
1033 audio1 |= WM8400_AIF_FMT_LEFTJ;
1034 audio1 &= ~WM8400_AIF_LRCLK_INV;
1035 break;
1036 case SND_SOC_DAIFMT_DSP_A:
1037 audio1 |= WM8400_AIF_FMT_DSP;
1038 audio1 &= ~WM8400_AIF_LRCLK_INV;
1039 break;
1040 case SND_SOC_DAIFMT_DSP_B:
1041 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
1042 break;
1043 default:
1044 return -EINVAL;
1045 }
1046
5fa87d34
MB		 1047 snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1048 snd_soc_write(codec, WM8400_AUDIO_INTERFACE_3, audio3);
aaf1e176
MB		 1049 return 0;
1050}
1051
1052static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1053 int div_id, int div)
1054{
1055 struct snd_soc_codec *codec = codec_dai->codec;
1056 u16 reg;
1057
1058 switch (div_id) {
1059 case WM8400_MCLK_DIV:
5fa87d34 1060 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
aaf1e176 1061 ~WM8400_MCLK_DIV_MASK;
5fa87d34 1062 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
aaf1e176
MB		 1063 break;
1064 case WM8400_DACCLK_DIV:
5fa87d34 1065 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
aaf1e176 1066 ~WM8400_DAC_CLKDIV_MASK;
5fa87d34 1067 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
aaf1e176
MB		 1068 break;
1069 case WM8400_ADCCLK_DIV:
5fa87d34 1070 reg = snd_soc_read(codec, WM8400_CLOCKING_2) &
aaf1e176 1071 ~WM8400_ADC_CLKDIV_MASK;
5fa87d34 1072 snd_soc_write(codec, WM8400_CLOCKING_2, reg | div);
aaf1e176
MB		 1073 break;
1074 case WM8400_BCLK_DIV:
5fa87d34 1075 reg = snd_soc_read(codec, WM8400_CLOCKING_1) &
aaf1e176 1076 ~WM8400_BCLK_DIV_MASK;
5fa87d34 1077 snd_soc_write(codec, WM8400_CLOCKING_1, reg | div);
aaf1e176
MB		 1078 break;
1079 default:
1080 return -EINVAL;
1081 }
1082
1083 return 0;
1084}
1085
1086/*
1087 * Set PCM DAI bit size and sample rate.
1088 */
1089static int wm8400_hw_params(struct snd_pcm_substream *substream,
1090 struct snd_pcm_hw_params *params,
1091 struct snd_soc_dai *dai)
1092{
e6968a17 1093 struct snd_soc_codec *codec = dai->codec;
5fa87d34 1094 u16 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1);
aaf1e176
MB		 1095
1096 audio1 &= ~WM8400_AIF_WL_MASK;
1097 /* bit size */
1098 switch (params_format(params)) {
1099 case SNDRV_PCM_FORMAT_S16_LE:
1100 break;
1101 case SNDRV_PCM_FORMAT_S20_3LE:
1102 audio1 |= WM8400_AIF_WL_20BITS;
1103 break;
1104 case SNDRV_PCM_FORMAT_S24_LE:
1105 audio1 |= WM8400_AIF_WL_24BITS;
1106 break;
1107 case SNDRV_PCM_FORMAT_S32_LE:
1108 audio1 |= WM8400_AIF_WL_32BITS;
1109 break;
1110 }
1111
5fa87d34 1112 snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
aaf1e176
MB		 1113 return 0;
1114}
1115
1116static int wm8400_mute(struct snd_soc_dai *dai, int mute)
1117{
1118 struct snd_soc_codec *codec = dai->codec;
5fa87d34 1119 u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
aaf1e176
MB		 1120
1121 if (mute)
5fa87d34 1122 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
aaf1e176 1123 else
5fa87d34 1124 snd_soc_write(codec, WM8400_DAC_CTRL, val);
aaf1e176
MB		 1125
1126 return 0;
1127}
1128
1129/* TODO: set bias for best performance at standby */
1130static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1131 enum snd_soc_bias_level level)
1132{
b2c812e2 1133 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
aaf1e176
MB		 1134 u16 val;
1135 int ret;
1136
1137 switch (level) {
1138 case SND_SOC_BIAS_ON:
1139 break;
1140
1141 case SND_SOC_BIAS_PREPARE:
1142 /* VMID=2*50k */
5fa87d34 1143 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
aaf1e176 1144 ~WM8400_VMID_MODE_MASK;
5fa87d34 1145 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2);
aaf1e176
MB		 1146 break;
1147
1148 case SND_SOC_BIAS_STANDBY:
ce6120cc 1149 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
aaf1e176
MB		 1150 ret = regulator_bulk_enable(ARRAY_SIZE(power),
1151 &power[0]);
1152 if (ret != 0) {
1153 dev_err(wm8400->wm8400->dev,
1154 "Failed to enable regulators: %d\n",
1155 ret);
1156 return ret;
1157 }
1158
5fa87d34 1159 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
aaf1e176
MB		 1160 WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1161
aaf1e176 1162 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
5fa87d34 1163 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
aaf1e176
MB		 1164 WM8400_BUFDCOPEN | WM8400_POBCTRL);
1165
e3598f6e 1166 msleep(50);
aaf1e176
MB		 1167
1168 /* Enable VREF & VMID at 2x50k */
5fa87d34 1169 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
aaf1e176 1170 val |= 0x2 | WM8400_VREF_ENA;
5fa87d34 1171 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
aaf1e176 1172
aaf1e176 1173 /* Enable BUFIOEN */
5fa87d34 1174 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
aaf1e176
MB		 1175 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1176 WM8400_BUFIOEN);
1177
aaf1e176 1178 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
5fa87d34 1179 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN);
aaf1e176
MB		 1180 }
1181
1182 /* VMID=2*300k */
5fa87d34 1183 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) &
aaf1e176 1184 ~WM8400_VMID_MODE_MASK;
5fa87d34 1185 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4);
aaf1e176
MB		 1186 break;
1187
1188 case SND_SOC_BIAS_OFF:
1189 /* Enable POBCTRL and SOFT_ST */
5fa87d34 1190 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
aaf1e176
MB		 1191 WM8400_POBCTRL | WM8400_BUFIOEN);
1192
1193 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
5fa87d34 1194 snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
aaf1e176
MB		 1195 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1196 WM8400_BUFIOEN);
1197
1198 /* mute DAC */
5fa87d34
MB		 1199 val = snd_soc_read(codec, WM8400_DAC_CTRL);
1200 snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
aaf1e176
MB		 1201
1202 /* Enable any disabled outputs */
5fa87d34 1203 val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
aaf1e176
MB		 1204 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1205 WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1206 WM8400_ROUT_ENA;
5fa87d34 1207 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
aaf1e176
MB		 1208
1209 /* Disable VMID */
1210 val &= ~WM8400_VMID_MODE_MASK;
5fa87d34 1211 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
aaf1e176
MB		 1212
1213 msleep(300);
1214
1215 /* Enable all output discharge bits */
5fa87d34 1216 snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
aaf1e176
MB		 1217 WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1218 WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1219 WM8400_DIS_ROUT);
1220
1221 /* Disable VREF */
1222 val &= ~WM8400_VREF_ENA;
5fa87d34 1223 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val);
aaf1e176
MB		 1224
1225 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
5fa87d34 1226 snd_soc_write(codec, WM8400_ANTIPOP2, 0x0);
aaf1e176
MB		 1227
1228 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1229 &power[0]);
1230 if (ret != 0)
1231 return ret;
1232
1233 break;
1234 }
1235
ce6120cc 1236 codec->dapm.bias_level = level;
aaf1e176
MB		 1237 return 0;
1238}
1239
1240#define WM8400_RATES SNDRV_PCM_RATE_8000_96000
1241
1242#define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1243 SNDRV_PCM_FMTBIT_S24_LE)
1244
85e7652d 1245static const struct snd_soc_dai_ops wm8400_dai_ops = {
65ec1cd1
MB		 1246 .hw_params = wm8400_hw_params,
1247 .digital_mute = wm8400_mute,
1248 .set_fmt = wm8400_set_dai_fmt,
1249 .set_clkdiv = wm8400_set_dai_clkdiv,
1250 .set_sysclk = wm8400_set_dai_sysclk,
e8523b64 1251 .set_pll = wm8400_set_dai_pll,
65ec1cd1
MB		 1252};
1253
aaf1e176
MB		 1254/*
1255 * The WM8400 supports 2 different and mutually exclusive DAI
1256 * configurations.
1257 *
1258 * 1. ADC/DAC on Primary Interface
1259 * 2. ADC on Primary Interface/DAC on secondary
1260 */
f0fba2ad 1261static struct snd_soc_dai_driver wm8400_dai = {
aaf1e176 1262/* ADC/DAC on primary */
f0fba2ad 1263 .name = "wm8400-hifi",
aaf1e176
MB		 1264 .playback = {
1265 .stream_name = "Playback",
1266 .channels_min = 1,
1267 .channels_max = 2,
1268 .rates = WM8400_RATES,
1269 .formats = WM8400_FORMATS,
1270 },
1271 .capture = {
1272 .stream_name = "Capture",
1273 .channels_min = 1,
1274 .channels_max = 2,
1275 .rates = WM8400_RATES,
1276 .formats = WM8400_FORMATS,
1277 },
65ec1cd1 1278 .ops = &wm8400_dai_ops,
aaf1e176 1279};
aaf1e176 1280
84b315ee 1281static int wm8400_suspend(struct snd_soc_codec *codec)
aaf1e176 1282{
aaf1e176
MB		 1283 wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF);
1284
1285 return 0;
1286}
1287
f0fba2ad 1288static int wm8400_resume(struct snd_soc_codec *codec)
aaf1e176 1289{
aaf1e176
MB		 1290 wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1291
1292 return 0;
1293}
1294
aaf1e176
MB		 1295static void wm8400_probe_deferred(struct work_struct *work)
1296{
1297 struct wm8400_priv *priv = container_of(work, struct wm8400_priv,
1298 work);
f0fba2ad 1299 struct snd_soc_codec *codec = priv->codec;
aaf1e176
MB		 1300
1301 /* charge output caps */
1302 wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
aaf1e176
MB		 1303}
1304
f0fba2ad 1305static int wm8400_codec_probe(struct snd_soc_codec *codec)
aaf1e176 1306{
e45be4b5 1307 struct wm8400 *wm8400 = dev_get_platdata(codec->dev);
aaf1e176
MB		 1308 struct wm8400_priv *priv;
1309 int ret;
1310 u16 reg;
aaf1e176 1311
b903c0ed
MB		 1312 priv = devm_kzalloc(codec->dev, sizeof(struct wm8400_priv),
1313 GFP_KERNEL);
aaf1e176
MB		 1314 if (priv == NULL)
1315 return -ENOMEM;
1316
b2c812e2 1317 snd_soc_codec_set_drvdata(codec, priv);
b8cc4151 1318 priv->wm8400 = wm8400;
f0fba2ad 1319 priv->codec = codec;
aaf1e176 1320
092eba93 1321 snd_soc_codec_set_cache_io(codec, wm8400->regmap);
b8cc4151 1322
95a5b240 1323 ret = devm_regulator_bulk_get(wm8400->dev,
aaf1e176
MB		 1324 ARRAY_SIZE(power), &power[0]);
1325 if (ret != 0) {
f0fba2ad 1326 dev_err(codec->dev, "Failed to get regulators: %d\n", ret);
b903c0ed 1327 return ret;
aaf1e176
MB		 1328 }
1329
aaf1e176
MB		 1330 INIT_WORK(&priv->work, wm8400_probe_deferred);
1331
1332 wm8400_codec_reset(codec);
1333
5fa87d34
MB		 1334 reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1335 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
aaf1e176
MB		 1336
1337 /* Latch volume update bits */
5fa87d34
MB		 1338 reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1339 snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
aaf1e176 1340 reg & WM8400_IPVU);
5fa87d34
MB		 1341 reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1342 snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
aaf1e176
MB		 1343 reg & WM8400_IPVU);
1344
5fa87d34
MB		 1345 snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1346 snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
aaf1e176 1347
95a5b240
SK		 1348 if (!schedule_work(&priv->work))
1349 return -EINVAL;
aaf1e176 1350 return 0;
aaf1e176
MB		 1351}
1352
f0fba2ad 1353static int wm8400_codec_remove(struct snd_soc_codec *codec)
aaf1e176 1354{
aaf1e176
MB		 1355 u16 reg;
1356
5fa87d34
MB		 1357 reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1);
1358 snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1,
aaf1e176
MB		 1359 reg & (~WM8400_CODEC_ENA));
1360
f0fba2ad
LG		 1361 return 0;
1362}
1363
1364static struct snd_soc_codec_driver soc_codec_dev_wm8400 = {
1365 .probe = wm8400_codec_probe,
1366 .remove = wm8400_codec_remove,
1367 .suspend = wm8400_suspend,
1368 .resume = wm8400_resume,
f0fba2ad 1369 .set_bias_level = wm8400_set_bias_level,
b4505ab1
MB		 1370
1371 .controls = wm8400_snd_controls,
1372 .num_controls = ARRAY_SIZE(wm8400_snd_controls),
1373 .dapm_widgets = wm8400_dapm_widgets,
1374 .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets),
1375 .dapm_routes = wm8400_dapm_routes,
1376 .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes),
f0fba2ad
LG		 1377};
1378
7a79e94e 1379static int wm8400_probe(struct platform_device *pdev)
f0fba2ad
LG		 1380{
1381 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400,
1382 &wm8400_dai, 1);
1383}
aaf1e176 1384
7a79e94e 1385static int wm8400_remove(struct platform_device *pdev)
f0fba2ad
LG		 1386{
1387 snd_soc_unregister_codec(&pdev->dev);
aaf1e176
MB		 1388 return 0;
1389}
1390
1391static struct platform_driver wm8400_codec_driver = {
1392 .driver = {
f0fba2ad
LG		 1393 .name = "wm8400-codec",
1394 .owner = THIS_MODULE,
1395 },
1396 .probe = wm8400_probe,
7a79e94e 1397 .remove = wm8400_remove,
aaf1e176
MB		 1398};
1399
5bbcc3c0 1400module_platform_driver(wm8400_codec_driver);
aaf1e176
MB		 1401
1402MODULE_DESCRIPTION("ASoC WM8400 driver");
1403MODULE_AUTHOR("Mark Brown");
1404MODULE_LICENSE("GPL");
1405MODULE_ALIAS("platform:wm8400-codec");
Linux kernel - Deliverables
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