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1 | /* |
2 | * wm8400.c -- WM8400 ALSA Soc Audio driver | |
3 | * | |
656baaeb | 4 | * Copyright 2008-11 Wolfson Microelectronics PLC. |
aaf1e176 MB |
5 | * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/module.h> | |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/kernel.h> | |
5a0e3ad6 | 17 | #include <linux/slab.h> |
aaf1e176 MB |
18 | #include <linux/init.h> |
19 | #include <linux/delay.h> | |
20 | #include <linux/pm.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/regulator/consumer.h> | |
23 | #include <linux/mfd/wm8400-audio.h> | |
24 | #include <linux/mfd/wm8400-private.h> | |
dab1547a | 25 | #include <linux/mfd/core.h> |
aaf1e176 MB |
26 | #include <sound/core.h> |
27 | #include <sound/pcm.h> | |
28 | #include <sound/pcm_params.h> | |
29 | #include <sound/soc.h> | |
aaf1e176 MB |
30 | #include <sound/initval.h> |
31 | #include <sound/tlv.h> | |
32 | ||
33 | #include "wm8400.h" | |
34 | ||
35 | /* Fake register for internal state */ | |
36 | #define WM8400_INTDRIVBITS (WM8400_REGISTER_COUNT + 1) | |
37 | #define WM8400_INMIXL_PWR 0 | |
38 | #define WM8400_AINLMUX_PWR 1 | |
39 | #define WM8400_INMIXR_PWR 2 | |
40 | #define WM8400_AINRMUX_PWR 3 | |
41 | ||
42 | static struct regulator_bulk_data power[] = { | |
43 | { | |
44 | .supply = "I2S1VDD", | |
45 | }, | |
46 | { | |
47 | .supply = "I2S2VDD", | |
48 | }, | |
49 | { | |
50 | .supply = "DCVDD", | |
51 | }, | |
24a51029 MB |
52 | { |
53 | .supply = "AVDD", | |
54 | }, | |
aaf1e176 MB |
55 | { |
56 | .supply = "FLLVDD", | |
57 | }, | |
58 | { | |
59 | .supply = "HPVDD", | |
60 | }, | |
61 | { | |
62 | .supply = "SPKVDD", | |
63 | }, | |
64 | }; | |
65 | ||
66 | /* codec private data */ | |
67 | struct wm8400_priv { | |
f0fba2ad | 68 | struct snd_soc_codec *codec; |
aaf1e176 MB |
69 | struct wm8400 *wm8400; |
70 | u16 fake_register; | |
71 | unsigned int sysclk; | |
72 | unsigned int pcmclk; | |
73 | struct work_struct work; | |
e8523b64 | 74 | int fll_in, fll_out; |
aaf1e176 MB |
75 | }; |
76 | ||
77 | static inline unsigned int wm8400_read(struct snd_soc_codec *codec, | |
78 | unsigned int reg) | |
79 | { | |
b2c812e2 | 80 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
aaf1e176 MB |
81 | |
82 | if (reg == WM8400_INTDRIVBITS) | |
83 | return wm8400->fake_register; | |
84 | else | |
85 | return wm8400_reg_read(wm8400->wm8400, reg); | |
86 | } | |
87 | ||
88 | /* | |
89 | * write to the wm8400 register space | |
90 | */ | |
91 | static int wm8400_write(struct snd_soc_codec *codec, unsigned int reg, | |
92 | unsigned int value) | |
93 | { | |
b2c812e2 | 94 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
aaf1e176 MB |
95 | |
96 | if (reg == WM8400_INTDRIVBITS) { | |
97 | wm8400->fake_register = value; | |
98 | return 0; | |
99 | } else | |
100 | return wm8400_set_bits(wm8400->wm8400, reg, 0xffff, value); | |
101 | } | |
102 | ||
103 | static void wm8400_codec_reset(struct snd_soc_codec *codec) | |
104 | { | |
b2c812e2 | 105 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
aaf1e176 MB |
106 | |
107 | wm8400_reset_codec_reg_cache(wm8400->wm8400); | |
108 | } | |
109 | ||
3351e9fb | 110 | static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0); |
aaf1e176 | 111 | |
3351e9fb | 112 | static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0); |
aaf1e176 | 113 | |
3351e9fb | 114 | static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0); |
aaf1e176 | 115 | |
3351e9fb | 116 | static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0); |
aaf1e176 | 117 | |
3351e9fb | 118 | static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0); |
aaf1e176 | 119 | |
3351e9fb | 120 | static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0); |
aaf1e176 | 121 | |
3351e9fb | 122 | static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0); |
aaf1e176 | 123 | |
3351e9fb | 124 | static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0); |
aaf1e176 MB |
125 | |
126 | static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol, | |
127 | struct snd_ctl_elem_value *ucontrol) | |
128 | { | |
129 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); | |
130 | struct soc_mixer_control *mc = | |
131 | (struct soc_mixer_control *)kcontrol->private_value; | |
132 | int reg = mc->reg; | |
133 | int ret; | |
134 | u16 val; | |
135 | ||
136 | ret = snd_soc_put_volsw(kcontrol, ucontrol); | |
137 | if (ret < 0) | |
138 | return ret; | |
139 | ||
140 | /* now hit the volume update bits (always bit 8) */ | |
5fa87d34 MB |
141 | val = snd_soc_read(codec, reg); |
142 | return snd_soc_write(codec, reg, val | 0x0100); | |
aaf1e176 MB |
143 | } |
144 | ||
145 | #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \ | |
a44b5177 LPC |
146 | SOC_SINGLE_EXT_TLV(xname, reg, shift, max, invert, \ |
147 | snd_soc_get_volsw, wm8400_outpga_put_volsw_vu, tlv_array) | |
aaf1e176 MB |
148 | |
149 | ||
150 | static const char *wm8400_digital_sidetone[] = | |
151 | {"None", "Left ADC", "Right ADC", "Reserved"}; | |
152 | ||
153 | static const struct soc_enum wm8400_left_digital_sidetone_enum = | |
154 | SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE, | |
155 | WM8400_ADC_TO_DACL_SHIFT, 2, wm8400_digital_sidetone); | |
156 | ||
157 | static const struct soc_enum wm8400_right_digital_sidetone_enum = | |
158 | SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE, | |
159 | WM8400_ADC_TO_DACR_SHIFT, 2, wm8400_digital_sidetone); | |
160 | ||
161 | static const char *wm8400_adcmode[] = | |
162 | {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"}; | |
163 | ||
164 | static const struct soc_enum wm8400_right_adcmode_enum = | |
165 | SOC_ENUM_SINGLE(WM8400_ADC_CTRL, WM8400_ADC_HPF_CUT_SHIFT, 3, wm8400_adcmode); | |
166 | ||
167 | static const struct snd_kcontrol_new wm8400_snd_controls[] = { | |
168 | /* INMIXL */ | |
169 | SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT, | |
170 | 1, 0), | |
171 | SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT, | |
172 | 1, 0), | |
173 | /* INMIXR */ | |
174 | SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT, | |
175 | 1, 0), | |
176 | SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT, | |
177 | 1, 0), | |
178 | ||
179 | /* LOMIX */ | |
180 | SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3, | |
181 | WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv), | |
182 | SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, | |
183 | WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv), | |
184 | SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3, | |
185 | WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv), | |
186 | SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5, | |
187 | WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv), | |
188 | SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5, | |
189 | WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), | |
190 | SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5, | |
191 | WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv), | |
192 | ||
193 | /* ROMIX */ | |
194 | SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4, | |
195 | WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv), | |
196 | SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, | |
197 | WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv), | |
198 | SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4, | |
199 | WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv), | |
200 | SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6, | |
201 | WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv), | |
202 | SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6, | |
203 | WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv), | |
204 | SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6, | |
205 | WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv), | |
206 | ||
207 | /* LOUT */ | |
208 | WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME, | |
209 | WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv), | |
210 | SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0), | |
211 | ||
212 | /* ROUT */ | |
213 | WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME, | |
214 | WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv), | |
215 | SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0), | |
216 | ||
217 | /* LOPGA */ | |
218 | WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME, | |
219 | WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv), | |
220 | SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME, | |
221 | WM8400_LOPGAZC_SHIFT, 1, 0), | |
222 | ||
223 | /* ROPGA */ | |
224 | WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME, | |
225 | WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv), | |
226 | SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME, | |
227 | WM8400_ROPGAZC_SHIFT, 1, 0), | |
228 | ||
229 | SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, | |
230 | WM8400_LONMUTE_SHIFT, 1, 0), | |
231 | SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, | |
232 | WM8400_LOPMUTE_SHIFT, 1, 0), | |
233 | SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, | |
234 | WM8400_LOATTN_SHIFT, 1, 0), | |
235 | SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, | |
236 | WM8400_RONMUTE_SHIFT, 1, 0), | |
237 | SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME, | |
238 | WM8400_ROPMUTE_SHIFT, 1, 0), | |
239 | SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME, | |
240 | WM8400_ROATTN_SHIFT, 1, 0), | |
241 | ||
242 | SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME, | |
243 | WM8400_OUT3MUTE_SHIFT, 1, 0), | |
244 | SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME, | |
245 | WM8400_OUT3ATTN_SHIFT, 1, 0), | |
246 | ||
247 | SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME, | |
248 | WM8400_OUT4MUTE_SHIFT, 1, 0), | |
249 | SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME, | |
250 | WM8400_OUT4ATTN_SHIFT, 1, 0), | |
251 | ||
252 | SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1, | |
253 | WM8400_CDMODE_SHIFT, 1, 0), | |
254 | ||
255 | SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME, | |
256 | WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0), | |
257 | SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3, | |
258 | WM8400_DCGAIN_SHIFT, 6, 0), | |
259 | SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3, | |
260 | WM8400_ACGAIN_SHIFT, 6, 0), | |
261 | ||
262 | WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume", | |
263 | WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT, | |
264 | 127, 0, out_dac_tlv), | |
265 | ||
266 | WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume", | |
267 | WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT, | |
268 | 127, 0, out_dac_tlv), | |
269 | ||
270 | SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum), | |
271 | SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum), | |
272 | ||
273 | SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, | |
274 | WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), | |
275 | SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE, | |
276 | WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv), | |
277 | ||
278 | SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL, | |
279 | WM8400_ADC_HPF_ENA_SHIFT, 1, 0), | |
280 | ||
281 | SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum), | |
282 | ||
283 | WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume", | |
284 | WM8400_LEFT_ADC_DIGITAL_VOLUME, | |
285 | WM8400_ADCL_VOL_SHIFT, | |
286 | WM8400_ADCL_VOL_MASK, | |
287 | 0, | |
288 | in_adc_tlv), | |
289 | ||
290 | WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume", | |
291 | WM8400_RIGHT_ADC_DIGITAL_VOLUME, | |
292 | WM8400_ADCR_VOL_SHIFT, | |
293 | WM8400_ADCR_VOL_MASK, | |
294 | 0, | |
295 | in_adc_tlv), | |
296 | ||
297 | WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume", | |
298 | WM8400_LEFT_LINE_INPUT_1_2_VOLUME, | |
299 | WM8400_LIN12VOL_SHIFT, | |
300 | WM8400_LIN12VOL_MASK, | |
301 | 0, | |
302 | in_pga_tlv), | |
303 | ||
304 | SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, | |
305 | WM8400_LI12ZC_SHIFT, 1, 0), | |
306 | ||
307 | SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME, | |
308 | WM8400_LI12MUTE_SHIFT, 1, 0), | |
309 | ||
310 | WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume", | |
311 | WM8400_LEFT_LINE_INPUT_3_4_VOLUME, | |
312 | WM8400_LIN34VOL_SHIFT, | |
313 | WM8400_LIN34VOL_MASK, | |
314 | 0, | |
315 | in_pga_tlv), | |
316 | ||
317 | SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, | |
318 | WM8400_LI34ZC_SHIFT, 1, 0), | |
319 | ||
320 | SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME, | |
321 | WM8400_LI34MUTE_SHIFT, 1, 0), | |
322 | ||
323 | WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume", | |
324 | WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, | |
325 | WM8400_RIN12VOL_SHIFT, | |
326 | WM8400_RIN12VOL_MASK, | |
327 | 0, | |
328 | in_pga_tlv), | |
329 | ||
330 | SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, | |
331 | WM8400_RI12ZC_SHIFT, 1, 0), | |
332 | ||
333 | SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, | |
334 | WM8400_RI12MUTE_SHIFT, 1, 0), | |
335 | ||
336 | WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume", | |
337 | WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, | |
338 | WM8400_RIN34VOL_SHIFT, | |
339 | WM8400_RIN34VOL_MASK, | |
340 | 0, | |
341 | in_pga_tlv), | |
342 | ||
343 | SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, | |
344 | WM8400_RI34ZC_SHIFT, 1, 0), | |
345 | ||
346 | SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME, | |
347 | WM8400_RI34MUTE_SHIFT, 1, 0), | |
348 | ||
349 | }; | |
350 | ||
aaf1e176 MB |
351 | /* |
352 | * _DAPM_ Controls | |
353 | */ | |
354 | ||
355 | static int inmixer_event (struct snd_soc_dapm_widget *w, | |
356 | struct snd_kcontrol *kcontrol, int event) | |
357 | { | |
358 | u16 reg, fakepower; | |
359 | ||
5fa87d34 MB |
360 | reg = snd_soc_read(w->codec, WM8400_POWER_MANAGEMENT_2); |
361 | fakepower = snd_soc_read(w->codec, WM8400_INTDRIVBITS); | |
aaf1e176 MB |
362 | |
363 | if (fakepower & ((1 << WM8400_INMIXL_PWR) | | |
364 | (1 << WM8400_AINLMUX_PWR))) { | |
365 | reg |= WM8400_AINL_ENA; | |
366 | } else { | |
367 | reg &= ~WM8400_AINL_ENA; | |
368 | } | |
369 | ||
370 | if (fakepower & ((1 << WM8400_INMIXR_PWR) | | |
371 | (1 << WM8400_AINRMUX_PWR))) { | |
372 | reg |= WM8400_AINR_ENA; | |
373 | } else { | |
1a8e8d22 | 374 | reg &= ~WM8400_AINR_ENA; |
aaf1e176 | 375 | } |
5fa87d34 | 376 | snd_soc_write(w->codec, WM8400_POWER_MANAGEMENT_2, reg); |
aaf1e176 MB |
377 | |
378 | return 0; | |
379 | } | |
380 | ||
381 | static int outmixer_event (struct snd_soc_dapm_widget *w, | |
382 | struct snd_kcontrol * kcontrol, int event) | |
383 | { | |
384 | struct soc_mixer_control *mc = | |
385 | (struct soc_mixer_control *)kcontrol->private_value; | |
386 | u32 reg_shift = mc->shift; | |
387 | int ret = 0; | |
388 | u16 reg; | |
389 | ||
390 | switch (reg_shift) { | |
391 | case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) : | |
5fa87d34 | 392 | reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER1); |
aaf1e176 MB |
393 | if (reg & WM8400_LDLO) { |
394 | printk(KERN_WARNING | |
395 | "Cannot set as Output Mixer 1 LDLO Set\n"); | |
396 | ret = -1; | |
397 | } | |
398 | break; | |
399 | case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8): | |
5fa87d34 | 400 | reg = snd_soc_read(w->codec, WM8400_OUTPUT_MIXER2); |
aaf1e176 MB |
401 | if (reg & WM8400_RDRO) { |
402 | printk(KERN_WARNING | |
403 | "Cannot set as Output Mixer 2 RDRO Set\n"); | |
404 | ret = -1; | |
405 | } | |
406 | break; | |
407 | case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8): | |
5fa87d34 | 408 | reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER); |
aaf1e176 MB |
409 | if (reg & WM8400_LDSPK) { |
410 | printk(KERN_WARNING | |
411 | "Cannot set as Speaker Mixer LDSPK Set\n"); | |
412 | ret = -1; | |
413 | } | |
414 | break; | |
415 | case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8): | |
5fa87d34 | 416 | reg = snd_soc_read(w->codec, WM8400_SPEAKER_MIXER); |
aaf1e176 MB |
417 | if (reg & WM8400_RDSPK) { |
418 | printk(KERN_WARNING | |
419 | "Cannot set as Speaker Mixer RDSPK Set\n"); | |
420 | ret = -1; | |
421 | } | |
422 | break; | |
423 | } | |
424 | ||
425 | return ret; | |
426 | } | |
427 | ||
428 | /* INMIX dB values */ | |
429 | static const unsigned int in_mix_tlv[] = { | |
430 | TLV_DB_RANGE_HEAD(1), | |
3351e9fb | 431 | 0,7, TLV_DB_SCALE_ITEM(-1200, 600, 0), |
aaf1e176 MB |
432 | }; |
433 | ||
434 | /* Left In PGA Connections */ | |
435 | static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = { | |
436 | SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0), | |
437 | SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0), | |
438 | }; | |
439 | ||
440 | static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = { | |
441 | SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0), | |
442 | SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0), | |
443 | }; | |
444 | ||
445 | /* Right In PGA Connections */ | |
446 | static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = { | |
447 | SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0), | |
448 | SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0), | |
449 | }; | |
450 | ||
451 | static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = { | |
452 | SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0), | |
453 | SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0), | |
454 | }; | |
455 | ||
456 | /* INMIXL */ | |
457 | static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = { | |
458 | SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3, | |
459 | WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv), | |
460 | SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT, | |
461 | 7, 0, in_mix_tlv), | |
462 | SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT, | |
463 | 1, 0), | |
464 | SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT, | |
465 | 1, 0), | |
466 | }; | |
467 | ||
468 | /* INMIXR */ | |
469 | static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = { | |
470 | SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4, | |
471 | WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv), | |
472 | SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT, | |
473 | 7, 0, in_mix_tlv), | |
474 | SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT, | |
475 | 1, 0), | |
476 | SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT, | |
477 | 1, 0), | |
478 | }; | |
479 | ||
480 | /* AINLMUX */ | |
481 | static const char *wm8400_ainlmux[] = | |
482 | {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"}; | |
483 | ||
484 | static const struct soc_enum wm8400_ainlmux_enum = | |
485 | SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINLMODE_SHIFT, | |
486 | ARRAY_SIZE(wm8400_ainlmux), wm8400_ainlmux); | |
487 | ||
488 | static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls = | |
489 | SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum); | |
490 | ||
491 | /* DIFFINL */ | |
492 | ||
493 | /* AINRMUX */ | |
494 | static const char *wm8400_ainrmux[] = | |
495 | {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"}; | |
496 | ||
497 | static const struct soc_enum wm8400_ainrmux_enum = | |
498 | SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINRMODE_SHIFT, | |
499 | ARRAY_SIZE(wm8400_ainrmux), wm8400_ainrmux); | |
500 | ||
501 | static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls = | |
502 | SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum); | |
503 | ||
504 | /* RXVOICE */ | |
505 | static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = { | |
506 | SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT, | |
507 | WM8400_LR4BVOL_MASK, 0, in_mix_tlv), | |
508 | SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT, | |
509 | WM8400_RL4BVOL_MASK, 0, in_mix_tlv), | |
510 | }; | |
511 | ||
512 | /* LOMIX */ | |
513 | static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = { | |
514 | SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1, | |
515 | WM8400_LRBLO_SHIFT, 1, 0), | |
516 | SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1, | |
517 | WM8400_LLBLO_SHIFT, 1, 0), | |
518 | SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1, | |
519 | WM8400_LRI3LO_SHIFT, 1, 0), | |
520 | SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1, | |
521 | WM8400_LLI3LO_SHIFT, 1, 0), | |
522 | SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1, | |
523 | WM8400_LR12LO_SHIFT, 1, 0), | |
524 | SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1, | |
525 | WM8400_LL12LO_SHIFT, 1, 0), | |
526 | SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1, | |
527 | WM8400_LDLO_SHIFT, 1, 0), | |
528 | }; | |
529 | ||
530 | /* ROMIX */ | |
531 | static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = { | |
532 | SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2, | |
533 | WM8400_RLBRO_SHIFT, 1, 0), | |
534 | SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2, | |
535 | WM8400_RRBRO_SHIFT, 1, 0), | |
536 | SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2, | |
537 | WM8400_RLI3RO_SHIFT, 1, 0), | |
538 | SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2, | |
539 | WM8400_RRI3RO_SHIFT, 1, 0), | |
540 | SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2, | |
541 | WM8400_RL12RO_SHIFT, 1, 0), | |
542 | SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2, | |
543 | WM8400_RR12RO_SHIFT, 1, 0), | |
544 | SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2, | |
545 | WM8400_RDRO_SHIFT, 1, 0), | |
546 | }; | |
547 | ||
548 | /* LONMIX */ | |
549 | static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = { | |
550 | SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1, | |
551 | WM8400_LLOPGALON_SHIFT, 1, 0), | |
552 | SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1, | |
553 | WM8400_LROPGALON_SHIFT, 1, 0), | |
554 | SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1, | |
555 | WM8400_LOPLON_SHIFT, 1, 0), | |
556 | }; | |
557 | ||
558 | /* LOPMIX */ | |
559 | static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = { | |
560 | SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1, | |
561 | WM8400_LR12LOP_SHIFT, 1, 0), | |
562 | SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1, | |
563 | WM8400_LL12LOP_SHIFT, 1, 0), | |
564 | SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1, | |
565 | WM8400_LLOPGALOP_SHIFT, 1, 0), | |
566 | }; | |
567 | ||
568 | /* RONMIX */ | |
569 | static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = { | |
570 | SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2, | |
571 | WM8400_RROPGARON_SHIFT, 1, 0), | |
572 | SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2, | |
573 | WM8400_RLOPGARON_SHIFT, 1, 0), | |
574 | SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2, | |
575 | WM8400_ROPRON_SHIFT, 1, 0), | |
576 | }; | |
577 | ||
578 | /* ROPMIX */ | |
579 | static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = { | |
580 | SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2, | |
581 | WM8400_RL12ROP_SHIFT, 1, 0), | |
582 | SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2, | |
583 | WM8400_RR12ROP_SHIFT, 1, 0), | |
584 | SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2, | |
585 | WM8400_RROPGAROP_SHIFT, 1, 0), | |
586 | }; | |
587 | ||
588 | /* OUT3MIX */ | |
589 | static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = { | |
590 | SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER, | |
591 | WM8400_LI4O3_SHIFT, 1, 0), | |
592 | SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER, | |
593 | WM8400_LPGAO3_SHIFT, 1, 0), | |
594 | }; | |
595 | ||
596 | /* OUT4MIX */ | |
597 | static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = { | |
598 | SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER, | |
599 | WM8400_RPGAO4_SHIFT, 1, 0), | |
600 | SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER, | |
601 | WM8400_RI4O4_SHIFT, 1, 0), | |
602 | }; | |
603 | ||
604 | /* SPKMIX */ | |
605 | static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = { | |
606 | SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER, | |
607 | WM8400_LI2SPK_SHIFT, 1, 0), | |
608 | SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER, | |
609 | WM8400_LB2SPK_SHIFT, 1, 0), | |
610 | SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER, | |
611 | WM8400_LOPGASPK_SHIFT, 1, 0), | |
612 | SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER, | |
613 | WM8400_LDSPK_SHIFT, 1, 0), | |
614 | SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER, | |
615 | WM8400_RDSPK_SHIFT, 1, 0), | |
616 | SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER, | |
617 | WM8400_ROPGASPK_SHIFT, 1, 0), | |
618 | SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER, | |
619 | WM8400_RL12ROP_SHIFT, 1, 0), | |
620 | SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER, | |
621 | WM8400_RI2SPK_SHIFT, 1, 0), | |
622 | }; | |
623 | ||
624 | static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = { | |
625 | /* Input Side */ | |
626 | /* Input Lines */ | |
627 | SND_SOC_DAPM_INPUT("LIN1"), | |
628 | SND_SOC_DAPM_INPUT("LIN2"), | |
629 | SND_SOC_DAPM_INPUT("LIN3"), | |
630 | SND_SOC_DAPM_INPUT("LIN4/RXN"), | |
631 | SND_SOC_DAPM_INPUT("RIN3"), | |
632 | SND_SOC_DAPM_INPUT("RIN4/RXP"), | |
633 | SND_SOC_DAPM_INPUT("RIN1"), | |
634 | SND_SOC_DAPM_INPUT("RIN2"), | |
635 | SND_SOC_DAPM_INPUT("Internal ADC Source"), | |
636 | ||
637 | /* DACs */ | |
638 | SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2, | |
639 | WM8400_ADCL_ENA_SHIFT, 0), | |
640 | SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2, | |
641 | WM8400_ADCR_ENA_SHIFT, 0), | |
642 | ||
643 | /* Input PGAs */ | |
644 | SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2, | |
645 | WM8400_LIN12_ENA_SHIFT, | |
646 | 0, &wm8400_dapm_lin12_pga_controls[0], | |
647 | ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)), | |
648 | SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2, | |
649 | WM8400_LIN34_ENA_SHIFT, | |
650 | 0, &wm8400_dapm_lin34_pga_controls[0], | |
651 | ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)), | |
652 | SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2, | |
653 | WM8400_RIN12_ENA_SHIFT, | |
654 | 0, &wm8400_dapm_rin12_pga_controls[0], | |
655 | ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)), | |
656 | SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2, | |
657 | WM8400_RIN34_ENA_SHIFT, | |
658 | 0, &wm8400_dapm_rin34_pga_controls[0], | |
659 | ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)), | |
660 | ||
661 | /* INMIXL */ | |
662 | SND_SOC_DAPM_MIXER_E("INMIXL", WM8400_INTDRIVBITS, WM8400_INMIXL_PWR, 0, | |
663 | &wm8400_dapm_inmixl_controls[0], | |
664 | ARRAY_SIZE(wm8400_dapm_inmixl_controls), | |
665 | inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
666 | ||
667 | /* AINLMUX */ | |
668 | SND_SOC_DAPM_MUX_E("AILNMUX", WM8400_INTDRIVBITS, WM8400_AINLMUX_PWR, 0, | |
669 | &wm8400_dapm_ainlmux_controls, inmixer_event, | |
670 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
671 | ||
672 | /* INMIXR */ | |
673 | SND_SOC_DAPM_MIXER_E("INMIXR", WM8400_INTDRIVBITS, WM8400_INMIXR_PWR, 0, | |
674 | &wm8400_dapm_inmixr_controls[0], | |
675 | ARRAY_SIZE(wm8400_dapm_inmixr_controls), | |
676 | inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
677 | ||
678 | /* AINRMUX */ | |
679 | SND_SOC_DAPM_MUX_E("AIRNMUX", WM8400_INTDRIVBITS, WM8400_AINRMUX_PWR, 0, | |
680 | &wm8400_dapm_ainrmux_controls, inmixer_event, | |
681 | SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), | |
682 | ||
683 | /* Output Side */ | |
684 | /* DACs */ | |
685 | SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3, | |
686 | WM8400_DACL_ENA_SHIFT, 0), | |
687 | SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3, | |
688 | WM8400_DACR_ENA_SHIFT, 0), | |
689 | ||
690 | /* LOMIX */ | |
691 | SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3, | |
692 | WM8400_LOMIX_ENA_SHIFT, | |
693 | 0, &wm8400_dapm_lomix_controls[0], | |
694 | ARRAY_SIZE(wm8400_dapm_lomix_controls), | |
695 | outmixer_event, SND_SOC_DAPM_PRE_REG), | |
696 | ||
697 | /* LONMIX */ | |
698 | SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT, | |
699 | 0, &wm8400_dapm_lonmix_controls[0], | |
700 | ARRAY_SIZE(wm8400_dapm_lonmix_controls)), | |
701 | ||
702 | /* LOPMIX */ | |
703 | SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT, | |
704 | 0, &wm8400_dapm_lopmix_controls[0], | |
705 | ARRAY_SIZE(wm8400_dapm_lopmix_controls)), | |
706 | ||
707 | /* OUT3MIX */ | |
708 | SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT, | |
709 | 0, &wm8400_dapm_out3mix_controls[0], | |
710 | ARRAY_SIZE(wm8400_dapm_out3mix_controls)), | |
711 | ||
712 | /* SPKMIX */ | |
713 | SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT, | |
714 | 0, &wm8400_dapm_spkmix_controls[0], | |
715 | ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event, | |
716 | SND_SOC_DAPM_PRE_REG), | |
717 | ||
718 | /* OUT4MIX */ | |
719 | SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT, | |
720 | 0, &wm8400_dapm_out4mix_controls[0], | |
721 | ARRAY_SIZE(wm8400_dapm_out4mix_controls)), | |
722 | ||
723 | /* ROPMIX */ | |
724 | SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT, | |
725 | 0, &wm8400_dapm_ropmix_controls[0], | |
726 | ARRAY_SIZE(wm8400_dapm_ropmix_controls)), | |
727 | ||
728 | /* RONMIX */ | |
729 | SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT, | |
730 | 0, &wm8400_dapm_ronmix_controls[0], | |
731 | ARRAY_SIZE(wm8400_dapm_ronmix_controls)), | |
732 | ||
733 | /* ROMIX */ | |
734 | SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3, | |
735 | WM8400_ROMIX_ENA_SHIFT, | |
736 | 0, &wm8400_dapm_romix_controls[0], | |
737 | ARRAY_SIZE(wm8400_dapm_romix_controls), | |
738 | outmixer_event, SND_SOC_DAPM_PRE_REG), | |
739 | ||
740 | /* LOUT PGA */ | |
741 | SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT, | |
742 | 0, NULL, 0), | |
743 | ||
744 | /* ROUT PGA */ | |
745 | SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT, | |
746 | 0, NULL, 0), | |
747 | ||
748 | /* LOPGA */ | |
749 | SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0, | |
750 | NULL, 0), | |
751 | ||
752 | /* ROPGA */ | |
753 | SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0, | |
754 | NULL, 0), | |
755 | ||
756 | /* MICBIAS */ | |
3ff51c85 MB |
757 | SND_SOC_DAPM_SUPPLY("MICBIAS", WM8400_POWER_MANAGEMENT_1, |
758 | WM8400_MIC1BIAS_ENA_SHIFT, 0, NULL, 0), | |
aaf1e176 MB |
759 | |
760 | SND_SOC_DAPM_OUTPUT("LON"), | |
761 | SND_SOC_DAPM_OUTPUT("LOP"), | |
762 | SND_SOC_DAPM_OUTPUT("OUT3"), | |
763 | SND_SOC_DAPM_OUTPUT("LOUT"), | |
764 | SND_SOC_DAPM_OUTPUT("SPKN"), | |
765 | SND_SOC_DAPM_OUTPUT("SPKP"), | |
766 | SND_SOC_DAPM_OUTPUT("ROUT"), | |
767 | SND_SOC_DAPM_OUTPUT("OUT4"), | |
768 | SND_SOC_DAPM_OUTPUT("ROP"), | |
769 | SND_SOC_DAPM_OUTPUT("RON"), | |
770 | ||
771 | SND_SOC_DAPM_OUTPUT("Internal DAC Sink"), | |
772 | }; | |
773 | ||
b4505ab1 | 774 | static const struct snd_soc_dapm_route wm8400_dapm_routes[] = { |
aaf1e176 MB |
775 | /* Make DACs turn on when playing even if not mixed into any outputs */ |
776 | {"Internal DAC Sink", NULL, "Left DAC"}, | |
777 | {"Internal DAC Sink", NULL, "Right DAC"}, | |
778 | ||
779 | /* Make ADCs turn on when recording | |
780 | * even if not mixed from any inputs */ | |
781 | {"Left ADC", NULL, "Internal ADC Source"}, | |
782 | {"Right ADC", NULL, "Internal ADC Source"}, | |
783 | ||
784 | /* Input Side */ | |
785 | /* LIN12 PGA */ | |
786 | {"LIN12 PGA", "LIN1 Switch", "LIN1"}, | |
787 | {"LIN12 PGA", "LIN2 Switch", "LIN2"}, | |
788 | /* LIN34 PGA */ | |
789 | {"LIN34 PGA", "LIN3 Switch", "LIN3"}, | |
790 | {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"}, | |
791 | /* INMIXL */ | |
792 | {"INMIXL", "Record Left Volume", "LOMIX"}, | |
793 | {"INMIXL", "LIN2 Volume", "LIN2"}, | |
794 | {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"}, | |
795 | {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"}, | |
796 | /* AILNMUX */ | |
797 | {"AILNMUX", "INMIXL Mix", "INMIXL"}, | |
798 | {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"}, | |
799 | {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"}, | |
800 | {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"}, | |
801 | {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"}, | |
802 | /* ADC */ | |
803 | {"Left ADC", NULL, "AILNMUX"}, | |
804 | ||
805 | /* RIN12 PGA */ | |
806 | {"RIN12 PGA", "RIN1 Switch", "RIN1"}, | |
807 | {"RIN12 PGA", "RIN2 Switch", "RIN2"}, | |
808 | /* RIN34 PGA */ | |
809 | {"RIN34 PGA", "RIN3 Switch", "RIN3"}, | |
810 | {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"}, | |
811 | /* INMIXL */ | |
812 | {"INMIXR", "Record Right Volume", "ROMIX"}, | |
813 | {"INMIXR", "RIN2 Volume", "RIN2"}, | |
814 | {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"}, | |
815 | {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"}, | |
816 | /* AIRNMUX */ | |
817 | {"AIRNMUX", "INMIXR Mix", "INMIXR"}, | |
818 | {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"}, | |
819 | {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"}, | |
820 | {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"}, | |
821 | {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"}, | |
822 | /* ADC */ | |
823 | {"Right ADC", NULL, "AIRNMUX"}, | |
824 | ||
825 | /* LOMIX */ | |
826 | {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"}, | |
827 | {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"}, | |
828 | {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, | |
829 | {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, | |
830 | {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"}, | |
831 | {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"}, | |
832 | {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"}, | |
833 | ||
834 | /* ROMIX */ | |
835 | {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"}, | |
836 | {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"}, | |
837 | {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"}, | |
838 | {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"}, | |
839 | {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"}, | |
840 | {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"}, | |
841 | {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"}, | |
842 | ||
843 | /* SPKMIX */ | |
844 | {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"}, | |
845 | {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"}, | |
846 | {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"}, | |
847 | {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"}, | |
848 | {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"}, | |
849 | {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"}, | |
850 | {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"}, | |
851 | {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"}, | |
852 | ||
853 | /* LONMIX */ | |
854 | {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"}, | |
855 | {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"}, | |
856 | {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"}, | |
857 | ||
858 | /* LOPMIX */ | |
859 | {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"}, | |
860 | {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"}, | |
861 | {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"}, | |
862 | ||
863 | /* OUT3MIX */ | |
864 | {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"}, | |
865 | {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"}, | |
866 | ||
867 | /* OUT4MIX */ | |
868 | {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"}, | |
869 | {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"}, | |
870 | ||
871 | /* RONMIX */ | |
872 | {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"}, | |
873 | {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"}, | |
874 | {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"}, | |
875 | ||
876 | /* ROPMIX */ | |
877 | {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"}, | |
878 | {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"}, | |
879 | {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"}, | |
880 | ||
881 | /* Out Mixer PGAs */ | |
882 | {"LOPGA", NULL, "LOMIX"}, | |
883 | {"ROPGA", NULL, "ROMIX"}, | |
884 | ||
885 | {"LOUT PGA", NULL, "LOMIX"}, | |
886 | {"ROUT PGA", NULL, "ROMIX"}, | |
887 | ||
888 | /* Output Pins */ | |
889 | {"LON", NULL, "LONMIX"}, | |
890 | {"LOP", NULL, "LOPMIX"}, | |
891 | {"OUT3", NULL, "OUT3MIX"}, | |
892 | {"LOUT", NULL, "LOUT PGA"}, | |
893 | {"SPKN", NULL, "SPKMIX"}, | |
894 | {"ROUT", NULL, "ROUT PGA"}, | |
895 | {"OUT4", NULL, "OUT4MIX"}, | |
896 | {"ROP", NULL, "ROPMIX"}, | |
897 | {"RON", NULL, "RONMIX"}, | |
898 | }; | |
899 | ||
aaf1e176 MB |
900 | /* |
901 | * Clock after FLL and dividers | |
902 | */ | |
903 | static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai, | |
904 | int clk_id, unsigned int freq, int dir) | |
905 | { | |
906 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 907 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
aaf1e176 MB |
908 | |
909 | wm8400->sysclk = freq; | |
910 | return 0; | |
911 | } | |
912 | ||
e8523b64 MB |
913 | struct fll_factors { |
914 | u16 n; | |
915 | u16 k; | |
916 | u16 outdiv; | |
917 | u16 fratio; | |
918 | u16 freq_ref; | |
919 | }; | |
920 | ||
921 | #define FIXED_FLL_SIZE ((1 << 16) * 10) | |
922 | ||
923 | static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors, | |
924 | unsigned int Fref, unsigned int Fout) | |
925 | { | |
926 | u64 Kpart; | |
927 | unsigned int K, Nmod, target; | |
928 | ||
929 | factors->outdiv = 2; | |
930 | while (Fout * factors->outdiv < 90000000 || | |
931 | Fout * factors->outdiv > 100000000) { | |
932 | factors->outdiv *= 2; | |
933 | if (factors->outdiv > 32) { | |
934 | dev_err(wm8400->wm8400->dev, | |
449bd54d | 935 | "Unsupported FLL output frequency %uHz\n", |
e8523b64 MB |
936 | Fout); |
937 | return -EINVAL; | |
938 | } | |
939 | } | |
940 | target = Fout * factors->outdiv; | |
941 | factors->outdiv = factors->outdiv >> 2; | |
942 | ||
943 | if (Fref < 48000) | |
944 | factors->freq_ref = 1; | |
945 | else | |
946 | factors->freq_ref = 0; | |
947 | ||
948 | if (Fref < 1000000) | |
949 | factors->fratio = 9; | |
950 | else | |
951 | factors->fratio = 0; | |
952 | ||
953 | /* Ensure we have a fractional part */ | |
954 | do { | |
955 | if (Fref < 1000000) | |
956 | factors->fratio--; | |
957 | else | |
958 | factors->fratio++; | |
959 | ||
960 | if (factors->fratio < 1 || factors->fratio > 8) { | |
961 | dev_err(wm8400->wm8400->dev, | |
962 | "Unable to calculate FRATIO\n"); | |
963 | return -EINVAL; | |
964 | } | |
965 | ||
966 | factors->n = target / (Fref * factors->fratio); | |
967 | Nmod = target % (Fref * factors->fratio); | |
968 | } while (Nmod == 0); | |
969 | ||
970 | /* Calculate fractional part - scale up so we can round. */ | |
971 | Kpart = FIXED_FLL_SIZE * (long long)Nmod; | |
972 | ||
973 | do_div(Kpart, (Fref * factors->fratio)); | |
974 | ||
975 | K = Kpart & 0xFFFFFFFF; | |
976 | ||
977 | if ((K % 10) >= 5) | |
978 | K += 5; | |
979 | ||
980 | /* Move down to proper range now rounding is done */ | |
981 | factors->k = K / 10; | |
982 | ||
983 | dev_dbg(wm8400->wm8400->dev, | |
449bd54d | 984 | "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n", |
e8523b64 MB |
985 | Fref, Fout, |
986 | factors->n, factors->k, factors->fratio, factors->outdiv); | |
987 | ||
988 | return 0; | |
989 | } | |
990 | ||
991 | static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, | |
85488037 MB |
992 | int source, unsigned int freq_in, |
993 | unsigned int freq_out) | |
e8523b64 MB |
994 | { |
995 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 996 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
e8523b64 MB |
997 | struct fll_factors factors; |
998 | int ret; | |
999 | u16 reg; | |
1000 | ||
1001 | if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out) | |
1002 | return 0; | |
1003 | ||
8aa2df53 | 1004 | if (freq_out) { |
e8523b64 MB |
1005 | ret = fll_factors(wm8400, &factors, freq_in, freq_out); |
1006 | if (ret != 0) | |
1007 | return ret; | |
8aa2df53 MB |
1008 | } else { |
1009 | /* Bodge GCC 4.4.0 uninitialised variable warning - it | |
1010 | * doesn't seem capable of working out that we exit if | |
1011 | * freq_out is 0 before any of the uses. */ | |
1012 | memset(&factors, 0, sizeof(factors)); | |
e8523b64 MB |
1013 | } |
1014 | ||
1015 | wm8400->fll_out = freq_out; | |
1016 | wm8400->fll_in = freq_in; | |
1017 | ||
1018 | /* We *must* disable the FLL before any changes */ | |
5fa87d34 | 1019 | reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_2); |
e8523b64 | 1020 | reg &= ~WM8400_FLL_ENA; |
5fa87d34 | 1021 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_2, reg); |
e8523b64 | 1022 | |
5fa87d34 | 1023 | reg = snd_soc_read(codec, WM8400_FLL_CONTROL_1); |
e8523b64 | 1024 | reg &= ~WM8400_FLL_OSC_ENA; |
5fa87d34 | 1025 | snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg); |
e8523b64 | 1026 | |
8aa2df53 | 1027 | if (!freq_out) |
e8523b64 MB |
1028 | return 0; |
1029 | ||
1030 | reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK); | |
1031 | reg |= WM8400_FLL_FRAC | factors.fratio; | |
1032 | reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT; | |
5fa87d34 | 1033 | snd_soc_write(codec, WM8400_FLL_CONTROL_1, reg); |
e8523b64 | 1034 | |
5fa87d34 MB |
1035 | snd_soc_write(codec, WM8400_FLL_CONTROL_2, factors.k); |
1036 | snd_soc_write(codec, WM8400_FLL_CONTROL_3, factors.n); | |
e8523b64 | 1037 | |
5fa87d34 | 1038 | reg = snd_soc_read(codec, WM8400_FLL_CONTROL_4); |
1d533de9 | 1039 | reg &= ~WM8400_FLL_OUTDIV_MASK; |
e8523b64 | 1040 | reg |= factors.outdiv; |
5fa87d34 | 1041 | snd_soc_write(codec, WM8400_FLL_CONTROL_4, reg); |
e8523b64 MB |
1042 | |
1043 | return 0; | |
1044 | } | |
1045 | ||
aaf1e176 MB |
1046 | /* |
1047 | * Sets ADC and Voice DAC format. | |
1048 | */ | |
1049 | static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai, | |
1050 | unsigned int fmt) | |
1051 | { | |
1052 | struct snd_soc_codec *codec = codec_dai->codec; | |
1053 | u16 audio1, audio3; | |
1054 | ||
5fa87d34 MB |
1055 | audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1); |
1056 | audio3 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_3); | |
aaf1e176 MB |
1057 | |
1058 | /* set master/slave audio interface */ | |
1059 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
1060 | case SND_SOC_DAIFMT_CBS_CFS: | |
1061 | audio3 &= ~WM8400_AIF_MSTR1; | |
1062 | break; | |
1063 | case SND_SOC_DAIFMT_CBM_CFM: | |
1064 | audio3 |= WM8400_AIF_MSTR1; | |
1065 | break; | |
1066 | default: | |
1067 | return -EINVAL; | |
1068 | } | |
1069 | ||
1070 | audio1 &= ~WM8400_AIF_FMT_MASK; | |
1071 | ||
1072 | /* interface format */ | |
1073 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
1074 | case SND_SOC_DAIFMT_I2S: | |
1075 | audio1 |= WM8400_AIF_FMT_I2S; | |
1076 | audio1 &= ~WM8400_AIF_LRCLK_INV; | |
1077 | break; | |
1078 | case SND_SOC_DAIFMT_RIGHT_J: | |
1079 | audio1 |= WM8400_AIF_FMT_RIGHTJ; | |
1080 | audio1 &= ~WM8400_AIF_LRCLK_INV; | |
1081 | break; | |
1082 | case SND_SOC_DAIFMT_LEFT_J: | |
1083 | audio1 |= WM8400_AIF_FMT_LEFTJ; | |
1084 | audio1 &= ~WM8400_AIF_LRCLK_INV; | |
1085 | break; | |
1086 | case SND_SOC_DAIFMT_DSP_A: | |
1087 | audio1 |= WM8400_AIF_FMT_DSP; | |
1088 | audio1 &= ~WM8400_AIF_LRCLK_INV; | |
1089 | break; | |
1090 | case SND_SOC_DAIFMT_DSP_B: | |
1091 | audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV; | |
1092 | break; | |
1093 | default: | |
1094 | return -EINVAL; | |
1095 | } | |
1096 | ||
5fa87d34 MB |
1097 | snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); |
1098 | snd_soc_write(codec, WM8400_AUDIO_INTERFACE_3, audio3); | |
aaf1e176 MB |
1099 | return 0; |
1100 | } | |
1101 | ||
1102 | static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai, | |
1103 | int div_id, int div) | |
1104 | { | |
1105 | struct snd_soc_codec *codec = codec_dai->codec; | |
1106 | u16 reg; | |
1107 | ||
1108 | switch (div_id) { | |
1109 | case WM8400_MCLK_DIV: | |
5fa87d34 | 1110 | reg = snd_soc_read(codec, WM8400_CLOCKING_2) & |
aaf1e176 | 1111 | ~WM8400_MCLK_DIV_MASK; |
5fa87d34 | 1112 | snd_soc_write(codec, WM8400_CLOCKING_2, reg | div); |
aaf1e176 MB |
1113 | break; |
1114 | case WM8400_DACCLK_DIV: | |
5fa87d34 | 1115 | reg = snd_soc_read(codec, WM8400_CLOCKING_2) & |
aaf1e176 | 1116 | ~WM8400_DAC_CLKDIV_MASK; |
5fa87d34 | 1117 | snd_soc_write(codec, WM8400_CLOCKING_2, reg | div); |
aaf1e176 MB |
1118 | break; |
1119 | case WM8400_ADCCLK_DIV: | |
5fa87d34 | 1120 | reg = snd_soc_read(codec, WM8400_CLOCKING_2) & |
aaf1e176 | 1121 | ~WM8400_ADC_CLKDIV_MASK; |
5fa87d34 | 1122 | snd_soc_write(codec, WM8400_CLOCKING_2, reg | div); |
aaf1e176 MB |
1123 | break; |
1124 | case WM8400_BCLK_DIV: | |
5fa87d34 | 1125 | reg = snd_soc_read(codec, WM8400_CLOCKING_1) & |
aaf1e176 | 1126 | ~WM8400_BCLK_DIV_MASK; |
5fa87d34 | 1127 | snd_soc_write(codec, WM8400_CLOCKING_1, reg | div); |
aaf1e176 MB |
1128 | break; |
1129 | default: | |
1130 | return -EINVAL; | |
1131 | } | |
1132 | ||
1133 | return 0; | |
1134 | } | |
1135 | ||
1136 | /* | |
1137 | * Set PCM DAI bit size and sample rate. | |
1138 | */ | |
1139 | static int wm8400_hw_params(struct snd_pcm_substream *substream, | |
1140 | struct snd_pcm_hw_params *params, | |
1141 | struct snd_soc_dai *dai) | |
1142 | { | |
e6968a17 | 1143 | struct snd_soc_codec *codec = dai->codec; |
5fa87d34 | 1144 | u16 audio1 = snd_soc_read(codec, WM8400_AUDIO_INTERFACE_1); |
aaf1e176 MB |
1145 | |
1146 | audio1 &= ~WM8400_AIF_WL_MASK; | |
1147 | /* bit size */ | |
1148 | switch (params_format(params)) { | |
1149 | case SNDRV_PCM_FORMAT_S16_LE: | |
1150 | break; | |
1151 | case SNDRV_PCM_FORMAT_S20_3LE: | |
1152 | audio1 |= WM8400_AIF_WL_20BITS; | |
1153 | break; | |
1154 | case SNDRV_PCM_FORMAT_S24_LE: | |
1155 | audio1 |= WM8400_AIF_WL_24BITS; | |
1156 | break; | |
1157 | case SNDRV_PCM_FORMAT_S32_LE: | |
1158 | audio1 |= WM8400_AIF_WL_32BITS; | |
1159 | break; | |
1160 | } | |
1161 | ||
5fa87d34 | 1162 | snd_soc_write(codec, WM8400_AUDIO_INTERFACE_1, audio1); |
aaf1e176 MB |
1163 | return 0; |
1164 | } | |
1165 | ||
1166 | static int wm8400_mute(struct snd_soc_dai *dai, int mute) | |
1167 | { | |
1168 | struct snd_soc_codec *codec = dai->codec; | |
5fa87d34 | 1169 | u16 val = snd_soc_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE; |
aaf1e176 MB |
1170 | |
1171 | if (mute) | |
5fa87d34 | 1172 | snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); |
aaf1e176 | 1173 | else |
5fa87d34 | 1174 | snd_soc_write(codec, WM8400_DAC_CTRL, val); |
aaf1e176 MB |
1175 | |
1176 | return 0; | |
1177 | } | |
1178 | ||
1179 | /* TODO: set bias for best performance at standby */ | |
1180 | static int wm8400_set_bias_level(struct snd_soc_codec *codec, | |
1181 | enum snd_soc_bias_level level) | |
1182 | { | |
b2c812e2 | 1183 | struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec); |
aaf1e176 MB |
1184 | u16 val; |
1185 | int ret; | |
1186 | ||
1187 | switch (level) { | |
1188 | case SND_SOC_BIAS_ON: | |
1189 | break; | |
1190 | ||
1191 | case SND_SOC_BIAS_PREPARE: | |
1192 | /* VMID=2*50k */ | |
5fa87d34 | 1193 | val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) & |
aaf1e176 | 1194 | ~WM8400_VMID_MODE_MASK; |
5fa87d34 | 1195 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2); |
aaf1e176 MB |
1196 | break; |
1197 | ||
1198 | case SND_SOC_BIAS_STANDBY: | |
ce6120cc | 1199 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
aaf1e176 MB |
1200 | ret = regulator_bulk_enable(ARRAY_SIZE(power), |
1201 | &power[0]); | |
1202 | if (ret != 0) { | |
1203 | dev_err(wm8400->wm8400->dev, | |
1204 | "Failed to enable regulators: %d\n", | |
1205 | ret); | |
1206 | return ret; | |
1207 | } | |
1208 | ||
5fa87d34 | 1209 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, |
aaf1e176 MB |
1210 | WM8400_CODEC_ENA | WM8400_SYSCLK_ENA); |
1211 | ||
aaf1e176 | 1212 | /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */ |
5fa87d34 | 1213 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | |
aaf1e176 MB |
1214 | WM8400_BUFDCOPEN | WM8400_POBCTRL); |
1215 | ||
e3598f6e | 1216 | msleep(50); |
aaf1e176 MB |
1217 | |
1218 | /* Enable VREF & VMID at 2x50k */ | |
5fa87d34 | 1219 | val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); |
aaf1e176 | 1220 | val |= 0x2 | WM8400_VREF_ENA; |
5fa87d34 | 1221 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); |
aaf1e176 | 1222 | |
aaf1e176 | 1223 | /* Enable BUFIOEN */ |
5fa87d34 | 1224 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | |
aaf1e176 MB |
1225 | WM8400_BUFDCOPEN | WM8400_POBCTRL | |
1226 | WM8400_BUFIOEN); | |
1227 | ||
aaf1e176 | 1228 | /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ |
5fa87d34 | 1229 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN); |
aaf1e176 MB |
1230 | } |
1231 | ||
1232 | /* VMID=2*300k */ | |
5fa87d34 | 1233 | val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1) & |
aaf1e176 | 1234 | ~WM8400_VMID_MODE_MASK; |
5fa87d34 | 1235 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4); |
aaf1e176 MB |
1236 | break; |
1237 | ||
1238 | case SND_SOC_BIAS_OFF: | |
1239 | /* Enable POBCTRL and SOFT_ST */ | |
5fa87d34 | 1240 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | |
aaf1e176 MB |
1241 | WM8400_POBCTRL | WM8400_BUFIOEN); |
1242 | ||
1243 | /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */ | |
5fa87d34 | 1244 | snd_soc_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST | |
aaf1e176 MB |
1245 | WM8400_BUFDCOPEN | WM8400_POBCTRL | |
1246 | WM8400_BUFIOEN); | |
1247 | ||
1248 | /* mute DAC */ | |
5fa87d34 MB |
1249 | val = snd_soc_read(codec, WM8400_DAC_CTRL); |
1250 | snd_soc_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE); | |
aaf1e176 MB |
1251 | |
1252 | /* Enable any disabled outputs */ | |
5fa87d34 | 1253 | val = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); |
aaf1e176 MB |
1254 | val |= WM8400_SPK_ENA | WM8400_OUT3_ENA | |
1255 | WM8400_OUT4_ENA | WM8400_LOUT_ENA | | |
1256 | WM8400_ROUT_ENA; | |
5fa87d34 | 1257 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); |
aaf1e176 MB |
1258 | |
1259 | /* Disable VMID */ | |
1260 | val &= ~WM8400_VMID_MODE_MASK; | |
5fa87d34 | 1261 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); |
aaf1e176 MB |
1262 | |
1263 | msleep(300); | |
1264 | ||
1265 | /* Enable all output discharge bits */ | |
5fa87d34 | 1266 | snd_soc_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE | |
aaf1e176 MB |
1267 | WM8400_DIS_RLINE | WM8400_DIS_OUT3 | |
1268 | WM8400_DIS_OUT4 | WM8400_DIS_LOUT | | |
1269 | WM8400_DIS_ROUT); | |
1270 | ||
1271 | /* Disable VREF */ | |
1272 | val &= ~WM8400_VREF_ENA; | |
5fa87d34 | 1273 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, val); |
aaf1e176 MB |
1274 | |
1275 | /* disable POBCTRL, SOFT_ST and BUFDCOPEN */ | |
5fa87d34 | 1276 | snd_soc_write(codec, WM8400_ANTIPOP2, 0x0); |
aaf1e176 MB |
1277 | |
1278 | ret = regulator_bulk_disable(ARRAY_SIZE(power), | |
1279 | &power[0]); | |
1280 | if (ret != 0) | |
1281 | return ret; | |
1282 | ||
1283 | break; | |
1284 | } | |
1285 | ||
ce6120cc | 1286 | codec->dapm.bias_level = level; |
aaf1e176 MB |
1287 | return 0; |
1288 | } | |
1289 | ||
1290 | #define WM8400_RATES SNDRV_PCM_RATE_8000_96000 | |
1291 | ||
1292 | #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
1293 | SNDRV_PCM_FMTBIT_S24_LE) | |
1294 | ||
85e7652d | 1295 | static const struct snd_soc_dai_ops wm8400_dai_ops = { |
65ec1cd1 MB |
1296 | .hw_params = wm8400_hw_params, |
1297 | .digital_mute = wm8400_mute, | |
1298 | .set_fmt = wm8400_set_dai_fmt, | |
1299 | .set_clkdiv = wm8400_set_dai_clkdiv, | |
1300 | .set_sysclk = wm8400_set_dai_sysclk, | |
e8523b64 | 1301 | .set_pll = wm8400_set_dai_pll, |
65ec1cd1 MB |
1302 | }; |
1303 | ||
aaf1e176 MB |
1304 | /* |
1305 | * The WM8400 supports 2 different and mutually exclusive DAI | |
1306 | * configurations. | |
1307 | * | |
1308 | * 1. ADC/DAC on Primary Interface | |
1309 | * 2. ADC on Primary Interface/DAC on secondary | |
1310 | */ | |
f0fba2ad | 1311 | static struct snd_soc_dai_driver wm8400_dai = { |
aaf1e176 | 1312 | /* ADC/DAC on primary */ |
f0fba2ad | 1313 | .name = "wm8400-hifi", |
aaf1e176 MB |
1314 | .playback = { |
1315 | .stream_name = "Playback", | |
1316 | .channels_min = 1, | |
1317 | .channels_max = 2, | |
1318 | .rates = WM8400_RATES, | |
1319 | .formats = WM8400_FORMATS, | |
1320 | }, | |
1321 | .capture = { | |
1322 | .stream_name = "Capture", | |
1323 | .channels_min = 1, | |
1324 | .channels_max = 2, | |
1325 | .rates = WM8400_RATES, | |
1326 | .formats = WM8400_FORMATS, | |
1327 | }, | |
65ec1cd1 | 1328 | .ops = &wm8400_dai_ops, |
aaf1e176 | 1329 | }; |
aaf1e176 | 1330 | |
84b315ee | 1331 | static int wm8400_suspend(struct snd_soc_codec *codec) |
aaf1e176 | 1332 | { |
aaf1e176 MB |
1333 | wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF); |
1334 | ||
1335 | return 0; | |
1336 | } | |
1337 | ||
f0fba2ad | 1338 | static int wm8400_resume(struct snd_soc_codec *codec) |
aaf1e176 | 1339 | { |
aaf1e176 MB |
1340 | wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
1341 | ||
1342 | return 0; | |
1343 | } | |
1344 | ||
aaf1e176 MB |
1345 | static void wm8400_probe_deferred(struct work_struct *work) |
1346 | { | |
1347 | struct wm8400_priv *priv = container_of(work, struct wm8400_priv, | |
1348 | work); | |
f0fba2ad | 1349 | struct snd_soc_codec *codec = priv->codec; |
aaf1e176 MB |
1350 | |
1351 | /* charge output caps */ | |
1352 | wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY); | |
aaf1e176 MB |
1353 | } |
1354 | ||
f0fba2ad | 1355 | static int wm8400_codec_probe(struct snd_soc_codec *codec) |
aaf1e176 | 1356 | { |
e45be4b5 | 1357 | struct wm8400 *wm8400 = dev_get_platdata(codec->dev); |
aaf1e176 MB |
1358 | struct wm8400_priv *priv; |
1359 | int ret; | |
1360 | u16 reg; | |
aaf1e176 | 1361 | |
b903c0ed MB |
1362 | priv = devm_kzalloc(codec->dev, sizeof(struct wm8400_priv), |
1363 | GFP_KERNEL); | |
aaf1e176 MB |
1364 | if (priv == NULL) |
1365 | return -ENOMEM; | |
1366 | ||
b2c812e2 | 1367 | snd_soc_codec_set_drvdata(codec, priv); |
f0fba2ad LG |
1368 | codec->control_data = priv->wm8400 = wm8400; |
1369 | priv->codec = codec; | |
aaf1e176 | 1370 | |
95a5b240 | 1371 | ret = devm_regulator_bulk_get(wm8400->dev, |
aaf1e176 MB |
1372 | ARRAY_SIZE(power), &power[0]); |
1373 | if (ret != 0) { | |
f0fba2ad | 1374 | dev_err(codec->dev, "Failed to get regulators: %d\n", ret); |
b903c0ed | 1375 | return ret; |
aaf1e176 MB |
1376 | } |
1377 | ||
aaf1e176 MB |
1378 | INIT_WORK(&priv->work, wm8400_probe_deferred); |
1379 | ||
1380 | wm8400_codec_reset(codec); | |
1381 | ||
5fa87d34 MB |
1382 | reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); |
1383 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA); | |
aaf1e176 MB |
1384 | |
1385 | /* Latch volume update bits */ | |
5fa87d34 MB |
1386 | reg = snd_soc_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME); |
1387 | snd_soc_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME, | |
aaf1e176 | 1388 | reg & WM8400_IPVU); |
5fa87d34 MB |
1389 | reg = snd_soc_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME); |
1390 | snd_soc_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME, | |
aaf1e176 MB |
1391 | reg & WM8400_IPVU); |
1392 | ||
5fa87d34 MB |
1393 | snd_soc_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8)); |
1394 | snd_soc_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8)); | |
aaf1e176 | 1395 | |
95a5b240 SK |
1396 | if (!schedule_work(&priv->work)) |
1397 | return -EINVAL; | |
aaf1e176 | 1398 | return 0; |
aaf1e176 MB |
1399 | } |
1400 | ||
f0fba2ad | 1401 | static int wm8400_codec_remove(struct snd_soc_codec *codec) |
aaf1e176 | 1402 | { |
aaf1e176 MB |
1403 | u16 reg; |
1404 | ||
5fa87d34 MB |
1405 | reg = snd_soc_read(codec, WM8400_POWER_MANAGEMENT_1); |
1406 | snd_soc_write(codec, WM8400_POWER_MANAGEMENT_1, | |
aaf1e176 MB |
1407 | reg & (~WM8400_CODEC_ENA)); |
1408 | ||
f0fba2ad LG |
1409 | return 0; |
1410 | } | |
1411 | ||
1412 | static struct snd_soc_codec_driver soc_codec_dev_wm8400 = { | |
1413 | .probe = wm8400_codec_probe, | |
1414 | .remove = wm8400_codec_remove, | |
1415 | .suspend = wm8400_suspend, | |
1416 | .resume = wm8400_resume, | |
5fa87d34 | 1417 | .read = snd_soc_read, |
f0fba2ad LG |
1418 | .write = wm8400_write, |
1419 | .set_bias_level = wm8400_set_bias_level, | |
b4505ab1 MB |
1420 | |
1421 | .controls = wm8400_snd_controls, | |
1422 | .num_controls = ARRAY_SIZE(wm8400_snd_controls), | |
1423 | .dapm_widgets = wm8400_dapm_widgets, | |
1424 | .num_dapm_widgets = ARRAY_SIZE(wm8400_dapm_widgets), | |
1425 | .dapm_routes = wm8400_dapm_routes, | |
1426 | .num_dapm_routes = ARRAY_SIZE(wm8400_dapm_routes), | |
f0fba2ad LG |
1427 | }; |
1428 | ||
7a79e94e | 1429 | static int wm8400_probe(struct platform_device *pdev) |
f0fba2ad LG |
1430 | { |
1431 | return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400, | |
1432 | &wm8400_dai, 1); | |
1433 | } | |
aaf1e176 | 1434 | |
7a79e94e | 1435 | static int wm8400_remove(struct platform_device *pdev) |
f0fba2ad LG |
1436 | { |
1437 | snd_soc_unregister_codec(&pdev->dev); | |
aaf1e176 MB |
1438 | return 0; |
1439 | } | |
1440 | ||
1441 | static struct platform_driver wm8400_codec_driver = { | |
1442 | .driver = { | |
f0fba2ad LG |
1443 | .name = "wm8400-codec", |
1444 | .owner = THIS_MODULE, | |
1445 | }, | |
1446 | .probe = wm8400_probe, | |
7a79e94e | 1447 | .remove = wm8400_remove, |
aaf1e176 MB |
1448 | }; |
1449 | ||
5bbcc3c0 | 1450 | module_platform_driver(wm8400_codec_driver); |
aaf1e176 MB |
1451 | |
1452 | MODULE_DESCRIPTION("ASoC WM8400 driver"); | |
1453 | MODULE_AUTHOR("Mark Brown"); | |
1454 | MODULE_LICENSE("GPL"); | |
1455 | MODULE_ALIAS("platform:wm8400-codec"); |