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ASoC: tlv320dac33: Limit the US_TO_SAMPLES macro
[deliverable/linux.git] / sound / soc / codecs / wm8580.c
CommitLineData
e88ba015
MB		 1/*
2 * wm8580.c -- WM8580 ALSA Soc Audio driver
3 *
6f7cb44b 4 * Copyright 2008, 2009 Wolfson Microelectronics PLC.
e88ba015
MB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Notes:
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
14 *
15 * Currently only the primary audio interface is supported - S/PDIF and
16 * the secondary audio interfaces are not.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
e88ba015
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
a583cd53 27#include <linux/regulator/consumer.h>
5a0e3ad6 28#include <linux/slab.h>
a583cd53 29
e88ba015
MB		 30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/tlv.h>
36#include <sound/initval.h>
37#include <asm/div64.h>
38
39#include "wm8580.h"
40
e88ba015
MB		 41/* WM8580 register space */
42#define WM8580_PLLA1 0x00
43#define WM8580_PLLA2 0x01
44#define WM8580_PLLA3 0x02
45#define WM8580_PLLA4 0x03
46#define WM8580_PLLB1 0x04
47#define WM8580_PLLB2 0x05
48#define WM8580_PLLB3 0x06
49#define WM8580_PLLB4 0x07
50#define WM8580_CLKSEL 0x08
51#define WM8580_PAIF1 0x09
52#define WM8580_PAIF2 0x0A
53#define WM8580_SAIF1 0x0B
54#define WM8580_PAIF3 0x0C
55#define WM8580_PAIF4 0x0D
56#define WM8580_SAIF2 0x0E
57#define WM8580_DAC_CONTROL1 0x0F
58#define WM8580_DAC_CONTROL2 0x10
59#define WM8580_DAC_CONTROL3 0x11
60#define WM8580_DAC_CONTROL4 0x12
61#define WM8580_DAC_CONTROL5 0x13
62#define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
63#define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
64#define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
65#define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
66#define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
67#define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
68#define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
69#define WM8580_ADC_CONTROL1 0x1D
70#define WM8580_SPDTXCHAN0 0x1E
71#define WM8580_SPDTXCHAN1 0x1F
72#define WM8580_SPDTXCHAN2 0x20
73#define WM8580_SPDTXCHAN3 0x21
74#define WM8580_SPDTXCHAN4 0x22
75#define WM8580_SPDTXCHAN5 0x23
76#define WM8580_SPDMODE 0x24
77#define WM8580_INTMASK 0x25
78#define WM8580_GPO1 0x26
79#define WM8580_GPO2 0x27
80#define WM8580_GPO3 0x28
81#define WM8580_GPO4 0x29
82#define WM8580_GPO5 0x2A
83#define WM8580_INTSTAT 0x2B
84#define WM8580_SPDRXCHAN1 0x2C
85#define WM8580_SPDRXCHAN2 0x2D
86#define WM8580_SPDRXCHAN3 0x2E
87#define WM8580_SPDRXCHAN4 0x2F
88#define WM8580_SPDRXCHAN5 0x30
89#define WM8580_SPDSTAT 0x31
90#define WM8580_PWRDN1 0x32
91#define WM8580_PWRDN2 0x33
92#define WM8580_READBACK 0x34
93#define WM8580_RESET 0x35
94
6f7cb44b
MB		 95#define WM8580_MAX_REGISTER 0x35
96
6bfb6aa9
MB		 97#define WM8580_DACOSR 0x40
98
e88ba015
MB		 99/* PLLB4 (register 7h) */
100#define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
101#define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
102#define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
103#define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
104
105#define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
106#define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
107#define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
108#define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
109
110/* CLKSEL (register 8h) */
111#define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
112#define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
113#define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
114
115/* AIF control 1 (registers 9h-bh) */
116#define WM8580_AIF_RATE_MASK 0x7
e88ba015 117#define WM8580_AIF_BCLKSEL_MASK 0x18
e88ba015
MB		 118
119#define WM8580_AIF_MS 0x20
120
121#define WM8580_AIF_CLKSRC_MASK 0xc0
122#define WM8580_AIF_CLKSRC_PLLA 0x40
123#define WM8580_AIF_CLKSRC_PLLB 0x40
124#define WM8580_AIF_CLKSRC_MCLK 0xc0
125
126/* AIF control 2 (registers ch-eh) */
127#define WM8580_AIF_FMT_MASK 0x03
128#define WM8580_AIF_FMT_RIGHTJ 0x00
129#define WM8580_AIF_FMT_LEFTJ 0x01
130#define WM8580_AIF_FMT_I2S 0x02
131#define WM8580_AIF_FMT_DSP 0x03
132
133#define WM8580_AIF_LENGTH_MASK 0x0c
134#define WM8580_AIF_LENGTH_16 0x00
135#define WM8580_AIF_LENGTH_20 0x04
136#define WM8580_AIF_LENGTH_24 0x08
137#define WM8580_AIF_LENGTH_32 0x0c
138
139#define WM8580_AIF_LRP 0x10
140#define WM8580_AIF_BCP 0x20
141
142/* Powerdown Register 1 (register 32h) */
143#define WM8580_PWRDN1_PWDN 0x001
144#define WM8580_PWRDN1_ALLDACPD 0x040
145
146/* Powerdown Register 2 (register 33h) */
147#define WM8580_PWRDN2_OSSCPD 0x001
148#define WM8580_PWRDN2_PLLAPD 0x002
149#define WM8580_PWRDN2_PLLBPD 0x004
150#define WM8580_PWRDN2_SPDIFPD 0x008
151#define WM8580_PWRDN2_SPDIFTXD 0x010
152#define WM8580_PWRDN2_SPDIFRXD 0x020
153
154#define WM8580_DAC_CONTROL5_MUTEALL 0x10
155
156/*
157 * wm8580 register cache
158 * We can't read the WM8580 register space when we
159 * are using 2 wire for device control, so we cache them instead.
160 */
161static const u16 wm8580_reg[] = {
162 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
163 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
164 0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
165 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
166 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
167 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
168 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
169 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
170 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
171 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
172 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
173 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
174 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
175 0x0000, 0x0000 /*R53*/
176};
177
6f7cb44b
MB		 178struct pll_state {
179 unsigned int in;
180 unsigned int out;
181};
182
a583cd53
MB		 183#define WM8580_NUM_SUPPLIES 3
184static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
185 "AVDD",
186 "DVDD",
187 "PVDD",
188};
189
6f7cb44b
MB		 190/* codec private data */
191struct wm8580_priv {
f0fba2ad 192 enum snd_soc_control_type control_type;
a583cd53 193 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
6f7cb44b
MB		 194 u16 reg_cache[WM8580_MAX_REGISTER + 1];
195 struct pll_state a;
196 struct pll_state b;
c5607d8e 197 int sysclk[2];
6f7cb44b
MB		 198};
199
e88ba015
MB		 200static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
201
202static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
203 struct snd_ctl_elem_value *ucontrol)
204{
ccb077fd
MB		 205 struct soc_mixer_control *mc =
206 (struct soc_mixer_control *)kcontrol->private_value;
e88ba015 207 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f6f1eb10 208 u16 *reg_cache = codec->reg_cache;
ccb077fd
MB		 209 unsigned int reg = mc->reg;
210 unsigned int reg2 = mc->rreg;
e88ba015 211 int ret;
e88ba015
MB		 212
213 /* Clear the register cache so we write without VU set */
f6f1eb10
MB		 214 reg_cache[reg] = 0;
215 reg_cache[reg2] = 0;
e88ba015
MB		 216
217 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
218 if (ret < 0)
219 return ret;
220
221 /* Now write again with the volume update bit set */
f6f1eb10
MB		 222 snd_soc_update_bits(codec, reg, 0x100, 0x100);
223 snd_soc_update_bits(codec, reg2, 0x100, 0x100);
e88ba015
MB		 224
225 return 0;
226}
227
ccb077fd
MB		 228#define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
229 xinvert, tlv_array) \
e88ba015
MB		 230{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
231 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
232 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
233 .tlv.p = (tlv_array), \
234 .info = snd_soc_info_volsw_2r, \
235 .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
ccb077fd
MB		 236 .private_value = (unsigned long)&(struct soc_mixer_control) \
237 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
238 .max = xmax, .invert = xinvert} }
e88ba015
MB		 239
240static const struct snd_kcontrol_new wm8580_snd_controls[] = {
241SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
242 WM8580_DIGITAL_ATTENUATION_DACL1,
243 WM8580_DIGITAL_ATTENUATION_DACR1,
244 0, 0xff, 0, dac_tlv),
245SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
246 WM8580_DIGITAL_ATTENUATION_DACL2,
247 WM8580_DIGITAL_ATTENUATION_DACR2,
248 0, 0xff, 0, dac_tlv),
249SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
250 WM8580_DIGITAL_ATTENUATION_DACL3,
251 WM8580_DIGITAL_ATTENUATION_DACR3,
252 0, 0xff, 0, dac_tlv),
253
254SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
255SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
256SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
257
258SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
259SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
260SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
261
262SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
4f0ed9a5
MB		 263SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
264SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
265SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
e88ba015 266
dacfe9f2 267SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
6f341d14 268SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
e88ba015
MB		 269};
270
e88ba015
MB		 271static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
272SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
273SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
274SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
275
276SND_SOC_DAPM_OUTPUT("VOUT1L"),
277SND_SOC_DAPM_OUTPUT("VOUT1R"),
278SND_SOC_DAPM_OUTPUT("VOUT2L"),
279SND_SOC_DAPM_OUTPUT("VOUT2R"),
280SND_SOC_DAPM_OUTPUT("VOUT3L"),
281SND_SOC_DAPM_OUTPUT("VOUT3R"),
282
283SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
284
285SND_SOC_DAPM_INPUT("AINL"),
286SND_SOC_DAPM_INPUT("AINR"),
287};
288
289static const struct snd_soc_dapm_route audio_map[] = {
290 { "VOUT1L", NULL, "DAC1" },
291 { "VOUT1R", NULL, "DAC1" },
292
293 { "VOUT2L", NULL, "DAC2" },
294 { "VOUT2R", NULL, "DAC2" },
295
296 { "VOUT3L", NULL, "DAC3" },
297 { "VOUT3R", NULL, "DAC3" },
298
299 { "ADC", NULL, "AINL" },
300 { "ADC", NULL, "AINR" },
301};
302
303static int wm8580_add_widgets(struct snd_soc_codec *codec)
304{
305 snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
306 ARRAY_SIZE(wm8580_dapm_widgets));
307
308 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
309
e88ba015
MB		 310 return 0;
311}
312
313/* PLL divisors */
314struct _pll_div {
315 u32 prescale:1;
316 u32 postscale:1;
317 u32 freqmode:2;
318 u32 n:4;
319 u32 k:24;
320};
321
322/* The size in bits of the pll divide */
323#define FIXED_PLL_SIZE (1 << 22)
324
325/* PLL rate to output rate divisions */
326static struct {
327 unsigned int div;
328 unsigned int freqmode;
329 unsigned int postscale;
330} post_table[] = {
331 { 2, 0, 0 },
332 { 4, 0, 1 },
333 { 4, 1, 0 },
334 { 8, 1, 1 },
335 { 8, 2, 0 },
336 { 16, 2, 1 },
337 { 12, 3, 0 },
338 { 24, 3, 1 }
339};
340
341static int pll_factors(struct _pll_div *pll_div, unsigned int target,
342 unsigned int source)
343{
344 u64 Kpart;
345 unsigned int K, Ndiv, Nmod;
346 int i;
347
449bd54d 348 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
e88ba015
MB		 349
350 /* Scale the output frequency up; the PLL should run in the
351 * region of 90-100MHz.
352 */
353 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
354 if (target * post_table[i].div >= 90000000 &&
355 target * post_table[i].div <= 100000000) {
356 pll_div->freqmode = post_table[i].freqmode;
357 pll_div->postscale = post_table[i].postscale;
358 target *= post_table[i].div;
359 break;
360 }
361 }
362
363 if (i == ARRAY_SIZE(post_table)) {
364 printk(KERN_ERR "wm8580: Unable to scale output frequency "
365 "%u\n", target);
366 return -EINVAL;
367 }
368
369 Ndiv = target / source;
370
371 if (Ndiv < 5) {
372 source /= 2;
373 pll_div->prescale = 1;
374 Ndiv = target / source;
375 } else
376 pll_div->prescale = 0;
377
378 if ((Ndiv < 5) || (Ndiv > 13)) {
379 printk(KERN_ERR
449bd54d 380 "WM8580 N=%u outside supported range\n", Ndiv);
e88ba015
MB		 381 return -EINVAL;
382 }
383
384 pll_div->n = Ndiv;
385 Nmod = target % source;
386 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
387
388 do_div(Kpart, source);
389
390 K = Kpart & 0xFFFFFFFF;
391
392 pll_div->k = K;
393
394 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
395 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
396 pll_div->postscale);
397
398 return 0;
399}
400
85488037
MB		 401static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
402 int source, unsigned int freq_in, unsigned int freq_out)
e88ba015
MB		 403{
404 int offset;
405 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 406 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
e88ba015
MB		 407 struct pll_state *state;
408 struct _pll_div pll_div;
409 unsigned int reg;
410 unsigned int pwr_mask;
411 int ret;
412
413 /* GCC isn't able to work out the ifs below for initialising/using
414 * pll_div so suppress warnings.
415 */
416 memset(&pll_div, 0, sizeof(pll_div));
417
418 switch (pll_id) {
419 case WM8580_PLLA:
420 state = &wm8580->a;
421 offset = 0;
422 pwr_mask = WM8580_PWRDN2_PLLAPD;
423 break;
424 case WM8580_PLLB:
425 state = &wm8580->b;
426 offset = 4;
427 pwr_mask = WM8580_PWRDN2_PLLBPD;
428 break;
429 default:
430 return -ENODEV;
431 }
432
433 if (freq_in && freq_out) {
434 ret = pll_factors(&pll_div, freq_out, freq_in);
435 if (ret != 0)
436 return ret;
437 }
438
439 state->in = freq_in;
440 state->out = freq_out;
441
442 /* Always disable the PLL - it is not safe to leave it running
443 * while reprogramming it.
444 */
f6f1eb10
MB		 445 reg = snd_soc_read(codec, WM8580_PWRDN2);
446 snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
e88ba015
MB		 447
448 if (!freq_in || !freq_out)
449 return 0;
450
f6f1eb10 451 snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
5c0d38c9 452 snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
f6f1eb10 453 snd_soc_write(codec, WM8580_PLLA3 + offset,
e88ba015
MB		 454 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
455
f6f1eb10 456 reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
5c0d38c9 457 reg &= ~0x1b;
e88ba015 458 reg |= pll_div.prescale | pll_div.postscale << 1 |
ce88168f 459 pll_div.freqmode << 3;
e88ba015 460
f6f1eb10 461 snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
e88ba015
MB		 462
463 /* All done, turn it on */
f6f1eb10
MB		 464 reg = snd_soc_read(codec, WM8580_PWRDN2);
465 snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
e88ba015
MB		 466
467 return 0;
468}
469
c5607d8e
MB		 470static const int wm8580_sysclk_ratios[] = {
471 128, 192, 256, 384, 512, 768, 1152,
472};
473
e88ba015
MB		 474/*
475 * Set PCM DAI bit size and sample rate.
476 */
477static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 478 struct snd_pcm_hw_params *params,
479 struct snd_soc_dai *dai)
e88ba015
MB		 480{
481 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 482 struct snd_soc_codec *codec = rtd->codec;
c5607d8e
MB		 483 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
484 u16 paifa = 0;
e231cab0 485 u16 paifb = 0;
6bfb6aa9 486 int i, ratio, osr;
e88ba015 487
e88ba015
MB		 488 /* bit size */
489 switch (params_format(params)) {
490 case SNDRV_PCM_FORMAT_S16_LE:
ba2772ed 491 paifa |= 0x8;
e88ba015
MB		 492 break;
493 case SNDRV_PCM_FORMAT_S20_3LE:
ba2772ed 494 paifa |= 0x10;
e88ba015
MB		 495 paifb |= WM8580_AIF_LENGTH_20;
496 break;
497 case SNDRV_PCM_FORMAT_S24_LE:
ba2772ed 498 paifa |= 0x10;
e88ba015
MB		 499 paifb |= WM8580_AIF_LENGTH_24;
500 break;
501 case SNDRV_PCM_FORMAT_S32_LE:
ba2772ed 502 paifa |= 0x10;
e88ba015
MB		 503 paifb |= WM8580_AIF_LENGTH_24;
504 break;
505 default:
506 return -EINVAL;
507 }
508
c5607d8e
MB		 509 /* Look up the SYSCLK ratio; accept only exact matches */
510 ratio = wm8580->sysclk[dai->id] / params_rate(params);
511 for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
512 if (ratio == wm8580_sysclk_ratios[i])
513 break;
514 if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
515 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
516 wm8580->sysclk[dai->id], params_rate(params));
517 return -EINVAL;
518 }
519 paifa |= i;
520 dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
521 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
522
6bfb6aa9
MB		 523 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
524 switch (ratio) {
525 case 128:
526 case 192:
527 osr = WM8580_DACOSR;
528 dev_dbg(codec->dev, "Selecting 64x OSR\n");
529 break;
530 default:
531 osr = 0;
532 dev_dbg(codec->dev, "Selecting 128x OSR\n");
533 break;
534 }
535
536 snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr);
537 }
538
c5607d8e 539 snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
ba2772ed
MB		 540 WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
541 paifa);
e231cab0
MB		 542 snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
543 WM8580_AIF_LENGTH_MASK, paifb);
e88ba015
MB		 544 return 0;
545}
546
547static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
548 unsigned int fmt)
549{
550 struct snd_soc_codec *codec = codec_dai->codec;
c5607d8e 551 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
e88ba015
MB		 552 unsigned int aifa;
553 unsigned int aifb;
554 int can_invert_lrclk;
c5607d8e 555 int sysclk;
e88ba015 556
f0fba2ad
LG		 557 aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
558 aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
e88ba015
MB		 559
560 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
561
562 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
563 case SND_SOC_DAIFMT_CBS_CFS:
564 aifa &= ~WM8580_AIF_MS;
565 break;
566 case SND_SOC_DAIFMT_CBM_CFM:
567 aifa |= WM8580_AIF_MS;
568 break;
569 default:
570 return -EINVAL;
571 }
572
573 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
574 case SND_SOC_DAIFMT_I2S:
575 can_invert_lrclk = 1;
576 aifb |= WM8580_AIF_FMT_I2S;
577 break;
578 case SND_SOC_DAIFMT_RIGHT_J:
579 can_invert_lrclk = 1;
580 aifb |= WM8580_AIF_FMT_RIGHTJ;
581 break;
582 case SND_SOC_DAIFMT_LEFT_J:
583 can_invert_lrclk = 1;
584 aifb |= WM8580_AIF_FMT_LEFTJ;
585 break;
586 case SND_SOC_DAIFMT_DSP_A:
587 can_invert_lrclk = 0;
588 aifb |= WM8580_AIF_FMT_DSP;
589 break;
590 case SND_SOC_DAIFMT_DSP_B:
591 can_invert_lrclk = 0;
592 aifb |= WM8580_AIF_FMT_DSP;
593 aifb |= WM8580_AIF_LRP;
594 break;
595 default:
596 return -EINVAL;
597 }
598
599 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
600 case SND_SOC_DAIFMT_NB_NF:
601 break;
602
603 case SND_SOC_DAIFMT_IB_IF:
604 if (!can_invert_lrclk)
605 return -EINVAL;
606 aifb |= WM8580_AIF_BCP;
607 aifb |= WM8580_AIF_LRP;
608 break;
609
610 case SND_SOC_DAIFMT_IB_NF:
611 aifb |= WM8580_AIF_BCP;
612 break;
613
614 case SND_SOC_DAIFMT_NB_IF:
615 if (!can_invert_lrclk)
616 return -EINVAL;
617 aifb |= WM8580_AIF_LRP;
618 break;
619
620 default:
621 return -EINVAL;
622 }
623
c5607d8e
MB		 624 sysclk = wm8580->sysclk[codec_dai->driver->id];
625
f0fba2ad
LG		 626 snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
627 snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
e88ba015
MB		 628
629 return 0;
630}
631
632static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
633 int div_id, int div)
634{
635 struct snd_soc_codec *codec = codec_dai->codec;
636 unsigned int reg;
637
638 switch (div_id) {
639 case WM8580_MCLK:
f6f1eb10 640 reg = snd_soc_read(codec, WM8580_PLLB4);
e88ba015
MB		 641 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
642
643 switch (div) {
644 case WM8580_CLKSRC_MCLK:
645 /* Input */
646 break;
647
648 case WM8580_CLKSRC_PLLA:
649 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
650 break;
651 case WM8580_CLKSRC_PLLB:
652 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
653 break;
654
655 case WM8580_CLKSRC_OSC:
656 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
657 break;
658
659 default:
660 return -EINVAL;
661 }
f6f1eb10 662 snd_soc_write(codec, WM8580_PLLB4, reg);
e88ba015
MB		 663 break;
664
e88ba015 665 case WM8580_CLKOUTSRC:
f6f1eb10 666 reg = snd_soc_read(codec, WM8580_PLLB4);
e88ba015
MB		 667 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
668
669 switch (div) {
670 case WM8580_CLKSRC_NONE:
671 break;
672
673 case WM8580_CLKSRC_PLLA:
674 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
675 break;
676
677 case WM8580_CLKSRC_PLLB:
678 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
679 break;
680
681 case WM8580_CLKSRC_OSC:
682 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
683 break;
684
685 default:
686 return -EINVAL;
687 }
f6f1eb10 688 snd_soc_write(codec, WM8580_PLLB4, reg);
e88ba015
MB		 689 break;
690
691 default:
692 return -EINVAL;
693 }
694
695 return 0;
696}
697
c5607d8e
MB		 698static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
699 unsigned int freq, int dir)
700{
701 struct snd_soc_codec *codec = dai->codec;
702 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
703 int sel, sel_mask, sel_shift;
704
705 switch (dai->driver->id) {
c25edef8 706 case WM8580_DAI_PAIFRX:
c5607d8e
MB		 707 sel_mask = 0x3;
708 sel_shift = 0;
709 break;
710
c25edef8 711 case WM8580_DAI_PAIFTX:
c5607d8e
MB		 712 sel_mask = 0xc;
713 sel_shift = 2;
714 break;
715
716 default:
717 BUG_ON("Unknown DAI driver ID\n");
718 return -EINVAL;
719 }
720
721 switch (clk_id) {
722 case WM8580_CLKSRC_ADCMCLK:
723 if (dai->id != WM8580_DAI_PAIFTX)
724 return -EINVAL;
725 sel = 0 << sel_shift;
726 break;
727 case WM8580_CLKSRC_PLLA:
728 sel = 1 << sel_shift;
729 break;
730 case WM8580_CLKSRC_PLLB:
731 sel = 2 << sel_shift;
732 break;
733 case WM8580_CLKSRC_MCLK:
734 sel = 3 << sel_shift;
735 break;
736 default:
737 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
738 return -EINVAL;
739 }
740
741 /* We really should validate PLL settings but not yet */
742 wm8580->sysclk[dai->id] = freq;
743
f538281c 744 return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
c5607d8e
MB		 745}
746
e88ba015
MB		 747static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
748{
749 struct snd_soc_codec *codec = codec_dai->codec;
750 unsigned int reg;
751
f6f1eb10 752 reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
e88ba015
MB		 753
754 if (mute)
755 reg |= WM8580_DAC_CONTROL5_MUTEALL;
756 else
757 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
758
f6f1eb10 759 snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
e88ba015
MB		 760
761 return 0;
762}
763
764static int wm8580_set_bias_level(struct snd_soc_codec *codec,
765 enum snd_soc_bias_level level)
766{
767 u16 reg;
768 switch (level) {
769 case SND_SOC_BIAS_ON:
770 case SND_SOC_BIAS_PREPARE:
6f7cb44b
MB		 771 break;
772
e88ba015 773 case SND_SOC_BIAS_STANDBY:
6f7cb44b
MB		 774 if (codec->bias_level == SND_SOC_BIAS_OFF) {
775 /* Power up and get individual control of the DACs */
f6f1eb10 776 reg = snd_soc_read(codec, WM8580_PWRDN1);
6f7cb44b 777 reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
f6f1eb10 778 snd_soc_write(codec, WM8580_PWRDN1, reg);
6f7cb44b
MB		 779
780 /* Make VMID high impedence */
f6f1eb10 781 reg = snd_soc_read(codec, WM8580_ADC_CONTROL1);
6f7cb44b 782 reg &= ~0x100;
f6f1eb10 783 snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
6f7cb44b 784 }
e88ba015 785 break;
6f7cb44b 786
e88ba015 787 case SND_SOC_BIAS_OFF:
f6f1eb10
MB		 788 reg = snd_soc_read(codec, WM8580_PWRDN1);
789 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
e88ba015
MB		 790 break;
791 }
792 codec->bias_level = level;
793 return 0;
794}
795
796#define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
797 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
798
6335d055 799static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
c5607d8e 800 .set_sysclk = wm8580_set_sysclk,
6335d055
EM		 801 .hw_params = wm8580_paif_hw_params,
802 .set_fmt = wm8580_set_paif_dai_fmt,
803 .set_clkdiv = wm8580_set_dai_clkdiv,
804 .set_pll = wm8580_set_dai_pll,
805 .digital_mute = wm8580_digital_mute,
806};
807
808static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
c5607d8e 809 .set_sysclk = wm8580_set_sysclk,
6335d055
EM		 810 .hw_params = wm8580_paif_hw_params,
811 .set_fmt = wm8580_set_paif_dai_fmt,
812 .set_clkdiv = wm8580_set_dai_clkdiv,
813 .set_pll = wm8580_set_dai_pll,
814};
815
f0fba2ad 816static struct snd_soc_dai_driver wm8580_dai[] = {
e88ba015 817 {
f0fba2ad
LG		 818 .name = "wm8580-hifi-playback",
819 .id = WM8580_DAI_PAIFRX,
e88ba015
MB		 820 .playback = {
821 .stream_name = "Playback",
822 .channels_min = 1,
823 .channels_max = 6,
824 .rates = SNDRV_PCM_RATE_8000_192000,
825 .formats = WM8580_FORMATS,
826 },
6335d055 827 .ops = &wm8580_dai_ops_playback,
e88ba015
MB		 828 },
829 {
f0fba2ad
LG		 830 .name = "wm8580-hifi-capture",
831 .id = WM8580_DAI_PAIFTX,
e88ba015
MB		 832 .capture = {
833 .stream_name = "Capture",
834 .channels_min = 2,
835 .channels_max = 2,
836 .rates = SNDRV_PCM_RATE_8000_192000,
837 .formats = WM8580_FORMATS,
838 },
6335d055 839 .ops = &wm8580_dai_ops_capture,
e88ba015
MB		 840 },
841};
e88ba015 842
f0fba2ad 843static int wm8580_probe(struct snd_soc_codec *codec)
e88ba015 844{
f0fba2ad
LG		 845 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
846 int ret = 0,i;
6f7cb44b 847
f0fba2ad 848 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
f6f1eb10
MB		 849 if (ret < 0) {
850 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 851 return ret;
f6f1eb10
MB		 852 }
853
a583cd53
MB		 854 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
855 wm8580->supplies[i].supply = wm8580_supply_names[i];
856
857 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
858 wm8580->supplies);
859 if (ret != 0) {
860 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
f0fba2ad 861 return ret;
a583cd53
MB		 862 }
863
864 ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
865 wm8580->supplies);
866 if (ret != 0) {
867 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
868 goto err_regulator_get;
869 }
870
6f7cb44b 871 /* Get the codec into a known state */
f6f1eb10 872 ret = snd_soc_write(codec, WM8580_RESET, 0);
6f7cb44b
MB		 873 if (ret != 0) {
874 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
a583cd53 875 goto err_regulator_enable;
6f7cb44b
MB		 876 }
877
6f7cb44b 878 wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
e88ba015 879
f0fba2ad
LG		 880 snd_soc_add_controls(codec, wm8580_snd_controls,
881 ARRAY_SIZE(wm8580_snd_controls));
882 wm8580_add_widgets(codec);
6f7cb44b
MB		 883
884 return 0;
885
a583cd53
MB		 886err_regulator_enable:
887 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
888err_regulator_get:
889 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
6f7cb44b
MB		 890 return ret;
891}
892
f0fba2ad
LG		 893/* power down chip */
894static int wm8580_remove(struct snd_soc_codec *codec)
6f7cb44b 895{
f0fba2ad
LG		 896 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
897
898 wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
899
a583cd53
MB		 900 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
901 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
f0fba2ad
LG		 902
903 return 0;
6f7cb44b
MB		 904}
905
f0fba2ad
LG		 906static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
907 .probe = wm8580_probe,
908 .remove = wm8580_remove,
909 .set_bias_level = wm8580_set_bias_level,
e5eec34c 910 .reg_cache_size = ARRAY_SIZE(wm8580_reg),
f0fba2ad
LG		 911 .reg_word_size = sizeof(u16),
912 .reg_cache_default = &wm8580_reg,
913};
914
6f7cb44b 915#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
17be5522
JD		 916static int wm8580_i2c_probe(struct i2c_client *i2c,
917 const struct i2c_device_id *id)
e88ba015 918{
6f7cb44b 919 struct wm8580_priv *wm8580;
f0fba2ad 920 int ret;
6f7cb44b
MB		 921
922 wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
923 if (wm8580 == NULL)
924 return -ENOMEM;
925
6f7cb44b 926 i2c_set_clientdata(i2c, wm8580);
f0fba2ad 927 wm8580->control_type = SND_SOC_I2C;
6f7cb44b 928
f0fba2ad
LG		 929 ret = snd_soc_register_codec(&i2c->dev,
930 &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
931 if (ret < 0)
932 kfree(wm8580);
933 return ret;
e88ba015
MB		 934}
935
17be5522 936static int wm8580_i2c_remove(struct i2c_client *client)
e88ba015 937{
f0fba2ad
LG		 938 snd_soc_unregister_codec(&client->dev);
939 kfree(i2c_get_clientdata(client));
e88ba015
MB		 940 return 0;
941}
942
17be5522
JD		 943static const struct i2c_device_id wm8580_i2c_id[] = {
944 { "wm8580", 0 },
945 { }
946};
947MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
e88ba015 948
e88ba015
MB		 949static struct i2c_driver wm8580_i2c_driver = {
950 .driver = {
f0fba2ad 951 .name = "wm8580-codec",
e88ba015
MB		 952 .owner = THIS_MODULE,
953 },
17be5522
JD		 954 .probe = wm8580_i2c_probe,
955 .remove = wm8580_i2c_remove,
956 .id_table = wm8580_i2c_id,
e88ba015 957};
6f7cb44b 958#endif
e88ba015 959
6f7cb44b 960static int __init wm8580_modinit(void)
17be5522 961{
f0fba2ad 962 int ret = 0;
17be5522 963
6f7cb44b 964#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
17be5522
JD		 965 ret = i2c_add_driver(&wm8580_i2c_driver);
966 if (ret != 0) {
6f7cb44b 967 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
e88ba015 968 }
e88ba015 969#endif
e88ba015 970
f0fba2ad 971 return ret;
e88ba015 972}
64089b84
MB		 973module_init(wm8580_modinit);
974
975static void __exit wm8580_exit(void)
976{
6f7cb44b
MB		 977#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
978 i2c_del_driver(&wm8580_i2c_driver);
979#endif
64089b84
MB		 980}
981module_exit(wm8580_exit);
982
e88ba015
MB		 983MODULE_DESCRIPTION("ASoC WM8580 driver");
984MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
985MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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