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e88ba015 MB |
1 | /* |
2 | * wm8580.c -- WM8580 ALSA Soc Audio driver | |
3 | * | |
b689d9f9 | 4 | * Copyright 2008-12 Wolfson Microelectronics PLC. |
e88ba015 MB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; either version 2 of the License, or (at your | |
9 | * option) any later version. | |
10 | * | |
11 | * Notes: | |
12 | * The WM8580 is a multichannel codec with S/PDIF support, featuring six | |
13 | * DAC channels and two ADC channels. | |
14 | * | |
15 | * Currently only the primary audio interface is supported - S/PDIF and | |
16 | * the secondary audio interfaces are not. | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/moduleparam.h> | |
e88ba015 MB |
21 | #include <linux/kernel.h> |
22 | #include <linux/init.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/pm.h> | |
25 | #include <linux/i2c.h> | |
b689d9f9 | 26 | #include <linux/regmap.h> |
a583cd53 | 27 | #include <linux/regulator/consumer.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
733eef3e | 29 | #include <linux/of_device.h> |
a583cd53 | 30 | |
e88ba015 MB |
31 | #include <sound/core.h> |
32 | #include <sound/pcm.h> | |
33 | #include <sound/pcm_params.h> | |
34 | #include <sound/soc.h> | |
e88ba015 MB |
35 | #include <sound/tlv.h> |
36 | #include <sound/initval.h> | |
37 | #include <asm/div64.h> | |
38 | ||
39 | #include "wm8580.h" | |
40 | ||
e88ba015 MB |
41 | /* WM8580 register space */ |
42 | #define WM8580_PLLA1 0x00 | |
43 | #define WM8580_PLLA2 0x01 | |
44 | #define WM8580_PLLA3 0x02 | |
45 | #define WM8580_PLLA4 0x03 | |
46 | #define WM8580_PLLB1 0x04 | |
47 | #define WM8580_PLLB2 0x05 | |
48 | #define WM8580_PLLB3 0x06 | |
49 | #define WM8580_PLLB4 0x07 | |
50 | #define WM8580_CLKSEL 0x08 | |
51 | #define WM8580_PAIF1 0x09 | |
52 | #define WM8580_PAIF2 0x0A | |
53 | #define WM8580_SAIF1 0x0B | |
54 | #define WM8580_PAIF3 0x0C | |
55 | #define WM8580_PAIF4 0x0D | |
56 | #define WM8580_SAIF2 0x0E | |
57 | #define WM8580_DAC_CONTROL1 0x0F | |
58 | #define WM8580_DAC_CONTROL2 0x10 | |
59 | #define WM8580_DAC_CONTROL3 0x11 | |
60 | #define WM8580_DAC_CONTROL4 0x12 | |
61 | #define WM8580_DAC_CONTROL5 0x13 | |
62 | #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14 | |
63 | #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15 | |
64 | #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16 | |
65 | #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17 | |
66 | #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18 | |
67 | #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19 | |
68 | #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C | |
69 | #define WM8580_ADC_CONTROL1 0x1D | |
70 | #define WM8580_SPDTXCHAN0 0x1E | |
71 | #define WM8580_SPDTXCHAN1 0x1F | |
72 | #define WM8580_SPDTXCHAN2 0x20 | |
73 | #define WM8580_SPDTXCHAN3 0x21 | |
74 | #define WM8580_SPDTXCHAN4 0x22 | |
75 | #define WM8580_SPDTXCHAN5 0x23 | |
76 | #define WM8580_SPDMODE 0x24 | |
77 | #define WM8580_INTMASK 0x25 | |
78 | #define WM8580_GPO1 0x26 | |
79 | #define WM8580_GPO2 0x27 | |
80 | #define WM8580_GPO3 0x28 | |
81 | #define WM8580_GPO4 0x29 | |
82 | #define WM8580_GPO5 0x2A | |
83 | #define WM8580_INTSTAT 0x2B | |
84 | #define WM8580_SPDRXCHAN1 0x2C | |
85 | #define WM8580_SPDRXCHAN2 0x2D | |
86 | #define WM8580_SPDRXCHAN3 0x2E | |
87 | #define WM8580_SPDRXCHAN4 0x2F | |
88 | #define WM8580_SPDRXCHAN5 0x30 | |
89 | #define WM8580_SPDSTAT 0x31 | |
90 | #define WM8580_PWRDN1 0x32 | |
91 | #define WM8580_PWRDN2 0x33 | |
92 | #define WM8580_READBACK 0x34 | |
93 | #define WM8580_RESET 0x35 | |
94 | ||
6f7cb44b MB |
95 | #define WM8580_MAX_REGISTER 0x35 |
96 | ||
6bfb6aa9 MB |
97 | #define WM8580_DACOSR 0x40 |
98 | ||
e88ba015 MB |
99 | /* PLLB4 (register 7h) */ |
100 | #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60 | |
101 | #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20 | |
102 | #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40 | |
103 | #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60 | |
104 | ||
105 | #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180 | |
106 | #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080 | |
107 | #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100 | |
108 | #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180 | |
109 | ||
110 | /* CLKSEL (register 8h) */ | |
111 | #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03 | |
112 | #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01 | |
113 | #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02 | |
114 | ||
115 | /* AIF control 1 (registers 9h-bh) */ | |
116 | #define WM8580_AIF_RATE_MASK 0x7 | |
e88ba015 | 117 | #define WM8580_AIF_BCLKSEL_MASK 0x18 |
e88ba015 MB |
118 | |
119 | #define WM8580_AIF_MS 0x20 | |
120 | ||
121 | #define WM8580_AIF_CLKSRC_MASK 0xc0 | |
122 | #define WM8580_AIF_CLKSRC_PLLA 0x40 | |
123 | #define WM8580_AIF_CLKSRC_PLLB 0x40 | |
124 | #define WM8580_AIF_CLKSRC_MCLK 0xc0 | |
125 | ||
126 | /* AIF control 2 (registers ch-eh) */ | |
127 | #define WM8580_AIF_FMT_MASK 0x03 | |
128 | #define WM8580_AIF_FMT_RIGHTJ 0x00 | |
129 | #define WM8580_AIF_FMT_LEFTJ 0x01 | |
130 | #define WM8580_AIF_FMT_I2S 0x02 | |
131 | #define WM8580_AIF_FMT_DSP 0x03 | |
132 | ||
133 | #define WM8580_AIF_LENGTH_MASK 0x0c | |
134 | #define WM8580_AIF_LENGTH_16 0x00 | |
135 | #define WM8580_AIF_LENGTH_20 0x04 | |
136 | #define WM8580_AIF_LENGTH_24 0x08 | |
137 | #define WM8580_AIF_LENGTH_32 0x0c | |
138 | ||
139 | #define WM8580_AIF_LRP 0x10 | |
140 | #define WM8580_AIF_BCP 0x20 | |
141 | ||
142 | /* Powerdown Register 1 (register 32h) */ | |
143 | #define WM8580_PWRDN1_PWDN 0x001 | |
144 | #define WM8580_PWRDN1_ALLDACPD 0x040 | |
145 | ||
146 | /* Powerdown Register 2 (register 33h) */ | |
147 | #define WM8580_PWRDN2_OSSCPD 0x001 | |
148 | #define WM8580_PWRDN2_PLLAPD 0x002 | |
149 | #define WM8580_PWRDN2_PLLBPD 0x004 | |
150 | #define WM8580_PWRDN2_SPDIFPD 0x008 | |
151 | #define WM8580_PWRDN2_SPDIFTXD 0x010 | |
152 | #define WM8580_PWRDN2_SPDIFRXD 0x020 | |
153 | ||
154 | #define WM8580_DAC_CONTROL5_MUTEALL 0x10 | |
155 | ||
156 | /* | |
157 | * wm8580 register cache | |
158 | * We can't read the WM8580 register space when we | |
159 | * are using 2 wire for device control, so we cache them instead. | |
160 | */ | |
b689d9f9 MB |
161 | static const struct reg_default wm8580_reg_defaults[] = { |
162 | { 0, 0x0121 }, | |
163 | { 1, 0x017e }, | |
164 | { 2, 0x007d }, | |
165 | { 3, 0x0014 }, | |
166 | { 4, 0x0121 }, | |
167 | { 5, 0x017e }, | |
168 | { 6, 0x007d }, | |
169 | { 7, 0x0194 }, | |
170 | { 8, 0x0010 }, | |
171 | { 9, 0x0002 }, | |
172 | { 10, 0x0002 }, | |
173 | { 11, 0x00c2 }, | |
174 | { 12, 0x0182 }, | |
175 | { 13, 0x0082 }, | |
176 | { 14, 0x000a }, | |
177 | { 15, 0x0024 }, | |
178 | { 16, 0x0009 }, | |
179 | { 17, 0x0000 }, | |
180 | { 18, 0x00ff }, | |
181 | { 19, 0x0000 }, | |
182 | { 20, 0x00ff }, | |
183 | { 21, 0x00ff }, | |
184 | { 22, 0x00ff }, | |
185 | { 23, 0x00ff }, | |
186 | { 24, 0x00ff }, | |
187 | { 25, 0x00ff }, | |
188 | { 26, 0x00ff }, | |
189 | { 27, 0x00ff }, | |
190 | { 28, 0x01f0 }, | |
191 | { 29, 0x0040 }, | |
192 | { 30, 0x0000 }, | |
193 | { 31, 0x0000 }, | |
194 | { 32, 0x0000 }, | |
195 | { 33, 0x0000 }, | |
196 | { 34, 0x0031 }, | |
197 | { 35, 0x000b }, | |
198 | { 36, 0x0039 }, | |
199 | { 37, 0x0000 }, | |
200 | { 38, 0x0010 }, | |
201 | { 39, 0x0032 }, | |
202 | { 40, 0x0054 }, | |
203 | { 41, 0x0076 }, | |
204 | { 42, 0x0098 }, | |
205 | { 43, 0x0000 }, | |
206 | { 44, 0x0000 }, | |
207 | { 45, 0x0000 }, | |
208 | { 46, 0x0000 }, | |
209 | { 47, 0x0000 }, | |
210 | { 48, 0x0000 }, | |
211 | { 49, 0x0000 }, | |
212 | { 50, 0x005e }, | |
213 | { 51, 0x003e }, | |
214 | { 52, 0x0000 }, | |
e88ba015 MB |
215 | }; |
216 | ||
b689d9f9 MB |
217 | static bool wm8580_volatile(struct device *dev, unsigned int reg) |
218 | { | |
219 | switch (reg) { | |
220 | case WM8580_RESET: | |
221 | return true; | |
222 | default: | |
223 | return false; | |
224 | } | |
225 | } | |
226 | ||
6f7cb44b MB |
227 | struct pll_state { |
228 | unsigned int in; | |
229 | unsigned int out; | |
230 | }; | |
231 | ||
a583cd53 MB |
232 | #define WM8580_NUM_SUPPLIES 3 |
233 | static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = { | |
234 | "AVDD", | |
235 | "DVDD", | |
236 | "PVDD", | |
237 | }; | |
238 | ||
6f7cb44b MB |
239 | /* codec private data */ |
240 | struct wm8580_priv { | |
b689d9f9 | 241 | struct regmap *regmap; |
a583cd53 | 242 | struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES]; |
6f7cb44b MB |
243 | struct pll_state a; |
244 | struct pll_state b; | |
c5607d8e | 245 | int sysclk[2]; |
6f7cb44b MB |
246 | }; |
247 | ||
e88ba015 MB |
248 | static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1); |
249 | ||
250 | static int wm8580_out_vu(struct snd_kcontrol *kcontrol, | |
251 | struct snd_ctl_elem_value *ucontrol) | |
252 | { | |
ccb077fd MB |
253 | struct soc_mixer_control *mc = |
254 | (struct soc_mixer_control *)kcontrol->private_value; | |
e88ba015 | 255 | struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); |
b689d9f9 | 256 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
ccb077fd MB |
257 | unsigned int reg = mc->reg; |
258 | unsigned int reg2 = mc->rreg; | |
e88ba015 | 259 | int ret; |
e88ba015 | 260 | |
b689d9f9 MB |
261 | /* Clear the register cache VU so we write without VU set */ |
262 | regcache_cache_only(wm8580->regmap, true); | |
263 | regmap_update_bits(wm8580->regmap, reg, 0x100, 0x000); | |
264 | regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000); | |
265 | regcache_cache_only(wm8580->regmap, false); | |
e88ba015 | 266 | |
c4671a95 | 267 | ret = snd_soc_put_volsw(kcontrol, ucontrol); |
e88ba015 MB |
268 | if (ret < 0) |
269 | return ret; | |
270 | ||
271 | /* Now write again with the volume update bit set */ | |
f6f1eb10 MB |
272 | snd_soc_update_bits(codec, reg, 0x100, 0x100); |
273 | snd_soc_update_bits(codec, reg2, 0x100, 0x100); | |
e88ba015 MB |
274 | |
275 | return 0; | |
276 | } | |
277 | ||
e88ba015 | 278 | static const struct snd_kcontrol_new wm8580_snd_controls[] = { |
0f9887d1 PU |
279 | SOC_DOUBLE_R_EXT_TLV("DAC1 Playback Volume", |
280 | WM8580_DIGITAL_ATTENUATION_DACL1, | |
281 | WM8580_DIGITAL_ATTENUATION_DACR1, | |
c4671a95 | 282 | 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv), |
0f9887d1 PU |
283 | SOC_DOUBLE_R_EXT_TLV("DAC2 Playback Volume", |
284 | WM8580_DIGITAL_ATTENUATION_DACL2, | |
285 | WM8580_DIGITAL_ATTENUATION_DACR2, | |
c4671a95 | 286 | 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv), |
0f9887d1 PU |
287 | SOC_DOUBLE_R_EXT_TLV("DAC3 Playback Volume", |
288 | WM8580_DIGITAL_ATTENUATION_DACL3, | |
289 | WM8580_DIGITAL_ATTENUATION_DACR3, | |
c4671a95 | 290 | 0, 0xff, 0, snd_soc_get_volsw, wm8580_out_vu, dac_tlv), |
e88ba015 MB |
291 | |
292 | SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0), | |
293 | SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0), | |
294 | SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0), | |
295 | ||
296 | SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0), | |
297 | SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0), | |
298 | SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0), | |
299 | ||
300 | SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0), | |
4f0ed9a5 MB |
301 | SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1), |
302 | SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1), | |
303 | SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1), | |
e88ba015 | 304 | |
dacfe9f2 | 305 | SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1), |
6f341d14 | 306 | SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0), |
e88ba015 MB |
307 | }; |
308 | ||
e88ba015 MB |
309 | static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = { |
310 | SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1), | |
311 | SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1), | |
312 | SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1), | |
313 | ||
314 | SND_SOC_DAPM_OUTPUT("VOUT1L"), | |
315 | SND_SOC_DAPM_OUTPUT("VOUT1R"), | |
316 | SND_SOC_DAPM_OUTPUT("VOUT2L"), | |
317 | SND_SOC_DAPM_OUTPUT("VOUT2R"), | |
318 | SND_SOC_DAPM_OUTPUT("VOUT3L"), | |
319 | SND_SOC_DAPM_OUTPUT("VOUT3R"), | |
320 | ||
321 | SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1), | |
322 | ||
323 | SND_SOC_DAPM_INPUT("AINL"), | |
324 | SND_SOC_DAPM_INPUT("AINR"), | |
325 | }; | |
326 | ||
f235c649 | 327 | static const struct snd_soc_dapm_route wm8580_dapm_routes[] = { |
e88ba015 MB |
328 | { "VOUT1L", NULL, "DAC1" }, |
329 | { "VOUT1R", NULL, "DAC1" }, | |
330 | ||
331 | { "VOUT2L", NULL, "DAC2" }, | |
332 | { "VOUT2R", NULL, "DAC2" }, | |
333 | ||
334 | { "VOUT3L", NULL, "DAC3" }, | |
335 | { "VOUT3R", NULL, "DAC3" }, | |
336 | ||
337 | { "ADC", NULL, "AINL" }, | |
338 | { "ADC", NULL, "AINR" }, | |
339 | }; | |
340 | ||
e88ba015 MB |
341 | /* PLL divisors */ |
342 | struct _pll_div { | |
343 | u32 prescale:1; | |
344 | u32 postscale:1; | |
345 | u32 freqmode:2; | |
346 | u32 n:4; | |
347 | u32 k:24; | |
348 | }; | |
349 | ||
350 | /* The size in bits of the pll divide */ | |
351 | #define FIXED_PLL_SIZE (1 << 22) | |
352 | ||
353 | /* PLL rate to output rate divisions */ | |
354 | static struct { | |
355 | unsigned int div; | |
356 | unsigned int freqmode; | |
357 | unsigned int postscale; | |
358 | } post_table[] = { | |
359 | { 2, 0, 0 }, | |
360 | { 4, 0, 1 }, | |
361 | { 4, 1, 0 }, | |
362 | { 8, 1, 1 }, | |
363 | { 8, 2, 0 }, | |
364 | { 16, 2, 1 }, | |
365 | { 12, 3, 0 }, | |
366 | { 24, 3, 1 } | |
367 | }; | |
368 | ||
369 | static int pll_factors(struct _pll_div *pll_div, unsigned int target, | |
370 | unsigned int source) | |
371 | { | |
372 | u64 Kpart; | |
373 | unsigned int K, Ndiv, Nmod; | |
374 | int i; | |
375 | ||
449bd54d | 376 | pr_debug("wm8580: PLL %uHz->%uHz\n", source, target); |
e88ba015 MB |
377 | |
378 | /* Scale the output frequency up; the PLL should run in the | |
379 | * region of 90-100MHz. | |
380 | */ | |
381 | for (i = 0; i < ARRAY_SIZE(post_table); i++) { | |
382 | if (target * post_table[i].div >= 90000000 && | |
383 | target * post_table[i].div <= 100000000) { | |
384 | pll_div->freqmode = post_table[i].freqmode; | |
385 | pll_div->postscale = post_table[i].postscale; | |
386 | target *= post_table[i].div; | |
387 | break; | |
388 | } | |
389 | } | |
390 | ||
391 | if (i == ARRAY_SIZE(post_table)) { | |
392 | printk(KERN_ERR "wm8580: Unable to scale output frequency " | |
393 | "%u\n", target); | |
394 | return -EINVAL; | |
395 | } | |
396 | ||
397 | Ndiv = target / source; | |
398 | ||
399 | if (Ndiv < 5) { | |
400 | source /= 2; | |
401 | pll_div->prescale = 1; | |
402 | Ndiv = target / source; | |
403 | } else | |
404 | pll_div->prescale = 0; | |
405 | ||
406 | if ((Ndiv < 5) || (Ndiv > 13)) { | |
407 | printk(KERN_ERR | |
449bd54d | 408 | "WM8580 N=%u outside supported range\n", Ndiv); |
e88ba015 MB |
409 | return -EINVAL; |
410 | } | |
411 | ||
412 | pll_div->n = Ndiv; | |
413 | Nmod = target % source; | |
414 | Kpart = FIXED_PLL_SIZE * (long long)Nmod; | |
415 | ||
416 | do_div(Kpart, source); | |
417 | ||
418 | K = Kpart & 0xFFFFFFFF; | |
419 | ||
420 | pll_div->k = K; | |
421 | ||
422 | pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n", | |
423 | pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode, | |
424 | pll_div->postscale); | |
425 | ||
426 | return 0; | |
427 | } | |
428 | ||
85488037 MB |
429 | static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
430 | int source, unsigned int freq_in, unsigned int freq_out) | |
e88ba015 MB |
431 | { |
432 | int offset; | |
433 | struct snd_soc_codec *codec = codec_dai->codec; | |
b2c812e2 | 434 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
e88ba015 MB |
435 | struct pll_state *state; |
436 | struct _pll_div pll_div; | |
437 | unsigned int reg; | |
438 | unsigned int pwr_mask; | |
439 | int ret; | |
440 | ||
441 | /* GCC isn't able to work out the ifs below for initialising/using | |
442 | * pll_div so suppress warnings. | |
443 | */ | |
444 | memset(&pll_div, 0, sizeof(pll_div)); | |
445 | ||
446 | switch (pll_id) { | |
447 | case WM8580_PLLA: | |
448 | state = &wm8580->a; | |
449 | offset = 0; | |
450 | pwr_mask = WM8580_PWRDN2_PLLAPD; | |
451 | break; | |
452 | case WM8580_PLLB: | |
453 | state = &wm8580->b; | |
454 | offset = 4; | |
455 | pwr_mask = WM8580_PWRDN2_PLLBPD; | |
456 | break; | |
457 | default: | |
458 | return -ENODEV; | |
459 | } | |
460 | ||
461 | if (freq_in && freq_out) { | |
462 | ret = pll_factors(&pll_div, freq_out, freq_in); | |
463 | if (ret != 0) | |
464 | return ret; | |
465 | } | |
466 | ||
467 | state->in = freq_in; | |
468 | state->out = freq_out; | |
469 | ||
470 | /* Always disable the PLL - it is not safe to leave it running | |
471 | * while reprogramming it. | |
472 | */ | |
a6785d7d | 473 | snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, pwr_mask); |
e88ba015 MB |
474 | |
475 | if (!freq_in || !freq_out) | |
476 | return 0; | |
477 | ||
f6f1eb10 | 478 | snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff); |
5c0d38c9 | 479 | snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff); |
f6f1eb10 | 480 | snd_soc_write(codec, WM8580_PLLA3 + offset, |
e88ba015 MB |
481 | (pll_div.k >> 18 & 0xf) | (pll_div.n << 4)); |
482 | ||
f6f1eb10 | 483 | reg = snd_soc_read(codec, WM8580_PLLA4 + offset); |
5c0d38c9 | 484 | reg &= ~0x1b; |
e88ba015 | 485 | reg |= pll_div.prescale | pll_div.postscale << 1 | |
ce88168f | 486 | pll_div.freqmode << 3; |
e88ba015 | 487 | |
f6f1eb10 | 488 | snd_soc_write(codec, WM8580_PLLA4 + offset, reg); |
e88ba015 MB |
489 | |
490 | /* All done, turn it on */ | |
a6785d7d | 491 | snd_soc_update_bits(codec, WM8580_PWRDN2, pwr_mask, 0); |
e88ba015 MB |
492 | |
493 | return 0; | |
494 | } | |
495 | ||
c5607d8e MB |
496 | static const int wm8580_sysclk_ratios[] = { |
497 | 128, 192, 256, 384, 512, 768, 1152, | |
498 | }; | |
499 | ||
e88ba015 MB |
500 | /* |
501 | * Set PCM DAI bit size and sample rate. | |
502 | */ | |
503 | static int wm8580_paif_hw_params(struct snd_pcm_substream *substream, | |
dee89c4d MB |
504 | struct snd_pcm_hw_params *params, |
505 | struct snd_soc_dai *dai) | |
e88ba015 MB |
506 | { |
507 | struct snd_soc_pcm_runtime *rtd = substream->private_data; | |
f0fba2ad | 508 | struct snd_soc_codec *codec = rtd->codec; |
c5607d8e MB |
509 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
510 | u16 paifa = 0; | |
e231cab0 | 511 | u16 paifb = 0; |
6bfb6aa9 | 512 | int i, ratio, osr; |
e88ba015 | 513 | |
e88ba015 MB |
514 | /* bit size */ |
515 | switch (params_format(params)) { | |
516 | case SNDRV_PCM_FORMAT_S16_LE: | |
ba2772ed | 517 | paifa |= 0x8; |
e88ba015 MB |
518 | break; |
519 | case SNDRV_PCM_FORMAT_S20_3LE: | |
6b464321 | 520 | paifa |= 0x0; |
e88ba015 MB |
521 | paifb |= WM8580_AIF_LENGTH_20; |
522 | break; | |
523 | case SNDRV_PCM_FORMAT_S24_LE: | |
6b464321 | 524 | paifa |= 0x0; |
e88ba015 MB |
525 | paifb |= WM8580_AIF_LENGTH_24; |
526 | break; | |
527 | case SNDRV_PCM_FORMAT_S32_LE: | |
6b464321 JB |
528 | paifa |= 0x0; |
529 | paifb |= WM8580_AIF_LENGTH_32; | |
e88ba015 MB |
530 | break; |
531 | default: | |
532 | return -EINVAL; | |
533 | } | |
534 | ||
c5607d8e | 535 | /* Look up the SYSCLK ratio; accept only exact matches */ |
06286938 | 536 | ratio = wm8580->sysclk[dai->driver->id] / params_rate(params); |
c5607d8e MB |
537 | for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++) |
538 | if (ratio == wm8580_sysclk_ratios[i]) | |
539 | break; | |
540 | if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) { | |
541 | dev_err(codec->dev, "Invalid clock ratio %d/%d\n", | |
06286938 | 542 | wm8580->sysclk[dai->driver->id], params_rate(params)); |
c5607d8e MB |
543 | return -EINVAL; |
544 | } | |
545 | paifa |= i; | |
546 | dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n", | |
547 | wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]); | |
548 | ||
6bfb6aa9 MB |
549 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
550 | switch (ratio) { | |
551 | case 128: | |
552 | case 192: | |
553 | osr = WM8580_DACOSR; | |
554 | dev_dbg(codec->dev, "Selecting 64x OSR\n"); | |
555 | break; | |
556 | default: | |
557 | osr = 0; | |
558 | dev_dbg(codec->dev, "Selecting 128x OSR\n"); | |
559 | break; | |
560 | } | |
561 | ||
562 | snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr); | |
563 | } | |
564 | ||
c5607d8e | 565 | snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id, |
ba2772ed MB |
566 | WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK, |
567 | paifa); | |
e231cab0 MB |
568 | snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id, |
569 | WM8580_AIF_LENGTH_MASK, paifb); | |
e88ba015 MB |
570 | return 0; |
571 | } | |
572 | ||
573 | static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai, | |
574 | unsigned int fmt) | |
575 | { | |
576 | struct snd_soc_codec *codec = codec_dai->codec; | |
577 | unsigned int aifa; | |
578 | unsigned int aifb; | |
579 | int can_invert_lrclk; | |
580 | ||
f0fba2ad LG |
581 | aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id); |
582 | aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id); | |
e88ba015 MB |
583 | |
584 | aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP); | |
585 | ||
586 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | |
587 | case SND_SOC_DAIFMT_CBS_CFS: | |
588 | aifa &= ~WM8580_AIF_MS; | |
589 | break; | |
590 | case SND_SOC_DAIFMT_CBM_CFM: | |
591 | aifa |= WM8580_AIF_MS; | |
592 | break; | |
593 | default: | |
594 | return -EINVAL; | |
595 | } | |
596 | ||
597 | switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { | |
598 | case SND_SOC_DAIFMT_I2S: | |
599 | can_invert_lrclk = 1; | |
600 | aifb |= WM8580_AIF_FMT_I2S; | |
601 | break; | |
602 | case SND_SOC_DAIFMT_RIGHT_J: | |
603 | can_invert_lrclk = 1; | |
604 | aifb |= WM8580_AIF_FMT_RIGHTJ; | |
605 | break; | |
606 | case SND_SOC_DAIFMT_LEFT_J: | |
607 | can_invert_lrclk = 1; | |
608 | aifb |= WM8580_AIF_FMT_LEFTJ; | |
609 | break; | |
610 | case SND_SOC_DAIFMT_DSP_A: | |
611 | can_invert_lrclk = 0; | |
612 | aifb |= WM8580_AIF_FMT_DSP; | |
613 | break; | |
614 | case SND_SOC_DAIFMT_DSP_B: | |
615 | can_invert_lrclk = 0; | |
616 | aifb |= WM8580_AIF_FMT_DSP; | |
617 | aifb |= WM8580_AIF_LRP; | |
618 | break; | |
619 | default: | |
620 | return -EINVAL; | |
621 | } | |
622 | ||
623 | switch (fmt & SND_SOC_DAIFMT_INV_MASK) { | |
624 | case SND_SOC_DAIFMT_NB_NF: | |
625 | break; | |
626 | ||
627 | case SND_SOC_DAIFMT_IB_IF: | |
628 | if (!can_invert_lrclk) | |
629 | return -EINVAL; | |
630 | aifb |= WM8580_AIF_BCP; | |
631 | aifb |= WM8580_AIF_LRP; | |
632 | break; | |
633 | ||
634 | case SND_SOC_DAIFMT_IB_NF: | |
635 | aifb |= WM8580_AIF_BCP; | |
636 | break; | |
637 | ||
638 | case SND_SOC_DAIFMT_NB_IF: | |
639 | if (!can_invert_lrclk) | |
640 | return -EINVAL; | |
641 | aifb |= WM8580_AIF_LRP; | |
642 | break; | |
643 | ||
644 | default: | |
645 | return -EINVAL; | |
646 | } | |
647 | ||
f0fba2ad LG |
648 | snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa); |
649 | snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb); | |
e88ba015 MB |
650 | |
651 | return 0; | |
652 | } | |
653 | ||
654 | static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai, | |
655 | int div_id, int div) | |
656 | { | |
657 | struct snd_soc_codec *codec = codec_dai->codec; | |
658 | unsigned int reg; | |
659 | ||
660 | switch (div_id) { | |
661 | case WM8580_MCLK: | |
f6f1eb10 | 662 | reg = snd_soc_read(codec, WM8580_PLLB4); |
e88ba015 MB |
663 | reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK; |
664 | ||
665 | switch (div) { | |
666 | case WM8580_CLKSRC_MCLK: | |
667 | /* Input */ | |
668 | break; | |
669 | ||
670 | case WM8580_CLKSRC_PLLA: | |
671 | reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA; | |
672 | break; | |
673 | case WM8580_CLKSRC_PLLB: | |
674 | reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB; | |
675 | break; | |
676 | ||
677 | case WM8580_CLKSRC_OSC: | |
678 | reg |= WM8580_PLLB4_MCLKOUTSRC_OSC; | |
679 | break; | |
680 | ||
681 | default: | |
682 | return -EINVAL; | |
683 | } | |
f6f1eb10 | 684 | snd_soc_write(codec, WM8580_PLLB4, reg); |
e88ba015 MB |
685 | break; |
686 | ||
e88ba015 | 687 | case WM8580_CLKOUTSRC: |
f6f1eb10 | 688 | reg = snd_soc_read(codec, WM8580_PLLB4); |
e88ba015 MB |
689 | reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK; |
690 | ||
691 | switch (div) { | |
692 | case WM8580_CLKSRC_NONE: | |
693 | break; | |
694 | ||
695 | case WM8580_CLKSRC_PLLA: | |
696 | reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK; | |
697 | break; | |
698 | ||
699 | case WM8580_CLKSRC_PLLB: | |
700 | reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK; | |
701 | break; | |
702 | ||
703 | case WM8580_CLKSRC_OSC: | |
704 | reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK; | |
705 | break; | |
706 | ||
707 | default: | |
708 | return -EINVAL; | |
709 | } | |
f6f1eb10 | 710 | snd_soc_write(codec, WM8580_PLLB4, reg); |
e88ba015 MB |
711 | break; |
712 | ||
713 | default: | |
714 | return -EINVAL; | |
715 | } | |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
c5607d8e MB |
720 | static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id, |
721 | unsigned int freq, int dir) | |
722 | { | |
723 | struct snd_soc_codec *codec = dai->codec; | |
724 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); | |
748b2178 | 725 | int ret, sel, sel_mask, sel_shift; |
c5607d8e MB |
726 | |
727 | switch (dai->driver->id) { | |
c25edef8 | 728 | case WM8580_DAI_PAIFRX: |
c5607d8e MB |
729 | sel_mask = 0x3; |
730 | sel_shift = 0; | |
731 | break; | |
732 | ||
c25edef8 | 733 | case WM8580_DAI_PAIFTX: |
c5607d8e MB |
734 | sel_mask = 0xc; |
735 | sel_shift = 2; | |
736 | break; | |
737 | ||
738 | default: | |
4a9e0f91 | 739 | WARN(1, "Unknown DAI driver ID\n"); |
c5607d8e MB |
740 | return -EINVAL; |
741 | } | |
742 | ||
743 | switch (clk_id) { | |
744 | case WM8580_CLKSRC_ADCMCLK: | |
06286938 | 745 | if (dai->driver->id != WM8580_DAI_PAIFTX) |
c5607d8e MB |
746 | return -EINVAL; |
747 | sel = 0 << sel_shift; | |
748 | break; | |
749 | case WM8580_CLKSRC_PLLA: | |
750 | sel = 1 << sel_shift; | |
751 | break; | |
752 | case WM8580_CLKSRC_PLLB: | |
753 | sel = 2 << sel_shift; | |
754 | break; | |
755 | case WM8580_CLKSRC_MCLK: | |
756 | sel = 3 << sel_shift; | |
757 | break; | |
758 | default: | |
759 | dev_err(codec->dev, "Unknown clock %d\n", clk_id); | |
760 | return -EINVAL; | |
761 | } | |
762 | ||
763 | /* We really should validate PLL settings but not yet */ | |
06286938 | 764 | wm8580->sysclk[dai->driver->id] = freq; |
c5607d8e | 765 | |
748b2178 AL |
766 | ret = snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel); |
767 | if (ret < 0) | |
768 | return ret; | |
769 | ||
770 | return 0; | |
c5607d8e MB |
771 | } |
772 | ||
e88ba015 MB |
773 | static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute) |
774 | { | |
775 | struct snd_soc_codec *codec = codec_dai->codec; | |
776 | unsigned int reg; | |
777 | ||
f6f1eb10 | 778 | reg = snd_soc_read(codec, WM8580_DAC_CONTROL5); |
e88ba015 MB |
779 | |
780 | if (mute) | |
781 | reg |= WM8580_DAC_CONTROL5_MUTEALL; | |
782 | else | |
783 | reg &= ~WM8580_DAC_CONTROL5_MUTEALL; | |
784 | ||
f6f1eb10 | 785 | snd_soc_write(codec, WM8580_DAC_CONTROL5, reg); |
e88ba015 MB |
786 | |
787 | return 0; | |
788 | } | |
789 | ||
790 | static int wm8580_set_bias_level(struct snd_soc_codec *codec, | |
791 | enum snd_soc_bias_level level) | |
792 | { | |
e88ba015 MB |
793 | switch (level) { |
794 | case SND_SOC_BIAS_ON: | |
795 | case SND_SOC_BIAS_PREPARE: | |
6f7cb44b MB |
796 | break; |
797 | ||
e88ba015 | 798 | case SND_SOC_BIAS_STANDBY: |
ce6120cc | 799 | if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { |
6f7cb44b | 800 | /* Power up and get individual control of the DACs */ |
a6785d7d AL |
801 | snd_soc_update_bits(codec, WM8580_PWRDN1, |
802 | WM8580_PWRDN1_PWDN | | |
803 | WM8580_PWRDN1_ALLDACPD, 0); | |
6f7cb44b | 804 | |
25985edc | 805 | /* Make VMID high impedance */ |
a6785d7d AL |
806 | snd_soc_update_bits(codec, WM8580_ADC_CONTROL1, |
807 | 0x100, 0); | |
6f7cb44b | 808 | } |
e88ba015 | 809 | break; |
6f7cb44b | 810 | |
e88ba015 | 811 | case SND_SOC_BIAS_OFF: |
a6785d7d AL |
812 | snd_soc_update_bits(codec, WM8580_PWRDN1, |
813 | WM8580_PWRDN1_PWDN, WM8580_PWRDN1_PWDN); | |
e88ba015 MB |
814 | break; |
815 | } | |
ce6120cc | 816 | codec->dapm.bias_level = level; |
e88ba015 MB |
817 | return 0; |
818 | } | |
819 | ||
820 | #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ | |
821 | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) | |
822 | ||
85e7652d | 823 | static const struct snd_soc_dai_ops wm8580_dai_ops_playback = { |
c5607d8e | 824 | .set_sysclk = wm8580_set_sysclk, |
6335d055 EM |
825 | .hw_params = wm8580_paif_hw_params, |
826 | .set_fmt = wm8580_set_paif_dai_fmt, | |
827 | .set_clkdiv = wm8580_set_dai_clkdiv, | |
828 | .set_pll = wm8580_set_dai_pll, | |
829 | .digital_mute = wm8580_digital_mute, | |
830 | }; | |
831 | ||
85e7652d | 832 | static const struct snd_soc_dai_ops wm8580_dai_ops_capture = { |
c5607d8e | 833 | .set_sysclk = wm8580_set_sysclk, |
6335d055 EM |
834 | .hw_params = wm8580_paif_hw_params, |
835 | .set_fmt = wm8580_set_paif_dai_fmt, | |
836 | .set_clkdiv = wm8580_set_dai_clkdiv, | |
837 | .set_pll = wm8580_set_dai_pll, | |
838 | }; | |
839 | ||
f0fba2ad | 840 | static struct snd_soc_dai_driver wm8580_dai[] = { |
e88ba015 | 841 | { |
f0fba2ad LG |
842 | .name = "wm8580-hifi-playback", |
843 | .id = WM8580_DAI_PAIFRX, | |
e88ba015 MB |
844 | .playback = { |
845 | .stream_name = "Playback", | |
846 | .channels_min = 1, | |
847 | .channels_max = 6, | |
848 | .rates = SNDRV_PCM_RATE_8000_192000, | |
849 | .formats = WM8580_FORMATS, | |
850 | }, | |
6335d055 | 851 | .ops = &wm8580_dai_ops_playback, |
e88ba015 MB |
852 | }, |
853 | { | |
f0fba2ad LG |
854 | .name = "wm8580-hifi-capture", |
855 | .id = WM8580_DAI_PAIFTX, | |
e88ba015 MB |
856 | .capture = { |
857 | .stream_name = "Capture", | |
858 | .channels_min = 2, | |
859 | .channels_max = 2, | |
860 | .rates = SNDRV_PCM_RATE_8000_192000, | |
861 | .formats = WM8580_FORMATS, | |
862 | }, | |
6335d055 | 863 | .ops = &wm8580_dai_ops_capture, |
e88ba015 MB |
864 | }, |
865 | }; | |
e88ba015 | 866 | |
f0fba2ad | 867 | static int wm8580_probe(struct snd_soc_codec *codec) |
e88ba015 | 868 | { |
f0fba2ad | 869 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
18273b05 | 870 | int ret = 0; |
6f7cb44b | 871 | |
b689d9f9 | 872 | ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP); |
f6f1eb10 MB |
873 | if (ret < 0) { |
874 | dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); | |
f0fba2ad | 875 | return ret; |
f6f1eb10 MB |
876 | } |
877 | ||
a583cd53 MB |
878 | ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies), |
879 | wm8580->supplies); | |
880 | if (ret != 0) { | |
881 | dev_err(codec->dev, "Failed to enable supplies: %d\n", ret); | |
882 | goto err_regulator_get; | |
883 | } | |
884 | ||
6f7cb44b | 885 | /* Get the codec into a known state */ |
f6f1eb10 | 886 | ret = snd_soc_write(codec, WM8580_RESET, 0); |
6f7cb44b MB |
887 | if (ret != 0) { |
888 | dev_err(codec->dev, "Failed to reset codec: %d\n", ret); | |
a583cd53 | 889 | goto err_regulator_enable; |
6f7cb44b MB |
890 | } |
891 | ||
6f7cb44b | 892 | wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY); |
e88ba015 | 893 | |
6f7cb44b MB |
894 | return 0; |
895 | ||
a583cd53 MB |
896 | err_regulator_enable: |
897 | regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies); | |
898 | err_regulator_get: | |
6f7cb44b MB |
899 | return ret; |
900 | } | |
901 | ||
f0fba2ad LG |
902 | /* power down chip */ |
903 | static int wm8580_remove(struct snd_soc_codec *codec) | |
6f7cb44b | 904 | { |
f0fba2ad LG |
905 | struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec); |
906 | ||
907 | wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF); | |
908 | ||
a583cd53 | 909 | regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies); |
f0fba2ad LG |
910 | |
911 | return 0; | |
6f7cb44b MB |
912 | } |
913 | ||
f0fba2ad LG |
914 | static struct snd_soc_codec_driver soc_codec_dev_wm8580 = { |
915 | .probe = wm8580_probe, | |
916 | .remove = wm8580_remove, | |
917 | .set_bias_level = wm8580_set_bias_level, | |
f235c649 MB |
918 | |
919 | .controls = wm8580_snd_controls, | |
920 | .num_controls = ARRAY_SIZE(wm8580_snd_controls), | |
921 | .dapm_widgets = wm8580_dapm_widgets, | |
922 | .num_dapm_widgets = ARRAY_SIZE(wm8580_dapm_widgets), | |
923 | .dapm_routes = wm8580_dapm_routes, | |
924 | .num_dapm_routes = ARRAY_SIZE(wm8580_dapm_routes), | |
f0fba2ad LG |
925 | }; |
926 | ||
733eef3e MB |
927 | static const struct of_device_id wm8580_of_match[] = { |
928 | { .compatible = "wlf,wm8580" }, | |
929 | { }, | |
930 | }; | |
931 | ||
b689d9f9 MB |
932 | static const struct regmap_config wm8580_regmap = { |
933 | .reg_bits = 7, | |
934 | .val_bits = 9, | |
935 | .max_register = WM8580_MAX_REGISTER, | |
936 | ||
937 | .reg_defaults = wm8580_reg_defaults, | |
938 | .num_reg_defaults = ARRAY_SIZE(wm8580_reg_defaults), | |
939 | .cache_type = REGCACHE_RBTREE, | |
940 | ||
941 | .volatile_reg = wm8580_volatile, | |
942 | }; | |
943 | ||
6f7cb44b | 944 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
17be5522 JD |
945 | static int wm8580_i2c_probe(struct i2c_client *i2c, |
946 | const struct i2c_device_id *id) | |
e88ba015 | 947 | { |
6f7cb44b | 948 | struct wm8580_priv *wm8580; |
18273b05 | 949 | int ret, i; |
6f7cb44b | 950 | |
398c02f6 MB |
951 | wm8580 = devm_kzalloc(&i2c->dev, sizeof(struct wm8580_priv), |
952 | GFP_KERNEL); | |
6f7cb44b MB |
953 | if (wm8580 == NULL) |
954 | return -ENOMEM; | |
955 | ||
b689d9f9 MB |
956 | wm8580->regmap = devm_regmap_init_i2c(i2c, &wm8580_regmap); |
957 | if (IS_ERR(wm8580->regmap)) | |
958 | return PTR_ERR(wm8580->regmap); | |
959 | ||
18273b05 MB |
960 | for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++) |
961 | wm8580->supplies[i].supply = wm8580_supply_names[i]; | |
962 | ||
963 | ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8580->supplies), | |
964 | wm8580->supplies); | |
965 | if (ret != 0) { | |
966 | dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret); | |
967 | return ret; | |
968 | } | |
969 | ||
6f7cb44b | 970 | i2c_set_clientdata(i2c, wm8580); |
6f7cb44b | 971 | |
f0fba2ad LG |
972 | ret = snd_soc_register_codec(&i2c->dev, |
973 | &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai)); | |
398c02f6 | 974 | |
f0fba2ad | 975 | return ret; |
e88ba015 MB |
976 | } |
977 | ||
17be5522 | 978 | static int wm8580_i2c_remove(struct i2c_client *client) |
e88ba015 | 979 | { |
f0fba2ad | 980 | snd_soc_unregister_codec(&client->dev); |
e88ba015 MB |
981 | return 0; |
982 | } | |
983 | ||
17be5522 JD |
984 | static const struct i2c_device_id wm8580_i2c_id[] = { |
985 | { "wm8580", 0 }, | |
986 | { } | |
987 | }; | |
988 | MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id); | |
e88ba015 | 989 | |
e88ba015 MB |
990 | static struct i2c_driver wm8580_i2c_driver = { |
991 | .driver = { | |
722d0daf | 992 | .name = "wm8580", |
e88ba015 | 993 | .owner = THIS_MODULE, |
733eef3e | 994 | .of_match_table = wm8580_of_match, |
e88ba015 | 995 | }, |
17be5522 JD |
996 | .probe = wm8580_i2c_probe, |
997 | .remove = wm8580_i2c_remove, | |
998 | .id_table = wm8580_i2c_id, | |
e88ba015 | 999 | }; |
6f7cb44b | 1000 | #endif |
e88ba015 | 1001 | |
6f7cb44b | 1002 | static int __init wm8580_modinit(void) |
17be5522 | 1003 | { |
f0fba2ad | 1004 | int ret = 0; |
17be5522 | 1005 | |
6f7cb44b | 1006 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
17be5522 JD |
1007 | ret = i2c_add_driver(&wm8580_i2c_driver); |
1008 | if (ret != 0) { | |
6f7cb44b | 1009 | pr_err("Failed to register WM8580 I2C driver: %d\n", ret); |
e88ba015 | 1010 | } |
e88ba015 | 1011 | #endif |
e88ba015 | 1012 | |
f0fba2ad | 1013 | return ret; |
e88ba015 | 1014 | } |
64089b84 MB |
1015 | module_init(wm8580_modinit); |
1016 | ||
1017 | static void __exit wm8580_exit(void) | |
1018 | { | |
6f7cb44b MB |
1019 | #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) |
1020 | i2c_del_driver(&wm8580_i2c_driver); | |
1021 | #endif | |
64089b84 MB |
1022 | } |
1023 | module_exit(wm8580_exit); | |
1024 | ||
e88ba015 MB |
1025 | MODULE_DESCRIPTION("ASoC WM8580 driver"); |
1026 | MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); | |
1027 | MODULE_LICENSE("GPL"); |