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ASoC: multi-component - ASoC Multi-Component Support
[deliverable/linux.git] / sound / soc / codecs / wm8580.c
CommitLineData
e88ba015
MB		 1/*
2 * wm8580.c -- WM8580 ALSA Soc Audio driver
3 *
6f7cb44b 4 * Copyright 2008, 2009 Wolfson Microelectronics PLC.
e88ba015
MB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Notes:
12 * The WM8580 is a multichannel codec with S/PDIF support, featuring six
13 * DAC channels and two ADC channels.
14 *
15 * Currently only the primary audio interface is supported - S/PDIF and
16 * the secondary audio interfaces are not.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
e88ba015
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
a583cd53 27#include <linux/regulator/consumer.h>
5a0e3ad6 28#include <linux/slab.h>
a583cd53 29
e88ba015
MB		 30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/soc.h>
34#include <sound/soc-dapm.h>
35#include <sound/tlv.h>
36#include <sound/initval.h>
37#include <asm/div64.h>
38
39#include "wm8580.h"
40
e88ba015
MB		 41/* WM8580 register space */
42#define WM8580_PLLA1 0x00
43#define WM8580_PLLA2 0x01
44#define WM8580_PLLA3 0x02
45#define WM8580_PLLA4 0x03
46#define WM8580_PLLB1 0x04
47#define WM8580_PLLB2 0x05
48#define WM8580_PLLB3 0x06
49#define WM8580_PLLB4 0x07
50#define WM8580_CLKSEL 0x08
51#define WM8580_PAIF1 0x09
52#define WM8580_PAIF2 0x0A
53#define WM8580_SAIF1 0x0B
54#define WM8580_PAIF3 0x0C
55#define WM8580_PAIF4 0x0D
56#define WM8580_SAIF2 0x0E
57#define WM8580_DAC_CONTROL1 0x0F
58#define WM8580_DAC_CONTROL2 0x10
59#define WM8580_DAC_CONTROL3 0x11
60#define WM8580_DAC_CONTROL4 0x12
61#define WM8580_DAC_CONTROL5 0x13
62#define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
63#define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
64#define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
65#define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
66#define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
67#define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
68#define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
69#define WM8580_ADC_CONTROL1 0x1D
70#define WM8580_SPDTXCHAN0 0x1E
71#define WM8580_SPDTXCHAN1 0x1F
72#define WM8580_SPDTXCHAN2 0x20
73#define WM8580_SPDTXCHAN3 0x21
74#define WM8580_SPDTXCHAN4 0x22
75#define WM8580_SPDTXCHAN5 0x23
76#define WM8580_SPDMODE 0x24
77#define WM8580_INTMASK 0x25
78#define WM8580_GPO1 0x26
79#define WM8580_GPO2 0x27
80#define WM8580_GPO3 0x28
81#define WM8580_GPO4 0x29
82#define WM8580_GPO5 0x2A
83#define WM8580_INTSTAT 0x2B
84#define WM8580_SPDRXCHAN1 0x2C
85#define WM8580_SPDRXCHAN2 0x2D
86#define WM8580_SPDRXCHAN3 0x2E
87#define WM8580_SPDRXCHAN4 0x2F
88#define WM8580_SPDRXCHAN5 0x30
89#define WM8580_SPDSTAT 0x31
90#define WM8580_PWRDN1 0x32
91#define WM8580_PWRDN2 0x33
92#define WM8580_READBACK 0x34
93#define WM8580_RESET 0x35
94
6f7cb44b
MB		 95#define WM8580_MAX_REGISTER 0x35
96
e88ba015
MB		 97/* PLLB4 (register 7h) */
98#define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
99#define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
100#define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
101#define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
102
103#define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
104#define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
105#define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
106#define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
107
108/* CLKSEL (register 8h) */
109#define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
110#define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
111#define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
112
113/* AIF control 1 (registers 9h-bh) */
114#define WM8580_AIF_RATE_MASK 0x7
115#define WM8580_AIF_RATE_128 0x0
116#define WM8580_AIF_RATE_192 0x1
117#define WM8580_AIF_RATE_256 0x2
118#define WM8580_AIF_RATE_384 0x3
119#define WM8580_AIF_RATE_512 0x4
120#define WM8580_AIF_RATE_768 0x5
121#define WM8580_AIF_RATE_1152 0x6
122
123#define WM8580_AIF_BCLKSEL_MASK 0x18
124#define WM8580_AIF_BCLKSEL_64 0x00
125#define WM8580_AIF_BCLKSEL_128 0x08
126#define WM8580_AIF_BCLKSEL_256 0x10
127#define WM8580_AIF_BCLKSEL_SYSCLK 0x18
128
129#define WM8580_AIF_MS 0x20
130
131#define WM8580_AIF_CLKSRC_MASK 0xc0
132#define WM8580_AIF_CLKSRC_PLLA 0x40
133#define WM8580_AIF_CLKSRC_PLLB 0x40
134#define WM8580_AIF_CLKSRC_MCLK 0xc0
135
136/* AIF control 2 (registers ch-eh) */
137#define WM8580_AIF_FMT_MASK 0x03
138#define WM8580_AIF_FMT_RIGHTJ 0x00
139#define WM8580_AIF_FMT_LEFTJ 0x01
140#define WM8580_AIF_FMT_I2S 0x02
141#define WM8580_AIF_FMT_DSP 0x03
142
143#define WM8580_AIF_LENGTH_MASK 0x0c
144#define WM8580_AIF_LENGTH_16 0x00
145#define WM8580_AIF_LENGTH_20 0x04
146#define WM8580_AIF_LENGTH_24 0x08
147#define WM8580_AIF_LENGTH_32 0x0c
148
149#define WM8580_AIF_LRP 0x10
150#define WM8580_AIF_BCP 0x20
151
152/* Powerdown Register 1 (register 32h) */
153#define WM8580_PWRDN1_PWDN 0x001
154#define WM8580_PWRDN1_ALLDACPD 0x040
155
156/* Powerdown Register 2 (register 33h) */
157#define WM8580_PWRDN2_OSSCPD 0x001
158#define WM8580_PWRDN2_PLLAPD 0x002
159#define WM8580_PWRDN2_PLLBPD 0x004
160#define WM8580_PWRDN2_SPDIFPD 0x008
161#define WM8580_PWRDN2_SPDIFTXD 0x010
162#define WM8580_PWRDN2_SPDIFRXD 0x020
163
164#define WM8580_DAC_CONTROL5_MUTEALL 0x10
165
166/*
167 * wm8580 register cache
168 * We can't read the WM8580 register space when we
169 * are using 2 wire for device control, so we cache them instead.
170 */
171static const u16 wm8580_reg[] = {
172 0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
173 0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
174 0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
175 0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
176 0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
177 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
178 0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
179 0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
180 0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
181 0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
182 0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
183 0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
184 0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
185 0x0000, 0x0000 /*R53*/
186};
187
6f7cb44b
MB		 188struct pll_state {
189 unsigned int in;
190 unsigned int out;
191};
192
a583cd53
MB		 193#define WM8580_NUM_SUPPLIES 3
194static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
195 "AVDD",
196 "DVDD",
197 "PVDD",
198};
199
6f7cb44b
MB		 200/* codec private data */
201struct wm8580_priv {
f0fba2ad
LG		 202 enum snd_soc_control_type control_type;
203 void *control_data;
a583cd53 204 struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
6f7cb44b
MB		 205 u16 reg_cache[WM8580_MAX_REGISTER + 1];
206 struct pll_state a;
207 struct pll_state b;
208};
209
e88ba015
MB		 210static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
211
212static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
213 struct snd_ctl_elem_value *ucontrol)
214{
ccb077fd
MB		 215 struct soc_mixer_control *mc =
216 (struct soc_mixer_control *)kcontrol->private_value;
e88ba015 217 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f6f1eb10 218 u16 *reg_cache = codec->reg_cache;
ccb077fd
MB		 219 unsigned int reg = mc->reg;
220 unsigned int reg2 = mc->rreg;
e88ba015 221 int ret;
e88ba015
MB		 222
223 /* Clear the register cache so we write without VU set */
f6f1eb10
MB		 224 reg_cache[reg] = 0;
225 reg_cache[reg2] = 0;
e88ba015
MB		 226
227 ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
228 if (ret < 0)
229 return ret;
230
231 /* Now write again with the volume update bit set */
f6f1eb10
MB		 232 snd_soc_update_bits(codec, reg, 0x100, 0x100);
233 snd_soc_update_bits(codec, reg2, 0x100, 0x100);
e88ba015
MB		 234
235 return 0;
236}
237
ccb077fd
MB		 238#define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
239 xinvert, tlv_array) \
e88ba015
MB		 240{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
241 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
242 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
243 .tlv.p = (tlv_array), \
244 .info = snd_soc_info_volsw_2r, \
245 .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
ccb077fd
MB		 246 .private_value = (unsigned long)&(struct soc_mixer_control) \
247 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
248 .max = xmax, .invert = xinvert} }
e88ba015
MB		 249
250static const struct snd_kcontrol_new wm8580_snd_controls[] = {
251SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
252 WM8580_DIGITAL_ATTENUATION_DACL1,
253 WM8580_DIGITAL_ATTENUATION_DACR1,
254 0, 0xff, 0, dac_tlv),
255SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
256 WM8580_DIGITAL_ATTENUATION_DACL2,
257 WM8580_DIGITAL_ATTENUATION_DACR2,
258 0, 0xff, 0, dac_tlv),
259SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
260 WM8580_DIGITAL_ATTENUATION_DACL3,
261 WM8580_DIGITAL_ATTENUATION_DACR3,
262 0, 0xff, 0, dac_tlv),
263
264SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
265SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
266SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
267
268SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4, 0, 1, 1, 0),
269SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4, 2, 3, 1, 0),
270SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4, 4, 5, 1, 0),
271
272SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
273SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
274SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
275SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
276
277SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
278SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
279};
280
e88ba015
MB		 281static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
282SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
283SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
284SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
285
286SND_SOC_DAPM_OUTPUT("VOUT1L"),
287SND_SOC_DAPM_OUTPUT("VOUT1R"),
288SND_SOC_DAPM_OUTPUT("VOUT2L"),
289SND_SOC_DAPM_OUTPUT("VOUT2R"),
290SND_SOC_DAPM_OUTPUT("VOUT3L"),
291SND_SOC_DAPM_OUTPUT("VOUT3R"),
292
293SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
294
295SND_SOC_DAPM_INPUT("AINL"),
296SND_SOC_DAPM_INPUT("AINR"),
297};
298
299static const struct snd_soc_dapm_route audio_map[] = {
300 { "VOUT1L", NULL, "DAC1" },
301 { "VOUT1R", NULL, "DAC1" },
302
303 { "VOUT2L", NULL, "DAC2" },
304 { "VOUT2R", NULL, "DAC2" },
305
306 { "VOUT3L", NULL, "DAC3" },
307 { "VOUT3R", NULL, "DAC3" },
308
309 { "ADC", NULL, "AINL" },
310 { "ADC", NULL, "AINR" },
311};
312
313static int wm8580_add_widgets(struct snd_soc_codec *codec)
314{
315 snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
316 ARRAY_SIZE(wm8580_dapm_widgets));
317
318 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
319
e88ba015
MB		 320 return 0;
321}
322
323/* PLL divisors */
324struct _pll_div {
325 u32 prescale:1;
326 u32 postscale:1;
327 u32 freqmode:2;
328 u32 n:4;
329 u32 k:24;
330};
331
332/* The size in bits of the pll divide */
333#define FIXED_PLL_SIZE (1 << 22)
334
335/* PLL rate to output rate divisions */
336static struct {
337 unsigned int div;
338 unsigned int freqmode;
339 unsigned int postscale;
340} post_table[] = {
341 { 2, 0, 0 },
342 { 4, 0, 1 },
343 { 4, 1, 0 },
344 { 8, 1, 1 },
345 { 8, 2, 0 },
346 { 16, 2, 1 },
347 { 12, 3, 0 },
348 { 24, 3, 1 }
349};
350
351static int pll_factors(struct _pll_div *pll_div, unsigned int target,
352 unsigned int source)
353{
354 u64 Kpart;
355 unsigned int K, Ndiv, Nmod;
356 int i;
357
449bd54d 358 pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
e88ba015
MB		 359
360 /* Scale the output frequency up; the PLL should run in the
361 * region of 90-100MHz.
362 */
363 for (i = 0; i < ARRAY_SIZE(post_table); i++) {
364 if (target * post_table[i].div >= 90000000 &&
365 target * post_table[i].div <= 100000000) {
366 pll_div->freqmode = post_table[i].freqmode;
367 pll_div->postscale = post_table[i].postscale;
368 target *= post_table[i].div;
369 break;
370 }
371 }
372
373 if (i == ARRAY_SIZE(post_table)) {
374 printk(KERN_ERR "wm8580: Unable to scale output frequency "
375 "%u\n", target);
376 return -EINVAL;
377 }
378
379 Ndiv = target / source;
380
381 if (Ndiv < 5) {
382 source /= 2;
383 pll_div->prescale = 1;
384 Ndiv = target / source;
385 } else
386 pll_div->prescale = 0;
387
388 if ((Ndiv < 5) || (Ndiv > 13)) {
389 printk(KERN_ERR
449bd54d 390 "WM8580 N=%u outside supported range\n", Ndiv);
e88ba015
MB		 391 return -EINVAL;
392 }
393
394 pll_div->n = Ndiv;
395 Nmod = target % source;
396 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
397
398 do_div(Kpart, source);
399
400 K = Kpart & 0xFFFFFFFF;
401
402 pll_div->k = K;
403
404 pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
405 pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
406 pll_div->postscale);
407
408 return 0;
409}
410
85488037
MB		 411static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
412 int source, unsigned int freq_in, unsigned int freq_out)
e88ba015
MB		 413{
414 int offset;
415 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 416 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
e88ba015
MB		 417 struct pll_state *state;
418 struct _pll_div pll_div;
419 unsigned int reg;
420 unsigned int pwr_mask;
421 int ret;
422
423 /* GCC isn't able to work out the ifs below for initialising/using
424 * pll_div so suppress warnings.
425 */
426 memset(&pll_div, 0, sizeof(pll_div));
427
428 switch (pll_id) {
429 case WM8580_PLLA:
430 state = &wm8580->a;
431 offset = 0;
432 pwr_mask = WM8580_PWRDN2_PLLAPD;
433 break;
434 case WM8580_PLLB:
435 state = &wm8580->b;
436 offset = 4;
437 pwr_mask = WM8580_PWRDN2_PLLBPD;
438 break;
439 default:
440 return -ENODEV;
441 }
442
443 if (freq_in && freq_out) {
444 ret = pll_factors(&pll_div, freq_out, freq_in);
445 if (ret != 0)
446 return ret;
447 }
448
449 state->in = freq_in;
450 state->out = freq_out;
451
452 /* Always disable the PLL - it is not safe to leave it running
453 * while reprogramming it.
454 */
f6f1eb10
MB		 455 reg = snd_soc_read(codec, WM8580_PWRDN2);
456 snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
e88ba015
MB		 457
458 if (!freq_in || !freq_out)
459 return 0;
460
f6f1eb10 461 snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
5c0d38c9 462 snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
f6f1eb10 463 snd_soc_write(codec, WM8580_PLLA3 + offset,
e88ba015
MB		 464 (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
465
f6f1eb10 466 reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
5c0d38c9 467 reg &= ~0x1b;
e88ba015 468 reg |= pll_div.prescale | pll_div.postscale << 1 |
ce88168f 469 pll_div.freqmode << 3;
e88ba015 470
f6f1eb10 471 snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
e88ba015
MB		 472
473 /* All done, turn it on */
f6f1eb10
MB		 474 reg = snd_soc_read(codec, WM8580_PWRDN2);
475 snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
e88ba015
MB		 476
477 return 0;
478}
479
480/*
481 * Set PCM DAI bit size and sample rate.
482 */
483static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 484 struct snd_pcm_hw_params *params,
485 struct snd_soc_dai *dai)
e88ba015
MB		 486{
487 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad
LG		 488 struct snd_soc_codec *codec = rtd->codec;
489 u16 paifb = snd_soc_read(codec, WM8580_PAIF3 + dai->driver->id);
e88ba015
MB		 490
491 paifb &= ~WM8580_AIF_LENGTH_MASK;
492 /* bit size */
493 switch (params_format(params)) {
494 case SNDRV_PCM_FORMAT_S16_LE:
495 break;
496 case SNDRV_PCM_FORMAT_S20_3LE:
497 paifb |= WM8580_AIF_LENGTH_20;
498 break;
499 case SNDRV_PCM_FORMAT_S24_LE:
500 paifb |= WM8580_AIF_LENGTH_24;
501 break;
502 case SNDRV_PCM_FORMAT_S32_LE:
503 paifb |= WM8580_AIF_LENGTH_24;
504 break;
505 default:
506 return -EINVAL;
507 }
508
f0fba2ad 509 snd_soc_write(codec, WM8580_PAIF3 + dai->driver->id, paifb);
e88ba015
MB		 510 return 0;
511}
512
513static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
514 unsigned int fmt)
515{
516 struct snd_soc_codec *codec = codec_dai->codec;
517 unsigned int aifa;
518 unsigned int aifb;
519 int can_invert_lrclk;
520
f0fba2ad
LG		 521 aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
522 aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
e88ba015
MB		 523
524 aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
525
526 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
527 case SND_SOC_DAIFMT_CBS_CFS:
528 aifa &= ~WM8580_AIF_MS;
529 break;
530 case SND_SOC_DAIFMT_CBM_CFM:
531 aifa |= WM8580_AIF_MS;
532 break;
533 default:
534 return -EINVAL;
535 }
536
537 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
538 case SND_SOC_DAIFMT_I2S:
539 can_invert_lrclk = 1;
540 aifb |= WM8580_AIF_FMT_I2S;
541 break;
542 case SND_SOC_DAIFMT_RIGHT_J:
543 can_invert_lrclk = 1;
544 aifb |= WM8580_AIF_FMT_RIGHTJ;
545 break;
546 case SND_SOC_DAIFMT_LEFT_J:
547 can_invert_lrclk = 1;
548 aifb |= WM8580_AIF_FMT_LEFTJ;
549 break;
550 case SND_SOC_DAIFMT_DSP_A:
551 can_invert_lrclk = 0;
552 aifb |= WM8580_AIF_FMT_DSP;
553 break;
554 case SND_SOC_DAIFMT_DSP_B:
555 can_invert_lrclk = 0;
556 aifb |= WM8580_AIF_FMT_DSP;
557 aifb |= WM8580_AIF_LRP;
558 break;
559 default:
560 return -EINVAL;
561 }
562
563 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
564 case SND_SOC_DAIFMT_NB_NF:
565 break;
566
567 case SND_SOC_DAIFMT_IB_IF:
568 if (!can_invert_lrclk)
569 return -EINVAL;
570 aifb |= WM8580_AIF_BCP;
571 aifb |= WM8580_AIF_LRP;
572 break;
573
574 case SND_SOC_DAIFMT_IB_NF:
575 aifb |= WM8580_AIF_BCP;
576 break;
577
578 case SND_SOC_DAIFMT_NB_IF:
579 if (!can_invert_lrclk)
580 return -EINVAL;
581 aifb |= WM8580_AIF_LRP;
582 break;
583
584 default:
585 return -EINVAL;
586 }
587
f0fba2ad
LG		 588 snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
589 snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
e88ba015
MB		 590
591 return 0;
592}
593
594static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
595 int div_id, int div)
596{
597 struct snd_soc_codec *codec = codec_dai->codec;
598 unsigned int reg;
599
600 switch (div_id) {
601 case WM8580_MCLK:
f6f1eb10 602 reg = snd_soc_read(codec, WM8580_PLLB4);
e88ba015
MB		 603 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
604
605 switch (div) {
606 case WM8580_CLKSRC_MCLK:
607 /* Input */
608 break;
609
610 case WM8580_CLKSRC_PLLA:
611 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
612 break;
613 case WM8580_CLKSRC_PLLB:
614 reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
615 break;
616
617 case WM8580_CLKSRC_OSC:
618 reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
619 break;
620
621 default:
622 return -EINVAL;
623 }
f6f1eb10 624 snd_soc_write(codec, WM8580_PLLB4, reg);
e88ba015
MB		 625 break;
626
627 case WM8580_DAC_CLKSEL:
f6f1eb10 628 reg = snd_soc_read(codec, WM8580_CLKSEL);
e88ba015
MB		 629 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
630
631 switch (div) {
632 case WM8580_CLKSRC_MCLK:
633 break;
634
635 case WM8580_CLKSRC_PLLA:
636 reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
637 break;
638
639 case WM8580_CLKSRC_PLLB:
640 reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
641 break;
642
643 default:
644 return -EINVAL;
645 }
f6f1eb10 646 snd_soc_write(codec, WM8580_CLKSEL, reg);
e88ba015
MB		 647 break;
648
649 case WM8580_CLKOUTSRC:
f6f1eb10 650 reg = snd_soc_read(codec, WM8580_PLLB4);
e88ba015
MB		 651 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
652
653 switch (div) {
654 case WM8580_CLKSRC_NONE:
655 break;
656
657 case WM8580_CLKSRC_PLLA:
658 reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
659 break;
660
661 case WM8580_CLKSRC_PLLB:
662 reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
663 break;
664
665 case WM8580_CLKSRC_OSC:
666 reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
667 break;
668
669 default:
670 return -EINVAL;
671 }
f6f1eb10 672 snd_soc_write(codec, WM8580_PLLB4, reg);
e88ba015
MB		 673 break;
674
675 default:
676 return -EINVAL;
677 }
678
679 return 0;
680}
681
682static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
683{
684 struct snd_soc_codec *codec = codec_dai->codec;
685 unsigned int reg;
686
f6f1eb10 687 reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
e88ba015
MB		 688
689 if (mute)
690 reg |= WM8580_DAC_CONTROL5_MUTEALL;
691 else
692 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
693
f6f1eb10 694 snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
e88ba015
MB		 695
696 return 0;
697}
698
699static int wm8580_set_bias_level(struct snd_soc_codec *codec,
700 enum snd_soc_bias_level level)
701{
702 u16 reg;
703 switch (level) {
704 case SND_SOC_BIAS_ON:
705 case SND_SOC_BIAS_PREPARE:
6f7cb44b
MB		 706 break;
707
e88ba015 708 case SND_SOC_BIAS_STANDBY:
6f7cb44b
MB		 709 if (codec->bias_level == SND_SOC_BIAS_OFF) {
710 /* Power up and get individual control of the DACs */
f6f1eb10 711 reg = snd_soc_read(codec, WM8580_PWRDN1);
6f7cb44b 712 reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
f6f1eb10 713 snd_soc_write(codec, WM8580_PWRDN1, reg);
6f7cb44b
MB		 714
715 /* Make VMID high impedence */
f6f1eb10 716 reg = snd_soc_read(codec, WM8580_ADC_CONTROL1);
6f7cb44b 717 reg &= ~0x100;
f6f1eb10 718 snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
6f7cb44b 719 }
e88ba015 720 break;
6f7cb44b 721
e88ba015 722 case SND_SOC_BIAS_OFF:
f6f1eb10
MB		 723 reg = snd_soc_read(codec, WM8580_PWRDN1);
724 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
e88ba015
MB		 725 break;
726 }
727 codec->bias_level = level;
728 return 0;
729}
730
731#define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
732 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
733
6335d055
EM		 734static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
735 .hw_params = wm8580_paif_hw_params,
736 .set_fmt = wm8580_set_paif_dai_fmt,
737 .set_clkdiv = wm8580_set_dai_clkdiv,
738 .set_pll = wm8580_set_dai_pll,
739 .digital_mute = wm8580_digital_mute,
740};
741
742static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
743 .hw_params = wm8580_paif_hw_params,
744 .set_fmt = wm8580_set_paif_dai_fmt,
745 .set_clkdiv = wm8580_set_dai_clkdiv,
746 .set_pll = wm8580_set_dai_pll,
747};
748
f0fba2ad 749static struct snd_soc_dai_driver wm8580_dai[] = {
e88ba015 750 {
f0fba2ad
LG		 751 .name = "wm8580-hifi-playback",
752 .id = WM8580_DAI_PAIFRX,
e88ba015
MB		 753 .playback = {
754 .stream_name = "Playback",
755 .channels_min = 1,
756 .channels_max = 6,
757 .rates = SNDRV_PCM_RATE_8000_192000,
758 .formats = WM8580_FORMATS,
759 },
6335d055 760 .ops = &wm8580_dai_ops_playback,
e88ba015
MB		 761 },
762 {
f0fba2ad
LG		 763 .name = "wm8580-hifi-capture",
764 .id = WM8580_DAI_PAIFTX,
e88ba015
MB		 765 .capture = {
766 .stream_name = "Capture",
767 .channels_min = 2,
768 .channels_max = 2,
769 .rates = SNDRV_PCM_RATE_8000_192000,
770 .formats = WM8580_FORMATS,
771 },
6335d055 772 .ops = &wm8580_dai_ops_capture,
e88ba015
MB		 773 },
774};
e88ba015 775
f0fba2ad 776static int wm8580_probe(struct snd_soc_codec *codec)
e88ba015 777{
f0fba2ad
LG		 778 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
779 int ret = 0,i;
6f7cb44b 780
f0fba2ad
LG		 781 codec->control_data = wm8580->control_data;
782 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
f6f1eb10
MB		 783 if (ret < 0) {
784 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
f0fba2ad 785 return ret;
f6f1eb10
MB		 786 }
787
a583cd53
MB		 788 for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
789 wm8580->supplies[i].supply = wm8580_supply_names[i];
790
791 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
792 wm8580->supplies);
793 if (ret != 0) {
794 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
f0fba2ad 795 return ret;
a583cd53
MB		 796 }
797
798 ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
799 wm8580->supplies);
800 if (ret != 0) {
801 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
802 goto err_regulator_get;
803 }
804
6f7cb44b 805 /* Get the codec into a known state */
f6f1eb10 806 ret = snd_soc_write(codec, WM8580_RESET, 0);
6f7cb44b
MB		 807 if (ret != 0) {
808 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
a583cd53 809 goto err_regulator_enable;
6f7cb44b
MB		 810 }
811
6f7cb44b 812 wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
e88ba015 813
f0fba2ad
LG		 814 snd_soc_add_controls(codec, wm8580_snd_controls,
815 ARRAY_SIZE(wm8580_snd_controls));
816 wm8580_add_widgets(codec);
6f7cb44b
MB		 817
818 return 0;
819
a583cd53
MB		 820err_regulator_enable:
821 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
822err_regulator_get:
823 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
6f7cb44b
MB		 824 return ret;
825}
826
f0fba2ad
LG		 827/* power down chip */
828static int wm8580_remove(struct snd_soc_codec *codec)
6f7cb44b 829{
f0fba2ad
LG		 830 struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
831
832 wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
833
a583cd53
MB		 834 regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
835 regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
f0fba2ad
LG		 836
837 return 0;
6f7cb44b
MB		 838}
839
f0fba2ad
LG		 840static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
841 .probe = wm8580_probe,
842 .remove = wm8580_remove,
843 .set_bias_level = wm8580_set_bias_level,
844 .reg_cache_size = sizeof(wm8580_reg),
845 .reg_word_size = sizeof(u16),
846 .reg_cache_default = &wm8580_reg,
847};
848
6f7cb44b 849#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
17be5522
JD		 850static int wm8580_i2c_probe(struct i2c_client *i2c,
851 const struct i2c_device_id *id)
e88ba015 852{
6f7cb44b 853 struct wm8580_priv *wm8580;
f0fba2ad 854 int ret;
6f7cb44b
MB		 855
856 wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
857 if (wm8580 == NULL)
858 return -ENOMEM;
859
6f7cb44b 860 i2c_set_clientdata(i2c, wm8580);
f0fba2ad
LG		 861 wm8580->control_data = i2c;
862 wm8580->control_type = SND_SOC_I2C;
6f7cb44b 863
f0fba2ad
LG		 864 ret = snd_soc_register_codec(&i2c->dev,
865 &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
866 if (ret < 0)
867 kfree(wm8580);
868 return ret;
e88ba015
MB		 869}
870
17be5522 871static int wm8580_i2c_remove(struct i2c_client *client)
e88ba015 872{
f0fba2ad
LG		 873 snd_soc_unregister_codec(&client->dev);
874 kfree(i2c_get_clientdata(client));
e88ba015
MB		 875 return 0;
876}
877
17be5522
JD		 878static const struct i2c_device_id wm8580_i2c_id[] = {
879 { "wm8580", 0 },
880 { }
881};
882MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
e88ba015 883
e88ba015
MB		 884static struct i2c_driver wm8580_i2c_driver = {
885 .driver = {
f0fba2ad 886 .name = "wm8580-codec",
e88ba015
MB		 887 .owner = THIS_MODULE,
888 },
17be5522
JD		 889 .probe = wm8580_i2c_probe,
890 .remove = wm8580_i2c_remove,
891 .id_table = wm8580_i2c_id,
e88ba015 892};
6f7cb44b 893#endif
e88ba015 894
6f7cb44b 895static int __init wm8580_modinit(void)
17be5522 896{
f0fba2ad 897 int ret = 0;
17be5522 898
6f7cb44b 899#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
17be5522
JD		 900 ret = i2c_add_driver(&wm8580_i2c_driver);
901 if (ret != 0) {
6f7cb44b 902 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
e88ba015 903 }
e88ba015 904#endif
e88ba015 905
f0fba2ad 906 return ret;
e88ba015 907}
64089b84
MB		 908module_init(wm8580_modinit);
909
910static void __exit wm8580_exit(void)
911{
6f7cb44b
MB		 912#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
913 i2c_del_driver(&wm8580_i2c_driver);
914#endif
64089b84
MB		 915}
916module_exit(wm8580_exit);
917
e88ba015
MB		 918MODULE_DESCRIPTION("ASoC WM8580 driver");
919MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
920MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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