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Merge tag 'xfs-for-linus-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / sound / soc / codecs / wm8737.c
CommitLineData
2a9ae13a
MB		 1/*
2 * wm8737.c -- WM8737 ALSA SoC Audio driver
3 *
4 * Copyright 2010 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/i2c.h>
3ef8ac0d 19#include <linux/regmap.h>
2a9ae13a
MB		 20#include <linux/regulator/consumer.h>
21#include <linux/spi/spi.h>
22#include <linux/slab.h>
53a5a83d 23#include <linux/of_device.h>
2a9ae13a
MB		 24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
28#include <sound/soc-dapm.h>
29#include <sound/initval.h>
30#include <sound/tlv.h>
31
32#include "wm8737.h"
33
34#define WM8737_NUM_SUPPLIES 4
35static const char *wm8737_supply_names[WM8737_NUM_SUPPLIES] = {
36 "DCVDD",
37 "DBVDD",
38 "AVDD",
39 "MVDD",
40};
41
42/* codec private data */
43struct wm8737_priv {
3ef8ac0d 44 struct regmap *regmap;
2a9ae13a
MB		 45 struct regulator_bulk_data supplies[WM8737_NUM_SUPPLIES];
46 unsigned int mclk;
47};
48
3ef8ac0d
MB		 49static const struct reg_default wm8737_reg_defaults[] = {
50 { 0, 0x00C3 }, /* R0 - Left PGA volume */
51 { 1, 0x00C3 }, /* R1 - Right PGA volume */
52 { 2, 0x0007 }, /* R2 - AUDIO path L */
53 { 3, 0x0007 }, /* R3 - AUDIO path R */
54 { 4, 0x0000 }, /* R4 - 3D Enhance */
55 { 5, 0x0000 }, /* R5 - ADC Control */
56 { 6, 0x0000 }, /* R6 - Power Management */
57 { 7, 0x000A }, /* R7 - Audio Format */
58 { 8, 0x0000 }, /* R8 - Clocking */
59 { 9, 0x000F }, /* R9 - MIC Preamp Control */
60 { 10, 0x0003 }, /* R10 - Misc Bias Control */
61 { 11, 0x0000 }, /* R11 - Noise Gate */
62 { 12, 0x007C }, /* R12 - ALC1 */
63 { 13, 0x0000 }, /* R13 - ALC2 */
64 { 14, 0x0032 }, /* R14 - ALC3 */
2a9ae13a
MB		 65};
66
3ef8ac0d
MB		 67static bool wm8737_volatile(struct device *dev, unsigned int reg)
68{
69 switch (reg) {
70 case WM8737_RESET:
71 return true;
72 default:
73 return false;
74 }
75}
76
2a9ae13a
MB		 77static int wm8737_reset(struct snd_soc_codec *codec)
78{
79 return snd_soc_write(codec, WM8737_RESET, 0);
80}
81
82static const unsigned int micboost_tlv[] = {
83 TLV_DB_RANGE_HEAD(4),
84 0, 0, TLV_DB_SCALE_ITEM(1300, 0, 0),
85 1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
86 2, 2, TLV_DB_SCALE_ITEM(2800, 0, 0),
87 3, 3, TLV_DB_SCALE_ITEM(3300, 0, 0),
88};
89static const DECLARE_TLV_DB_SCALE(pga_tlv, -9750, 50, 1);
90static const DECLARE_TLV_DB_SCALE(adc_tlv, -600, 600, 0);
91static const DECLARE_TLV_DB_SCALE(ng_tlv, -7800, 600, 0);
fcd02e26
MB		 92static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -1200, 600, 0);
93static const DECLARE_TLV_DB_SCALE(alc_target_tlv, -1800, 100, 0);
2a9ae13a
MB		 94
95static const char *micbias_enum_text[] = {
96 "25%",
97 "50%",
98 "75%",
99 "100%",
100};
101
ca275811
TI		 102static SOC_ENUM_SINGLE_DECL(micbias_enum,
103 WM8737_MIC_PREAMP_CONTROL, 0, micbias_enum_text);
2a9ae13a
MB		 104
105static const char *low_cutoff_text[] = {
106 "Low", "High"
107};
108
ca275811
TI		 109static SOC_ENUM_SINGLE_DECL(low_3d,
110 WM8737_3D_ENHANCE, 6, low_cutoff_text);
2a9ae13a
MB		 111
112static const char *high_cutoff_text[] = {
113 "High", "Low"
114};
115
ca275811
TI		 116static SOC_ENUM_SINGLE_DECL(high_3d,
117 WM8737_3D_ENHANCE, 5, high_cutoff_text);
2a9ae13a 118
fcd02e26
MB		 119static const char *alc_fn_text[] = {
120 "Disabled", "Right", "Left", "Stereo"
121};
122
ca275811
TI		 123static SOC_ENUM_SINGLE_DECL(alc_fn,
124 WM8737_ALC1, 7, alc_fn_text);
fcd02e26
MB		 125
126static const char *alc_hold_text[] = {
127 "0", "2.67ms", "5.33ms", "10.66ms", "21.32ms", "42.64ms", "85.28ms",
128 "170.56ms", "341.12ms", "682.24ms", "1.364s", "2.728s", "5.458s",
129 "10.916s", "21.832s", "43.691s"
130};
131
ca275811
TI		 132static SOC_ENUM_SINGLE_DECL(alc_hold,
133 WM8737_ALC2, 0, alc_hold_text);
fcd02e26
MB		 134
135static const char *alc_atk_text[] = {
136 "8.4ms", "16.8ms", "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms",
137 "1.075s", "2.15s", "4.3s", "8.6s"
138};
139
ca275811
TI		 140static SOC_ENUM_SINGLE_DECL(alc_atk,
141 WM8737_ALC3, 0, alc_atk_text);
fcd02e26
MB		 142
143static const char *alc_dcy_text[] = {
144 "33.6ms", "67.2ms", "134.4ms", "268.8ms", "537.6ms", "1.075s", "2.15s",
145 "4.3s", "8.6s", "17.2s", "34.41s"
146};
147
ca275811
TI		 148static SOC_ENUM_SINGLE_DECL(alc_dcy,
149 WM8737_ALC3, 4, alc_dcy_text);
fcd02e26 150
2a9ae13a
MB		 151static const struct snd_kcontrol_new wm8737_snd_controls[] = {
152SOC_DOUBLE_R_TLV("Mic Boost Volume", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
153 6, 3, 0, micboost_tlv),
154SOC_DOUBLE_R("Mic Boost Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
155 4, 1, 0),
156SOC_DOUBLE("Mic ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
157 3, 1, 0),
158
159SOC_DOUBLE_R_TLV("Capture Volume", WM8737_LEFT_PGA_VOLUME,
160 WM8737_RIGHT_PGA_VOLUME, 0, 255, 0, pga_tlv),
161SOC_DOUBLE("Capture ZC Switch", WM8737_AUDIO_PATH_L, WM8737_AUDIO_PATH_R,
162 2, 1, 0),
163
164SOC_DOUBLE("INPUT1 DC Bias Switch", WM8737_MISC_BIAS_CONTROL, 0, 1, 1, 0),
165
166SOC_ENUM("Mic PGA Bias", micbias_enum),
167SOC_SINGLE("ADC Low Power Switch", WM8737_ADC_CONTROL, 2, 1, 0),
168SOC_SINGLE("High Pass Filter Switch", WM8737_ADC_CONTROL, 0, 1, 1),
169SOC_DOUBLE("Polarity Invert Switch", WM8737_ADC_CONTROL, 5, 6, 1, 0),
170
171SOC_SINGLE("3D Switch", WM8737_3D_ENHANCE, 0, 1, 0),
172SOC_SINGLE("3D Depth", WM8737_3D_ENHANCE, 1, 15, 0),
173SOC_ENUM("3D Low Cut-off", low_3d),
174SOC_ENUM("3D High Cut-off", low_3d),
175SOC_SINGLE_TLV("3D ADC Volume", WM8737_3D_ENHANCE, 7, 1, 1, adc_tlv),
176
177SOC_SINGLE("Noise Gate Switch", WM8737_NOISE_GATE, 0, 1, 0),
178SOC_SINGLE_TLV("Noise Gate Threshold Volume", WM8737_NOISE_GATE, 2, 7, 0,
179 ng_tlv),
fcd02e26
MB		 180
181SOC_ENUM("ALC", alc_fn),
182SOC_SINGLE_TLV("ALC Max Gain Volume", WM8737_ALC1, 4, 7, 0, alc_max_tlv),
183SOC_SINGLE_TLV("ALC Target Volume", WM8737_ALC1, 0, 15, 0, alc_target_tlv),
184SOC_ENUM("ALC Hold Time", alc_hold),
185SOC_SINGLE("ALC ZC Switch", WM8737_ALC2, 4, 1, 0),
186SOC_ENUM("ALC Attack Time", alc_atk),
187SOC_ENUM("ALC Decay Time", alc_dcy),
2a9ae13a
MB		 188};
189
190static const char *linsel_text[] = {
191 "LINPUT1", "LINPUT2", "LINPUT3", "LINPUT1 DC",
192};
193
ca275811
TI		 194static SOC_ENUM_SINGLE_DECL(linsel_enum,
195 WM8737_AUDIO_PATH_L, 7, linsel_text);
2a9ae13a
MB		 196
197static const struct snd_kcontrol_new linsel_mux =
198 SOC_DAPM_ENUM("LINSEL", linsel_enum);
199
200
201static const char *rinsel_text[] = {
202 "RINPUT1", "RINPUT2", "RINPUT3", "RINPUT1 DC",
203};
204
ca275811
TI		 205static SOC_ENUM_SINGLE_DECL(rinsel_enum,
206 WM8737_AUDIO_PATH_R, 7, rinsel_text);
2a9ae13a
MB		 207
208static const struct snd_kcontrol_new rinsel_mux =
209 SOC_DAPM_ENUM("RINSEL", rinsel_enum);
210
211static const char *bypass_text[] = {
212 "Direct", "Preamp"
213};
214
ca275811
TI		 215static SOC_ENUM_SINGLE_DECL(lbypass_enum,
216 WM8737_MIC_PREAMP_CONTROL, 2, bypass_text);
2a9ae13a
MB		 217
218static const struct snd_kcontrol_new lbypass_mux =
219 SOC_DAPM_ENUM("Left Bypass", lbypass_enum);
220
221
ca275811
TI		 222static SOC_ENUM_SINGLE_DECL(rbypass_enum,
223 WM8737_MIC_PREAMP_CONTROL, 3, bypass_text);
2a9ae13a
MB		 224
225static const struct snd_kcontrol_new rbypass_mux =
226 SOC_DAPM_ENUM("Left Bypass", rbypass_enum);
227
228static const struct snd_soc_dapm_widget wm8737_dapm_widgets[] = {
229SND_SOC_DAPM_INPUT("LINPUT1"),
230SND_SOC_DAPM_INPUT("LINPUT2"),
231SND_SOC_DAPM_INPUT("LINPUT3"),
232SND_SOC_DAPM_INPUT("RINPUT1"),
233SND_SOC_DAPM_INPUT("RINPUT2"),
234SND_SOC_DAPM_INPUT("RINPUT3"),
235SND_SOC_DAPM_INPUT("LACIN"),
236SND_SOC_DAPM_INPUT("RACIN"),
237
238SND_SOC_DAPM_MUX("LINSEL", SND_SOC_NOPM, 0, 0, &linsel_mux),
239SND_SOC_DAPM_MUX("RINSEL", SND_SOC_NOPM, 0, 0, &rinsel_mux),
240
241SND_SOC_DAPM_MUX("Left Preamp Mux", SND_SOC_NOPM, 0, 0, &lbypass_mux),
242SND_SOC_DAPM_MUX("Right Preamp Mux", SND_SOC_NOPM, 0, 0, &rbypass_mux),
243
244SND_SOC_DAPM_PGA("PGAL", WM8737_POWER_MANAGEMENT, 5, 0, NULL, 0),
245SND_SOC_DAPM_PGA("PGAR", WM8737_POWER_MANAGEMENT, 4, 0, NULL, 0),
246
247SND_SOC_DAPM_DAC("ADCL", NULL, WM8737_POWER_MANAGEMENT, 3, 0),
248SND_SOC_DAPM_DAC("ADCR", NULL, WM8737_POWER_MANAGEMENT, 2, 0),
249
250SND_SOC_DAPM_AIF_OUT("AIF", "Capture", 0, WM8737_POWER_MANAGEMENT, 6, 0),
251};
252
253static const struct snd_soc_dapm_route intercon[] = {
254 { "LINSEL", "LINPUT1", "LINPUT1" },
255 { "LINSEL", "LINPUT2", "LINPUT2" },
256 { "LINSEL", "LINPUT3", "LINPUT3" },
257 { "LINSEL", "LINPUT1 DC", "LINPUT1" },
258
259 { "RINSEL", "RINPUT1", "RINPUT1" },
260 { "RINSEL", "RINPUT2", "RINPUT2" },
261 { "RINSEL", "RINPUT3", "RINPUT3" },
262 { "RINSEL", "RINPUT1 DC", "RINPUT1" },
263
264 { "Left Preamp Mux", "Preamp", "LINSEL" },
265 { "Left Preamp Mux", "Direct", "LACIN" },
266
267 { "Right Preamp Mux", "Preamp", "RINSEL" },
268 { "Right Preamp Mux", "Direct", "RACIN" },
269
270 { "PGAL", NULL, "Left Preamp Mux" },
271 { "PGAR", NULL, "Right Preamp Mux" },
272
273 { "ADCL", NULL, "PGAL" },
274 { "ADCR", NULL, "PGAR" },
275
276 { "AIF", NULL, "ADCL" },
277 { "AIF", NULL, "ADCR" },
278};
279
2a9ae13a
MB		 280/* codec mclk clock divider coefficients */
281static const struct {
282 u32 mclk;
283 u32 rate;
284 u8 usb;
285 u8 sr;
286} coeff_div[] = {
287 { 12288000, 8000, 0, 0x4 },
288 { 12288000, 12000, 0, 0x8 },
289 { 12288000, 16000, 0, 0xa },
290 { 12288000, 24000, 0, 0x1c },
291 { 12288000, 32000, 0, 0xc },
292 { 12288000, 48000, 0, 0 },
293 { 12288000, 96000, 0, 0xe },
294
295 { 11289600, 8000, 0, 0x14 },
296 { 11289600, 11025, 0, 0x18 },
297 { 11289600, 22050, 0, 0x1a },
298 { 11289600, 44100, 0, 0x10 },
299 { 11289600, 88200, 0, 0x1e },
300
301 { 18432000, 8000, 0, 0x5 },
302 { 18432000, 12000, 0, 0x9 },
303 { 18432000, 16000, 0, 0xb },
304 { 18432000, 24000, 0, 0x1b },
305 { 18432000, 32000, 0, 0xd },
306 { 18432000, 48000, 0, 0x1 },
307 { 18432000, 96000, 0, 0x1f },
308
309 { 16934400, 8000, 0, 0x15 },
310 { 16934400, 11025, 0, 0x19 },
311 { 16934400, 22050, 0, 0x1b },
312 { 16934400, 44100, 0, 0x11 },
313 { 16934400, 88200, 0, 0x1f },
314
315 { 12000000, 8000, 1, 0x4 },
316 { 12000000, 11025, 1, 0x19 },
317 { 12000000, 12000, 1, 0x8 },
318 { 12000000, 16000, 1, 0xa },
319 { 12000000, 22050, 1, 0x1b },
320 { 12000000, 24000, 1, 0x1c },
321 { 12000000, 32000, 1, 0xc },
322 { 12000000, 44100, 1, 0x11 },
323 { 12000000, 48000, 1, 0x0 },
324 { 12000000, 88200, 1, 0x1f },
325 { 12000000, 96000, 1, 0xe },
326};
327
328static int wm8737_hw_params(struct snd_pcm_substream *substream,
329 struct snd_pcm_hw_params *params,
330 struct snd_soc_dai *dai)
331{
e6968a17 332 struct snd_soc_codec *codec = dai->codec;
2a9ae13a
MB		 333 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
334 int i;
335 u16 clocking = 0;
336 u16 af = 0;
337
338 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
339 if (coeff_div[i].rate != params_rate(params))
340 continue;
341
342 if (coeff_div[i].mclk == wm8737->mclk)
343 break;
344
345 if (coeff_div[i].mclk == wm8737->mclk * 2) {
346 clocking |= WM8737_CLKDIV2;
347 break;
348 }
349 }
350
351 if (i == ARRAY_SIZE(coeff_div)) {
352 dev_err(codec->dev, "%dHz MCLK can't support %dHz\n",
353 wm8737->mclk, params_rate(params));
354 return -EINVAL;
355 }
356
357 clocking |= coeff_div[i].usb | (coeff_div[i].sr << WM8737_SR_SHIFT);
358
a5d0de23
MB		 359 switch (params_width(params)) {
360 case 16:
2a9ae13a 361 break;
a5d0de23 362 case 20:
2a9ae13a
MB		 363 af |= 0x8;
364 break;
a5d0de23 365 case 24:
2a9ae13a
MB		 366 af |= 0x10;
367 break;
a5d0de23 368 case 32:
2a9ae13a
MB		 369 af |= 0x18;
370 break;
371 default:
372 return -EINVAL;
373 }
374
375 snd_soc_update_bits(codec, WM8737_AUDIO_FORMAT, WM8737_WL_MASK, af);
376 snd_soc_update_bits(codec, WM8737_CLOCKING,
377 WM8737_USB_MODE | WM8737_CLKDIV2 | WM8737_SR_MASK,
378 clocking);
379
380 return 0;
381}
382
383static int wm8737_set_dai_sysclk(struct snd_soc_dai *codec_dai,
384 int clk_id, unsigned int freq, int dir)
385{
386 struct snd_soc_codec *codec = codec_dai->codec;
387 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
388 int i;
389
390 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
391 if (freq == coeff_div[i].mclk ||
392 freq == coeff_div[i].mclk * 2) {
393 wm8737->mclk = freq;
394 return 0;
395 }
396 }
397
398 dev_err(codec->dev, "MCLK rate %dHz not supported\n", freq);
399
400 return -EINVAL;
401}
402
403
404static int wm8737_set_dai_fmt(struct snd_soc_dai *codec_dai,
405 unsigned int fmt)
406{
407 struct snd_soc_codec *codec = codec_dai->codec;
408 u16 af = 0;
409
410 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
411 case SND_SOC_DAIFMT_CBM_CFM:
412 af |= WM8737_MS;
413 break;
414 case SND_SOC_DAIFMT_CBS_CFS:
415 break;
416 default:
417 return -EINVAL;
418 }
419
420 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
421 case SND_SOC_DAIFMT_I2S:
422 af |= 0x2;
423 break;
424 case SND_SOC_DAIFMT_RIGHT_J:
425 break;
426 case SND_SOC_DAIFMT_LEFT_J:
427 af |= 0x1;
428 break;
429 case SND_SOC_DAIFMT_DSP_A:
430 af |= 0x3;
431 break;
432 case SND_SOC_DAIFMT_DSP_B:
433 af |= 0x13;
434 break;
435 default:
436 return -EINVAL;
437 }
438
439 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
440 case SND_SOC_DAIFMT_NB_NF:
441 break;
442 case SND_SOC_DAIFMT_NB_IF:
443 af |= WM8737_LRP;
444 break;
445 default:
446 return -EINVAL;
447 }
448
449 snd_soc_update_bits(codec, WM8737_AUDIO_FORMAT,
450 WM8737_FORMAT_MASK | WM8737_LRP | WM8737_MS, af);
451
452 return 0;
453}
454
455static int wm8737_set_bias_level(struct snd_soc_codec *codec,
456 enum snd_soc_bias_level level)
457{
458 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
459 int ret;
460
461 switch (level) {
462 case SND_SOC_BIAS_ON:
463 break;
464
465 case SND_SOC_BIAS_PREPARE:
466 /* VMID at 2*75k */
467 snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL,
468 WM8737_VMIDSEL_MASK, 0);
469 break;
470
471 case SND_SOC_BIAS_STANDBY:
472 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
473 ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
474 wm8737->supplies);
475 if (ret != 0) {
476 dev_err(codec->dev,
477 "Failed to enable supplies: %d\n",
478 ret);
479 return ret;
480 }
481
3ef8ac0d 482 regcache_sync(wm8737->regmap);
2a9ae13a
MB		 483
484 /* Fast VMID ramp at 2*2.5k */
485 snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL,
486 WM8737_VMIDSEL_MASK, 0x4);
487
488 /* Bring VMID up */
489 snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT,
490 WM8737_VMID_MASK |
491 WM8737_VREF_MASK,
492 WM8737_VMID_MASK |
493 WM8737_VREF_MASK);
494
495 msleep(500);
496 }
497
498 /* VMID at 2*300k */
499 snd_soc_update_bits(codec, WM8737_MISC_BIAS_CONTROL,
500 WM8737_VMIDSEL_MASK, 2);
501
502 break;
503
504 case SND_SOC_BIAS_OFF:
505 snd_soc_update_bits(codec, WM8737_POWER_MANAGEMENT,
506 WM8737_VMID_MASK | WM8737_VREF_MASK, 0);
507
508 regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies),
509 wm8737->supplies);
510 break;
511 }
512
513 codec->dapm.bias_level = level;
514 return 0;
515}
516
517#define WM8737_RATES SNDRV_PCM_RATE_8000_96000
518
519#define WM8737_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
520 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
521
85e7652d 522static const struct snd_soc_dai_ops wm8737_dai_ops = {
2a9ae13a
MB		 523 .hw_params = wm8737_hw_params,
524 .set_sysclk = wm8737_set_dai_sysclk,
525 .set_fmt = wm8737_set_dai_fmt,
526};
527
528static struct snd_soc_dai_driver wm8737_dai = {
529 .name = "wm8737",
530 .capture = {
531 .stream_name = "Capture",
532 .channels_min = 2, /* Mono modes not yet supported */
533 .channels_max = 2,
534 .rates = WM8737_RATES,
535 .formats = WM8737_FORMATS,
536 },
537 .ops = &wm8737_dai_ops,
538};
539
2a9ae13a
MB		 540static int wm8737_probe(struct snd_soc_codec *codec)
541{
542 struct wm8737_priv *wm8737 = snd_soc_codec_get_drvdata(codec);
4f69bb31 543 int ret;
2a9ae13a 544
2a9ae13a
MB		 545 ret = regulator_bulk_enable(ARRAY_SIZE(wm8737->supplies),
546 wm8737->supplies);
547 if (ret != 0) {
548 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
549 goto err_get;
550 }
551
552 ret = wm8737_reset(codec);
553 if (ret < 0) {
554 dev_err(codec->dev, "Failed to issue reset\n");
555 goto err_enable;
556 }
557
558 snd_soc_update_bits(codec, WM8737_LEFT_PGA_VOLUME, WM8737_LVU,
559 WM8737_LVU);
560 snd_soc_update_bits(codec, WM8737_RIGHT_PGA_VOLUME, WM8737_RVU,
561 WM8737_RVU);
562
563 wm8737_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
564
565 /* Bias level configuration will have done an extra enable */
566 regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
567
2a9ae13a
MB		 568 return 0;
569
570err_enable:
571 regulator_bulk_disable(ARRAY_SIZE(wm8737->supplies), wm8737->supplies);
572err_get:
2a9ae13a
MB		 573 return ret;
574}
575
2a9ae13a
MB		 576static struct snd_soc_codec_driver soc_codec_dev_wm8737 = {
577 .probe = wm8737_probe,
2a9ae13a 578 .set_bias_level = wm8737_set_bias_level,
67cac3a3 579 .suspend_bias_off = true,
a6bf3069
LPC		 580
581 .controls = wm8737_snd_controls,
582 .num_controls = ARRAY_SIZE(wm8737_snd_controls),
583 .dapm_widgets = wm8737_dapm_widgets,
584 .num_dapm_widgets = ARRAY_SIZE(wm8737_dapm_widgets),
585 .dapm_routes = intercon,
586 .num_dapm_routes = ARRAY_SIZE(intercon),
2a9ae13a
MB		 587};
588
53a5a83d
MB		 589static const struct of_device_id wm8737_of_match[] = {
590 { .compatible = "wlf,wm8737", },
591 { }
592};
593
594MODULE_DEVICE_TABLE(of, wm8737_of_match);
595
3ef8ac0d
MB		 596static const struct regmap_config wm8737_regmap = {
597 .reg_bits = 7,
598 .val_bits = 9,
599 .max_register = WM8737_MAX_REGISTER,
600
601 .reg_defaults = wm8737_reg_defaults,
602 .num_reg_defaults = ARRAY_SIZE(wm8737_reg_defaults),
603 .cache_type = REGCACHE_RBTREE,
604
605 .volatile_reg = wm8737_volatile,
606};
607
1037d567 608#if IS_ENABLED(CONFIG_I2C)
7a79e94e
BP		 609static int wm8737_i2c_probe(struct i2c_client *i2c,
610 const struct i2c_device_id *id)
2a9ae13a
MB		 611{
612 struct wm8737_priv *wm8737;
4f69bb31 613 int ret, i;
2a9ae13a 614
65fdd9bf
MB		 615 wm8737 = devm_kzalloc(&i2c->dev, sizeof(struct wm8737_priv),
616 GFP_KERNEL);
2a9ae13a
MB		 617 if (wm8737 == NULL)
618 return -ENOMEM;
619
4f69bb31
MB		 620 for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++)
621 wm8737->supplies[i].supply = wm8737_supply_names[i];
622
623 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8737->supplies),
624 wm8737->supplies);
625 if (ret != 0) {
626 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
627 return ret;
628 }
629
3ef8ac0d
MB		 630 wm8737->regmap = devm_regmap_init_i2c(i2c, &wm8737_regmap);
631 if (IS_ERR(wm8737->regmap))
632 return PTR_ERR(wm8737->regmap);
633
2a9ae13a 634 i2c_set_clientdata(i2c, wm8737);
2a9ae13a
MB		 635
636 ret = snd_soc_register_codec(&i2c->dev,
637 &soc_codec_dev_wm8737, &wm8737_dai, 1);
65fdd9bf 638
2a9ae13a
MB		 639 return ret;
640
641}
642
7a79e94e 643static int wm8737_i2c_remove(struct i2c_client *client)
2a9ae13a
MB		 644{
645 snd_soc_unregister_codec(&client->dev);
65fdd9bf 646
2a9ae13a
MB		 647 return 0;
648}
649
650static const struct i2c_device_id wm8737_i2c_id[] = {
651 { "wm8737", 0 },
652 { }
653};
654MODULE_DEVICE_TABLE(i2c, wm8737_i2c_id);
655
656static struct i2c_driver wm8737_i2c_driver = {
657 .driver = {
658 .name = "wm8737",
659 .owner = THIS_MODULE,
53a5a83d 660 .of_match_table = wm8737_of_match,
2a9ae13a
MB		 661 },
662 .probe = wm8737_i2c_probe,
7a79e94e 663 .remove = wm8737_i2c_remove,
2a9ae13a
MB		 664 .id_table = wm8737_i2c_id,
665};
666#endif
667
668#if defined(CONFIG_SPI_MASTER)
7a79e94e 669static int wm8737_spi_probe(struct spi_device *spi)
2a9ae13a
MB		 670{
671 struct wm8737_priv *wm8737;
4f69bb31 672 int ret, i;
2a9ae13a 673
65fdd9bf
MB		 674 wm8737 = devm_kzalloc(&spi->dev, sizeof(struct wm8737_priv),
675 GFP_KERNEL);
2a9ae13a
MB		 676 if (wm8737 == NULL)
677 return -ENOMEM;
678
4f69bb31
MB		 679 for (i = 0; i < ARRAY_SIZE(wm8737->supplies); i++)
680 wm8737->supplies[i].supply = wm8737_supply_names[i];
681
682 ret = devm_regulator_bulk_get(&spi->dev, ARRAY_SIZE(wm8737->supplies),
683 wm8737->supplies);
684 if (ret != 0) {
685 dev_err(&spi->dev, "Failed to request supplies: %d\n", ret);
686 return ret;
687 }
688
3ef8ac0d
MB		 689 wm8737->regmap = devm_regmap_init_spi(spi, &wm8737_regmap);
690 if (IS_ERR(wm8737->regmap))
691 return PTR_ERR(wm8737->regmap);
692
2a9ae13a
MB		 693 spi_set_drvdata(spi, wm8737);
694
695 ret = snd_soc_register_codec(&spi->dev,
696 &soc_codec_dev_wm8737, &wm8737_dai, 1);
65fdd9bf 697
2a9ae13a
MB		 698 return ret;
699}
700
7a79e94e 701static int wm8737_spi_remove(struct spi_device *spi)
2a9ae13a
MB		 702{
703 snd_soc_unregister_codec(&spi->dev);
65fdd9bf 704
2a9ae13a
MB		 705 return 0;
706}
707
708static struct spi_driver wm8737_spi_driver = {
709 .driver = {
710 .name = "wm8737",
711 .owner = THIS_MODULE,
53a5a83d 712 .of_match_table = wm8737_of_match,
2a9ae13a
MB		 713 },
714 .probe = wm8737_spi_probe,
7a79e94e 715 .remove = wm8737_spi_remove,
2a9ae13a
MB		 716};
717#endif /* CONFIG_SPI_MASTER */
718
719static int __init wm8737_modinit(void)
720{
721 int ret;
1037d567 722#if IS_ENABLED(CONFIG_I2C)
2a9ae13a
MB		 723 ret = i2c_add_driver(&wm8737_i2c_driver);
724 if (ret != 0) {
725 printk(KERN_ERR "Failed to register WM8737 I2C driver: %d\n",
726 ret);
727 }
728#endif
729#if defined(CONFIG_SPI_MASTER)
730 ret = spi_register_driver(&wm8737_spi_driver);
731 if (ret != 0) {
732 printk(KERN_ERR "Failed to register WM8737 SPI driver: %d\n",
733 ret);
734 }
735#endif
736 return 0;
737}
738module_init(wm8737_modinit);
739
740static void __exit wm8737_exit(void)
741{
742#if defined(CONFIG_SPI_MASTER)
743 spi_unregister_driver(&wm8737_spi_driver);
744#endif
1037d567 745#if IS_ENABLED(CONFIG_I2C)
2a9ae13a
MB		 746 i2c_del_driver(&wm8737_i2c_driver);
747#endif
748}
749module_exit(wm8737_exit);
750
751MODULE_DESCRIPTION("ASoC WM8737 driver");
752MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
753MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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