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ASoC: One more x86 typo fix
[deliverable/linux.git] / sound / soc / codecs / wm8750.c
CommitLineData
abadfc92
RP		 1/*
2 * wm8750.c -- WM8750 ALSA SoC audio driver
3 *
4 * Copyright 2005 Openedhand Ltd.
5 *
6 * Author: Richard Purdie <richard@openedhand.com>
7 *
8 * Based on WM8753.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/moduleparam.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/pm.h>
20#include <linux/i2c.h>
21#include <linux/platform_device.h>
2f3dfaf5 22#include <linux/spi/spi.h>
5a0e3ad6 23#include <linux/slab.h>
abadfc92
RP		 24#include <sound/core.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc.h>
abadfc92
RP		 28#include <sound/initval.h>
29
30#include "wm8750.h"
31
abadfc92
RP		 32/*
33 * wm8750 register cache
34 * We can't read the WM8750 register space when we
35 * are using 2 wire for device control, so we cache them instead.
36 */
37static const u16 wm8750_reg[] = {
38 0x0097, 0x0097, 0x0079, 0x0079, /* 0 */
39 0x0000, 0x0008, 0x0000, 0x000a, /* 4 */
40 0x0000, 0x0000, 0x00ff, 0x00ff, /* 8 */
41 0x000f, 0x000f, 0x0000, 0x0000, /* 12 */
42 0x0000, 0x007b, 0x0000, 0x0032, /* 16 */
43 0x0000, 0x00c3, 0x00c3, 0x00c0, /* 20 */
44 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
45 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
46 0x0000, 0x0000, 0x0050, 0x0050, /* 32 */
47 0x0050, 0x0050, 0x0050, 0x0050, /* 36 */
48 0x0079, 0x0079, 0x0079, /* 40 */
49};
50
6ca0c22e
MV		 51/* codec private data */
52struct wm8750_priv {
53 unsigned int sysclk;
f0fba2ad 54 enum snd_soc_control_type control_type;
6ca0c22e
MV		 55 u16 reg_cache[ARRAY_SIZE(wm8750_reg)];
56};
57
17a52fd6 58#define wm8750_reset(c) snd_soc_write(c, WM8750_RESET, 0)
abadfc92
RP		 59
60/*
61 * WM8750 Controls
62 */
63static const char *wm8750_bass[] = {"Linear Control", "Adaptive Boost"};
64static const char *wm8750_bass_filter[] = { "130Hz @ 48kHz", "200Hz @ 48kHz" };
65static const char *wm8750_treble[] = {"8kHz", "4kHz"};
66static const char *wm8750_3d_lc[] = {"200Hz", "500Hz"};
67static const char *wm8750_3d_uc[] = {"2.2kHz", "1.5kHz"};
68static const char *wm8750_3d_func[] = {"Capture", "Playback"};
69static const char *wm8750_alc_func[] = {"Off", "Right", "Left", "Stereo"};
70static const char *wm8750_ng_type[] = {"Constant PGA Gain",
71 "Mute ADC Output"};
72static const char *wm8750_line_mux[] = {"Line 1", "Line 2", "Line 3", "PGA",
73 "Differential"};
74static const char *wm8750_pga_sel[] = {"Line 1", "Line 2", "Line 3",
75 "Differential"};
76static const char *wm8750_out3[] = {"VREF", "ROUT1 + Vol", "MonoOut",
77 "ROUT1"};
78static const char *wm8750_diff_sel[] = {"Line 1", "Line 2"};
79static const char *wm8750_adcpol[] = {"Normal", "L Invert", "R Invert",
80 "L + R Invert"};
81static const char *wm8750_deemph[] = {"None", "32Khz", "44.1Khz", "48Khz"};
82static const char *wm8750_mono_mux[] = {"Stereo", "Mono (Left)",
83 "Mono (Right)", "Digital Mono"};
84
85static const struct soc_enum wm8750_enum[] = {
86SOC_ENUM_SINGLE(WM8750_BASS, 7, 2, wm8750_bass),
87SOC_ENUM_SINGLE(WM8750_BASS, 6, 2, wm8750_bass_filter),
88SOC_ENUM_SINGLE(WM8750_TREBLE, 6, 2, wm8750_treble),
89SOC_ENUM_SINGLE(WM8750_3D, 5, 2, wm8750_3d_lc),
90SOC_ENUM_SINGLE(WM8750_3D, 6, 2, wm8750_3d_uc),
91SOC_ENUM_SINGLE(WM8750_3D, 7, 2, wm8750_3d_func),
92SOC_ENUM_SINGLE(WM8750_ALC1, 7, 4, wm8750_alc_func),
93SOC_ENUM_SINGLE(WM8750_NGATE, 1, 2, wm8750_ng_type),
94SOC_ENUM_SINGLE(WM8750_LOUTM1, 0, 5, wm8750_line_mux),
95SOC_ENUM_SINGLE(WM8750_ROUTM1, 0, 5, wm8750_line_mux),
96SOC_ENUM_SINGLE(WM8750_LADCIN, 6, 4, wm8750_pga_sel), /* 10 */
97SOC_ENUM_SINGLE(WM8750_RADCIN, 6, 4, wm8750_pga_sel),
98SOC_ENUM_SINGLE(WM8750_ADCTL2, 7, 4, wm8750_out3),
99SOC_ENUM_SINGLE(WM8750_ADCIN, 8, 2, wm8750_diff_sel),
100SOC_ENUM_SINGLE(WM8750_ADCDAC, 5, 4, wm8750_adcpol),
101SOC_ENUM_SINGLE(WM8750_ADCDAC, 1, 4, wm8750_deemph),
102SOC_ENUM_SINGLE(WM8750_ADCIN, 6, 4, wm8750_mono_mux), /* 16 */
103
104};
105
106static const struct snd_kcontrol_new wm8750_snd_controls[] = {
107
108SOC_DOUBLE_R("Capture Volume", WM8750_LINVOL, WM8750_RINVOL, 0, 63, 0),
109SOC_DOUBLE_R("Capture ZC Switch", WM8750_LINVOL, WM8750_RINVOL, 6, 1, 0),
110SOC_DOUBLE_R("Capture Switch", WM8750_LINVOL, WM8750_RINVOL, 7, 1, 1),
111
bd903b6e 112SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8750_LOUT1V,
abadfc92 113 WM8750_ROUT1V, 7, 1, 0),
bd903b6e 114SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8750_LOUT2V,
abadfc92
RP		 115 WM8750_ROUT2V, 7, 1, 0),
116
117SOC_ENUM("Playback De-emphasis", wm8750_enum[15]),
118
119SOC_ENUM("Capture Polarity", wm8750_enum[14]),
120SOC_SINGLE("Playback 6dB Attenuate", WM8750_ADCDAC, 7, 1, 0),
121SOC_SINGLE("Capture 6dB Attenuate", WM8750_ADCDAC, 8, 1, 0),
122
123SOC_DOUBLE_R("PCM Volume", WM8750_LDAC, WM8750_RDAC, 0, 255, 0),
124
125SOC_ENUM("Bass Boost", wm8750_enum[0]),
126SOC_ENUM("Bass Filter", wm8750_enum[1]),
127SOC_SINGLE("Bass Volume", WM8750_BASS, 0, 15, 1),
128
6a7b8cf4 129SOC_SINGLE("Treble Volume", WM8750_TREBLE, 0, 15, 1),
abadfc92
RP		 130SOC_ENUM("Treble Cut-off", wm8750_enum[2]),
131
132SOC_SINGLE("3D Switch", WM8750_3D, 0, 1, 0),
133SOC_SINGLE("3D Volume", WM8750_3D, 1, 15, 0),
134SOC_ENUM("3D Lower Cut-off", wm8750_enum[3]),
135SOC_ENUM("3D Upper Cut-off", wm8750_enum[4]),
136SOC_ENUM("3D Mode", wm8750_enum[5]),
137
138SOC_SINGLE("ALC Capture Target Volume", WM8750_ALC1, 0, 7, 0),
139SOC_SINGLE("ALC Capture Max Volume", WM8750_ALC1, 4, 7, 0),
140SOC_ENUM("ALC Capture Function", wm8750_enum[6]),
141SOC_SINGLE("ALC Capture ZC Switch", WM8750_ALC2, 7, 1, 0),
142SOC_SINGLE("ALC Capture Hold Time", WM8750_ALC2, 0, 15, 0),
143SOC_SINGLE("ALC Capture Decay Time", WM8750_ALC3, 4, 15, 0),
144SOC_SINGLE("ALC Capture Attack Time", WM8750_ALC3, 0, 15, 0),
145SOC_SINGLE("ALC Capture NG Threshold", WM8750_NGATE, 3, 31, 0),
146SOC_ENUM("ALC Capture NG Type", wm8750_enum[4]),
147SOC_SINGLE("ALC Capture NG Switch", WM8750_NGATE, 0, 1, 0),
148
149SOC_SINGLE("Left ADC Capture Volume", WM8750_LADC, 0, 255, 0),
150SOC_SINGLE("Right ADC Capture Volume", WM8750_RADC, 0, 255, 0),
151
152SOC_SINGLE("ZC Timeout Switch", WM8750_ADCTL1, 0, 1, 0),
153SOC_SINGLE("Playback Invert Switch", WM8750_ADCTL1, 1, 1, 0),
154
bd903b6e 155SOC_SINGLE("Right Speaker Playback Invert Switch", WM8750_ADCTL2, 4, 1, 0),
abadfc92
RP		 156
157/* Unimplemented */
158/* ADCDAC Bit 0 - ADCHPD */
159/* ADCDAC Bit 4 - HPOR */
160/* ADCTL1 Bit 2,3 - DATSEL */
161/* ADCTL1 Bit 4,5 - DMONOMIX */
162/* ADCTL1 Bit 6,7 - VSEL */
163/* ADCTL2 Bit 2 - LRCM */
164/* ADCTL2 Bit 3 - TRI */
165/* ADCTL3 Bit 5 - HPFLREN */
166/* ADCTL3 Bit 6 - VROI */
167/* ADCTL3 Bit 7,8 - ADCLRM */
168/* ADCIN Bit 4 - LDCM */
169/* ADCIN Bit 5 - RDCM */
170
171SOC_DOUBLE_R("Mic Boost", WM8750_LADCIN, WM8750_RADCIN, 4, 3, 0),
172
173SOC_DOUBLE_R("Bypass Left Playback Volume", WM8750_LOUTM1,
174 WM8750_LOUTM2, 4, 7, 1),
175SOC_DOUBLE_R("Bypass Right Playback Volume", WM8750_ROUTM1,
176 WM8750_ROUTM2, 4, 7, 1),
177SOC_DOUBLE_R("Bypass Mono Playback Volume", WM8750_MOUTM1,
178 WM8750_MOUTM2, 4, 7, 1),
179
180SOC_SINGLE("Mono Playback ZC Switch", WM8750_MOUTV, 7, 1, 0),
181
bd903b6e
LG		 182SOC_DOUBLE_R("Headphone Playback Volume", WM8750_LOUT1V, WM8750_ROUT1V,
183 0, 127, 0),
184SOC_DOUBLE_R("Speaker Playback Volume", WM8750_LOUT2V, WM8750_ROUT2V,
185 0, 127, 0),
abadfc92
RP		 186
187SOC_SINGLE("Mono Playback Volume", WM8750_MOUTV, 0, 127, 0),
188
189};
190
abadfc92
RP		 191/*
192 * DAPM Controls
193 */
194
195/* Left Mixer */
196static const struct snd_kcontrol_new wm8750_left_mixer_controls[] = {
197SOC_DAPM_SINGLE("Playback Switch", WM8750_LOUTM1, 8, 1, 0),
198SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_LOUTM1, 7, 1, 0),
199SOC_DAPM_SINGLE("Right Playback Switch", WM8750_LOUTM2, 8, 1, 0),
200SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_LOUTM2, 7, 1, 0),
201};
202
203/* Right Mixer */
204static const struct snd_kcontrol_new wm8750_right_mixer_controls[] = {
205SOC_DAPM_SINGLE("Left Playback Switch", WM8750_ROUTM1, 8, 1, 0),
206SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_ROUTM1, 7, 1, 0),
207SOC_DAPM_SINGLE("Playback Switch", WM8750_ROUTM2, 8, 1, 0),
208SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_ROUTM2, 7, 1, 0),
209};
210
211/* Mono Mixer */
212static const struct snd_kcontrol_new wm8750_mono_mixer_controls[] = {
213SOC_DAPM_SINGLE("Left Playback Switch", WM8750_MOUTM1, 8, 1, 0),
214SOC_DAPM_SINGLE("Left Bypass Switch", WM8750_MOUTM1, 7, 1, 0),
215SOC_DAPM_SINGLE("Right Playback Switch", WM8750_MOUTM2, 8, 1, 0),
216SOC_DAPM_SINGLE("Right Bypass Switch", WM8750_MOUTM2, 7, 1, 0),
217};
218
219/* Left Line Mux */
220static const struct snd_kcontrol_new wm8750_left_line_controls =
221SOC_DAPM_ENUM("Route", wm8750_enum[8]);
222
223/* Right Line Mux */
224static const struct snd_kcontrol_new wm8750_right_line_controls =
225SOC_DAPM_ENUM("Route", wm8750_enum[9]);
226
227/* Left PGA Mux */
228static const struct snd_kcontrol_new wm8750_left_pga_controls =
229SOC_DAPM_ENUM("Route", wm8750_enum[10]);
230
231/* Right PGA Mux */
232static const struct snd_kcontrol_new wm8750_right_pga_controls =
233SOC_DAPM_ENUM("Route", wm8750_enum[11]);
234
235/* Out 3 Mux */
236static const struct snd_kcontrol_new wm8750_out3_controls =
237SOC_DAPM_ENUM("Route", wm8750_enum[12]);
238
239/* Differential Mux */
240static const struct snd_kcontrol_new wm8750_diffmux_controls =
241SOC_DAPM_ENUM("Route", wm8750_enum[13]);
242
243/* Mono ADC Mux */
244static const struct snd_kcontrol_new wm8750_monomux_controls =
245SOC_DAPM_ENUM("Route", wm8750_enum[16]);
246
247static const struct snd_soc_dapm_widget wm8750_dapm_widgets[] = {
248 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
249 &wm8750_left_mixer_controls[0],
250 ARRAY_SIZE(wm8750_left_mixer_controls)),
251 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
252 &wm8750_right_mixer_controls[0],
253 ARRAY_SIZE(wm8750_right_mixer_controls)),
254 SND_SOC_DAPM_MIXER("Mono Mixer", WM8750_PWR2, 2, 0,
255 &wm8750_mono_mixer_controls[0],
256 ARRAY_SIZE(wm8750_mono_mixer_controls)),
257
258 SND_SOC_DAPM_PGA("Right Out 2", WM8750_PWR2, 3, 0, NULL, 0),
259 SND_SOC_DAPM_PGA("Left Out 2", WM8750_PWR2, 4, 0, NULL, 0),
260 SND_SOC_DAPM_PGA("Right Out 1", WM8750_PWR2, 5, 0, NULL, 0),
261 SND_SOC_DAPM_PGA("Left Out 1", WM8750_PWR2, 6, 0, NULL, 0),
262 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8750_PWR2, 7, 0),
263 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8750_PWR2, 8, 0),
264
265 SND_SOC_DAPM_MICBIAS("Mic Bias", WM8750_PWR1, 1, 0),
266 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8750_PWR1, 2, 0),
267 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8750_PWR1, 3, 0),
268
269 SND_SOC_DAPM_MUX("Left PGA Mux", WM8750_PWR1, 5, 0,
270 &wm8750_left_pga_controls),
271 SND_SOC_DAPM_MUX("Right PGA Mux", WM8750_PWR1, 4, 0,
272 &wm8750_right_pga_controls),
273 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
274 &wm8750_left_line_controls),
275 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
276 &wm8750_right_line_controls),
277
278 SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8750_out3_controls),
279 SND_SOC_DAPM_PGA("Out 3", WM8750_PWR2, 1, 0, NULL, 0),
280 SND_SOC_DAPM_PGA("Mono Out 1", WM8750_PWR2, 2, 0, NULL, 0),
281
282 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
283 &wm8750_diffmux_controls),
284 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
285 &wm8750_monomux_controls),
286 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
287 &wm8750_monomux_controls),
288
289 SND_SOC_DAPM_OUTPUT("LOUT1"),
290 SND_SOC_DAPM_OUTPUT("ROUT1"),
291 SND_SOC_DAPM_OUTPUT("LOUT2"),
292 SND_SOC_DAPM_OUTPUT("ROUT2"),
23ba79bd 293 SND_SOC_DAPM_OUTPUT("MONO1"),
abadfc92 294 SND_SOC_DAPM_OUTPUT("OUT3"),
04489eeb 295 SND_SOC_DAPM_OUTPUT("VREF"),
abadfc92
RP		 296
297 SND_SOC_DAPM_INPUT("LINPUT1"),
298 SND_SOC_DAPM_INPUT("LINPUT2"),
299 SND_SOC_DAPM_INPUT("LINPUT3"),
300 SND_SOC_DAPM_INPUT("RINPUT1"),
301 SND_SOC_DAPM_INPUT("RINPUT2"),
302 SND_SOC_DAPM_INPUT("RINPUT3"),
303};
304
a65f0568 305static const struct snd_soc_dapm_route audio_map[] = {
abadfc92
RP		 306 /* left mixer */
307 {"Left Mixer", "Playback Switch", "Left DAC"},
308 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
309 {"Left Mixer", "Right Playback Switch", "Right DAC"},
310 {"Left Mixer", "Right Bypass Switch", "Right Line Mux"},
311
312 /* right mixer */
313 {"Right Mixer", "Left Playback Switch", "Left DAC"},
314 {"Right Mixer", "Left Bypass Switch", "Left Line Mux"},
315 {"Right Mixer", "Playback Switch", "Right DAC"},
316 {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
317
318 /* left out 1 */
319 {"Left Out 1", NULL, "Left Mixer"},
320 {"LOUT1", NULL, "Left Out 1"},
321
322 /* left out 2 */
323 {"Left Out 2", NULL, "Left Mixer"},
324 {"LOUT2", NULL, "Left Out 2"},
325
326 /* right out 1 */
327 {"Right Out 1", NULL, "Right Mixer"},
328 {"ROUT1", NULL, "Right Out 1"},
329
330 /* right out 2 */
331 {"Right Out 2", NULL, "Right Mixer"},
332 {"ROUT2", NULL, "Right Out 2"},
333
334 /* mono mixer */
335 {"Mono Mixer", "Left Playback Switch", "Left DAC"},
336 {"Mono Mixer", "Left Bypass Switch", "Left Line Mux"},
337 {"Mono Mixer", "Right Playback Switch", "Right DAC"},
338 {"Mono Mixer", "Right Bypass Switch", "Right Line Mux"},
339
340 /* mono out */
341 {"Mono Out 1", NULL, "Mono Mixer"},
342 {"MONO1", NULL, "Mono Out 1"},
343
344 /* out 3 */
345 {"Out3 Mux", "VREF", "VREF"},
346 {"Out3 Mux", "ROUT1 + Vol", "ROUT1"},
347 {"Out3 Mux", "ROUT1", "Right Mixer"},
348 {"Out3 Mux", "MonoOut", "MONO1"},
349 {"Out 3", NULL, "Out3 Mux"},
350 {"OUT3", NULL, "Out 3"},
351
352 /* Left Line Mux */
353 {"Left Line Mux", "Line 1", "LINPUT1"},
354 {"Left Line Mux", "Line 2", "LINPUT2"},
355 {"Left Line Mux", "Line 3", "LINPUT3"},
356 {"Left Line Mux", "PGA", "Left PGA Mux"},
357 {"Left Line Mux", "Differential", "Differential Mux"},
358
359 /* Right Line Mux */
360 {"Right Line Mux", "Line 1", "RINPUT1"},
361 {"Right Line Mux", "Line 2", "RINPUT2"},
362 {"Right Line Mux", "Line 3", "RINPUT3"},
363 {"Right Line Mux", "PGA", "Right PGA Mux"},
364 {"Right Line Mux", "Differential", "Differential Mux"},
365
366 /* Left PGA Mux */
367 {"Left PGA Mux", "Line 1", "LINPUT1"},
368 {"Left PGA Mux", "Line 2", "LINPUT2"},
369 {"Left PGA Mux", "Line 3", "LINPUT3"},
370 {"Left PGA Mux", "Differential", "Differential Mux"},
371
372 /* Right PGA Mux */
373 {"Right PGA Mux", "Line 1", "RINPUT1"},
374 {"Right PGA Mux", "Line 2", "RINPUT2"},
375 {"Right PGA Mux", "Line 3", "RINPUT3"},
376 {"Right PGA Mux", "Differential", "Differential Mux"},
377
378 /* Differential Mux */
379 {"Differential Mux", "Line 1", "LINPUT1"},
380 {"Differential Mux", "Line 1", "RINPUT1"},
381 {"Differential Mux", "Line 2", "LINPUT2"},
382 {"Differential Mux", "Line 2", "RINPUT2"},
383
384 /* Left ADC Mux */
385 {"Left ADC Mux", "Stereo", "Left PGA Mux"},
386 {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
387 {"Left ADC Mux", "Digital Mono", "Left PGA Mux"},
388
389 /* Right ADC Mux */
390 {"Right ADC Mux", "Stereo", "Right PGA Mux"},
391 {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
392 {"Right ADC Mux", "Digital Mono", "Right PGA Mux"},
393
394 /* ADC */
395 {"Left ADC", NULL, "Left ADC Mux"},
396 {"Right ADC", NULL, "Right ADC Mux"},
abadfc92
RP		 397};
398
399static int wm8750_add_widgets(struct snd_soc_codec *codec)
400{
ce6120cc 401 struct snd_soc_dapm_context *dapm = &codec->dapm;
abadfc92 402
ce6120cc
LG		 403 snd_soc_dapm_new_controls(dapm, wm8750_dapm_widgets,
404 ARRAY_SIZE(wm8750_dapm_widgets));
405 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
abadfc92 406
abadfc92
RP		 407 return 0;
408}
409
410struct _coeff_div {
411 u32 mclk;
412 u32 rate;
413 u16 fs;
414 u8 sr:5;
415 u8 usb:1;
416};
417
418/* codec hifi mclk clock divider coefficients */
419static const struct _coeff_div coeff_div[] = {
420 /* 8k */
421 {12288000, 8000, 1536, 0x6, 0x0},
422 {11289600, 8000, 1408, 0x16, 0x0},
423 {18432000, 8000, 2304, 0x7, 0x0},
424 {16934400, 8000, 2112, 0x17, 0x0},
425 {12000000, 8000, 1500, 0x6, 0x1},
426
427 /* 11.025k */
428 {11289600, 11025, 1024, 0x18, 0x0},
429 {16934400, 11025, 1536, 0x19, 0x0},
430 {12000000, 11025, 1088, 0x19, 0x1},
431
432 /* 16k */
433 {12288000, 16000, 768, 0xa, 0x0},
434 {18432000, 16000, 1152, 0xb, 0x0},
435 {12000000, 16000, 750, 0xa, 0x1},
436
437 /* 22.05k */
438 {11289600, 22050, 512, 0x1a, 0x0},
439 {16934400, 22050, 768, 0x1b, 0x0},
440 {12000000, 22050, 544, 0x1b, 0x1},
441
442 /* 32k */
443 {12288000, 32000, 384, 0xc, 0x0},
444 {18432000, 32000, 576, 0xd, 0x0},
445 {12000000, 32000, 375, 0xa, 0x1},
446
447 /* 44.1k */
448 {11289600, 44100, 256, 0x10, 0x0},
449 {16934400, 44100, 384, 0x11, 0x0},
450 {12000000, 44100, 272, 0x11, 0x1},
451
452 /* 48k */
453 {12288000, 48000, 256, 0x0, 0x0},
454 {18432000, 48000, 384, 0x1, 0x0},
455 {12000000, 48000, 250, 0x0, 0x1},
456
457 /* 88.2k */
458 {11289600, 88200, 128, 0x1e, 0x0},
459 {16934400, 88200, 192, 0x1f, 0x0},
460 {12000000, 88200, 136, 0x1f, 0x1},
461
462 /* 96k */
463 {12288000, 96000, 128, 0xe, 0x0},
464 {18432000, 96000, 192, 0xf, 0x0},
465 {12000000, 96000, 125, 0xe, 0x1},
466};
467
468static inline int get_coeff(int mclk, int rate)
469{
470 int i;
471
472 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
473 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
474 return i;
475 }
a71a468a
LG		 476
477 printk(KERN_ERR "wm8750: could not get coeff for mclk %d @ rate %d\n",
478 mclk, rate);
abadfc92
RP		 479 return -EINVAL;
480}
481
e550e17f 482static int wm8750_set_dai_sysclk(struct snd_soc_dai *codec_dai,
4422b606 483 int clk_id, unsigned int freq, int dir)
abadfc92 484{
4422b606 485 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 486 struct wm8750_priv *wm8750 = snd_soc_codec_get_drvdata(codec);
4422b606
LG		 487
488 switch (freq) {
489 case 11289600:
490 case 12000000:
491 case 12288000:
492 case 16934400:
493 case 18432000:
494 wm8750->sysclk = freq;
495 return 0;
496 }
497 return -EINVAL;
abadfc92
RP		 498}
499
e550e17f 500static int wm8750_set_dai_fmt(struct snd_soc_dai *codec_dai,
4422b606 501 unsigned int fmt)
abadfc92 502{
4422b606
LG		 503 struct snd_soc_codec *codec = codec_dai->codec;
504 u16 iface = 0;
abadfc92
RP		 505
506 /* set master/slave audio interface */
4422b606 507 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
abadfc92
RP		 508 case SND_SOC_DAIFMT_CBM_CFM:
509 iface = 0x0040;
510 break;
511 case SND_SOC_DAIFMT_CBS_CFS:
512 break;
4422b606
LG		 513 default:
514 return -EINVAL;
abadfc92
RP		 515 }
516
517 /* interface format */
4422b606 518 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
abadfc92
RP		 519 case SND_SOC_DAIFMT_I2S:
520 iface |= 0x0002;
521 break;
522 case SND_SOC_DAIFMT_RIGHT_J:
523 break;
524 case SND_SOC_DAIFMT_LEFT_J:
525 iface |= 0x0001;
526 break;
527 case SND_SOC_DAIFMT_DSP_A:
528 iface |= 0x0003;
529 break;
530 case SND_SOC_DAIFMT_DSP_B:
531 iface |= 0x0013;
532 break;
4422b606
LG		 533 default:
534 return -EINVAL;
abadfc92
RP		 535 }
536
537 /* clock inversion */
4422b606 538 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
abadfc92
RP		 539 case SND_SOC_DAIFMT_NB_NF:
540 break;
541 case SND_SOC_DAIFMT_IB_IF:
542 iface |= 0x0090;
543 break;
544 case SND_SOC_DAIFMT_IB_NF:
545 iface |= 0x0080;
546 break;
547 case SND_SOC_DAIFMT_NB_IF:
548 iface |= 0x0010;
549 break;
4422b606
LG		 550 default:
551 return -EINVAL;
abadfc92
RP		 552 }
553
17a52fd6 554 snd_soc_write(codec, WM8750_IFACE, iface);
4422b606
LG		 555 return 0;
556}
557
558static int wm8750_pcm_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 559 struct snd_pcm_hw_params *params,
560 struct snd_soc_dai *dai)
4422b606
LG		 561{
562 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 563 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 564 struct wm8750_priv *wm8750 = snd_soc_codec_get_drvdata(codec);
17a52fd6
MB		 565 u16 iface = snd_soc_read(codec, WM8750_IFACE) & 0x1f3;
566 u16 srate = snd_soc_read(codec, WM8750_SRATE) & 0x1c0;
4422b606
LG		 567 int coeff = get_coeff(wm8750->sysclk, params_rate(params));
568
569 /* bit size */
570 switch (params_format(params)) {
571 case SNDRV_PCM_FORMAT_S16_LE:
abadfc92 572 break;
4422b606
LG		 573 case SNDRV_PCM_FORMAT_S20_3LE:
574 iface |= 0x0004;
abadfc92 575 break;
4422b606
LG		 576 case SNDRV_PCM_FORMAT_S24_LE:
577 iface |= 0x0008;
abadfc92 578 break;
4422b606
LG		 579 case SNDRV_PCM_FORMAT_S32_LE:
580 iface |= 0x000c;
abadfc92
RP		 581 break;
582 }
583
584 /* set iface & srate */
17a52fd6 585 snd_soc_write(codec, WM8750_IFACE, iface);
4422b606 586 if (coeff >= 0)
17a52fd6 587 snd_soc_write(codec, WM8750_SRATE, srate |
4422b606 588 (coeff_div[coeff].sr << 1) | coeff_div[coeff].usb);
abadfc92
RP		 589
590 return 0;
591}
592
e550e17f 593static int wm8750_mute(struct snd_soc_dai *dai, int mute)
abadfc92 594{
4422b606 595 struct snd_soc_codec *codec = dai->codec;
17a52fd6 596 u16 mute_reg = snd_soc_read(codec, WM8750_ADCDAC) & 0xfff7;
4422b606 597
abadfc92 598 if (mute)
17a52fd6 599 snd_soc_write(codec, WM8750_ADCDAC, mute_reg | 0x8);
abadfc92 600 else
17a52fd6 601 snd_soc_write(codec, WM8750_ADCDAC, mute_reg);
abadfc92
RP		 602 return 0;
603}
604
0be9898a
MB		 605static int wm8750_set_bias_level(struct snd_soc_codec *codec,
606 enum snd_soc_bias_level level)
abadfc92 607{
17a52fd6 608 u16 pwr_reg = snd_soc_read(codec, WM8750_PWR1) & 0xfe3e;
abadfc92 609
0be9898a
MB		 610 switch (level) {
611 case SND_SOC_BIAS_ON:
abadfc92 612 /* set vmid to 50k and unmute dac */
17a52fd6 613 snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x00c0);
abadfc92 614 break;
0be9898a 615 case SND_SOC_BIAS_PREPARE:
abadfc92 616 break;
0be9898a 617 case SND_SOC_BIAS_STANDBY:
ce6120cc 618 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
dd76769d
MB		 619 /* Set VMID to 5k */
620 snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x01c1);
621
622 /* ...and ramp */
623 msleep(1000);
624 }
625
abadfc92 626 /* mute dac and set vmid to 500k, enable VREF */
17a52fd6 627 snd_soc_write(codec, WM8750_PWR1, pwr_reg | 0x0141);
abadfc92 628 break;
0be9898a 629 case SND_SOC_BIAS_OFF:
17a52fd6 630 snd_soc_write(codec, WM8750_PWR1, 0x0001);
abadfc92
RP		 631 break;
632 }
ce6120cc 633 codec->dapm.bias_level = level;
abadfc92
RP		 634 return 0;
635}
636
4422b606 637#define WM8750_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
42f3030f
MB		 638 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
639 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
4422b606
LG		 640
641#define WM8750_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
642 SNDRV_PCM_FMTBIT_S24_LE)
643
6335d055
EM		 644static struct snd_soc_dai_ops wm8750_dai_ops = {
645 .hw_params = wm8750_pcm_hw_params,
646 .digital_mute = wm8750_mute,
647 .set_fmt = wm8750_set_dai_fmt,
648 .set_sysclk = wm8750_set_dai_sysclk,
649};
650
f0fba2ad
LG		 651static struct snd_soc_dai_driver wm8750_dai = {
652 .name = "wm8750-hifi",
abadfc92
RP		 653 .playback = {
654 .stream_name = "Playback",
655 .channels_min = 1,
656 .channels_max = 2,
4422b606
LG		 657 .rates = WM8750_RATES,
658 .formats = WM8750_FORMATS,},
abadfc92
RP		 659 .capture = {
660 .stream_name = "Capture",
661 .channels_min = 1,
662 .channels_max = 2,
4422b606
LG		 663 .rates = WM8750_RATES,
664 .formats = WM8750_FORMATS,},
6335d055 665 .ops = &wm8750_dai_ops,
abadfc92 666};
abadfc92 667
f0fba2ad 668static int wm8750_suspend(struct snd_soc_codec *codec, pm_message_t state)
abadfc92 669{
0be9898a 670 wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
abadfc92
RP		 671 return 0;
672}
673
f0fba2ad 674static int wm8750_resume(struct snd_soc_codec *codec)
abadfc92 675{
abadfc92
RP		 676 int i;
677 u8 data[2];
678 u16 *cache = codec->reg_cache;
679
680 /* Sync reg_cache with the hardware */
681 for (i = 0; i < ARRAY_SIZE(wm8750_reg); i++) {
682 if (i == WM8750_RESET)
683 continue;
684 data[0] = (i << 1) | ((cache[i] >> 8) & 0x0001);
685 data[1] = cache[i] & 0x00ff;
686 codec->hw_write(codec->control_data, data, 2);
687 }
688
0be9898a 689 wm8750_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
abadfc92 690
abadfc92
RP		 691 return 0;
692}
693
f0fba2ad 694static int wm8750_probe(struct snd_soc_codec *codec)
6ca0c22e 695{
f0fba2ad
LG		 696 struct wm8750_priv *wm8750 = snd_soc_codec_get_drvdata(codec);
697 int reg, ret;
abadfc92 698
f0fba2ad 699 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8750->control_type);
17a52fd6
MB		 700 if (ret < 0) {
701 printk(KERN_ERR "wm8750: failed to set cache I/O: %d\n", ret);
f0fba2ad 702 return ret;
17a52fd6
MB		 703 }
704
705 ret = wm8750_reset(codec);
706 if (ret < 0) {
707 printk(KERN_ERR "wm8750: failed to reset: %d\n", ret);
f0fba2ad 708 return ret;
17a52fd6 709 }
abadfc92 710
abadfc92 711 /* charge output caps */
dd76769d 712 wm8750_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
abadfc92
RP		 713
714 /* set the update bits */
17a52fd6
MB		 715 reg = snd_soc_read(codec, WM8750_LDAC);
716 snd_soc_write(codec, WM8750_LDAC, reg | 0x0100);
717 reg = snd_soc_read(codec, WM8750_RDAC);
718 snd_soc_write(codec, WM8750_RDAC, reg | 0x0100);
719 reg = snd_soc_read(codec, WM8750_LOUT1V);
720 snd_soc_write(codec, WM8750_LOUT1V, reg | 0x0100);
721 reg = snd_soc_read(codec, WM8750_ROUT1V);
722 snd_soc_write(codec, WM8750_ROUT1V, reg | 0x0100);
723 reg = snd_soc_read(codec, WM8750_LOUT2V);
724 snd_soc_write(codec, WM8750_LOUT2V, reg | 0x0100);
725 reg = snd_soc_read(codec, WM8750_ROUT2V);
726 snd_soc_write(codec, WM8750_ROUT2V, reg | 0x0100);
727 reg = snd_soc_read(codec, WM8750_LINVOL);
728 snd_soc_write(codec, WM8750_LINVOL, reg | 0x0100);
729 reg = snd_soc_read(codec, WM8750_RINVOL);
730 snd_soc_write(codec, WM8750_RINVOL, reg | 0x0100);
abadfc92 731
f0fba2ad
LG		 732 snd_soc_add_controls(codec, wm8750_snd_controls,
733 ARRAY_SIZE(wm8750_snd_controls));
734 wm8750_add_widgets(codec);
abadfc92
RP		 735 return ret;
736}
737
f0fba2ad 738static int wm8750_remove(struct snd_soc_codec *codec)
6ca0c22e 739{
f0fba2ad
LG		 740 wm8750_set_bias_level(codec, SND_SOC_BIAS_OFF);
741 return 0;
6ca0c22e 742}
abadfc92 743
f0fba2ad
LG		 744static struct snd_soc_codec_driver soc_codec_dev_wm8750 = {
745 .probe = wm8750_probe,
746 .remove = wm8750_remove,
747 .suspend = wm8750_suspend,
748 .resume = wm8750_resume,
749 .set_bias_level = wm8750_set_bias_level,
e5eec34c 750 .reg_cache_size = ARRAY_SIZE(wm8750_reg),
f0fba2ad
LG		 751 .reg_word_size = sizeof(u16),
752 .reg_cache_default = wm8750_reg,
753};
abadfc92 754
f0fba2ad
LG		 755#if defined(CONFIG_SPI_MASTER)
756static int __devinit wm8750_spi_probe(struct spi_device *spi)
abadfc92 757{
6ca0c22e 758 struct wm8750_priv *wm8750;
f0fba2ad 759 int ret;
abadfc92 760
6ca0c22e
MV		 761 wm8750 = kzalloc(sizeof(struct wm8750_priv), GFP_KERNEL);
762 if (wm8750 == NULL)
763 return -ENOMEM;
abadfc92 764
f0fba2ad
LG		 765 wm8750->control_type = SND_SOC_SPI;
766 spi_set_drvdata(spi, wm8750);
abadfc92 767
f0fba2ad
LG		 768 ret = snd_soc_register_codec(&spi->dev,
769 &soc_codec_dev_wm8750, &wm8750_dai, 1);
770 if (ret < 0)
771 kfree(wm8750);
772 return ret;
abadfc92
RP		 773}
774
f0fba2ad 775static int __devexit wm8750_spi_remove(struct spi_device *spi)
abadfc92 776{
f0fba2ad
LG		 777 snd_soc_unregister_codec(&spi->dev);
778 kfree(spi_get_drvdata(spi));
abadfc92
RP		 779 return 0;
780}
781
f0fba2ad 782static struct spi_driver wm8750_spi_driver = {
abadfc92 783 .driver = {
f0fba2ad 784 .name = "wm8750-codec",
f0fba2ad 785 .owner = THIS_MODULE,
abadfc92 786 },
f0fba2ad
LG		 787 .probe = wm8750_spi_probe,
788 .remove = __devexit_p(wm8750_spi_remove),
abadfc92 789};
f0fba2ad 790#endif /* CONFIG_SPI_MASTER */
abadfc92 791
f0fba2ad
LG		 792#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
793static __devinit int wm8750_i2c_probe(struct i2c_client *i2c,
794 const struct i2c_device_id *id)
2f3dfaf5 795{
6ca0c22e 796 struct wm8750_priv *wm8750;
f0fba2ad 797 int ret;
2f3dfaf5 798
6ca0c22e
MV		 799 wm8750 = kzalloc(sizeof(struct wm8750_priv), GFP_KERNEL);
800 if (wm8750 == NULL)
801 return -ENOMEM;
2f3dfaf5 802
f0fba2ad 803 i2c_set_clientdata(i2c, wm8750);
f0fba2ad 804 wm8750->control_type = SND_SOC_I2C;
2f3dfaf5 805
f0fba2ad
LG		 806 ret = snd_soc_register_codec(&i2c->dev,
807 &soc_codec_dev_wm8750, &wm8750_dai, 1);
808 if (ret < 0)
809 kfree(wm8750);
810 return ret;
2f3dfaf5
MB		 811}
812
f0fba2ad 813static __devexit int wm8750_i2c_remove(struct i2c_client *client)
2f3dfaf5 814{
f0fba2ad
LG		 815 snd_soc_unregister_codec(&client->dev);
816 kfree(i2c_get_clientdata(client));
2f3dfaf5
MB		 817 return 0;
818}
819
f0fba2ad 820static const struct i2c_device_id wm8750_i2c_id[] = {
0d9c15e4
MC		 821 { "wm8750", 0 },
822 { "wm8987", 0 },
823 { }
824};
f0fba2ad 825MODULE_DEVICE_TABLE(i2c, wm8750_i2c_id);
0d9c15e4 826
f0fba2ad 827static struct i2c_driver wm8750_i2c_driver = {
2f3dfaf5 828 .driver = {
f0fba2ad
LG		 829 .name = "wm8750-codec",
830 .owner = THIS_MODULE,
2f3dfaf5 831 },
f0fba2ad
LG		 832 .probe = wm8750_i2c_probe,
833 .remove = __devexit_p(wm8750_i2c_remove),
834 .id_table = wm8750_i2c_id,
2f3dfaf5 835};
2f3dfaf5
MB		 836#endif
837
6ca0c22e 838static int __init wm8750_modinit(void)
abadfc92 839{
f0fba2ad 840 int ret = 0;
42f3030f 841#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
6ca0c22e 842 ret = i2c_add_driver(&wm8750_i2c_driver);
f0fba2ad
LG		 843 if (ret != 0) {
844 printk(KERN_ERR "Failed to register wm8750 I2C driver: %d\n",
845 ret);
846 }
abadfc92 847#endif
2f3dfaf5 848#if defined(CONFIG_SPI_MASTER)
6ca0c22e 849 ret = spi_register_driver(&wm8750_spi_driver);
f0fba2ad
LG		 850 if (ret != 0) {
851 printk(KERN_ERR "Failed to register wm8750 SPI driver: %d\n",
852 ret);
853 }
2f3dfaf5 854#endif
f0fba2ad 855 return ret;
4422b606 856}
6ca0c22e 857module_init(wm8750_modinit);
4422b606 858
6ca0c22e 859static void __exit wm8750_exit(void)
abadfc92 860{
42f3030f 861#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
abadfc92 862 i2c_del_driver(&wm8750_i2c_driver);
2f3dfaf5
MB		 863#endif
864#if defined(CONFIG_SPI_MASTER)
865 spi_unregister_driver(&wm8750_spi_driver);
abadfc92 866#endif
64089b84
MB		 867}
868module_exit(wm8750_exit);
869
abadfc92
RP		 870MODULE_DESCRIPTION("ASoC WM8750 driver");
871MODULE_AUTHOR("Liam Girdwood");
872MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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