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ASoC: Tegra I2S: Use devm_ APIs and module_platform_driver
[deliverable/linux.git] / sound / soc / codecs / wm8753.c
CommitLineData
1f53aee0
LG		 1/*
2 * wm8753.c -- WM8753 ALSA Soc Audio driver
3 *
4 * Copyright 2003 Wolfson Microelectronics PLC.
d331124d 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
1f53aee0
LG		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * Notes:
13 * The WM8753 is a low power, high quality stereo codec with integrated PCM
14 * codec designed for portable digital telephony applications.
15 *
16 * Dual DAI:-
17 *
18 * This driver support 2 DAI PCM's. This makes the default PCM available for
19 * HiFi audio (e.g. MP3, ogg) playback/capture and the other PCM available for
20 * voice.
21 *
22 * Please note that the voice PCM can be connected directly to a Bluetooth
23 * codec or GSM modem and thus cannot be read or written to, although it is
24 * available to be configured with snd_hw_params(), etc and kcontrols in the
25 * normal alsa manner.
26 *
27 * Fast DAI switching:-
28 *
29 * The driver can now fast switch between the DAI configurations via a
30 * an alsa kcontrol. This allows the PCM to remain open.
31 *
32 */
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
1f53aee0
LG		 36#include <linux/kernel.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
70e14122 41#include <linux/of_device.h>
1f53aee0 42#include <linux/platform_device.h>
dd0c0c80 43#include <linux/spi/spi.h>
5a0e3ad6 44#include <linux/slab.h>
1f53aee0
LG		 45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
1f53aee0 49#include <sound/initval.h>
2d6a4ac9 50#include <sound/tlv.h>
1f53aee0
LG		 51#include <asm/div64.h>
52
53#include "wm8753.h"
54
1f53aee0
LG		 55static int caps_charge = 2000;
56module_param(caps_charge, int, 0);
57MODULE_PARM_DESC(caps_charge, "WM8753 cap charge time (msecs)");
58
338ee253
LPC		 59static int wm8753_hifi_write_dai_fmt(struct snd_soc_codec *codec,
60 unsigned int fmt);
61static int wm8753_voice_write_dai_fmt(struct snd_soc_codec *codec,
62 unsigned int fmt);
1f53aee0 63
1f53aee0
LG		 64/*
65 * wm8753 register cache
66 * We can't read the WM8753 register space when we
67 * are using 2 wire for device control, so we cache them instead.
68 */
69static const u16 wm8753_reg[] = {
776065e3
LPC		 70 0x0000, 0x0008, 0x0000, 0x000a,
71 0x000a, 0x0033, 0x0000, 0x0007,
72 0x00ff, 0x00ff, 0x000f, 0x000f,
73 0x007b, 0x0000, 0x0032, 0x0000,
74 0x00c3, 0x00c3, 0x00c0, 0x0000,
1f53aee0
LG		 75 0x0000, 0x0000, 0x0000, 0x0000,
76 0x0000, 0x0000, 0x0000, 0x0000,
1f53aee0 77 0x0000, 0x0000, 0x0000, 0x0000,
776065e3
LPC		 78 0x0055, 0x0005, 0x0050, 0x0055,
79 0x0050, 0x0055, 0x0050, 0x0055,
80 0x0079, 0x0079, 0x0079, 0x0079,
81 0x0079, 0x0000, 0x0000, 0x0000,
82 0x0000, 0x0097, 0x0097, 0x0000,
83 0x0004, 0x0000, 0x0083, 0x0024,
84 0x01ba, 0x0000, 0x0083, 0x0024,
85 0x01ba, 0x0000, 0x0000, 0x0000
1f53aee0
LG		 86};
87
c2bac160
MB		 88/* codec private data */
89struct wm8753_priv {
f0fba2ad 90 enum snd_soc_control_type control_type;
c2bac160
MB		 91 unsigned int sysclk;
92 unsigned int pcmclk;
338ee253
LPC		 93
94 unsigned int voice_fmt;
95 unsigned int hifi_fmt;
96
f0fba2ad 97 int dai_func;
c2bac160
MB		 98};
99
776065e3 100#define wm8753_reset(c) snd_soc_write(c, WM8753_RESET, 0)
1f53aee0
LG		 101
102/*
103 * WM8753 Controls
104 */
105static const char *wm8753_base[] = {"Linear Control", "Adaptive Boost"};
106static const char *wm8753_base_filter[] =
107 {"130Hz @ 48kHz", "200Hz @ 48kHz", "100Hz @ 16kHz", "400Hz @ 48kHz",
108 "100Hz @ 8kHz", "200Hz @ 8kHz"};
109static const char *wm8753_treble[] = {"8kHz", "4kHz"};
110static const char *wm8753_alc_func[] = {"Off", "Right", "Left", "Stereo"};
111static const char *wm8753_ng_type[] = {"Constant PGA Gain", "Mute ADC Output"};
112static const char *wm8753_3d_func[] = {"Capture", "Playback"};
113static const char *wm8753_3d_uc[] = {"2.2kHz", "1.5kHz"};
114static const char *wm8753_3d_lc[] = {"200Hz", "500Hz"};
115static const char *wm8753_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz"};
116static const char *wm8753_mono_mix[] = {"Stereo", "Left", "Right", "Mono"};
117static const char *wm8753_dac_phase[] = {"Non Inverted", "Inverted"};
118static const char *wm8753_line_mix[] = {"Line 1 + 2", "Line 1 - 2",
119 "Line 1", "Line 2"};
120static const char *wm8753_mono_mux[] = {"Line Mix", "Rx Mix"};
121static const char *wm8753_right_mux[] = {"Line 2", "Rx Mix"};
122static const char *wm8753_left_mux[] = {"Line 1", "Rx Mix"};
123static const char *wm8753_rxmsel[] = {"RXP - RXN", "RXP + RXN", "RXP", "RXN"};
124static const char *wm8753_sidetone_mux[] = {"Left PGA", "Mic 1", "Mic 2",
125 "Right PGA"};
126static const char *wm8753_mono2_src[] = {"Inverted Mono 1", "Left", "Right",
127 "Left + Right"};
128static const char *wm8753_out3[] = {"VREF", "ROUT2", "Left + Right"};
129static const char *wm8753_out4[] = {"VREF", "Capture ST", "LOUT2"};
130static const char *wm8753_radcsel[] = {"PGA", "Line or RXP-RXN", "Sidetone"};
131static const char *wm8753_ladcsel[] = {"PGA", "Line or RXP-RXN", "Line"};
132static const char *wm8753_mono_adc[] = {"Stereo", "Analogue Mix Left",
133 "Analogue Mix Right", "Digital Mono Mix"};
134static const char *wm8753_adc_hp[] = {"3.4Hz @ 48kHz", "82Hz @ 16k",
135 "82Hz @ 8kHz", "170Hz @ 8kHz"};
136static const char *wm8753_adc_filter[] = {"HiFi", "Voice"};
137static const char *wm8753_mic_sel[] = {"Mic 1", "Mic 2", "Mic 3"};
138static const char *wm8753_dai_mode[] = {"DAI 0", "DAI 1", "DAI 2", "DAI 3"};
139static const char *wm8753_dat_sel[] = {"Stereo", "Left ADC", "Right ADC",
140 "Channel Swap"};
ae092c9e 141static const char *wm8753_rout2_phase[] = {"Non Inverted", "Inverted"};
1f53aee0
LG		 142
143static const struct soc_enum wm8753_enum[] = {
144SOC_ENUM_SINGLE(WM8753_BASS, 7, 2, wm8753_base),
145SOC_ENUM_SINGLE(WM8753_BASS, 4, 6, wm8753_base_filter),
146SOC_ENUM_SINGLE(WM8753_TREBLE, 6, 2, wm8753_treble),
147SOC_ENUM_SINGLE(WM8753_ALC1, 7, 4, wm8753_alc_func),
148SOC_ENUM_SINGLE(WM8753_NGATE, 1, 2, wm8753_ng_type),
149SOC_ENUM_SINGLE(WM8753_3D, 7, 2, wm8753_3d_func),
150SOC_ENUM_SINGLE(WM8753_3D, 6, 2, wm8753_3d_uc),
151SOC_ENUM_SINGLE(WM8753_3D, 5, 2, wm8753_3d_lc),
152SOC_ENUM_SINGLE(WM8753_DAC, 1, 4, wm8753_deemp),
153SOC_ENUM_SINGLE(WM8753_DAC, 4, 4, wm8753_mono_mix),
154SOC_ENUM_SINGLE(WM8753_DAC, 6, 2, wm8753_dac_phase),
155SOC_ENUM_SINGLE(WM8753_INCTL1, 3, 4, wm8753_line_mix),
156SOC_ENUM_SINGLE(WM8753_INCTL1, 2, 2, wm8753_mono_mux),
157SOC_ENUM_SINGLE(WM8753_INCTL1, 1, 2, wm8753_right_mux),
158SOC_ENUM_SINGLE(WM8753_INCTL1, 0, 2, wm8753_left_mux),
159SOC_ENUM_SINGLE(WM8753_INCTL2, 6, 4, wm8753_rxmsel),
160SOC_ENUM_SINGLE(WM8753_INCTL2, 4, 4, wm8753_sidetone_mux),
161SOC_ENUM_SINGLE(WM8753_OUTCTL, 7, 4, wm8753_mono2_src),
162SOC_ENUM_SINGLE(WM8753_OUTCTL, 0, 3, wm8753_out3),
163SOC_ENUM_SINGLE(WM8753_ADCTL2, 7, 3, wm8753_out4),
164SOC_ENUM_SINGLE(WM8753_ADCIN, 2, 3, wm8753_radcsel),
165SOC_ENUM_SINGLE(WM8753_ADCIN, 0, 3, wm8753_ladcsel),
166SOC_ENUM_SINGLE(WM8753_ADCIN, 4, 4, wm8753_mono_adc),
167SOC_ENUM_SINGLE(WM8753_ADC, 2, 4, wm8753_adc_hp),
168SOC_ENUM_SINGLE(WM8753_ADC, 4, 2, wm8753_adc_filter),
169SOC_ENUM_SINGLE(WM8753_MICBIAS, 6, 3, wm8753_mic_sel),
170SOC_ENUM_SINGLE(WM8753_IOCTL, 2, 4, wm8753_dai_mode),
171SOC_ENUM_SINGLE(WM8753_ADC, 7, 4, wm8753_dat_sel),
ae092c9e 172SOC_ENUM_SINGLE(WM8753_OUTCTL, 2, 2, wm8753_rout2_phase),
1f53aee0
LG		 173};
174
175
176static int wm8753_get_dai(struct snd_kcontrol *kcontrol,
177 struct snd_ctl_elem_value *ucontrol)
178{
179 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
338ee253 180 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0 181
338ee253 182 ucontrol->value.integer.value[0] = wm8753->dai_func;
1f53aee0
LG		 183 return 0;
184}
185
186static int wm8753_set_dai(struct snd_kcontrol *kcontrol,
187 struct snd_ctl_elem_value *ucontrol)
188{
189 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
f0fba2ad 190 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
338ee253
LPC		 191 u16 ioctl;
192
2391a0e0
TJL		 193 if (wm8753->dai_func == ucontrol->value.integer.value[0])
194 return 0;
195
338ee253
LPC		 196 if (codec->active)
197 return -EBUSY;
198
199 ioctl = snd_soc_read(codec, WM8753_IOCTL);
200
201 wm8753->dai_func = ucontrol->value.integer.value[0];
202
203 if (((ioctl >> 2) & 0x3) == wm8753->dai_func)
204 return 1;
205
206 ioctl = (ioctl & 0x1f3) | (wm8753->dai_func << 2);
207 snd_soc_write(codec, WM8753_IOCTL, ioctl);
1f53aee0 208
1f53aee0 209
338ee253
LPC		 210 wm8753_hifi_write_dai_fmt(codec, wm8753->hifi_fmt);
211 wm8753_voice_write_dai_fmt(codec, wm8753->voice_fmt);
1f53aee0 212
1f53aee0
LG		 213 return 1;
214}
215
2cc8c609
MM		 216static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 300, 0);
217static const DECLARE_TLV_DB_SCALE(mic_preamp_tlv, 1200, 600, 0);
218static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
219static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
220static const unsigned int out_tlv[] = {
221 TLV_DB_RANGE_HEAD(2),
222 /* 0000000 - 0101111 = "Analogue mute" */
223 0, 48, TLV_DB_SCALE_ITEM(-25500, 0, 0),
224 48, 127, TLV_DB_SCALE_ITEM(-7300, 100, 0),
225};
226static const DECLARE_TLV_DB_SCALE(mix_tlv, -1500, 300, 0);
227static const DECLARE_TLV_DB_SCALE(voice_mix_tlv, -1200, 300, 0);
228static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
2d6a4ac9 229
1f53aee0 230static const struct snd_kcontrol_new wm8753_snd_controls[] = {
2cc8c609
MM		 231SOC_DOUBLE_R_TLV("PCM Volume", WM8753_LDAC, WM8753_RDAC, 0, 255, 0, dac_tlv),
232
233SOC_DOUBLE_R_TLV("ADC Capture Volume", WM8753_LADC, WM8753_RADC, 0, 255, 0,
234 adc_tlv),
235
236SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8753_LOUT1V, WM8753_ROUT1V,
237 0, 127, 0, out_tlv),
238SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8753_LOUT2V, WM8753_ROUT2V, 0,
239 127, 0, out_tlv),
240
241SOC_SINGLE_TLV("Mono Playback Volume", WM8753_MOUTV, 0, 127, 0, out_tlv),
242
243SOC_DOUBLE_R_TLV("Bypass Playback Volume", WM8753_LOUTM1, WM8753_ROUTM1, 4, 7,
244 1, mix_tlv),
245SOC_DOUBLE_R_TLV("Sidetone Playback Volume", WM8753_LOUTM2, WM8753_ROUTM2, 4,
246 7, 1, mix_tlv),
247SOC_DOUBLE_R_TLV("Voice Playback Volume", WM8753_LOUTM2, WM8753_ROUTM2, 0, 7,
248 1, voice_mix_tlv),
249
250SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8753_LOUT1V, WM8753_ROUT1V, 7,
251 1, 0),
252SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8753_LOUT2V, WM8753_ROUT2V, 7,
253 1, 0),
254
255SOC_SINGLE_TLV("Mono Bypass Playback Volume", WM8753_MOUTM1, 4, 7, 1, mix_tlv),
256SOC_SINGLE_TLV("Mono Sidetone Playback Volume", WM8753_MOUTM2, 4, 7, 1,
257 mix_tlv),
258SOC_SINGLE_TLV("Mono Voice Playback Volume", WM8753_MOUTM2, 0, 7, 1,
259 voice_mix_tlv),
1f53aee0
LG		 260SOC_SINGLE("Mono Playback ZC Switch", WM8753_MOUTV, 7, 1, 0),
261
262SOC_ENUM("Bass Boost", wm8753_enum[0]),
263SOC_ENUM("Bass Filter", wm8753_enum[1]),
264SOC_SINGLE("Bass Volume", WM8753_BASS, 0, 15, 1),
265
266SOC_SINGLE("Treble Volume", WM8753_TREBLE, 0, 15, 1),
267SOC_ENUM("Treble Cut-off", wm8753_enum[2]),
268
2cc8c609
MM		 269SOC_DOUBLE_TLV("Sidetone Capture Volume", WM8753_RECMIX1, 0, 4, 7, 1,
270 rec_mix_tlv),
271SOC_SINGLE_TLV("Voice Sidetone Capture Volume", WM8753_RECMIX2, 0, 7, 1,
272 rec_mix_tlv),
1f53aee0 273
2cc8c609
MM		 274SOC_DOUBLE_R_TLV("Capture Volume", WM8753_LINVOL, WM8753_RINVOL, 0, 63, 0,
275 pga_tlv),
1f53aee0
LG		 276SOC_DOUBLE_R("Capture ZC Switch", WM8753_LINVOL, WM8753_RINVOL, 6, 1, 0),
277SOC_DOUBLE_R("Capture Switch", WM8753_LINVOL, WM8753_RINVOL, 7, 1, 1),
278
279SOC_ENUM("Capture Filter Select", wm8753_enum[23]),
280SOC_ENUM("Capture Filter Cut-off", wm8753_enum[24]),
281SOC_SINGLE("Capture Filter Switch", WM8753_ADC, 0, 1, 1),
282
283SOC_SINGLE("ALC Capture Target Volume", WM8753_ALC1, 0, 7, 0),
284SOC_SINGLE("ALC Capture Max Volume", WM8753_ALC1, 4, 7, 0),
285SOC_ENUM("ALC Capture Function", wm8753_enum[3]),
286SOC_SINGLE("ALC Capture ZC Switch", WM8753_ALC2, 8, 1, 0),
287SOC_SINGLE("ALC Capture Hold Time", WM8753_ALC2, 0, 15, 1),
288SOC_SINGLE("ALC Capture Decay Time", WM8753_ALC3, 4, 15, 1),
289SOC_SINGLE("ALC Capture Attack Time", WM8753_ALC3, 0, 15, 0),
290SOC_SINGLE("ALC Capture NG Threshold", WM8753_NGATE, 3, 31, 0),
291SOC_ENUM("ALC Capture NG Type", wm8753_enum[4]),
292SOC_SINGLE("ALC Capture NG Switch", WM8753_NGATE, 0, 1, 0),
293
294SOC_ENUM("3D Function", wm8753_enum[5]),
295SOC_ENUM("3D Upper Cut-off", wm8753_enum[6]),
296SOC_ENUM("3D Lower Cut-off", wm8753_enum[7]),
297SOC_SINGLE("3D Volume", WM8753_3D, 1, 15, 0),
298SOC_SINGLE("3D Switch", WM8753_3D, 0, 1, 0),
299
300SOC_SINGLE("Capture 6dB Attenuate", WM8753_ADCTL1, 2, 1, 0),
301SOC_SINGLE("Playback 6dB Attenuate", WM8753_ADCTL1, 1, 1, 0),
302
303SOC_ENUM("De-emphasis", wm8753_enum[8]),
304SOC_ENUM("Playback Mono Mix", wm8753_enum[9]),
305SOC_ENUM("Playback Phase", wm8753_enum[10]),
306
2cc8c609
MM		 307SOC_SINGLE_TLV("Mic2 Capture Volume", WM8753_INCTL1, 7, 3, 0, mic_preamp_tlv),
308SOC_SINGLE_TLV("Mic1 Capture Volume", WM8753_INCTL1, 5, 3, 0, mic_preamp_tlv),
1f53aee0
LG		 309
310SOC_ENUM_EXT("DAI Mode", wm8753_enum[26], wm8753_get_dai, wm8753_set_dai),
311
312SOC_ENUM("ADC Data Select", wm8753_enum[27]),
ae092c9e 313SOC_ENUM("ROUT2 Phase", wm8753_enum[28]),
1f53aee0
LG		 314};
315
1f53aee0
LG		 316/*
317 * _DAPM_ Controls
318 */
319
320/* Left Mixer */
321static const struct snd_kcontrol_new wm8753_left_mixer_controls[] = {
322SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_LOUTM2, 8, 1, 0),
323SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_LOUTM2, 7, 1, 0),
324SOC_DAPM_SINGLE("Left Playback Switch", WM8753_LOUTM1, 8, 1, 0),
325SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_LOUTM1, 7, 1, 0),
326};
327
328/* Right mixer */
329static const struct snd_kcontrol_new wm8753_right_mixer_controls[] = {
330SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_ROUTM2, 8, 1, 0),
331SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_ROUTM2, 7, 1, 0),
332SOC_DAPM_SINGLE("Right Playback Switch", WM8753_ROUTM1, 8, 1, 0),
333SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_ROUTM1, 7, 1, 0),
334};
335
336/* Mono mixer */
337static const struct snd_kcontrol_new wm8753_mono_mixer_controls[] = {
338SOC_DAPM_SINGLE("Left Playback Switch", WM8753_MOUTM1, 8, 1, 0),
339SOC_DAPM_SINGLE("Right Playback Switch", WM8753_MOUTM2, 8, 1, 0),
340SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_MOUTM2, 3, 1, 0),
341SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_MOUTM2, 7, 1, 0),
342SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_MOUTM1, 7, 1, 0),
343};
344
345/* Mono 2 Mux */
346static const struct snd_kcontrol_new wm8753_mono2_controls =
347SOC_DAPM_ENUM("Route", wm8753_enum[17]);
348
349/* Out 3 Mux */
350static const struct snd_kcontrol_new wm8753_out3_controls =
351SOC_DAPM_ENUM("Route", wm8753_enum[18]);
352
353/* Out 4 Mux */
354static const struct snd_kcontrol_new wm8753_out4_controls =
355SOC_DAPM_ENUM("Route", wm8753_enum[19]);
356
357/* ADC Mono Mix */
358static const struct snd_kcontrol_new wm8753_adc_mono_controls =
359SOC_DAPM_ENUM("Route", wm8753_enum[22]);
360
361/* Record mixer */
362static const struct snd_kcontrol_new wm8753_record_mixer_controls[] = {
363SOC_DAPM_SINGLE("Voice Capture Switch", WM8753_RECMIX2, 3, 1, 0),
364SOC_DAPM_SINGLE("Left Capture Switch", WM8753_RECMIX1, 3, 1, 0),
365SOC_DAPM_SINGLE("Right Capture Switch", WM8753_RECMIX1, 7, 1, 0),
366};
367
368/* Left ADC mux */
369static const struct snd_kcontrol_new wm8753_adc_left_controls =
370SOC_DAPM_ENUM("Route", wm8753_enum[21]);
371
372/* Right ADC mux */
373static const struct snd_kcontrol_new wm8753_adc_right_controls =
374SOC_DAPM_ENUM("Route", wm8753_enum[20]);
375
376/* MIC mux */
377static const struct snd_kcontrol_new wm8753_mic_mux_controls =
378SOC_DAPM_ENUM("Route", wm8753_enum[16]);
379
380/* ALC mixer */
381static const struct snd_kcontrol_new wm8753_alc_mixer_controls[] = {
382SOC_DAPM_SINGLE("Line Capture Switch", WM8753_INCTL2, 3, 1, 0),
383SOC_DAPM_SINGLE("Mic2 Capture Switch", WM8753_INCTL2, 2, 1, 0),
384SOC_DAPM_SINGLE("Mic1 Capture Switch", WM8753_INCTL2, 1, 1, 0),
385SOC_DAPM_SINGLE("Rx Capture Switch", WM8753_INCTL2, 0, 1, 0),
386};
387
388/* Left Line mux */
389static const struct snd_kcontrol_new wm8753_line_left_controls =
390SOC_DAPM_ENUM("Route", wm8753_enum[14]);
391
392/* Right Line mux */
393static const struct snd_kcontrol_new wm8753_line_right_controls =
394SOC_DAPM_ENUM("Route", wm8753_enum[13]);
395
396/* Mono Line mux */
397static const struct snd_kcontrol_new wm8753_line_mono_controls =
398SOC_DAPM_ENUM("Route", wm8753_enum[12]);
399
400/* Line mux and mixer */
401static const struct snd_kcontrol_new wm8753_line_mux_mix_controls =
402SOC_DAPM_ENUM("Route", wm8753_enum[11]);
403
404/* Rx mux and mixer */
405static const struct snd_kcontrol_new wm8753_rx_mux_mix_controls =
406SOC_DAPM_ENUM("Route", wm8753_enum[15]);
407
408/* Mic Selector Mux */
409static const struct snd_kcontrol_new wm8753_mic_sel_mux_controls =
410SOC_DAPM_ENUM("Route", wm8753_enum[25]);
411
412static const struct snd_soc_dapm_widget wm8753_dapm_widgets[] = {
413SND_SOC_DAPM_MICBIAS("Mic Bias", WM8753_PWR1, 5, 0),
414SND_SOC_DAPM_MIXER("Left Mixer", WM8753_PWR4, 0, 0,
415 &wm8753_left_mixer_controls[0], ARRAY_SIZE(wm8753_left_mixer_controls)),
416SND_SOC_DAPM_PGA("Left Out 1", WM8753_PWR3, 8, 0, NULL, 0),
417SND_SOC_DAPM_PGA("Left Out 2", WM8753_PWR3, 6, 0, NULL, 0),
418SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", WM8753_PWR1, 3, 0),
419SND_SOC_DAPM_OUTPUT("LOUT1"),
420SND_SOC_DAPM_OUTPUT("LOUT2"),
421SND_SOC_DAPM_MIXER("Right Mixer", WM8753_PWR4, 1, 0,
422 &wm8753_right_mixer_controls[0], ARRAY_SIZE(wm8753_right_mixer_controls)),
423SND_SOC_DAPM_PGA("Right Out 1", WM8753_PWR3, 7, 0, NULL, 0),
424SND_SOC_DAPM_PGA("Right Out 2", WM8753_PWR3, 5, 0, NULL, 0),
425SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", WM8753_PWR1, 2, 0),
426SND_SOC_DAPM_OUTPUT("ROUT1"),
427SND_SOC_DAPM_OUTPUT("ROUT2"),
428SND_SOC_DAPM_MIXER("Mono Mixer", WM8753_PWR4, 2, 0,
429 &wm8753_mono_mixer_controls[0], ARRAY_SIZE(wm8753_mono_mixer_controls)),
430SND_SOC_DAPM_PGA("Mono Out 1", WM8753_PWR3, 2, 0, NULL, 0),
431SND_SOC_DAPM_PGA("Mono Out 2", WM8753_PWR3, 1, 0, NULL, 0),
432SND_SOC_DAPM_DAC("Voice DAC", "Voice Playback", WM8753_PWR1, 4, 0),
433SND_SOC_DAPM_OUTPUT("MONO1"),
434SND_SOC_DAPM_MUX("Mono 2 Mux", SND_SOC_NOPM, 0, 0, &wm8753_mono2_controls),
435SND_SOC_DAPM_OUTPUT("MONO2"),
436SND_SOC_DAPM_MIXER("Out3 Left + Right", -1, 0, 0, NULL, 0),
437SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8753_out3_controls),
438SND_SOC_DAPM_PGA("Out 3", WM8753_PWR3, 4, 0, NULL, 0),
439SND_SOC_DAPM_OUTPUT("OUT3"),
440SND_SOC_DAPM_MUX("Out4 Mux", SND_SOC_NOPM, 0, 0, &wm8753_out4_controls),
441SND_SOC_DAPM_PGA("Out 4", WM8753_PWR3, 3, 0, NULL, 0),
442SND_SOC_DAPM_OUTPUT("OUT4"),
443SND_SOC_DAPM_MIXER("Playback Mixer", WM8753_PWR4, 3, 0,
444 &wm8753_record_mixer_controls[0],
445 ARRAY_SIZE(wm8753_record_mixer_controls)),
446SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8753_PWR2, 3, 0),
447SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8753_PWR2, 2, 0),
448SND_SOC_DAPM_MUX("Capture Left Mixer", SND_SOC_NOPM, 0, 0,
449 &wm8753_adc_mono_controls),
450SND_SOC_DAPM_MUX("Capture Right Mixer", SND_SOC_NOPM, 0, 0,
451 &wm8753_adc_mono_controls),
452SND_SOC_DAPM_MUX("Capture Left Mux", SND_SOC_NOPM, 0, 0,
453 &wm8753_adc_left_controls),
454SND_SOC_DAPM_MUX("Capture Right Mux", SND_SOC_NOPM, 0, 0,
455 &wm8753_adc_right_controls),
456SND_SOC_DAPM_MUX("Mic Sidetone Mux", SND_SOC_NOPM, 0, 0,
457 &wm8753_mic_mux_controls),
458SND_SOC_DAPM_PGA("Left Capture Volume", WM8753_PWR2, 5, 0, NULL, 0),
459SND_SOC_DAPM_PGA("Right Capture Volume", WM8753_PWR2, 4, 0, NULL, 0),
460SND_SOC_DAPM_MIXER("ALC Mixer", WM8753_PWR2, 6, 0,
461 &wm8753_alc_mixer_controls[0], ARRAY_SIZE(wm8753_alc_mixer_controls)),
462SND_SOC_DAPM_MUX("Line Left Mux", SND_SOC_NOPM, 0, 0,
463 &wm8753_line_left_controls),
464SND_SOC_DAPM_MUX("Line Right Mux", SND_SOC_NOPM, 0, 0,
465 &wm8753_line_right_controls),
466SND_SOC_DAPM_MUX("Line Mono Mux", SND_SOC_NOPM, 0, 0,
467 &wm8753_line_mono_controls),
468SND_SOC_DAPM_MUX("Line Mixer", WM8753_PWR2, 0, 0,
469 &wm8753_line_mux_mix_controls),
470SND_SOC_DAPM_MUX("Rx Mixer", WM8753_PWR2, 1, 0,
471 &wm8753_rx_mux_mix_controls),
472SND_SOC_DAPM_PGA("Mic 1 Volume", WM8753_PWR2, 8, 0, NULL, 0),
473SND_SOC_DAPM_PGA("Mic 2 Volume", WM8753_PWR2, 7, 0, NULL, 0),
474SND_SOC_DAPM_MUX("Mic Selection Mux", SND_SOC_NOPM, 0, 0,
475 &wm8753_mic_sel_mux_controls),
476SND_SOC_DAPM_INPUT("LINE1"),
477SND_SOC_DAPM_INPUT("LINE2"),
478SND_SOC_DAPM_INPUT("RXP"),
479SND_SOC_DAPM_INPUT("RXN"),
480SND_SOC_DAPM_INPUT("ACIN"),
481SND_SOC_DAPM_OUTPUT("ACOP"),
482SND_SOC_DAPM_INPUT("MIC1N"),
483SND_SOC_DAPM_INPUT("MIC1"),
484SND_SOC_DAPM_INPUT("MIC2N"),
485SND_SOC_DAPM_INPUT("MIC2"),
486SND_SOC_DAPM_VMID("VREF"),
487};
488
56a926dd 489static const struct snd_soc_dapm_route wm8753_dapm_routes[] = {
1f53aee0
LG		 490 /* left mixer */
491 {"Left Mixer", "Left Playback Switch", "Left DAC"},
492 {"Left Mixer", "Voice Playback Switch", "Voice DAC"},
493 {"Left Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
494 {"Left Mixer", "Bypass Playback Switch", "Line Left Mux"},
495
496 /* right mixer */
497 {"Right Mixer", "Right Playback Switch", "Right DAC"},
498 {"Right Mixer", "Voice Playback Switch", "Voice DAC"},
499 {"Right Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
500 {"Right Mixer", "Bypass Playback Switch", "Line Right Mux"},
501
502 /* mono mixer */
503 {"Mono Mixer", "Voice Playback Switch", "Voice DAC"},
504 {"Mono Mixer", "Left Playback Switch", "Left DAC"},
505 {"Mono Mixer", "Right Playback Switch", "Right DAC"},
506 {"Mono Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
507 {"Mono Mixer", "Bypass Playback Switch", "Line Mono Mux"},
508
509 /* left out */
510 {"Left Out 1", NULL, "Left Mixer"},
511 {"Left Out 2", NULL, "Left Mixer"},
512 {"LOUT1", NULL, "Left Out 1"},
513 {"LOUT2", NULL, "Left Out 2"},
514
515 /* right out */
516 {"Right Out 1", NULL, "Right Mixer"},
517 {"Right Out 2", NULL, "Right Mixer"},
518 {"ROUT1", NULL, "Right Out 1"},
519 {"ROUT2", NULL, "Right Out 2"},
520
521 /* mono 1 out */
522 {"Mono Out 1", NULL, "Mono Mixer"},
523 {"MONO1", NULL, "Mono Out 1"},
524
525 /* mono 2 out */
526 {"Mono 2 Mux", "Left + Right", "Out3 Left + Right"},
527 {"Mono 2 Mux", "Inverted Mono 1", "MONO1"},
528 {"Mono 2 Mux", "Left", "Left Mixer"},
529 {"Mono 2 Mux", "Right", "Right Mixer"},
530 {"Mono Out 2", NULL, "Mono 2 Mux"},
531 {"MONO2", NULL, "Mono Out 2"},
532
533 /* out 3 */
534 {"Out3 Left + Right", NULL, "Left Mixer"},
535 {"Out3 Left + Right", NULL, "Right Mixer"},
536 {"Out3 Mux", "VREF", "VREF"},
537 {"Out3 Mux", "Left + Right", "Out3 Left + Right"},
538 {"Out3 Mux", "ROUT2", "ROUT2"},
539 {"Out 3", NULL, "Out3 Mux"},
540 {"OUT3", NULL, "Out 3"},
541
542 /* out 4 */
543 {"Out4 Mux", "VREF", "VREF"},
4037314a 544 {"Out4 Mux", "Capture ST", "Playback Mixer"},
1f53aee0
LG		 545 {"Out4 Mux", "LOUT2", "LOUT2"},
546 {"Out 4", NULL, "Out4 Mux"},
547 {"OUT4", NULL, "Out 4"},
548
549 /* record mixer */
550 {"Playback Mixer", "Left Capture Switch", "Left Mixer"},
551 {"Playback Mixer", "Voice Capture Switch", "Mono Mixer"},
552 {"Playback Mixer", "Right Capture Switch", "Right Mixer"},
553
554 /* Mic/SideTone Mux */
555 {"Mic Sidetone Mux", "Left PGA", "Left Capture Volume"},
556 {"Mic Sidetone Mux", "Right PGA", "Right Capture Volume"},
557 {"Mic Sidetone Mux", "Mic 1", "Mic 1 Volume"},
558 {"Mic Sidetone Mux", "Mic 2", "Mic 2 Volume"},
559
560 /* Capture Left Mux */
561 {"Capture Left Mux", "PGA", "Left Capture Volume"},
562 {"Capture Left Mux", "Line or RXP-RXN", "Line Left Mux"},
563 {"Capture Left Mux", "Line", "LINE1"},
564
565 /* Capture Right Mux */
566 {"Capture Right Mux", "PGA", "Right Capture Volume"},
567 {"Capture Right Mux", "Line or RXP-RXN", "Line Right Mux"},
4037314a 568 {"Capture Right Mux", "Sidetone", "Playback Mixer"},
1f53aee0
LG		 569
570 /* Mono Capture mixer-mux */
571 {"Capture Right Mixer", "Stereo", "Capture Right Mux"},
877ae707 572 {"Capture Left Mixer", "Stereo", "Capture Left Mux"},
1f53aee0
LG		 573 {"Capture Left Mixer", "Analogue Mix Left", "Capture Left Mux"},
574 {"Capture Left Mixer", "Analogue Mix Left", "Capture Right Mux"},
575 {"Capture Right Mixer", "Analogue Mix Right", "Capture Left Mux"},
576 {"Capture Right Mixer", "Analogue Mix Right", "Capture Right Mux"},
577 {"Capture Left Mixer", "Digital Mono Mix", "Capture Left Mux"},
578 {"Capture Left Mixer", "Digital Mono Mix", "Capture Right Mux"},
579 {"Capture Right Mixer", "Digital Mono Mix", "Capture Left Mux"},
580 {"Capture Right Mixer", "Digital Mono Mix", "Capture Right Mux"},
581
582 /* ADC */
583 {"Left ADC", NULL, "Capture Left Mixer"},
584 {"Right ADC", NULL, "Capture Right Mixer"},
585
586 /* Left Capture Volume */
587 {"Left Capture Volume", NULL, "ACIN"},
588
589 /* Right Capture Volume */
590 {"Right Capture Volume", NULL, "Mic 2 Volume"},
591
592 /* ALC Mixer */
593 {"ALC Mixer", "Line Capture Switch", "Line Mixer"},
594 {"ALC Mixer", "Mic2 Capture Switch", "Mic 2 Volume"},
595 {"ALC Mixer", "Mic1 Capture Switch", "Mic 1 Volume"},
596 {"ALC Mixer", "Rx Capture Switch", "Rx Mixer"},
597
598 /* Line Left Mux */
599 {"Line Left Mux", "Line 1", "LINE1"},
600 {"Line Left Mux", "Rx Mix", "Rx Mixer"},
601
602 /* Line Right Mux */
603 {"Line Right Mux", "Line 2", "LINE2"},
604 {"Line Right Mux", "Rx Mix", "Rx Mixer"},
605
606 /* Line Mono Mux */
607 {"Line Mono Mux", "Line Mix", "Line Mixer"},
608 {"Line Mono Mux", "Rx Mix", "Rx Mixer"},
609
610 /* Line Mixer/Mux */
611 {"Line Mixer", "Line 1 + 2", "LINE1"},
612 {"Line Mixer", "Line 1 - 2", "LINE1"},
613 {"Line Mixer", "Line 1 + 2", "LINE2"},
614 {"Line Mixer", "Line 1 - 2", "LINE2"},
615 {"Line Mixer", "Line 1", "LINE1"},
616 {"Line Mixer", "Line 2", "LINE2"},
617
618 /* Rx Mixer/Mux */
619 {"Rx Mixer", "RXP - RXN", "RXP"},
620 {"Rx Mixer", "RXP + RXN", "RXP"},
621 {"Rx Mixer", "RXP - RXN", "RXN"},
622 {"Rx Mixer", "RXP + RXN", "RXN"},
623 {"Rx Mixer", "RXP", "RXP"},
624 {"Rx Mixer", "RXN", "RXN"},
625
626 /* Mic 1 Volume */
627 {"Mic 1 Volume", NULL, "MIC1N"},
628 {"Mic 1 Volume", NULL, "Mic Selection Mux"},
629
630 /* Mic 2 Volume */
631 {"Mic 2 Volume", NULL, "MIC2N"},
632 {"Mic 2 Volume", NULL, "MIC2"},
633
634 /* Mic Selector Mux */
635 {"Mic Selection Mux", "Mic 1", "MIC1"},
636 {"Mic Selection Mux", "Mic 2", "MIC2N"},
637 {"Mic Selection Mux", "Mic 3", "MIC2"},
638
639 /* ACOP */
640 {"ACOP", NULL, "ALC Mixer"},
1f53aee0
LG		 641};
642
1f53aee0
LG		 643/* PLL divisors */
644struct _pll_div {
645 u32 div2:1;
646 u32 n:4;
647 u32 k:24;
648};
649
650/* The size in bits of the pll divide multiplied by 10
651 * to allow rounding later */
652#define FIXED_PLL_SIZE ((1 << 22) * 10)
653
654static void pll_factors(struct _pll_div *pll_div, unsigned int target,
655 unsigned int source)
656{
657 u64 Kpart;
658 unsigned int K, Ndiv, Nmod;
659
660 Ndiv = target / source;
661 if (Ndiv < 6) {
662 source >>= 1;
663 pll_div->div2 = 1;
664 Ndiv = target / source;
665 } else
666 pll_div->div2 = 0;
667
668 if ((Ndiv < 6) || (Ndiv > 12))
669 printk(KERN_WARNING
449bd54d 670 "wm8753: unsupported N = %u\n", Ndiv);
1f53aee0
LG		 671
672 pll_div->n = Ndiv;
673 Nmod = target % source;
674 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
675
676 do_div(Kpart, source);
677
678 K = Kpart & 0xFFFFFFFF;
679
680 /* Check if we need to round */
681 if ((K % 10) >= 5)
682 K += 5;
683
684 /* Move down to proper range now rounding is done */
685 K /= 10;
686
687 pll_div->k = K;
688}
689
85488037
MB		 690static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
691 int source, unsigned int freq_in, unsigned int freq_out)
1f53aee0
LG		 692{
693 u16 reg, enable;
694 int offset;
695 struct snd_soc_codec *codec = codec_dai->codec;
696
697 if (pll_id < WM8753_PLL1 || pll_id > WM8753_PLL2)
698 return -ENODEV;
699
700 if (pll_id == WM8753_PLL1) {
701 offset = 0;
702 enable = 0x10;
776065e3 703 reg = snd_soc_read(codec, WM8753_CLOCK) & 0xffef;
1f53aee0
LG		 704 } else {
705 offset = 4;
706 enable = 0x8;
776065e3 707 reg = snd_soc_read(codec, WM8753_CLOCK) & 0xfff7;
1f53aee0
LG		 708 }
709
710 if (!freq_in || !freq_out) {
711 /* disable PLL */
776065e3
LPC		 712 snd_soc_write(codec, WM8753_PLL1CTL1 + offset, 0x0026);
713 snd_soc_write(codec, WM8753_CLOCK, reg);
1f53aee0
LG		 714 return 0;
715 } else {
716 u16 value = 0;
717 struct _pll_div pll_div;
718
719 pll_factors(&pll_div, freq_out * 8, freq_in);
720
721 /* set up N and K PLL divisor ratios */
722 /* bits 8:5 = PLL_N, bits 3:0 = PLL_K[21:18] */
723 value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18);
776065e3 724 snd_soc_write(codec, WM8753_PLL1CTL2 + offset, value);
1f53aee0
LG		 725
726 /* bits 8:0 = PLL_K[17:9] */
727 value = (pll_div.k & 0x03fe00) >> 9;
776065e3 728 snd_soc_write(codec, WM8753_PLL1CTL3 + offset, value);
1f53aee0
LG		 729
730 /* bits 8:0 = PLL_K[8:0] */
731 value = pll_div.k & 0x0001ff;
776065e3 732 snd_soc_write(codec, WM8753_PLL1CTL4 + offset, value);
1f53aee0
LG		 733
734 /* set PLL as input and enable */
776065e3 735 snd_soc_write(codec, WM8753_PLL1CTL1 + offset, 0x0027 |
1f53aee0 736 (pll_div.div2 << 3));
776065e3 737 snd_soc_write(codec, WM8753_CLOCK, reg | enable);
1f53aee0
LG		 738 }
739 return 0;
740}
741
742struct _coeff_div {
743 u32 mclk;
744 u32 rate;
745 u8 sr:5;
746 u8 usb:1;
747};
748
749/* codec hifi mclk (after PLL) clock divider coefficients */
750static const struct _coeff_div coeff_div[] = {
751 /* 8k */
752 {12288000, 8000, 0x6, 0x0},
753 {11289600, 8000, 0x16, 0x0},
754 {18432000, 8000, 0x7, 0x0},
755 {16934400, 8000, 0x17, 0x0},
756 {12000000, 8000, 0x6, 0x1},
757
758 /* 11.025k */
759 {11289600, 11025, 0x18, 0x0},
760 {16934400, 11025, 0x19, 0x0},
761 {12000000, 11025, 0x19, 0x1},
762
763 /* 16k */
764 {12288000, 16000, 0xa, 0x0},
765 {18432000, 16000, 0xb, 0x0},
766 {12000000, 16000, 0xa, 0x1},
767
768 /* 22.05k */
769 {11289600, 22050, 0x1a, 0x0},
770 {16934400, 22050, 0x1b, 0x0},
771 {12000000, 22050, 0x1b, 0x1},
772
773 /* 32k */
774 {12288000, 32000, 0xc, 0x0},
775 {18432000, 32000, 0xd, 0x0},
776 {12000000, 32000, 0xa, 0x1},
777
778 /* 44.1k */
779 {11289600, 44100, 0x10, 0x0},
780 {16934400, 44100, 0x11, 0x0},
781 {12000000, 44100, 0x11, 0x1},
782
783 /* 48k */
784 {12288000, 48000, 0x0, 0x0},
785 {18432000, 48000, 0x1, 0x0},
786 {12000000, 48000, 0x0, 0x1},
787
788 /* 88.2k */
789 {11289600, 88200, 0x1e, 0x0},
790 {16934400, 88200, 0x1f, 0x0},
791 {12000000, 88200, 0x1f, 0x1},
792
793 /* 96k */
794 {12288000, 96000, 0xe, 0x0},
795 {18432000, 96000, 0xf, 0x0},
796 {12000000, 96000, 0xe, 0x1},
797};
798
799static int get_coeff(int mclk, int rate)
800{
801 int i;
802
803 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
804 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
805 return i;
806 }
807 return -EINVAL;
808}
809
810/*
811 * Clock after PLL and dividers
812 */
e550e17f 813static int wm8753_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 814 int clk_id, unsigned int freq, int dir)
815{
816 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 817 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 818
819 switch (freq) {
820 case 11289600:
821 case 12000000:
822 case 12288000:
823 case 16934400:
824 case 18432000:
825 if (clk_id == WM8753_MCLK) {
826 wm8753->sysclk = freq;
827 return 0;
828 } else if (clk_id == WM8753_PCMCLK) {
829 wm8753->pcmclk = freq;
830 return 0;
831 }
832 break;
833 }
834 return -EINVAL;
835}
836
837/*
838 * Set's ADC and Voice DAC format.
839 */
338ee253 840static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_codec *codec,
1f53aee0
LG		 841 unsigned int fmt)
842{
776065e3 843 u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01ec;
1f53aee0
LG		 844
845 /* interface format */
846 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
847 case SND_SOC_DAIFMT_I2S:
848 voice |= 0x0002;
849 break;
850 case SND_SOC_DAIFMT_RIGHT_J:
851 break;
852 case SND_SOC_DAIFMT_LEFT_J:
853 voice |= 0x0001;
854 break;
855 case SND_SOC_DAIFMT_DSP_A:
856 voice |= 0x0003;
857 break;
858 case SND_SOC_DAIFMT_DSP_B:
859 voice |= 0x0013;
860 break;
861 default:
862 return -EINVAL;
863 }
864
776065e3 865 snd_soc_write(codec, WM8753_PCM, voice);
1f53aee0
LG		 866 return 0;
867}
868
869/*
870 * Set PCM DAI bit size and sample rate.
871 */
872static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 873 struct snd_pcm_hw_params *params,
874 struct snd_soc_dai *dai)
1f53aee0
LG		 875{
876 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 877 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 878 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
776065e3
LPC		 879 u16 voice = snd_soc_read(codec, WM8753_PCM) & 0x01f3;
880 u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x017f;
1f53aee0
LG		 881
882 /* bit size */
883 switch (params_format(params)) {
884 case SNDRV_PCM_FORMAT_S16_LE:
885 break;
886 case SNDRV_PCM_FORMAT_S20_3LE:
887 voice |= 0x0004;
888 break;
889 case SNDRV_PCM_FORMAT_S24_LE:
890 voice |= 0x0008;
891 break;
892 case SNDRV_PCM_FORMAT_S32_LE:
893 voice |= 0x000c;
894 break;
895 }
896
897 /* sample rate */
898 if (params_rate(params) * 384 == wm8753->pcmclk)
899 srate |= 0x80;
776065e3 900 snd_soc_write(codec, WM8753_SRATE1, srate);
1f53aee0 901
776065e3 902 snd_soc_write(codec, WM8753_PCM, voice);
1f53aee0
LG		 903 return 0;
904}
905
906/*
907 * Set's PCM dai fmt and BCLK.
908 */
338ee253 909static int wm8753_pcm_set_dai_fmt(struct snd_soc_codec *codec,
1f53aee0
LG		 910 unsigned int fmt)
911{
1f53aee0
LG		 912 u16 voice, ioctl;
913
776065e3
LPC		 914 voice = snd_soc_read(codec, WM8753_PCM) & 0x011f;
915 ioctl = snd_soc_read(codec, WM8753_IOCTL) & 0x015d;
1f53aee0
LG		 916
917 /* set master/slave audio interface */
918 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
919 case SND_SOC_DAIFMT_CBS_CFS:
920 break;
921 case SND_SOC_DAIFMT_CBM_CFM:
922 ioctl |= 0x2;
923 case SND_SOC_DAIFMT_CBM_CFS:
924 voice |= 0x0040;
925 break;
926 default:
927 return -EINVAL;
928 }
929
930 /* clock inversion */
931 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
932 case SND_SOC_DAIFMT_DSP_A:
933 case SND_SOC_DAIFMT_DSP_B:
934 /* frame inversion not valid for DSP modes */
935 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
936 case SND_SOC_DAIFMT_NB_NF:
937 break;
938 case SND_SOC_DAIFMT_IB_NF:
939 voice |= 0x0080;
940 break;
941 default:
942 return -EINVAL;
943 }
944 break;
945 case SND_SOC_DAIFMT_I2S:
946 case SND_SOC_DAIFMT_RIGHT_J:
947 case SND_SOC_DAIFMT_LEFT_J:
948 voice &= ~0x0010;
949 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
950 case SND_SOC_DAIFMT_NB_NF:
951 break;
952 case SND_SOC_DAIFMT_IB_IF:
953 voice |= 0x0090;
954 break;
955 case SND_SOC_DAIFMT_IB_NF:
956 voice |= 0x0080;
957 break;
958 case SND_SOC_DAIFMT_NB_IF:
959 voice |= 0x0010;
960 break;
961 default:
962 return -EINVAL;
963 }
964 break;
965 default:
966 return -EINVAL;
967 }
968
776065e3
LPC		 969 snd_soc_write(codec, WM8753_PCM, voice);
970 snd_soc_write(codec, WM8753_IOCTL, ioctl);
1f53aee0
LG		 971 return 0;
972}
973
e550e17f 974static int wm8753_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 975 int div_id, int div)
976{
977 struct snd_soc_codec *codec = codec_dai->codec;
978 u16 reg;
979
980 switch (div_id) {
981 case WM8753_PCMDIV:
776065e3
LPC		 982 reg = snd_soc_read(codec, WM8753_CLOCK) & 0x003f;
983 snd_soc_write(codec, WM8753_CLOCK, reg | div);
1f53aee0
LG		 984 break;
985 case WM8753_BCLKDIV:
776065e3
LPC		 986 reg = snd_soc_read(codec, WM8753_SRATE2) & 0x01c7;
987 snd_soc_write(codec, WM8753_SRATE2, reg | div);
1f53aee0
LG		 988 break;
989 case WM8753_VXCLKDIV:
776065e3
LPC		 990 reg = snd_soc_read(codec, WM8753_SRATE2) & 0x003f;
991 snd_soc_write(codec, WM8753_SRATE2, reg | div);
1f53aee0
LG		 992 break;
993 default:
994 return -EINVAL;
995 }
996 return 0;
997}
998
999/*
1000 * Set's HiFi DAC format.
1001 */
338ee253 1002static int wm8753_hdac_set_dai_fmt(struct snd_soc_codec *codec,
1f53aee0
LG		 1003 unsigned int fmt)
1004{
776065e3 1005 u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01e0;
1f53aee0
LG		 1006
1007 /* interface format */
1008 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1009 case SND_SOC_DAIFMT_I2S:
1010 hifi |= 0x0002;
1011 break;
1012 case SND_SOC_DAIFMT_RIGHT_J:
1013 break;
1014 case SND_SOC_DAIFMT_LEFT_J:
1015 hifi |= 0x0001;
1016 break;
1017 case SND_SOC_DAIFMT_DSP_A:
1018 hifi |= 0x0003;
1019 break;
1020 case SND_SOC_DAIFMT_DSP_B:
1021 hifi |= 0x0013;
1022 break;
1023 default:
1024 return -EINVAL;
1025 }
1026
776065e3 1027 snd_soc_write(codec, WM8753_HIFI, hifi);
1f53aee0
LG		 1028 return 0;
1029}
1030
1031/*
1032 * Set's I2S DAI format.
1033 */
338ee253 1034static int wm8753_i2s_set_dai_fmt(struct snd_soc_codec *codec,
1f53aee0
LG		 1035 unsigned int fmt)
1036{
1f53aee0
LG		 1037 u16 ioctl, hifi;
1038
776065e3
LPC		 1039 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x011f;
1040 ioctl = snd_soc_read(codec, WM8753_IOCTL) & 0x00ae;
1f53aee0
LG		 1041
1042 /* set master/slave audio interface */
1043 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1044 case SND_SOC_DAIFMT_CBS_CFS:
1045 break;
1046 case SND_SOC_DAIFMT_CBM_CFM:
1047 ioctl |= 0x1;
1048 case SND_SOC_DAIFMT_CBM_CFS:
1049 hifi |= 0x0040;
1050 break;
1051 default:
1052 return -EINVAL;
1053 }
1054
1055 /* clock inversion */
1056 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1057 case SND_SOC_DAIFMT_DSP_A:
1058 case SND_SOC_DAIFMT_DSP_B:
1059 /* frame inversion not valid for DSP modes */
1060 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1061 case SND_SOC_DAIFMT_NB_NF:
1062 break;
1063 case SND_SOC_DAIFMT_IB_NF:
1064 hifi |= 0x0080;
1065 break;
1066 default:
1067 return -EINVAL;
1068 }
1069 break;
1070 case SND_SOC_DAIFMT_I2S:
1071 case SND_SOC_DAIFMT_RIGHT_J:
1072 case SND_SOC_DAIFMT_LEFT_J:
1073 hifi &= ~0x0010;
1074 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1075 case SND_SOC_DAIFMT_NB_NF:
1076 break;
1077 case SND_SOC_DAIFMT_IB_IF:
1078 hifi |= 0x0090;
1079 break;
1080 case SND_SOC_DAIFMT_IB_NF:
1081 hifi |= 0x0080;
1082 break;
1083 case SND_SOC_DAIFMT_NB_IF:
1084 hifi |= 0x0010;
1085 break;
1086 default:
1087 return -EINVAL;
1088 }
1089 break;
1090 default:
1091 return -EINVAL;
1092 }
1093
776065e3
LPC		 1094 snd_soc_write(codec, WM8753_HIFI, hifi);
1095 snd_soc_write(codec, WM8753_IOCTL, ioctl);
1f53aee0
LG		 1096 return 0;
1097}
1098
1099/*
1100 * Set PCM DAI bit size and sample rate.
1101 */
1102static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1103 struct snd_pcm_hw_params *params,
1104 struct snd_soc_dai *dai)
1f53aee0
LG		 1105{
1106 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1107 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1108 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
776065e3
LPC		 1109 u16 srate = snd_soc_read(codec, WM8753_SRATE1) & 0x01c0;
1110 u16 hifi = snd_soc_read(codec, WM8753_HIFI) & 0x01f3;
1f53aee0
LG		 1111 int coeff;
1112
1113 /* is digital filter coefficient valid ? */
1114 coeff = get_coeff(wm8753->sysclk, params_rate(params));
1115 if (coeff < 0) {
1116 printk(KERN_ERR "wm8753 invalid MCLK or rate\n");
1117 return coeff;
1118 }
776065e3 1119 snd_soc_write(codec, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) |
1f53aee0
LG		 1120 coeff_div[coeff].usb);
1121
1122 /* bit size */
1123 switch (params_format(params)) {
1124 case SNDRV_PCM_FORMAT_S16_LE:
1125 break;
1126 case SNDRV_PCM_FORMAT_S20_3LE:
1127 hifi |= 0x0004;
1128 break;
1129 case SNDRV_PCM_FORMAT_S24_LE:
1130 hifi |= 0x0008;
1131 break;
1132 case SNDRV_PCM_FORMAT_S32_LE:
1133 hifi |= 0x000c;
1134 break;
1135 }
1136
776065e3 1137 snd_soc_write(codec, WM8753_HIFI, hifi);
1f53aee0
LG		 1138 return 0;
1139}
1140
338ee253 1141static int wm8753_mode1v_set_dai_fmt(struct snd_soc_codec *codec,
1f53aee0
LG		 1142 unsigned int fmt)
1143{
1f53aee0
LG		 1144 u16 clock;
1145
1146 /* set clk source as pcmclk */
776065e3
LPC		 1147 clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb;
1148 snd_soc_write(codec, WM8753_CLOCK, clock);
1f53aee0 1149
338ee253 1150 return wm8753_vdac_adc_set_dai_fmt(codec, fmt);
1f53aee0
LG		 1151}
1152
338ee253 1153static int wm8753_mode1h_set_dai_fmt(struct snd_soc_codec *codec,
1f53aee0
LG		 1154 unsigned int fmt)
1155{
338ee253 1156 return wm8753_hdac_set_dai_fmt(codec, fmt);
1f53aee0
LG		 1157}
1158
338ee253 1159static int wm8753_mode2_set_dai_fmt(struct snd_soc_codec *codec,
1f53aee0
LG		 1160 unsigned int fmt)
1161{
1f53aee0
LG		 1162 u16 clock;
1163
1164 /* set clk source as pcmclk */
776065e3
LPC		 1165 clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb;
1166 snd_soc_write(codec, WM8753_CLOCK, clock);
1f53aee0 1167
338ee253 1168 return wm8753_vdac_adc_set_dai_fmt(codec, fmt);
1f53aee0
LG		 1169}
1170
338ee253 1171static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_codec *codec,
1f53aee0
LG		 1172 unsigned int fmt)
1173{
1f53aee0
LG		 1174 u16 clock;
1175
1176 /* set clk source as mclk */
776065e3
LPC		 1177 clock = snd_soc_read(codec, WM8753_CLOCK) & 0xfffb;
1178 snd_soc_write(codec, WM8753_CLOCK, clock | 0x4);
1f53aee0 1179
338ee253 1180 if (wm8753_hdac_set_dai_fmt(codec, fmt) < 0)
1f53aee0 1181 return -EINVAL;
338ee253 1182 return wm8753_vdac_adc_set_dai_fmt(codec, fmt);
1f53aee0
LG		 1183}
1184
338ee253
LPC		 1185static int wm8753_hifi_write_dai_fmt(struct snd_soc_codec *codec,
1186 unsigned int fmt)
1187{
1188 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1189 int ret = 0;
1190
1191 switch (wm8753->dai_func) {
1192 case 0:
1193 ret = wm8753_mode1h_set_dai_fmt(codec, fmt);
1194 break;
1195 case 1:
1196 ret = wm8753_mode2_set_dai_fmt(codec, fmt);
1197 break;
1198 case 2:
1199 case 3:
1200 ret = wm8753_mode3_4_set_dai_fmt(codec, fmt);
1201 break;
1202 default:
1203 break;
1204 }
1205 if (ret)
1206 return ret;
1207
1208 return wm8753_i2s_set_dai_fmt(codec, fmt);
1209}
1210
1211static int wm8753_hifi_set_dai_fmt(struct snd_soc_dai *codec_dai,
1212 unsigned int fmt)
1213{
1214 struct snd_soc_codec *codec = codec_dai->codec;
1215 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1216
1217 wm8753->hifi_fmt = fmt;
1218
1219 return wm8753_hifi_write_dai_fmt(codec, fmt);
1220};
1221
1222static int wm8753_voice_write_dai_fmt(struct snd_soc_codec *codec,
1223 unsigned int fmt)
1224{
1225 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1226 int ret = 0;
1227
1228 if (wm8753->dai_func != 0)
1229 return 0;
1230
1231 ret = wm8753_mode1v_set_dai_fmt(codec, fmt);
1232 if (ret)
1233 return ret;
1234 ret = wm8753_pcm_set_dai_fmt(codec, fmt);
1235 if (ret)
1236 return ret;
1237
1238 return 0;
1239};
1240
1241static int wm8753_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
1242 unsigned int fmt)
1243{
1244 struct snd_soc_codec *codec = codec_dai->codec;
1245 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1246
1247 wm8753->voice_fmt = fmt;
1248
1249 return wm8753_voice_write_dai_fmt(codec, fmt);
1250};
1251
e550e17f 1252static int wm8753_mute(struct snd_soc_dai *dai, int mute)
1f53aee0
LG		 1253{
1254 struct snd_soc_codec *codec = dai->codec;
776065e3 1255 u16 mute_reg = snd_soc_read(codec, WM8753_DAC) & 0xfff7;
f0fba2ad 1256 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 1257
1258 /* the digital mute covers the HiFi and Voice DAC's on the WM8753.
1259 * make sure we check if they are not both active when we mute */
f0fba2ad
LG		 1260 if (mute && wm8753->dai_func == 1) {
1261 if (!codec->active)
776065e3 1262 snd_soc_write(codec, WM8753_DAC, mute_reg | 0x8);
1f53aee0
LG		 1263 } else {
1264 if (mute)
776065e3 1265 snd_soc_write(codec, WM8753_DAC, mute_reg | 0x8);
1f53aee0 1266 else
776065e3 1267 snd_soc_write(codec, WM8753_DAC, mute_reg);
1f53aee0
LG		 1268 }
1269
1270 return 0;
1271}
1272
0be9898a
MB		 1273static int wm8753_set_bias_level(struct snd_soc_codec *codec,
1274 enum snd_soc_bias_level level)
1f53aee0 1275{
776065e3 1276 u16 pwr_reg = snd_soc_read(codec, WM8753_PWR1) & 0xfe3e;
1f53aee0 1277
0be9898a
MB		 1278 switch (level) {
1279 case SND_SOC_BIAS_ON:
1f53aee0 1280 /* set vmid to 50k and unmute dac */
776065e3 1281 snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x00c0);
1f53aee0 1282 break;
0be9898a 1283 case SND_SOC_BIAS_PREPARE:
1f53aee0 1284 /* set vmid to 5k for quick power up */
776065e3 1285 snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x01c1);
1f53aee0 1286 break;
0be9898a 1287 case SND_SOC_BIAS_STANDBY:
1f53aee0 1288 /* mute dac and set vmid to 500k, enable VREF */
776065e3 1289 snd_soc_write(codec, WM8753_PWR1, pwr_reg | 0x0141);
1f53aee0 1290 break;
0be9898a 1291 case SND_SOC_BIAS_OFF:
776065e3 1292 snd_soc_write(codec, WM8753_PWR1, 0x0001);
1f53aee0
LG		 1293 break;
1294 }
ce6120cc 1295 codec->dapm.bias_level = level;
1f53aee0
LG		 1296 return 0;
1297}
1298
1299#define WM8753_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
60fc684a
MB		 1300 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1301 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1302 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
1f53aee0
LG		 1303
1304#define WM8753_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1305 SNDRV_PCM_FMTBIT_S24_LE)
1306
1307/*
25985edc 1308 * The WM8753 supports up to 4 different and mutually exclusive DAI
1f53aee0
LG		 1309 * configurations. This gives 2 PCM's available for use, hifi and voice.
1310 * NOTE: The Voice PCM cannot play or capture audio to the CPU as it's DAI
1311 * is connected between the wm8753 and a BT codec or GSM modem.
1312 *
1313 * 1. Voice over PCM DAI - HIFI DAC over HIFI DAI
1314 * 2. Voice over HIFI DAI - HIFI disabled
1315 * 3. Voice disabled - HIFI over HIFI
1316 * 4. Voice disabled - HIFI over HIFI, uses voice DAI LRC for capture
1317 */
338ee253 1318static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode = {
6335d055
EM		 1319 .hw_params = wm8753_i2s_hw_params,
1320 .digital_mute = wm8753_mute,
338ee253 1321 .set_fmt = wm8753_hifi_set_dai_fmt,
6335d055
EM		 1322 .set_clkdiv = wm8753_set_dai_clkdiv,
1323 .set_pll = wm8753_set_dai_pll,
1324 .set_sysclk = wm8753_set_dai_sysclk,
1325};
1326
338ee253 1327static struct snd_soc_dai_ops wm8753_dai_ops_voice_mode = {
6335d055
EM		 1328 .hw_params = wm8753_pcm_hw_params,
1329 .digital_mute = wm8753_mute,
338ee253 1330 .set_fmt = wm8753_voice_set_dai_fmt,
6335d055
EM		 1331 .set_clkdiv = wm8753_set_dai_clkdiv,
1332 .set_pll = wm8753_set_dai_pll,
1333 .set_sysclk = wm8753_set_dai_sysclk,
1334};
1335
338ee253 1336static struct snd_soc_dai_driver wm8753_dai[] = {
1f53aee0 1337/* DAI HiFi mode 1 */
f0fba2ad 1338{ .name = "wm8753-hifi",
1f53aee0
LG		 1339 .playback = {
1340 .stream_name = "HiFi Playback",
1341 .channels_min = 1,
1342 .channels_max = 2,
1343 .rates = WM8753_RATES,
338ee253
LPC		 1344 .formats = WM8753_FORMATS
1345 },
1f53aee0
LG		 1346 .capture = { /* dummy for fast DAI switching */
1347 .stream_name = "Capture",
1348 .channels_min = 1,
1349 .channels_max = 2,
1350 .rates = WM8753_RATES,
338ee253
LPC		 1351 .formats = WM8753_FORMATS
1352 },
1353 .ops = &wm8753_dai_ops_hifi_mode,
1f53aee0
LG		 1354},
1355/* DAI Voice mode 1 */
f0fba2ad 1356{ .name = "wm8753-voice",
1f53aee0
LG		 1357 .playback = {
1358 .stream_name = "Voice Playback",
1359 .channels_min = 1,
1360 .channels_max = 1,
1361 .rates = WM8753_RATES,
338ee253
LPC		 1362 .formats = WM8753_FORMATS,
1363 },
1f53aee0
LG		 1364 .capture = {
1365 .stream_name = "Capture",
1366 .channels_min = 1,
1367 .channels_max = 2,
1368 .rates = WM8753_RATES,
338ee253 1369 .formats = WM8753_FORMATS,
9e70c1f0 1370 },
338ee253
LPC		 1371 .ops = &wm8753_dai_ops_voice_mode,
1372},
9e70c1f0 1373};
1f53aee0 1374
1f53aee0
LG		 1375static void wm8753_work(struct work_struct *work)
1376{
ce6120cc
LG		 1377 struct snd_soc_dapm_context *dapm =
1378 container_of(work, struct snd_soc_dapm_context,
1379 delayed_work.work);
1380 struct snd_soc_codec *codec = dapm->codec;
1381 wm8753_set_bias_level(codec, dapm->bias_level);
1f53aee0
LG		 1382}
1383
f0fba2ad 1384static int wm8753_suspend(struct snd_soc_codec *codec, pm_message_t state)
1f53aee0 1385{
0be9898a 1386 wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF);
1f53aee0
LG		 1387 return 0;
1388}
1389
f0fba2ad 1390static int wm8753_resume(struct snd_soc_codec *codec)
1f53aee0 1391{
776065e3 1392 u16 *reg_cache = codec->reg_cache;
1f53aee0 1393 int i;
1f53aee0 1394
1f53aee0 1395 /* Sync reg_cache with the hardware */
776065e3
LPC		 1396 for (i = 1; i < ARRAY_SIZE(wm8753_reg); i++) {
1397 if (i == WM8753_RESET)
1f53aee0 1398 continue;
e611bd82
MB		 1399
1400 /* No point in writing hardware default values back */
776065e3 1401 if (reg_cache[i] == wm8753_reg[i])
e611bd82
MB		 1402 continue;
1403
776065e3 1404 snd_soc_write(codec, i, reg_cache[i]);
1f53aee0
LG		 1405 }
1406
0be9898a 1407 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1f53aee0
LG		 1408
1409 /* charge wm8753 caps */
ce6120cc 1410 if (codec->dapm.suspend_bias_level == SND_SOC_BIAS_ON) {
0be9898a 1411 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
ce6120cc
LG		 1412 codec->dapm.bias_level = SND_SOC_BIAS_ON;
1413 schedule_delayed_work(&codec->dapm.delayed_work,
1f53aee0
LG		 1414 msecs_to_jiffies(caps_charge));
1415 }
1416
1417 return 0;
1418}
1419
f0fba2ad 1420static int wm8753_probe(struct snd_soc_codec *codec)
1f53aee0 1421{
f0fba2ad 1422 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
776065e3 1423 int ret;
1f53aee0 1424
ce6120cc 1425 INIT_DELAYED_WORK(&codec->dapm.delayed_work, wm8753_work);
c2bac160 1426
f0fba2ad
LG		 1427 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8753->control_type);
1428 if (ret < 0) {
1429 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1430 return ret;
c2bac160
MB		 1431 }
1432
c2bac160
MB		 1433 ret = wm8753_reset(codec);
1434 if (ret < 0) {
f0fba2ad
LG		 1435 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1436 return ret;
c2bac160
MB		 1437 }
1438
f0fba2ad
LG		 1439 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1440 wm8753->dai_func = 0;
1441
c2bac160
MB		 1442 /* charge output caps */
1443 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
ce6120cc 1444 schedule_delayed_work(&codec->dapm.delayed_work,
c2bac160
MB		 1445 msecs_to_jiffies(caps_charge));
1446
1447 /* set the update bits */
776065e3
LPC		 1448 snd_soc_update_bits(codec, WM8753_LDAC, 0x0100, 0x0100);
1449 snd_soc_update_bits(codec, WM8753_RDAC, 0x0100, 0x0100);
21d17dd2
AL		 1450 snd_soc_update_bits(codec, WM8753_LADC, 0x0100, 0x0100);
1451 snd_soc_update_bits(codec, WM8753_RADC, 0x0100, 0x0100);
776065e3
LPC		 1452 snd_soc_update_bits(codec, WM8753_LOUT1V, 0x0100, 0x0100);
1453 snd_soc_update_bits(codec, WM8753_ROUT1V, 0x0100, 0x0100);
1454 snd_soc_update_bits(codec, WM8753_LOUT2V, 0x0100, 0x0100);
1455 snd_soc_update_bits(codec, WM8753_ROUT2V, 0x0100, 0x0100);
1456 snd_soc_update_bits(codec, WM8753_LINVOL, 0x0100, 0x0100);
1457 snd_soc_update_bits(codec, WM8753_RINVOL, 0x0100, 0x0100);
c2bac160 1458
c2bac160 1459 return 0;
c2bac160
MB		 1460}
1461
f0fba2ad
LG		 1462/* power down chip */
1463static int wm8753_remove(struct snd_soc_codec *codec)
c2bac160 1464{
fdea0571 1465 flush_delayed_work_sync(&codec->dapm.delayed_work);
f0fba2ad
LG		 1466 wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF);
1467
1468 return 0;
c2bac160
MB		 1469}
1470
f0fba2ad
LG		 1471static struct snd_soc_codec_driver soc_codec_dev_wm8753 = {
1472 .probe = wm8753_probe,
1473 .remove = wm8753_remove,
1474 .suspend = wm8753_suspend,
1475 .resume = wm8753_resume,
1476 .set_bias_level = wm8753_set_bias_level,
e5eec34c 1477 .reg_cache_size = ARRAY_SIZE(wm8753_reg),
f0fba2ad
LG		 1478 .reg_word_size = sizeof(u16),
1479 .reg_cache_default = wm8753_reg,
56a926dd
MB		 1480
1481 .controls = wm8753_snd_controls,
1482 .num_controls = ARRAY_SIZE(wm8753_snd_controls),
1483 .dapm_widgets = wm8753_dapm_widgets,
1484 .num_dapm_widgets = ARRAY_SIZE(wm8753_dapm_widgets),
1485 .dapm_routes = wm8753_dapm_routes,
1486 .num_dapm_routes = ARRAY_SIZE(wm8753_dapm_routes),
f0fba2ad 1487};
69e169da 1488
70e14122
MB		 1489static const struct of_device_id wm8753_of_match[] = {
1490 { .compatible = "wlf,wm8753", },
1491 { }
1492};
1493MODULE_DEVICE_TABLE(of, wm8753_of_match);
1494
f0fba2ad
LG		 1495#if defined(CONFIG_SPI_MASTER)
1496static int __devinit wm8753_spi_probe(struct spi_device *spi)
69e169da 1497{
c2bac160 1498 struct wm8753_priv *wm8753;
f0fba2ad 1499 int ret;
69e169da 1500
c2bac160
MB		 1501 wm8753 = kzalloc(sizeof(struct wm8753_priv), GFP_KERNEL);
1502 if (wm8753 == NULL)
1503 return -ENOMEM;
69e169da 1504
f0fba2ad
LG		 1505 wm8753->control_type = SND_SOC_SPI;
1506 spi_set_drvdata(spi, wm8753);
c2bac160 1507
f0fba2ad
LG		 1508 ret = snd_soc_register_codec(&spi->dev,
1509 &soc_codec_dev_wm8753, wm8753_dai, ARRAY_SIZE(wm8753_dai));
1510 if (ret < 0)
1511 kfree(wm8753);
1512 return ret;
69e169da
MB		 1513}
1514
f0fba2ad 1515static int __devexit wm8753_spi_remove(struct spi_device *spi)
69e169da 1516{
f0fba2ad
LG		 1517 snd_soc_unregister_codec(&spi->dev);
1518 kfree(spi_get_drvdata(spi));
1519 return 0;
69e169da
MB		 1520}
1521
f0fba2ad 1522static struct spi_driver wm8753_spi_driver = {
69e169da 1523 .driver = {
63010634 1524 .name = "wm8753",
f0fba2ad 1525 .owner = THIS_MODULE,
70e14122 1526 .of_match_table = wm8753_of_match,
69e169da 1527 },
f0fba2ad
LG		 1528 .probe = wm8753_spi_probe,
1529 .remove = __devexit_p(wm8753_spi_remove),
69e169da 1530};
f0fba2ad 1531#endif /* CONFIG_SPI_MASTER */
69e169da 1532
f0fba2ad
LG		 1533#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1534static __devinit int wm8753_i2c_probe(struct i2c_client *i2c,
1535 const struct i2c_device_id *id)
69e169da 1536{
c2bac160 1537 struct wm8753_priv *wm8753;
f0fba2ad 1538 int ret;
c2bac160
MB		 1539
1540 wm8753 = kzalloc(sizeof(struct wm8753_priv), GFP_KERNEL);
1541 if (wm8753 == NULL)
1542 return -ENOMEM;
69e169da 1543
f0fba2ad 1544 i2c_set_clientdata(i2c, wm8753);
f0fba2ad 1545 wm8753->control_type = SND_SOC_I2C;
69e169da 1546
f0fba2ad
LG		 1547 ret = snd_soc_register_codec(&i2c->dev,
1548 &soc_codec_dev_wm8753, wm8753_dai, ARRAY_SIZE(wm8753_dai));
1549 if (ret < 0)
1550 kfree(wm8753);
1551 return ret;
69e169da
MB		 1552}
1553
f0fba2ad 1554static __devexit int wm8753_i2c_remove(struct i2c_client *client)
69e169da 1555{
f0fba2ad
LG		 1556 snd_soc_unregister_codec(&client->dev);
1557 kfree(i2c_get_clientdata(client));
69e169da
MB		 1558 return 0;
1559}
1560
f0fba2ad
LG		 1561static const struct i2c_device_id wm8753_i2c_id[] = {
1562 { "wm8753", 0 },
1563 { }
1564};
1565MODULE_DEVICE_TABLE(i2c, wm8753_i2c_id);
1566
1567static struct i2c_driver wm8753_i2c_driver = {
69e169da 1568 .driver = {
63010634 1569 .name = "wm8753",
f0fba2ad 1570 .owner = THIS_MODULE,
70e14122 1571 .of_match_table = wm8753_of_match,
69e169da 1572 },
f0fba2ad
LG		 1573 .probe = wm8753_i2c_probe,
1574 .remove = __devexit_p(wm8753_i2c_remove),
1575 .id_table = wm8753_i2c_id,
69e169da
MB		 1576};
1577#endif
1578
c9b3a40f 1579static int __init wm8753_modinit(void)
64089b84 1580{
f0fba2ad 1581 int ret = 0;
c2bac160
MB		 1582#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1583 ret = i2c_add_driver(&wm8753_i2c_driver);
f0fba2ad
LG		 1584 if (ret != 0) {
1585 printk(KERN_ERR "Failed to register wm8753 I2C driver: %d\n",
1586 ret);
1587 }
c2bac160
MB		 1588#endif
1589#if defined(CONFIG_SPI_MASTER)
1590 ret = spi_register_driver(&wm8753_spi_driver);
f0fba2ad
LG		 1591 if (ret != 0) {
1592 printk(KERN_ERR "Failed to register wm8753 SPI driver: %d\n",
1593 ret);
1594 }
c2bac160 1595#endif
f0fba2ad 1596 return ret;
64089b84
MB		 1597}
1598module_init(wm8753_modinit);
1599
1600static void __exit wm8753_exit(void)
1601{
c2bac160
MB		 1602#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1603 i2c_del_driver(&wm8753_i2c_driver);
1604#endif
1605#if defined(CONFIG_SPI_MASTER)
1606 spi_unregister_driver(&wm8753_spi_driver);
1607#endif
64089b84
MB		 1608}
1609module_exit(wm8753_exit);
1610
1f53aee0
LG		 1611MODULE_DESCRIPTION("ASoC WM8753 driver");
1612MODULE_AUTHOR("Liam Girdwood");
1613MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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