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ASoC: codecs: wm9090: Fix register cache incoherency
[deliverable/linux.git] / sound / soc / codecs / wm8753.c
CommitLineData
1f53aee0
LG		 1/*
2 * wm8753.c -- WM8753 ALSA Soc Audio driver
3 *
4 * Copyright 2003 Wolfson Microelectronics PLC.
d331124d 5 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
1f53aee0
LG		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * Notes:
13 * The WM8753 is a low power, high quality stereo codec with integrated PCM
14 * codec designed for portable digital telephony applications.
15 *
16 * Dual DAI:-
17 *
18 * This driver support 2 DAI PCM's. This makes the default PCM available for
19 * HiFi audio (e.g. MP3, ogg) playback/capture and the other PCM available for
20 * voice.
21 *
22 * Please note that the voice PCM can be connected directly to a Bluetooth
23 * codec or GSM modem and thus cannot be read or written to, although it is
24 * available to be configured with snd_hw_params(), etc and kcontrols in the
25 * normal alsa manner.
26 *
27 * Fast DAI switching:-
28 *
29 * The driver can now fast switch between the DAI configurations via a
30 * an alsa kcontrol. This allows the PCM to remain open.
31 *
32 */
33
34#include <linux/module.h>
35#include <linux/moduleparam.h>
1f53aee0
LG		 36#include <linux/kernel.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
41#include <linux/platform_device.h>
dd0c0c80 42#include <linux/spi/spi.h>
5a0e3ad6 43#include <linux/slab.h>
1f53aee0
LG		 44#include <sound/core.h>
45#include <sound/pcm.h>
46#include <sound/pcm_params.h>
47#include <sound/soc.h>
48#include <sound/soc-dapm.h>
49#include <sound/initval.h>
2d6a4ac9 50#include <sound/tlv.h>
1f53aee0
LG		 51#include <asm/div64.h>
52
53#include "wm8753.h"
54
1f53aee0
LG		 55static int caps_charge = 2000;
56module_param(caps_charge, int, 0);
57MODULE_PARM_DESC(caps_charge, "WM8753 cap charge time (msecs)");
58
59static void wm8753_set_dai_mode(struct snd_soc_codec *codec,
f0fba2ad 60 struct snd_soc_dai *dai, unsigned int hifi);
1f53aee0 61
1f53aee0
LG		 62/*
63 * wm8753 register cache
64 * We can't read the WM8753 register space when we
65 * are using 2 wire for device control, so we cache them instead.
66 */
67static const u16 wm8753_reg[] = {
68 0x0008, 0x0000, 0x000a, 0x000a,
69 0x0033, 0x0000, 0x0007, 0x00ff,
70 0x00ff, 0x000f, 0x000f, 0x007b,
71 0x0000, 0x0032, 0x0000, 0x00c3,
72 0x00c3, 0x00c0, 0x0000, 0x0000,
73 0x0000, 0x0000, 0x0000, 0x0000,
74 0x0000, 0x0000, 0x0000, 0x0000,
75 0x0000, 0x0000, 0x0000, 0x0055,
76 0x0005, 0x0050, 0x0055, 0x0050,
77 0x0055, 0x0050, 0x0055, 0x0079,
78 0x0079, 0x0079, 0x0079, 0x0079,
79 0x0000, 0x0000, 0x0000, 0x0000,
80 0x0097, 0x0097, 0x0000, 0x0004,
81 0x0000, 0x0083, 0x0024, 0x01ba,
82 0x0000, 0x0083, 0x0024, 0x01ba,
637a935a 83 0x0000, 0x0000, 0x0000
1f53aee0
LG		 84};
85
c2bac160
MB		 86/* codec private data */
87struct wm8753_priv {
f0fba2ad 88 enum snd_soc_control_type control_type;
c2bac160
MB		 89 unsigned int sysclk;
90 unsigned int pcmclk;
c2bac160 91 u16 reg_cache[ARRAY_SIZE(wm8753_reg)];
f0fba2ad 92 int dai_func;
c2bac160
MB		 93};
94
1f53aee0
LG		 95/*
96 * read wm8753 register cache
97 */
98static inline unsigned int wm8753_read_reg_cache(struct snd_soc_codec *codec,
99 unsigned int reg)
100{
101 u16 *cache = codec->reg_cache;
91432e97 102 if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1))
1f53aee0
LG		 103 return -1;
104 return cache[reg - 1];
105}
106
107/*
108 * write wm8753 register cache
109 */
110static inline void wm8753_write_reg_cache(struct snd_soc_codec *codec,
111 unsigned int reg, unsigned int value)
112{
113 u16 *cache = codec->reg_cache;
91432e97 114 if (reg < 1 || reg >= (ARRAY_SIZE(wm8753_reg) + 1))
1f53aee0
LG		 115 return;
116 cache[reg - 1] = value;
117}
118
119/*
120 * write to the WM8753 register space
121 */
122static int wm8753_write(struct snd_soc_codec *codec, unsigned int reg,
123 unsigned int value)
124{
125 u8 data[2];
126
127 /* data is
128 * D15..D9 WM8753 register offset
129 * D8...D0 register data
130 */
131 data[0] = (reg << 1) | ((value >> 8) & 0x0001);
132 data[1] = value & 0x00ff;
133
60fc684a 134 wm8753_write_reg_cache(codec, reg, value);
1f53aee0
LG		 135 if (codec->hw_write(codec->control_data, data, 2) == 2)
136 return 0;
137 else
138 return -EIO;
139}
140
141#define wm8753_reset(c) wm8753_write(c, WM8753_RESET, 0)
142
143/*
144 * WM8753 Controls
145 */
146static const char *wm8753_base[] = {"Linear Control", "Adaptive Boost"};
147static const char *wm8753_base_filter[] =
148 {"130Hz @ 48kHz", "200Hz @ 48kHz", "100Hz @ 16kHz", "400Hz @ 48kHz",
149 "100Hz @ 8kHz", "200Hz @ 8kHz"};
150static const char *wm8753_treble[] = {"8kHz", "4kHz"};
151static const char *wm8753_alc_func[] = {"Off", "Right", "Left", "Stereo"};
152static const char *wm8753_ng_type[] = {"Constant PGA Gain", "Mute ADC Output"};
153static const char *wm8753_3d_func[] = {"Capture", "Playback"};
154static const char *wm8753_3d_uc[] = {"2.2kHz", "1.5kHz"};
155static const char *wm8753_3d_lc[] = {"200Hz", "500Hz"};
156static const char *wm8753_deemp[] = {"None", "32kHz", "44.1kHz", "48kHz"};
157static const char *wm8753_mono_mix[] = {"Stereo", "Left", "Right", "Mono"};
158static const char *wm8753_dac_phase[] = {"Non Inverted", "Inverted"};
159static const char *wm8753_line_mix[] = {"Line 1 + 2", "Line 1 - 2",
160 "Line 1", "Line 2"};
161static const char *wm8753_mono_mux[] = {"Line Mix", "Rx Mix"};
162static const char *wm8753_right_mux[] = {"Line 2", "Rx Mix"};
163static const char *wm8753_left_mux[] = {"Line 1", "Rx Mix"};
164static const char *wm8753_rxmsel[] = {"RXP - RXN", "RXP + RXN", "RXP", "RXN"};
165static const char *wm8753_sidetone_mux[] = {"Left PGA", "Mic 1", "Mic 2",
166 "Right PGA"};
167static const char *wm8753_mono2_src[] = {"Inverted Mono 1", "Left", "Right",
168 "Left + Right"};
169static const char *wm8753_out3[] = {"VREF", "ROUT2", "Left + Right"};
170static const char *wm8753_out4[] = {"VREF", "Capture ST", "LOUT2"};
171static const char *wm8753_radcsel[] = {"PGA", "Line or RXP-RXN", "Sidetone"};
172static const char *wm8753_ladcsel[] = {"PGA", "Line or RXP-RXN", "Line"};
173static const char *wm8753_mono_adc[] = {"Stereo", "Analogue Mix Left",
174 "Analogue Mix Right", "Digital Mono Mix"};
175static const char *wm8753_adc_hp[] = {"3.4Hz @ 48kHz", "82Hz @ 16k",
176 "82Hz @ 8kHz", "170Hz @ 8kHz"};
177static const char *wm8753_adc_filter[] = {"HiFi", "Voice"};
178static const char *wm8753_mic_sel[] = {"Mic 1", "Mic 2", "Mic 3"};
179static const char *wm8753_dai_mode[] = {"DAI 0", "DAI 1", "DAI 2", "DAI 3"};
180static const char *wm8753_dat_sel[] = {"Stereo", "Left ADC", "Right ADC",
181 "Channel Swap"};
ae092c9e 182static const char *wm8753_rout2_phase[] = {"Non Inverted", "Inverted"};
1f53aee0
LG		 183
184static const struct soc_enum wm8753_enum[] = {
185SOC_ENUM_SINGLE(WM8753_BASS, 7, 2, wm8753_base),
186SOC_ENUM_SINGLE(WM8753_BASS, 4, 6, wm8753_base_filter),
187SOC_ENUM_SINGLE(WM8753_TREBLE, 6, 2, wm8753_treble),
188SOC_ENUM_SINGLE(WM8753_ALC1, 7, 4, wm8753_alc_func),
189SOC_ENUM_SINGLE(WM8753_NGATE, 1, 2, wm8753_ng_type),
190SOC_ENUM_SINGLE(WM8753_3D, 7, 2, wm8753_3d_func),
191SOC_ENUM_SINGLE(WM8753_3D, 6, 2, wm8753_3d_uc),
192SOC_ENUM_SINGLE(WM8753_3D, 5, 2, wm8753_3d_lc),
193SOC_ENUM_SINGLE(WM8753_DAC, 1, 4, wm8753_deemp),
194SOC_ENUM_SINGLE(WM8753_DAC, 4, 4, wm8753_mono_mix),
195SOC_ENUM_SINGLE(WM8753_DAC, 6, 2, wm8753_dac_phase),
196SOC_ENUM_SINGLE(WM8753_INCTL1, 3, 4, wm8753_line_mix),
197SOC_ENUM_SINGLE(WM8753_INCTL1, 2, 2, wm8753_mono_mux),
198SOC_ENUM_SINGLE(WM8753_INCTL1, 1, 2, wm8753_right_mux),
199SOC_ENUM_SINGLE(WM8753_INCTL1, 0, 2, wm8753_left_mux),
200SOC_ENUM_SINGLE(WM8753_INCTL2, 6, 4, wm8753_rxmsel),
201SOC_ENUM_SINGLE(WM8753_INCTL2, 4, 4, wm8753_sidetone_mux),
202SOC_ENUM_SINGLE(WM8753_OUTCTL, 7, 4, wm8753_mono2_src),
203SOC_ENUM_SINGLE(WM8753_OUTCTL, 0, 3, wm8753_out3),
204SOC_ENUM_SINGLE(WM8753_ADCTL2, 7, 3, wm8753_out4),
205SOC_ENUM_SINGLE(WM8753_ADCIN, 2, 3, wm8753_radcsel),
206SOC_ENUM_SINGLE(WM8753_ADCIN, 0, 3, wm8753_ladcsel),
207SOC_ENUM_SINGLE(WM8753_ADCIN, 4, 4, wm8753_mono_adc),
208SOC_ENUM_SINGLE(WM8753_ADC, 2, 4, wm8753_adc_hp),
209SOC_ENUM_SINGLE(WM8753_ADC, 4, 2, wm8753_adc_filter),
210SOC_ENUM_SINGLE(WM8753_MICBIAS, 6, 3, wm8753_mic_sel),
211SOC_ENUM_SINGLE(WM8753_IOCTL, 2, 4, wm8753_dai_mode),
212SOC_ENUM_SINGLE(WM8753_ADC, 7, 4, wm8753_dat_sel),
ae092c9e 213SOC_ENUM_SINGLE(WM8753_OUTCTL, 2, 2, wm8753_rout2_phase),
1f53aee0
LG		 214};
215
216
217static int wm8753_get_dai(struct snd_kcontrol *kcontrol,
218 struct snd_ctl_elem_value *ucontrol)
219{
220 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
221 int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL);
222
223 ucontrol->value.integer.value[0] = (mode & 0xc) >> 2;
224 return 0;
225}
226
227static int wm8753_set_dai(struct snd_kcontrol *kcontrol,
228 struct snd_ctl_elem_value *ucontrol)
229{
230 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
231 int mode = wm8753_read_reg_cache(codec, WM8753_IOCTL);
f0fba2ad 232 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0 233
60fc684a 234 if (((mode & 0xc) >> 2) == ucontrol->value.integer.value[0])
1f53aee0
LG		 235 return 0;
236
237 mode &= 0xfff3;
238 mode |= (ucontrol->value.integer.value[0] << 2);
239
f0fba2ad 240 wm8753->dai_func = ucontrol->value.integer.value[0];
1f53aee0
LG		 241 return 1;
242}
243
2cc8c609
MM		 244static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 300, 0);
245static const DECLARE_TLV_DB_SCALE(mic_preamp_tlv, 1200, 600, 0);
246static const DECLARE_TLV_DB_SCALE(adc_tlv, -9750, 50, 1);
247static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
248static const unsigned int out_tlv[] = {
249 TLV_DB_RANGE_HEAD(2),
250 /* 0000000 - 0101111 = "Analogue mute" */
251 0, 48, TLV_DB_SCALE_ITEM(-25500, 0, 0),
252 48, 127, TLV_DB_SCALE_ITEM(-7300, 100, 0),
253};
254static const DECLARE_TLV_DB_SCALE(mix_tlv, -1500, 300, 0);
255static const DECLARE_TLV_DB_SCALE(voice_mix_tlv, -1200, 300, 0);
256static const DECLARE_TLV_DB_SCALE(pga_tlv, -1725, 75, 0);
2d6a4ac9 257
1f53aee0 258static const struct snd_kcontrol_new wm8753_snd_controls[] = {
2cc8c609
MM		 259SOC_DOUBLE_R_TLV("PCM Volume", WM8753_LDAC, WM8753_RDAC, 0, 255, 0, dac_tlv),
260
261SOC_DOUBLE_R_TLV("ADC Capture Volume", WM8753_LADC, WM8753_RADC, 0, 255, 0,
262 adc_tlv),
263
264SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8753_LOUT1V, WM8753_ROUT1V,
265 0, 127, 0, out_tlv),
266SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8753_LOUT2V, WM8753_ROUT2V, 0,
267 127, 0, out_tlv),
268
269SOC_SINGLE_TLV("Mono Playback Volume", WM8753_MOUTV, 0, 127, 0, out_tlv),
270
271SOC_DOUBLE_R_TLV("Bypass Playback Volume", WM8753_LOUTM1, WM8753_ROUTM1, 4, 7,
272 1, mix_tlv),
273SOC_DOUBLE_R_TLV("Sidetone Playback Volume", WM8753_LOUTM2, WM8753_ROUTM2, 4,
274 7, 1, mix_tlv),
275SOC_DOUBLE_R_TLV("Voice Playback Volume", WM8753_LOUTM2, WM8753_ROUTM2, 0, 7,
276 1, voice_mix_tlv),
277
278SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8753_LOUT1V, WM8753_ROUT1V, 7,
279 1, 0),
280SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8753_LOUT2V, WM8753_ROUT2V, 7,
281 1, 0),
282
283SOC_SINGLE_TLV("Mono Bypass Playback Volume", WM8753_MOUTM1, 4, 7, 1, mix_tlv),
284SOC_SINGLE_TLV("Mono Sidetone Playback Volume", WM8753_MOUTM2, 4, 7, 1,
285 mix_tlv),
286SOC_SINGLE_TLV("Mono Voice Playback Volume", WM8753_MOUTM2, 0, 7, 1,
287 voice_mix_tlv),
1f53aee0
LG		 288SOC_SINGLE("Mono Playback ZC Switch", WM8753_MOUTV, 7, 1, 0),
289
290SOC_ENUM("Bass Boost", wm8753_enum[0]),
291SOC_ENUM("Bass Filter", wm8753_enum[1]),
292SOC_SINGLE("Bass Volume", WM8753_BASS, 0, 15, 1),
293
294SOC_SINGLE("Treble Volume", WM8753_TREBLE, 0, 15, 1),
295SOC_ENUM("Treble Cut-off", wm8753_enum[2]),
296
2cc8c609
MM		 297SOC_DOUBLE_TLV("Sidetone Capture Volume", WM8753_RECMIX1, 0, 4, 7, 1,
298 rec_mix_tlv),
299SOC_SINGLE_TLV("Voice Sidetone Capture Volume", WM8753_RECMIX2, 0, 7, 1,
300 rec_mix_tlv),
1f53aee0 301
2cc8c609
MM		 302SOC_DOUBLE_R_TLV("Capture Volume", WM8753_LINVOL, WM8753_RINVOL, 0, 63, 0,
303 pga_tlv),
1f53aee0
LG		 304SOC_DOUBLE_R("Capture ZC Switch", WM8753_LINVOL, WM8753_RINVOL, 6, 1, 0),
305SOC_DOUBLE_R("Capture Switch", WM8753_LINVOL, WM8753_RINVOL, 7, 1, 1),
306
307SOC_ENUM("Capture Filter Select", wm8753_enum[23]),
308SOC_ENUM("Capture Filter Cut-off", wm8753_enum[24]),
309SOC_SINGLE("Capture Filter Switch", WM8753_ADC, 0, 1, 1),
310
311SOC_SINGLE("ALC Capture Target Volume", WM8753_ALC1, 0, 7, 0),
312SOC_SINGLE("ALC Capture Max Volume", WM8753_ALC1, 4, 7, 0),
313SOC_ENUM("ALC Capture Function", wm8753_enum[3]),
314SOC_SINGLE("ALC Capture ZC Switch", WM8753_ALC2, 8, 1, 0),
315SOC_SINGLE("ALC Capture Hold Time", WM8753_ALC2, 0, 15, 1),
316SOC_SINGLE("ALC Capture Decay Time", WM8753_ALC3, 4, 15, 1),
317SOC_SINGLE("ALC Capture Attack Time", WM8753_ALC3, 0, 15, 0),
318SOC_SINGLE("ALC Capture NG Threshold", WM8753_NGATE, 3, 31, 0),
319SOC_ENUM("ALC Capture NG Type", wm8753_enum[4]),
320SOC_SINGLE("ALC Capture NG Switch", WM8753_NGATE, 0, 1, 0),
321
322SOC_ENUM("3D Function", wm8753_enum[5]),
323SOC_ENUM("3D Upper Cut-off", wm8753_enum[6]),
324SOC_ENUM("3D Lower Cut-off", wm8753_enum[7]),
325SOC_SINGLE("3D Volume", WM8753_3D, 1, 15, 0),
326SOC_SINGLE("3D Switch", WM8753_3D, 0, 1, 0),
327
328SOC_SINGLE("Capture 6dB Attenuate", WM8753_ADCTL1, 2, 1, 0),
329SOC_SINGLE("Playback 6dB Attenuate", WM8753_ADCTL1, 1, 1, 0),
330
331SOC_ENUM("De-emphasis", wm8753_enum[8]),
332SOC_ENUM("Playback Mono Mix", wm8753_enum[9]),
333SOC_ENUM("Playback Phase", wm8753_enum[10]),
334
2cc8c609
MM		 335SOC_SINGLE_TLV("Mic2 Capture Volume", WM8753_INCTL1, 7, 3, 0, mic_preamp_tlv),
336SOC_SINGLE_TLV("Mic1 Capture Volume", WM8753_INCTL1, 5, 3, 0, mic_preamp_tlv),
1f53aee0
LG		 337
338SOC_ENUM_EXT("DAI Mode", wm8753_enum[26], wm8753_get_dai, wm8753_set_dai),
339
340SOC_ENUM("ADC Data Select", wm8753_enum[27]),
ae092c9e 341SOC_ENUM("ROUT2 Phase", wm8753_enum[28]),
1f53aee0
LG		 342};
343
1f53aee0
LG		 344/*
345 * _DAPM_ Controls
346 */
347
348/* Left Mixer */
349static const struct snd_kcontrol_new wm8753_left_mixer_controls[] = {
350SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_LOUTM2, 8, 1, 0),
351SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_LOUTM2, 7, 1, 0),
352SOC_DAPM_SINGLE("Left Playback Switch", WM8753_LOUTM1, 8, 1, 0),
353SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_LOUTM1, 7, 1, 0),
354};
355
356/* Right mixer */
357static const struct snd_kcontrol_new wm8753_right_mixer_controls[] = {
358SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_ROUTM2, 8, 1, 0),
359SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_ROUTM2, 7, 1, 0),
360SOC_DAPM_SINGLE("Right Playback Switch", WM8753_ROUTM1, 8, 1, 0),
361SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_ROUTM1, 7, 1, 0),
362};
363
364/* Mono mixer */
365static const struct snd_kcontrol_new wm8753_mono_mixer_controls[] = {
366SOC_DAPM_SINGLE("Left Playback Switch", WM8753_MOUTM1, 8, 1, 0),
367SOC_DAPM_SINGLE("Right Playback Switch", WM8753_MOUTM2, 8, 1, 0),
368SOC_DAPM_SINGLE("Voice Playback Switch", WM8753_MOUTM2, 3, 1, 0),
369SOC_DAPM_SINGLE("Sidetone Playback Switch", WM8753_MOUTM2, 7, 1, 0),
370SOC_DAPM_SINGLE("Bypass Playback Switch", WM8753_MOUTM1, 7, 1, 0),
371};
372
373/* Mono 2 Mux */
374static const struct snd_kcontrol_new wm8753_mono2_controls =
375SOC_DAPM_ENUM("Route", wm8753_enum[17]);
376
377/* Out 3 Mux */
378static const struct snd_kcontrol_new wm8753_out3_controls =
379SOC_DAPM_ENUM("Route", wm8753_enum[18]);
380
381/* Out 4 Mux */
382static const struct snd_kcontrol_new wm8753_out4_controls =
383SOC_DAPM_ENUM("Route", wm8753_enum[19]);
384
385/* ADC Mono Mix */
386static const struct snd_kcontrol_new wm8753_adc_mono_controls =
387SOC_DAPM_ENUM("Route", wm8753_enum[22]);
388
389/* Record mixer */
390static const struct snd_kcontrol_new wm8753_record_mixer_controls[] = {
391SOC_DAPM_SINGLE("Voice Capture Switch", WM8753_RECMIX2, 3, 1, 0),
392SOC_DAPM_SINGLE("Left Capture Switch", WM8753_RECMIX1, 3, 1, 0),
393SOC_DAPM_SINGLE("Right Capture Switch", WM8753_RECMIX1, 7, 1, 0),
394};
395
396/* Left ADC mux */
397static const struct snd_kcontrol_new wm8753_adc_left_controls =
398SOC_DAPM_ENUM("Route", wm8753_enum[21]);
399
400/* Right ADC mux */
401static const struct snd_kcontrol_new wm8753_adc_right_controls =
402SOC_DAPM_ENUM("Route", wm8753_enum[20]);
403
404/* MIC mux */
405static const struct snd_kcontrol_new wm8753_mic_mux_controls =
406SOC_DAPM_ENUM("Route", wm8753_enum[16]);
407
408/* ALC mixer */
409static const struct snd_kcontrol_new wm8753_alc_mixer_controls[] = {
410SOC_DAPM_SINGLE("Line Capture Switch", WM8753_INCTL2, 3, 1, 0),
411SOC_DAPM_SINGLE("Mic2 Capture Switch", WM8753_INCTL2, 2, 1, 0),
412SOC_DAPM_SINGLE("Mic1 Capture Switch", WM8753_INCTL2, 1, 1, 0),
413SOC_DAPM_SINGLE("Rx Capture Switch", WM8753_INCTL2, 0, 1, 0),
414};
415
416/* Left Line mux */
417static const struct snd_kcontrol_new wm8753_line_left_controls =
418SOC_DAPM_ENUM("Route", wm8753_enum[14]);
419
420/* Right Line mux */
421static const struct snd_kcontrol_new wm8753_line_right_controls =
422SOC_DAPM_ENUM("Route", wm8753_enum[13]);
423
424/* Mono Line mux */
425static const struct snd_kcontrol_new wm8753_line_mono_controls =
426SOC_DAPM_ENUM("Route", wm8753_enum[12]);
427
428/* Line mux and mixer */
429static const struct snd_kcontrol_new wm8753_line_mux_mix_controls =
430SOC_DAPM_ENUM("Route", wm8753_enum[11]);
431
432/* Rx mux and mixer */
433static const struct snd_kcontrol_new wm8753_rx_mux_mix_controls =
434SOC_DAPM_ENUM("Route", wm8753_enum[15]);
435
436/* Mic Selector Mux */
437static const struct snd_kcontrol_new wm8753_mic_sel_mux_controls =
438SOC_DAPM_ENUM("Route", wm8753_enum[25]);
439
440static const struct snd_soc_dapm_widget wm8753_dapm_widgets[] = {
441SND_SOC_DAPM_MICBIAS("Mic Bias", WM8753_PWR1, 5, 0),
442SND_SOC_DAPM_MIXER("Left Mixer", WM8753_PWR4, 0, 0,
443 &wm8753_left_mixer_controls[0], ARRAY_SIZE(wm8753_left_mixer_controls)),
444SND_SOC_DAPM_PGA("Left Out 1", WM8753_PWR3, 8, 0, NULL, 0),
445SND_SOC_DAPM_PGA("Left Out 2", WM8753_PWR3, 6, 0, NULL, 0),
446SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback", WM8753_PWR1, 3, 0),
447SND_SOC_DAPM_OUTPUT("LOUT1"),
448SND_SOC_DAPM_OUTPUT("LOUT2"),
449SND_SOC_DAPM_MIXER("Right Mixer", WM8753_PWR4, 1, 0,
450 &wm8753_right_mixer_controls[0], ARRAY_SIZE(wm8753_right_mixer_controls)),
451SND_SOC_DAPM_PGA("Right Out 1", WM8753_PWR3, 7, 0, NULL, 0),
452SND_SOC_DAPM_PGA("Right Out 2", WM8753_PWR3, 5, 0, NULL, 0),
453SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback", WM8753_PWR1, 2, 0),
454SND_SOC_DAPM_OUTPUT("ROUT1"),
455SND_SOC_DAPM_OUTPUT("ROUT2"),
456SND_SOC_DAPM_MIXER("Mono Mixer", WM8753_PWR4, 2, 0,
457 &wm8753_mono_mixer_controls[0], ARRAY_SIZE(wm8753_mono_mixer_controls)),
458SND_SOC_DAPM_PGA("Mono Out 1", WM8753_PWR3, 2, 0, NULL, 0),
459SND_SOC_DAPM_PGA("Mono Out 2", WM8753_PWR3, 1, 0, NULL, 0),
460SND_SOC_DAPM_DAC("Voice DAC", "Voice Playback", WM8753_PWR1, 4, 0),
461SND_SOC_DAPM_OUTPUT("MONO1"),
462SND_SOC_DAPM_MUX("Mono 2 Mux", SND_SOC_NOPM, 0, 0, &wm8753_mono2_controls),
463SND_SOC_DAPM_OUTPUT("MONO2"),
464SND_SOC_DAPM_MIXER("Out3 Left + Right", -1, 0, 0, NULL, 0),
465SND_SOC_DAPM_MUX("Out3 Mux", SND_SOC_NOPM, 0, 0, &wm8753_out3_controls),
466SND_SOC_DAPM_PGA("Out 3", WM8753_PWR3, 4, 0, NULL, 0),
467SND_SOC_DAPM_OUTPUT("OUT3"),
468SND_SOC_DAPM_MUX("Out4 Mux", SND_SOC_NOPM, 0, 0, &wm8753_out4_controls),
469SND_SOC_DAPM_PGA("Out 4", WM8753_PWR3, 3, 0, NULL, 0),
470SND_SOC_DAPM_OUTPUT("OUT4"),
471SND_SOC_DAPM_MIXER("Playback Mixer", WM8753_PWR4, 3, 0,
472 &wm8753_record_mixer_controls[0],
473 ARRAY_SIZE(wm8753_record_mixer_controls)),
474SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8753_PWR2, 3, 0),
475SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8753_PWR2, 2, 0),
476SND_SOC_DAPM_MUX("Capture Left Mixer", SND_SOC_NOPM, 0, 0,
477 &wm8753_adc_mono_controls),
478SND_SOC_DAPM_MUX("Capture Right Mixer", SND_SOC_NOPM, 0, 0,
479 &wm8753_adc_mono_controls),
480SND_SOC_DAPM_MUX("Capture Left Mux", SND_SOC_NOPM, 0, 0,
481 &wm8753_adc_left_controls),
482SND_SOC_DAPM_MUX("Capture Right Mux", SND_SOC_NOPM, 0, 0,
483 &wm8753_adc_right_controls),
484SND_SOC_DAPM_MUX("Mic Sidetone Mux", SND_SOC_NOPM, 0, 0,
485 &wm8753_mic_mux_controls),
486SND_SOC_DAPM_PGA("Left Capture Volume", WM8753_PWR2, 5, 0, NULL, 0),
487SND_SOC_DAPM_PGA("Right Capture Volume", WM8753_PWR2, 4, 0, NULL, 0),
488SND_SOC_DAPM_MIXER("ALC Mixer", WM8753_PWR2, 6, 0,
489 &wm8753_alc_mixer_controls[0], ARRAY_SIZE(wm8753_alc_mixer_controls)),
490SND_SOC_DAPM_MUX("Line Left Mux", SND_SOC_NOPM, 0, 0,
491 &wm8753_line_left_controls),
492SND_SOC_DAPM_MUX("Line Right Mux", SND_SOC_NOPM, 0, 0,
493 &wm8753_line_right_controls),
494SND_SOC_DAPM_MUX("Line Mono Mux", SND_SOC_NOPM, 0, 0,
495 &wm8753_line_mono_controls),
496SND_SOC_DAPM_MUX("Line Mixer", WM8753_PWR2, 0, 0,
497 &wm8753_line_mux_mix_controls),
498SND_SOC_DAPM_MUX("Rx Mixer", WM8753_PWR2, 1, 0,
499 &wm8753_rx_mux_mix_controls),
500SND_SOC_DAPM_PGA("Mic 1 Volume", WM8753_PWR2, 8, 0, NULL, 0),
501SND_SOC_DAPM_PGA("Mic 2 Volume", WM8753_PWR2, 7, 0, NULL, 0),
502SND_SOC_DAPM_MUX("Mic Selection Mux", SND_SOC_NOPM, 0, 0,
503 &wm8753_mic_sel_mux_controls),
504SND_SOC_DAPM_INPUT("LINE1"),
505SND_SOC_DAPM_INPUT("LINE2"),
506SND_SOC_DAPM_INPUT("RXP"),
507SND_SOC_DAPM_INPUT("RXN"),
508SND_SOC_DAPM_INPUT("ACIN"),
509SND_SOC_DAPM_OUTPUT("ACOP"),
510SND_SOC_DAPM_INPUT("MIC1N"),
511SND_SOC_DAPM_INPUT("MIC1"),
512SND_SOC_DAPM_INPUT("MIC2N"),
513SND_SOC_DAPM_INPUT("MIC2"),
514SND_SOC_DAPM_VMID("VREF"),
515};
516
a65f0568 517static const struct snd_soc_dapm_route audio_map[] = {
1f53aee0
LG		 518 /* left mixer */
519 {"Left Mixer", "Left Playback Switch", "Left DAC"},
520 {"Left Mixer", "Voice Playback Switch", "Voice DAC"},
521 {"Left Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
522 {"Left Mixer", "Bypass Playback Switch", "Line Left Mux"},
523
524 /* right mixer */
525 {"Right Mixer", "Right Playback Switch", "Right DAC"},
526 {"Right Mixer", "Voice Playback Switch", "Voice DAC"},
527 {"Right Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
528 {"Right Mixer", "Bypass Playback Switch", "Line Right Mux"},
529
530 /* mono mixer */
531 {"Mono Mixer", "Voice Playback Switch", "Voice DAC"},
532 {"Mono Mixer", "Left Playback Switch", "Left DAC"},
533 {"Mono Mixer", "Right Playback Switch", "Right DAC"},
534 {"Mono Mixer", "Sidetone Playback Switch", "Mic Sidetone Mux"},
535 {"Mono Mixer", "Bypass Playback Switch", "Line Mono Mux"},
536
537 /* left out */
538 {"Left Out 1", NULL, "Left Mixer"},
539 {"Left Out 2", NULL, "Left Mixer"},
540 {"LOUT1", NULL, "Left Out 1"},
541 {"LOUT2", NULL, "Left Out 2"},
542
543 /* right out */
544 {"Right Out 1", NULL, "Right Mixer"},
545 {"Right Out 2", NULL, "Right Mixer"},
546 {"ROUT1", NULL, "Right Out 1"},
547 {"ROUT2", NULL, "Right Out 2"},
548
549 /* mono 1 out */
550 {"Mono Out 1", NULL, "Mono Mixer"},
551 {"MONO1", NULL, "Mono Out 1"},
552
553 /* mono 2 out */
554 {"Mono 2 Mux", "Left + Right", "Out3 Left + Right"},
555 {"Mono 2 Mux", "Inverted Mono 1", "MONO1"},
556 {"Mono 2 Mux", "Left", "Left Mixer"},
557 {"Mono 2 Mux", "Right", "Right Mixer"},
558 {"Mono Out 2", NULL, "Mono 2 Mux"},
559 {"MONO2", NULL, "Mono Out 2"},
560
561 /* out 3 */
562 {"Out3 Left + Right", NULL, "Left Mixer"},
563 {"Out3 Left + Right", NULL, "Right Mixer"},
564 {"Out3 Mux", "VREF", "VREF"},
565 {"Out3 Mux", "Left + Right", "Out3 Left + Right"},
566 {"Out3 Mux", "ROUT2", "ROUT2"},
567 {"Out 3", NULL, "Out3 Mux"},
568 {"OUT3", NULL, "Out 3"},
569
570 /* out 4 */
571 {"Out4 Mux", "VREF", "VREF"},
4037314a 572 {"Out4 Mux", "Capture ST", "Playback Mixer"},
1f53aee0
LG		 573 {"Out4 Mux", "LOUT2", "LOUT2"},
574 {"Out 4", NULL, "Out4 Mux"},
575 {"OUT4", NULL, "Out 4"},
576
577 /* record mixer */
578 {"Playback Mixer", "Left Capture Switch", "Left Mixer"},
579 {"Playback Mixer", "Voice Capture Switch", "Mono Mixer"},
580 {"Playback Mixer", "Right Capture Switch", "Right Mixer"},
581
582 /* Mic/SideTone Mux */
583 {"Mic Sidetone Mux", "Left PGA", "Left Capture Volume"},
584 {"Mic Sidetone Mux", "Right PGA", "Right Capture Volume"},
585 {"Mic Sidetone Mux", "Mic 1", "Mic 1 Volume"},
586 {"Mic Sidetone Mux", "Mic 2", "Mic 2 Volume"},
587
588 /* Capture Left Mux */
589 {"Capture Left Mux", "PGA", "Left Capture Volume"},
590 {"Capture Left Mux", "Line or RXP-RXN", "Line Left Mux"},
591 {"Capture Left Mux", "Line", "LINE1"},
592
593 /* Capture Right Mux */
594 {"Capture Right Mux", "PGA", "Right Capture Volume"},
595 {"Capture Right Mux", "Line or RXP-RXN", "Line Right Mux"},
4037314a 596 {"Capture Right Mux", "Sidetone", "Playback Mixer"},
1f53aee0
LG		 597
598 /* Mono Capture mixer-mux */
599 {"Capture Right Mixer", "Stereo", "Capture Right Mux"},
877ae707 600 {"Capture Left Mixer", "Stereo", "Capture Left Mux"},
1f53aee0
LG		 601 {"Capture Left Mixer", "Analogue Mix Left", "Capture Left Mux"},
602 {"Capture Left Mixer", "Analogue Mix Left", "Capture Right Mux"},
603 {"Capture Right Mixer", "Analogue Mix Right", "Capture Left Mux"},
604 {"Capture Right Mixer", "Analogue Mix Right", "Capture Right Mux"},
605 {"Capture Left Mixer", "Digital Mono Mix", "Capture Left Mux"},
606 {"Capture Left Mixer", "Digital Mono Mix", "Capture Right Mux"},
607 {"Capture Right Mixer", "Digital Mono Mix", "Capture Left Mux"},
608 {"Capture Right Mixer", "Digital Mono Mix", "Capture Right Mux"},
609
610 /* ADC */
611 {"Left ADC", NULL, "Capture Left Mixer"},
612 {"Right ADC", NULL, "Capture Right Mixer"},
613
614 /* Left Capture Volume */
615 {"Left Capture Volume", NULL, "ACIN"},
616
617 /* Right Capture Volume */
618 {"Right Capture Volume", NULL, "Mic 2 Volume"},
619
620 /* ALC Mixer */
621 {"ALC Mixer", "Line Capture Switch", "Line Mixer"},
622 {"ALC Mixer", "Mic2 Capture Switch", "Mic 2 Volume"},
623 {"ALC Mixer", "Mic1 Capture Switch", "Mic 1 Volume"},
624 {"ALC Mixer", "Rx Capture Switch", "Rx Mixer"},
625
626 /* Line Left Mux */
627 {"Line Left Mux", "Line 1", "LINE1"},
628 {"Line Left Mux", "Rx Mix", "Rx Mixer"},
629
630 /* Line Right Mux */
631 {"Line Right Mux", "Line 2", "LINE2"},
632 {"Line Right Mux", "Rx Mix", "Rx Mixer"},
633
634 /* Line Mono Mux */
635 {"Line Mono Mux", "Line Mix", "Line Mixer"},
636 {"Line Mono Mux", "Rx Mix", "Rx Mixer"},
637
638 /* Line Mixer/Mux */
639 {"Line Mixer", "Line 1 + 2", "LINE1"},
640 {"Line Mixer", "Line 1 - 2", "LINE1"},
641 {"Line Mixer", "Line 1 + 2", "LINE2"},
642 {"Line Mixer", "Line 1 - 2", "LINE2"},
643 {"Line Mixer", "Line 1", "LINE1"},
644 {"Line Mixer", "Line 2", "LINE2"},
645
646 /* Rx Mixer/Mux */
647 {"Rx Mixer", "RXP - RXN", "RXP"},
648 {"Rx Mixer", "RXP + RXN", "RXP"},
649 {"Rx Mixer", "RXP - RXN", "RXN"},
650 {"Rx Mixer", "RXP + RXN", "RXN"},
651 {"Rx Mixer", "RXP", "RXP"},
652 {"Rx Mixer", "RXN", "RXN"},
653
654 /* Mic 1 Volume */
655 {"Mic 1 Volume", NULL, "MIC1N"},
656 {"Mic 1 Volume", NULL, "Mic Selection Mux"},
657
658 /* Mic 2 Volume */
659 {"Mic 2 Volume", NULL, "MIC2N"},
660 {"Mic 2 Volume", NULL, "MIC2"},
661
662 /* Mic Selector Mux */
663 {"Mic Selection Mux", "Mic 1", "MIC1"},
664 {"Mic Selection Mux", "Mic 2", "MIC2N"},
665 {"Mic Selection Mux", "Mic 3", "MIC2"},
666
667 /* ACOP */
668 {"ACOP", NULL, "ALC Mixer"},
1f53aee0
LG		 669};
670
671static int wm8753_add_widgets(struct snd_soc_codec *codec)
672{
a65f0568
MB		 673 snd_soc_dapm_new_controls(codec, wm8753_dapm_widgets,
674 ARRAY_SIZE(wm8753_dapm_widgets));
1f53aee0 675
a65f0568 676 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
1f53aee0 677
1f53aee0
LG		 678 return 0;
679}
680
681/* PLL divisors */
682struct _pll_div {
683 u32 div2:1;
684 u32 n:4;
685 u32 k:24;
686};
687
688/* The size in bits of the pll divide multiplied by 10
689 * to allow rounding later */
690#define FIXED_PLL_SIZE ((1 << 22) * 10)
691
692static void pll_factors(struct _pll_div *pll_div, unsigned int target,
693 unsigned int source)
694{
695 u64 Kpart;
696 unsigned int K, Ndiv, Nmod;
697
698 Ndiv = target / source;
699 if (Ndiv < 6) {
700 source >>= 1;
701 pll_div->div2 = 1;
702 Ndiv = target / source;
703 } else
704 pll_div->div2 = 0;
705
706 if ((Ndiv < 6) || (Ndiv > 12))
707 printk(KERN_WARNING
449bd54d 708 "wm8753: unsupported N = %u\n", Ndiv);
1f53aee0
LG		 709
710 pll_div->n = Ndiv;
711 Nmod = target % source;
712 Kpart = FIXED_PLL_SIZE * (long long)Nmod;
713
714 do_div(Kpart, source);
715
716 K = Kpart & 0xFFFFFFFF;
717
718 /* Check if we need to round */
719 if ((K % 10) >= 5)
720 K += 5;
721
722 /* Move down to proper range now rounding is done */
723 K /= 10;
724
725 pll_div->k = K;
726}
727
85488037
MB		 728static int wm8753_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
729 int source, unsigned int freq_in, unsigned int freq_out)
1f53aee0
LG		 730{
731 u16 reg, enable;
732 int offset;
733 struct snd_soc_codec *codec = codec_dai->codec;
734
735 if (pll_id < WM8753_PLL1 || pll_id > WM8753_PLL2)
736 return -ENODEV;
737
738 if (pll_id == WM8753_PLL1) {
739 offset = 0;
740 enable = 0x10;
741 reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xffef;
742 } else {
743 offset = 4;
744 enable = 0x8;
745 reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfff7;
746 }
747
748 if (!freq_in || !freq_out) {
749 /* disable PLL */
750 wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0026);
751 wm8753_write(codec, WM8753_CLOCK, reg);
752 return 0;
753 } else {
754 u16 value = 0;
755 struct _pll_div pll_div;
756
757 pll_factors(&pll_div, freq_out * 8, freq_in);
758
759 /* set up N and K PLL divisor ratios */
760 /* bits 8:5 = PLL_N, bits 3:0 = PLL_K[21:18] */
761 value = (pll_div.n << 5) + ((pll_div.k & 0x3c0000) >> 18);
762 wm8753_write(codec, WM8753_PLL1CTL2 + offset, value);
763
764 /* bits 8:0 = PLL_K[17:9] */
765 value = (pll_div.k & 0x03fe00) >> 9;
766 wm8753_write(codec, WM8753_PLL1CTL3 + offset, value);
767
768 /* bits 8:0 = PLL_K[8:0] */
769 value = pll_div.k & 0x0001ff;
770 wm8753_write(codec, WM8753_PLL1CTL4 + offset, value);
771
772 /* set PLL as input and enable */
773 wm8753_write(codec, WM8753_PLL1CTL1 + offset, 0x0027 |
774 (pll_div.div2 << 3));
775 wm8753_write(codec, WM8753_CLOCK, reg | enable);
776 }
777 return 0;
778}
779
780struct _coeff_div {
781 u32 mclk;
782 u32 rate;
783 u8 sr:5;
784 u8 usb:1;
785};
786
787/* codec hifi mclk (after PLL) clock divider coefficients */
788static const struct _coeff_div coeff_div[] = {
789 /* 8k */
790 {12288000, 8000, 0x6, 0x0},
791 {11289600, 8000, 0x16, 0x0},
792 {18432000, 8000, 0x7, 0x0},
793 {16934400, 8000, 0x17, 0x0},
794 {12000000, 8000, 0x6, 0x1},
795
796 /* 11.025k */
797 {11289600, 11025, 0x18, 0x0},
798 {16934400, 11025, 0x19, 0x0},
799 {12000000, 11025, 0x19, 0x1},
800
801 /* 16k */
802 {12288000, 16000, 0xa, 0x0},
803 {18432000, 16000, 0xb, 0x0},
804 {12000000, 16000, 0xa, 0x1},
805
806 /* 22.05k */
807 {11289600, 22050, 0x1a, 0x0},
808 {16934400, 22050, 0x1b, 0x0},
809 {12000000, 22050, 0x1b, 0x1},
810
811 /* 32k */
812 {12288000, 32000, 0xc, 0x0},
813 {18432000, 32000, 0xd, 0x0},
814 {12000000, 32000, 0xa, 0x1},
815
816 /* 44.1k */
817 {11289600, 44100, 0x10, 0x0},
818 {16934400, 44100, 0x11, 0x0},
819 {12000000, 44100, 0x11, 0x1},
820
821 /* 48k */
822 {12288000, 48000, 0x0, 0x0},
823 {18432000, 48000, 0x1, 0x0},
824 {12000000, 48000, 0x0, 0x1},
825
826 /* 88.2k */
827 {11289600, 88200, 0x1e, 0x0},
828 {16934400, 88200, 0x1f, 0x0},
829 {12000000, 88200, 0x1f, 0x1},
830
831 /* 96k */
832 {12288000, 96000, 0xe, 0x0},
833 {18432000, 96000, 0xf, 0x0},
834 {12000000, 96000, 0xe, 0x1},
835};
836
837static int get_coeff(int mclk, int rate)
838{
839 int i;
840
841 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
842 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
843 return i;
844 }
845 return -EINVAL;
846}
847
848/*
849 * Clock after PLL and dividers
850 */
e550e17f 851static int wm8753_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 852 int clk_id, unsigned int freq, int dir)
853{
854 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 855 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 856
857 switch (freq) {
858 case 11289600:
859 case 12000000:
860 case 12288000:
861 case 16934400:
862 case 18432000:
863 if (clk_id == WM8753_MCLK) {
864 wm8753->sysclk = freq;
865 return 0;
866 } else if (clk_id == WM8753_PCMCLK) {
867 wm8753->pcmclk = freq;
868 return 0;
869 }
870 break;
871 }
872 return -EINVAL;
873}
874
875/*
876 * Set's ADC and Voice DAC format.
877 */
e550e17f 878static int wm8753_vdac_adc_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 879 unsigned int fmt)
880{
881 struct snd_soc_codec *codec = codec_dai->codec;
882 u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01ec;
883
884 /* interface format */
885 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
886 case SND_SOC_DAIFMT_I2S:
887 voice |= 0x0002;
888 break;
889 case SND_SOC_DAIFMT_RIGHT_J:
890 break;
891 case SND_SOC_DAIFMT_LEFT_J:
892 voice |= 0x0001;
893 break;
894 case SND_SOC_DAIFMT_DSP_A:
895 voice |= 0x0003;
896 break;
897 case SND_SOC_DAIFMT_DSP_B:
898 voice |= 0x0013;
899 break;
900 default:
901 return -EINVAL;
902 }
903
904 wm8753_write(codec, WM8753_PCM, voice);
905 return 0;
906}
907
f0fba2ad
LG		 908static int wm8753_pcm_startup(struct snd_pcm_substream *substream,
909 struct snd_soc_dai *dai)
910{
911 wm8753_set_dai_mode(dai->codec, dai, 0);
912 return 0;
913}
914
1f53aee0
LG		 915/*
916 * Set PCM DAI bit size and sample rate.
917 */
918static int wm8753_pcm_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 919 struct snd_pcm_hw_params *params,
920 struct snd_soc_dai *dai)
1f53aee0
LG		 921{
922 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 923 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 924 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 925 u16 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x01f3;
926 u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x017f;
927
928 /* bit size */
929 switch (params_format(params)) {
930 case SNDRV_PCM_FORMAT_S16_LE:
931 break;
932 case SNDRV_PCM_FORMAT_S20_3LE:
933 voice |= 0x0004;
934 break;
935 case SNDRV_PCM_FORMAT_S24_LE:
936 voice |= 0x0008;
937 break;
938 case SNDRV_PCM_FORMAT_S32_LE:
939 voice |= 0x000c;
940 break;
941 }
942
943 /* sample rate */
944 if (params_rate(params) * 384 == wm8753->pcmclk)
945 srate |= 0x80;
946 wm8753_write(codec, WM8753_SRATE1, srate);
947
948 wm8753_write(codec, WM8753_PCM, voice);
949 return 0;
950}
951
952/*
953 * Set's PCM dai fmt and BCLK.
954 */
e550e17f 955static int wm8753_pcm_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 956 unsigned int fmt)
957{
958 struct snd_soc_codec *codec = codec_dai->codec;
959 u16 voice, ioctl;
960
961 voice = wm8753_read_reg_cache(codec, WM8753_PCM) & 0x011f;
962 ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x015d;
963
964 /* set master/slave audio interface */
965 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
966 case SND_SOC_DAIFMT_CBS_CFS:
967 break;
968 case SND_SOC_DAIFMT_CBM_CFM:
969 ioctl |= 0x2;
970 case SND_SOC_DAIFMT_CBM_CFS:
971 voice |= 0x0040;
972 break;
973 default:
974 return -EINVAL;
975 }
976
977 /* clock inversion */
978 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
979 case SND_SOC_DAIFMT_DSP_A:
980 case SND_SOC_DAIFMT_DSP_B:
981 /* frame inversion not valid for DSP modes */
982 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
983 case SND_SOC_DAIFMT_NB_NF:
984 break;
985 case SND_SOC_DAIFMT_IB_NF:
986 voice |= 0x0080;
987 break;
988 default:
989 return -EINVAL;
990 }
991 break;
992 case SND_SOC_DAIFMT_I2S:
993 case SND_SOC_DAIFMT_RIGHT_J:
994 case SND_SOC_DAIFMT_LEFT_J:
995 voice &= ~0x0010;
996 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
997 case SND_SOC_DAIFMT_NB_NF:
998 break;
999 case SND_SOC_DAIFMT_IB_IF:
1000 voice |= 0x0090;
1001 break;
1002 case SND_SOC_DAIFMT_IB_NF:
1003 voice |= 0x0080;
1004 break;
1005 case SND_SOC_DAIFMT_NB_IF:
1006 voice |= 0x0010;
1007 break;
1008 default:
1009 return -EINVAL;
1010 }
1011 break;
1012 default:
1013 return -EINVAL;
1014 }
1015
1016 wm8753_write(codec, WM8753_PCM, voice);
1017 wm8753_write(codec, WM8753_IOCTL, ioctl);
1018 return 0;
1019}
1020
e550e17f 1021static int wm8753_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1022 int div_id, int div)
1023{
1024 struct snd_soc_codec *codec = codec_dai->codec;
1025 u16 reg;
1026
1027 switch (div_id) {
1028 case WM8753_PCMDIV:
1029 reg = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0x003f;
1030 wm8753_write(codec, WM8753_CLOCK, reg | div);
1031 break;
1032 case WM8753_BCLKDIV:
1033 reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x01c7;
1034 wm8753_write(codec, WM8753_SRATE2, reg | div);
1035 break;
1036 case WM8753_VXCLKDIV:
1037 reg = wm8753_read_reg_cache(codec, WM8753_SRATE2) & 0x003f;
1038 wm8753_write(codec, WM8753_SRATE2, reg | div);
1039 break;
1040 default:
1041 return -EINVAL;
1042 }
1043 return 0;
1044}
1045
1046/*
1047 * Set's HiFi DAC format.
1048 */
e550e17f 1049static int wm8753_hdac_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1050 unsigned int fmt)
1051{
1052 struct snd_soc_codec *codec = codec_dai->codec;
1053 u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01e0;
1054
1055 /* interface format */
1056 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1057 case SND_SOC_DAIFMT_I2S:
1058 hifi |= 0x0002;
1059 break;
1060 case SND_SOC_DAIFMT_RIGHT_J:
1061 break;
1062 case SND_SOC_DAIFMT_LEFT_J:
1063 hifi |= 0x0001;
1064 break;
1065 case SND_SOC_DAIFMT_DSP_A:
1066 hifi |= 0x0003;
1067 break;
1068 case SND_SOC_DAIFMT_DSP_B:
1069 hifi |= 0x0013;
1070 break;
1071 default:
1072 return -EINVAL;
1073 }
1074
1075 wm8753_write(codec, WM8753_HIFI, hifi);
1076 return 0;
1077}
1078
1079/*
1080 * Set's I2S DAI format.
1081 */
e550e17f 1082static int wm8753_i2s_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1083 unsigned int fmt)
1084{
1085 struct snd_soc_codec *codec = codec_dai->codec;
1086 u16 ioctl, hifi;
1087
1088 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x011f;
1089 ioctl = wm8753_read_reg_cache(codec, WM8753_IOCTL) & 0x00ae;
1090
1091 /* set master/slave audio interface */
1092 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1093 case SND_SOC_DAIFMT_CBS_CFS:
1094 break;
1095 case SND_SOC_DAIFMT_CBM_CFM:
1096 ioctl |= 0x1;
1097 case SND_SOC_DAIFMT_CBM_CFS:
1098 hifi |= 0x0040;
1099 break;
1100 default:
1101 return -EINVAL;
1102 }
1103
1104 /* clock inversion */
1105 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1106 case SND_SOC_DAIFMT_DSP_A:
1107 case SND_SOC_DAIFMT_DSP_B:
1108 /* frame inversion not valid for DSP modes */
1109 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1110 case SND_SOC_DAIFMT_NB_NF:
1111 break;
1112 case SND_SOC_DAIFMT_IB_NF:
1113 hifi |= 0x0080;
1114 break;
1115 default:
1116 return -EINVAL;
1117 }
1118 break;
1119 case SND_SOC_DAIFMT_I2S:
1120 case SND_SOC_DAIFMT_RIGHT_J:
1121 case SND_SOC_DAIFMT_LEFT_J:
1122 hifi &= ~0x0010;
1123 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1124 case SND_SOC_DAIFMT_NB_NF:
1125 break;
1126 case SND_SOC_DAIFMT_IB_IF:
1127 hifi |= 0x0090;
1128 break;
1129 case SND_SOC_DAIFMT_IB_NF:
1130 hifi |= 0x0080;
1131 break;
1132 case SND_SOC_DAIFMT_NB_IF:
1133 hifi |= 0x0010;
1134 break;
1135 default:
1136 return -EINVAL;
1137 }
1138 break;
1139 default:
1140 return -EINVAL;
1141 }
1142
1143 wm8753_write(codec, WM8753_HIFI, hifi);
1144 wm8753_write(codec, WM8753_IOCTL, ioctl);
1145 return 0;
1146}
1147
f0fba2ad
LG		 1148static int wm8753_i2s_startup(struct snd_pcm_substream *substream,
1149 struct snd_soc_dai *dai)
1150{
1151 wm8753_set_dai_mode(dai->codec, dai, 1);
1152 return 0;
1153}
1154
1f53aee0
LG		 1155/*
1156 * Set PCM DAI bit size and sample rate.
1157 */
1158static int wm8753_i2s_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1159 struct snd_pcm_hw_params *params,
1160 struct snd_soc_dai *dai)
1f53aee0
LG		 1161{
1162 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1163 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1164 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 1165 u16 srate = wm8753_read_reg_cache(codec, WM8753_SRATE1) & 0x01c0;
1166 u16 hifi = wm8753_read_reg_cache(codec, WM8753_HIFI) & 0x01f3;
1167 int coeff;
1168
1169 /* is digital filter coefficient valid ? */
1170 coeff = get_coeff(wm8753->sysclk, params_rate(params));
1171 if (coeff < 0) {
1172 printk(KERN_ERR "wm8753 invalid MCLK or rate\n");
1173 return coeff;
1174 }
1175 wm8753_write(codec, WM8753_SRATE1, srate | (coeff_div[coeff].sr << 1) |
1176 coeff_div[coeff].usb);
1177
1178 /* bit size */
1179 switch (params_format(params)) {
1180 case SNDRV_PCM_FORMAT_S16_LE:
1181 break;
1182 case SNDRV_PCM_FORMAT_S20_3LE:
1183 hifi |= 0x0004;
1184 break;
1185 case SNDRV_PCM_FORMAT_S24_LE:
1186 hifi |= 0x0008;
1187 break;
1188 case SNDRV_PCM_FORMAT_S32_LE:
1189 hifi |= 0x000c;
1190 break;
1191 }
1192
1193 wm8753_write(codec, WM8753_HIFI, hifi);
1194 return 0;
1195}
1196
e550e17f 1197static int wm8753_mode1v_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1198 unsigned int fmt)
1199{
1200 struct snd_soc_codec *codec = codec_dai->codec;
1201 u16 clock;
1202
1203 /* set clk source as pcmclk */
1204 clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb;
1205 wm8753_write(codec, WM8753_CLOCK, clock);
1206
1207 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
1208 return -EINVAL;
1209 return wm8753_pcm_set_dai_fmt(codec_dai, fmt);
1210}
1211
e550e17f 1212static int wm8753_mode1h_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1213 unsigned int fmt)
1214{
1215 if (wm8753_hdac_set_dai_fmt(codec_dai, fmt) < 0)
1216 return -EINVAL;
1217 return wm8753_i2s_set_dai_fmt(codec_dai, fmt);
1218}
1219
e550e17f 1220static int wm8753_mode2_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1221 unsigned int fmt)
1222{
1223 struct snd_soc_codec *codec = codec_dai->codec;
1224 u16 clock;
1225
1226 /* set clk source as pcmclk */
1227 clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb;
1228 wm8753_write(codec, WM8753_CLOCK, clock);
1229
1230 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
1231 return -EINVAL;
1232 return wm8753_i2s_set_dai_fmt(codec_dai, fmt);
1233}
1234
e550e17f 1235static int wm8753_mode3_4_set_dai_fmt(struct snd_soc_dai *codec_dai,
1f53aee0
LG		 1236 unsigned int fmt)
1237{
1238 struct snd_soc_codec *codec = codec_dai->codec;
1239 u16 clock;
1240
1241 /* set clk source as mclk */
1242 clock = wm8753_read_reg_cache(codec, WM8753_CLOCK) & 0xfffb;
1243 wm8753_write(codec, WM8753_CLOCK, clock | 0x4);
1244
1245 if (wm8753_hdac_set_dai_fmt(codec_dai, fmt) < 0)
1246 return -EINVAL;
1247 if (wm8753_vdac_adc_set_dai_fmt(codec_dai, fmt) < 0)
1248 return -EINVAL;
1249 return wm8753_i2s_set_dai_fmt(codec_dai, fmt);
1250}
1251
e550e17f 1252static int wm8753_mute(struct snd_soc_dai *dai, int mute)
1f53aee0
LG		 1253{
1254 struct snd_soc_codec *codec = dai->codec;
1255 u16 mute_reg = wm8753_read_reg_cache(codec, WM8753_DAC) & 0xfff7;
f0fba2ad 1256 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1f53aee0
LG		 1257
1258 /* the digital mute covers the HiFi and Voice DAC's on the WM8753.
1259 * make sure we check if they are not both active when we mute */
f0fba2ad
LG		 1260 if (mute && wm8753->dai_func == 1) {
1261 if (!codec->active)
1f53aee0
LG		 1262 wm8753_write(codec, WM8753_DAC, mute_reg | 0x8);
1263 } else {
1264 if (mute)
1265 wm8753_write(codec, WM8753_DAC, mute_reg | 0x8);
1266 else
1267 wm8753_write(codec, WM8753_DAC, mute_reg);
1268 }
1269
1270 return 0;
1271}
1272
0be9898a
MB		 1273static int wm8753_set_bias_level(struct snd_soc_codec *codec,
1274 enum snd_soc_bias_level level)
1f53aee0
LG		 1275{
1276 u16 pwr_reg = wm8753_read_reg_cache(codec, WM8753_PWR1) & 0xfe3e;
1277
0be9898a
MB		 1278 switch (level) {
1279 case SND_SOC_BIAS_ON:
1f53aee0
LG		 1280 /* set vmid to 50k and unmute dac */
1281 wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x00c0);
1282 break;
0be9898a 1283 case SND_SOC_BIAS_PREPARE:
1f53aee0
LG		 1284 /* set vmid to 5k for quick power up */
1285 wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x01c1);
1286 break;
0be9898a 1287 case SND_SOC_BIAS_STANDBY:
1f53aee0
LG		 1288 /* mute dac and set vmid to 500k, enable VREF */
1289 wm8753_write(codec, WM8753_PWR1, pwr_reg | 0x0141);
1290 break;
0be9898a 1291 case SND_SOC_BIAS_OFF:
1f53aee0
LG		 1292 wm8753_write(codec, WM8753_PWR1, 0x0001);
1293 break;
1294 }
0be9898a 1295 codec->bias_level = level;
1f53aee0
LG		 1296 return 0;
1297}
1298
1299#define WM8753_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
60fc684a
MB		 1300 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1301 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1302 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
1f53aee0
LG		 1303
1304#define WM8753_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1305 SNDRV_PCM_FMTBIT_S24_LE)
1306
1307/*
1308 * The WM8753 supports upto 4 different and mutually exclusive DAI
1309 * configurations. This gives 2 PCM's available for use, hifi and voice.
1310 * NOTE: The Voice PCM cannot play or capture audio to the CPU as it's DAI
1311 * is connected between the wm8753 and a BT codec or GSM modem.
1312 *
1313 * 1. Voice over PCM DAI - HIFI DAC over HIFI DAI
1314 * 2. Voice over HIFI DAI - HIFI disabled
1315 * 3. Voice disabled - HIFI over HIFI
1316 * 4. Voice disabled - HIFI over HIFI, uses voice DAI LRC for capture
1317 */
6335d055 1318static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode1 = {
f0fba2ad 1319 .startup = wm8753_i2s_startup,
6335d055
EM		 1320 .hw_params = wm8753_i2s_hw_params,
1321 .digital_mute = wm8753_mute,
1322 .set_fmt = wm8753_mode1h_set_dai_fmt,
1323 .set_clkdiv = wm8753_set_dai_clkdiv,
1324 .set_pll = wm8753_set_dai_pll,
1325 .set_sysclk = wm8753_set_dai_sysclk,
1326};
1327
1328static struct snd_soc_dai_ops wm8753_dai_ops_voice_mode1 = {
f0fba2ad 1329 .startup = wm8753_pcm_startup,
6335d055
EM		 1330 .hw_params = wm8753_pcm_hw_params,
1331 .digital_mute = wm8753_mute,
1332 .set_fmt = wm8753_mode1v_set_dai_fmt,
1333 .set_clkdiv = wm8753_set_dai_clkdiv,
1334 .set_pll = wm8753_set_dai_pll,
1335 .set_sysclk = wm8753_set_dai_sysclk,
1336};
1337
1338static struct snd_soc_dai_ops wm8753_dai_ops_voice_mode2 = {
f0fba2ad 1339 .startup = wm8753_pcm_startup,
6335d055
EM		 1340 .hw_params = wm8753_pcm_hw_params,
1341 .digital_mute = wm8753_mute,
1342 .set_fmt = wm8753_mode2_set_dai_fmt,
1343 .set_clkdiv = wm8753_set_dai_clkdiv,
1344 .set_pll = wm8753_set_dai_pll,
1345 .set_sysclk = wm8753_set_dai_sysclk,
1346};
1347
1348static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode3 = {
f0fba2ad 1349 .startup = wm8753_i2s_startup,
6335d055
EM		 1350 .hw_params = wm8753_i2s_hw_params,
1351 .digital_mute = wm8753_mute,
1352 .set_fmt = wm8753_mode3_4_set_dai_fmt,
1353 .set_clkdiv = wm8753_set_dai_clkdiv,
1354 .set_pll = wm8753_set_dai_pll,
1355 .set_sysclk = wm8753_set_dai_sysclk,
1356};
1357
1358static struct snd_soc_dai_ops wm8753_dai_ops_hifi_mode4 = {
f0fba2ad 1359 .startup = wm8753_i2s_startup,
6335d055
EM		 1360 .hw_params = wm8753_i2s_hw_params,
1361 .digital_mute = wm8753_mute,
1362 .set_fmt = wm8753_mode3_4_set_dai_fmt,
1363 .set_clkdiv = wm8753_set_dai_clkdiv,
1364 .set_pll = wm8753_set_dai_pll,
1365 .set_sysclk = wm8753_set_dai_sysclk,
1366};
1367
f0fba2ad 1368static struct snd_soc_dai_driver wm8753_all_dai[] = {
1f53aee0 1369/* DAI HiFi mode 1 */
f0fba2ad 1370{ .name = "wm8753-hifi",
1f53aee0
LG		 1371 .playback = {
1372 .stream_name = "HiFi Playback",
1373 .channels_min = 1,
1374 .channels_max = 2,
1375 .rates = WM8753_RATES,
dee89c4d 1376 .formats = WM8753_FORMATS},
1f53aee0
LG		 1377 .capture = { /* dummy for fast DAI switching */
1378 .stream_name = "Capture",
1379 .channels_min = 1,
1380 .channels_max = 2,
1381 .rates = WM8753_RATES,
dee89c4d 1382 .formats = WM8753_FORMATS},
6335d055 1383 .ops = &wm8753_dai_ops_hifi_mode1,
1f53aee0
LG		 1384},
1385/* DAI Voice mode 1 */
f0fba2ad 1386{ .name = "wm8753-voice",
1f53aee0
LG		 1387 .playback = {
1388 .stream_name = "Voice Playback",
1389 .channels_min = 1,
1390 .channels_max = 1,
1391 .rates = WM8753_RATES,
1392 .formats = WM8753_FORMATS,},
1393 .capture = {
1394 .stream_name = "Capture",
1395 .channels_min = 1,
1396 .channels_max = 2,
1397 .rates = WM8753_RATES,
1398 .formats = WM8753_FORMATS,},
6335d055 1399 .ops = &wm8753_dai_ops_voice_mode1,
1f53aee0
LG		 1400},
1401/* DAI HiFi mode 2 - dummy */
f0fba2ad 1402{ .name = "wm8753-hifi",
1f53aee0
LG		 1403},
1404/* DAI Voice mode 2 */
f0fba2ad 1405{ .name = "wm8753-voice",
1f53aee0
LG		 1406 .playback = {
1407 .stream_name = "Voice Playback",
1408 .channels_min = 1,
1409 .channels_max = 1,
1410 .rates = WM8753_RATES,
1411 .formats = WM8753_FORMATS,},
1412 .capture = {
1413 .stream_name = "Capture",
1414 .channels_min = 1,
1415 .channels_max = 2,
1416 .rates = WM8753_RATES,
1417 .formats = WM8753_FORMATS,},
6335d055 1418 .ops = &wm8753_dai_ops_voice_mode2,
1f53aee0
LG		 1419},
1420/* DAI HiFi mode 3 */
f0fba2ad 1421{ .name = "wm8753-hifi",
1f53aee0
LG		 1422 .playback = {
1423 .stream_name = "HiFi Playback",
1424 .channels_min = 1,
1425 .channels_max = 2,
1426 .rates = WM8753_RATES,
1427 .formats = WM8753_FORMATS,},
1428 .capture = {
1429 .stream_name = "Capture",
1430 .channels_min = 1,
1431 .channels_max = 2,
1432 .rates = WM8753_RATES,
1433 .formats = WM8753_FORMATS,},
6335d055 1434 .ops = &wm8753_dai_ops_hifi_mode3,
1f53aee0
LG		 1435},
1436/* DAI Voice mode 3 - dummy */
f0fba2ad 1437{ .name = "wm8753-voice",
1f53aee0
LG		 1438},
1439/* DAI HiFi mode 4 */
f0fba2ad 1440{ .name = "wm8753-hifi",
1f53aee0
LG		 1441 .playback = {
1442 .stream_name = "HiFi Playback",
1443 .channels_min = 1,
1444 .channels_max = 2,
1445 .rates = WM8753_RATES,
1446 .formats = WM8753_FORMATS,},
1447 .capture = {
1448 .stream_name = "Capture",
1449 .channels_min = 1,
1450 .channels_max = 2,
1451 .rates = WM8753_RATES,
1452 .formats = WM8753_FORMATS,},
6335d055 1453 .ops = &wm8753_dai_ops_hifi_mode4,
1f53aee0
LG		 1454},
1455/* DAI Voice mode 4 - dummy */
f0fba2ad 1456{ .name = "wm8753-voice",
1f53aee0
LG		 1457},
1458};
1459
f0fba2ad 1460static struct snd_soc_dai_driver wm8753_dai[] = {
9e70c1f0 1461 {
f0fba2ad 1462 .name = "wm8753-aif0",
9e70c1f0
MB		 1463 },
1464 {
f0fba2ad 1465 .name = "wm8753-aif1",
9e70c1f0
MB		 1466 },
1467};
1f53aee0 1468
f0fba2ad
LG		 1469static void wm8753_set_dai_mode(struct snd_soc_codec *codec,
1470 struct snd_soc_dai *dai, unsigned int hifi)
1f53aee0 1471{
f0fba2ad
LG		 1472 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1473
1474 if (wm8753->dai_func < 4) {
1475 if (hifi)
1476 dai->driver = &wm8753_all_dai[wm8753->dai_func << 1];
1477 else
1478 dai->driver = &wm8753_all_dai[(wm8753->dai_func << 1) + 1];
1f53aee0 1479 }
f0fba2ad 1480 wm8753_write(codec, WM8753_IOCTL, wm8753->dai_func);
1f53aee0
LG		 1481}
1482
1483static void wm8753_work(struct work_struct *work)
1484{
1485 struct snd_soc_codec *codec =
1486 container_of(work, struct snd_soc_codec, delayed_work.work);
0be9898a 1487 wm8753_set_bias_level(codec, codec->bias_level);
1f53aee0
LG		 1488}
1489
f0fba2ad 1490static int wm8753_suspend(struct snd_soc_codec *codec, pm_message_t state)
1f53aee0 1491{
0be9898a 1492 wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF);
1f53aee0
LG		 1493 return 0;
1494}
1495
f0fba2ad 1496static int wm8753_resume(struct snd_soc_codec *codec)
1f53aee0 1497{
1f53aee0
LG		 1498 int i;
1499 u8 data[2];
1500 u16 *cache = codec->reg_cache;
1501
1f53aee0
LG		 1502 /* Sync reg_cache with the hardware */
1503 for (i = 0; i < ARRAY_SIZE(wm8753_reg); i++) {
1504 if (i + 1 == WM8753_RESET)
1505 continue;
e611bd82
MB		 1506
1507 /* No point in writing hardware default values back */
1508 if (cache[i] == wm8753_reg[i])
1509 continue;
1510
1f53aee0
LG		 1511 data[0] = ((i + 1) << 1) | ((cache[i] >> 8) & 0x0001);
1512 data[1] = cache[i] & 0x00ff;
1513 codec->hw_write(codec->control_data, data, 2);
1514 }
1515
0be9898a 1516 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1f53aee0
LG		 1517
1518 /* charge wm8753 caps */
0be9898a
MB		 1519 if (codec->suspend_bias_level == SND_SOC_BIAS_ON) {
1520 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1521 codec->bias_level = SND_SOC_BIAS_ON;
1f53aee0
LG		 1522 schedule_delayed_work(&codec->delayed_work,
1523 msecs_to_jiffies(caps_charge));
1524 }
1525
1526 return 0;
1527}
1528
1f53aee0
LG		 1529/*
1530 * This function forces any delayed work to be queued and run.
1531 */
1532static int run_delayed_work(struct delayed_work *dwork)
1533{
1534 int ret;
1535
1536 /* cancel any work waiting to be queued. */
1537 ret = cancel_delayed_work(dwork);
1538
1539 /* if there was any work waiting then we run it now and
1540 * wait for it's completion */
1541 if (ret) {
1542 schedule_delayed_work(dwork, 0);
1543 flush_scheduled_work();
1544 }
1545 return ret;
1546}
1547
f0fba2ad 1548static int wm8753_probe(struct snd_soc_codec *codec)
1f53aee0 1549{
f0fba2ad
LG		 1550 struct wm8753_priv *wm8753 = snd_soc_codec_get_drvdata(codec);
1551 int ret = 0, reg;
1f53aee0 1552
f0fba2ad 1553 INIT_DELAYED_WORK(&codec->delayed_work, wm8753_work);
c2bac160 1554
f0fba2ad
LG		 1555 ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8753->control_type);
1556 if (ret < 0) {
1557 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1558 return ret;
c2bac160
MB		 1559 }
1560
c2bac160
MB		 1561 ret = wm8753_reset(codec);
1562 if (ret < 0) {
f0fba2ad
LG		 1563 dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1564 return ret;
c2bac160
MB		 1565 }
1566
f0fba2ad
LG		 1567 wm8753_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1568 wm8753->dai_func = 0;
1569
c2bac160
MB		 1570 /* charge output caps */
1571 wm8753_set_bias_level(codec, SND_SOC_BIAS_PREPARE);
1572 schedule_delayed_work(&codec->delayed_work,
1573 msecs_to_jiffies(caps_charge));
1574
1575 /* set the update bits */
1576 reg = wm8753_read_reg_cache(codec, WM8753_LDAC);
1577 wm8753_write(codec, WM8753_LDAC, reg | 0x0100);
1578 reg = wm8753_read_reg_cache(codec, WM8753_RDAC);
1579 wm8753_write(codec, WM8753_RDAC, reg | 0x0100);
1580 reg = wm8753_read_reg_cache(codec, WM8753_LADC);
1581 wm8753_write(codec, WM8753_LADC, reg | 0x0100);
1582 reg = wm8753_read_reg_cache(codec, WM8753_RADC);
1583 wm8753_write(codec, WM8753_RADC, reg | 0x0100);
1584 reg = wm8753_read_reg_cache(codec, WM8753_LOUT1V);
1585 wm8753_write(codec, WM8753_LOUT1V, reg | 0x0100);
1586 reg = wm8753_read_reg_cache(codec, WM8753_ROUT1V);
1587 wm8753_write(codec, WM8753_ROUT1V, reg | 0x0100);
1588 reg = wm8753_read_reg_cache(codec, WM8753_LOUT2V);
1589 wm8753_write(codec, WM8753_LOUT2V, reg | 0x0100);
1590 reg = wm8753_read_reg_cache(codec, WM8753_ROUT2V);
1591 wm8753_write(codec, WM8753_ROUT2V, reg | 0x0100);
1592 reg = wm8753_read_reg_cache(codec, WM8753_LINVOL);
1593 wm8753_write(codec, WM8753_LINVOL, reg | 0x0100);
1594 reg = wm8753_read_reg_cache(codec, WM8753_RINVOL);
1595 wm8753_write(codec, WM8753_RINVOL, reg | 0x0100);
1596
f0fba2ad
LG		 1597 snd_soc_add_controls(codec, wm8753_snd_controls,
1598 ARRAY_SIZE(wm8753_snd_controls));
1599 wm8753_add_widgets(codec);
c2bac160
MB		 1600
1601 return 0;
c2bac160
MB		 1602}
1603
f0fba2ad
LG		 1604/* power down chip */
1605static int wm8753_remove(struct snd_soc_codec *codec)
c2bac160 1606{
f0fba2ad
LG		 1607 run_delayed_work(&codec->delayed_work);
1608 wm8753_set_bias_level(codec, SND_SOC_BIAS_OFF);
1609
1610 return 0;
c2bac160
MB		 1611}
1612
f0fba2ad
LG		 1613static struct snd_soc_codec_driver soc_codec_dev_wm8753 = {
1614 .probe = wm8753_probe,
1615 .remove = wm8753_remove,
1616 .suspend = wm8753_suspend,
1617 .resume = wm8753_resume,
1618 .set_bias_level = wm8753_set_bias_level,
e5eec34c 1619 .reg_cache_size = ARRAY_SIZE(wm8753_reg),
f0fba2ad
LG		 1620 .reg_word_size = sizeof(u16),
1621 .reg_cache_default = wm8753_reg,
1622};
69e169da 1623
f0fba2ad
LG		 1624#if defined(CONFIG_SPI_MASTER)
1625static int __devinit wm8753_spi_probe(struct spi_device *spi)
69e169da 1626{
c2bac160 1627 struct wm8753_priv *wm8753;
f0fba2ad 1628 int ret;
69e169da 1629
c2bac160
MB		 1630 wm8753 = kzalloc(sizeof(struct wm8753_priv), GFP_KERNEL);
1631 if (wm8753 == NULL)
1632 return -ENOMEM;
69e169da 1633
f0fba2ad
LG		 1634 wm8753->control_type = SND_SOC_SPI;
1635 spi_set_drvdata(spi, wm8753);
c2bac160 1636
f0fba2ad
LG		 1637 ret = snd_soc_register_codec(&spi->dev,
1638 &soc_codec_dev_wm8753, wm8753_dai, ARRAY_SIZE(wm8753_dai));
1639 if (ret < 0)
1640 kfree(wm8753);
1641 return ret;
69e169da
MB		 1642}
1643
f0fba2ad 1644static int __devexit wm8753_spi_remove(struct spi_device *spi)
69e169da 1645{
f0fba2ad
LG		 1646 snd_soc_unregister_codec(&spi->dev);
1647 kfree(spi_get_drvdata(spi));
1648 return 0;
69e169da
MB		 1649}
1650
f0fba2ad 1651static struct spi_driver wm8753_spi_driver = {
69e169da 1652 .driver = {
f0fba2ad 1653 .name = "wm8753-codec",
f0fba2ad 1654 .owner = THIS_MODULE,
69e169da 1655 },
f0fba2ad
LG		 1656 .probe = wm8753_spi_probe,
1657 .remove = __devexit_p(wm8753_spi_remove),
69e169da 1658};
f0fba2ad 1659#endif /* CONFIG_SPI_MASTER */
69e169da 1660
f0fba2ad
LG		 1661#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1662static __devinit int wm8753_i2c_probe(struct i2c_client *i2c,
1663 const struct i2c_device_id *id)
69e169da 1664{
c2bac160 1665 struct wm8753_priv *wm8753;
f0fba2ad 1666 int ret;
c2bac160
MB		 1667
1668 wm8753 = kzalloc(sizeof(struct wm8753_priv), GFP_KERNEL);
1669 if (wm8753 == NULL)
1670 return -ENOMEM;
69e169da 1671
f0fba2ad 1672 i2c_set_clientdata(i2c, wm8753);
f0fba2ad 1673 wm8753->control_type = SND_SOC_I2C;
69e169da 1674
f0fba2ad
LG		 1675 ret = snd_soc_register_codec(&i2c->dev,
1676 &soc_codec_dev_wm8753, wm8753_dai, ARRAY_SIZE(wm8753_dai));
1677 if (ret < 0)
1678 kfree(wm8753);
1679 return ret;
69e169da
MB		 1680}
1681
f0fba2ad 1682static __devexit int wm8753_i2c_remove(struct i2c_client *client)
69e169da 1683{
f0fba2ad
LG		 1684 snd_soc_unregister_codec(&client->dev);
1685 kfree(i2c_get_clientdata(client));
69e169da
MB		 1686 return 0;
1687}
1688
f0fba2ad
LG		 1689static const struct i2c_device_id wm8753_i2c_id[] = {
1690 { "wm8753", 0 },
1691 { }
1692};
1693MODULE_DEVICE_TABLE(i2c, wm8753_i2c_id);
1694
1695static struct i2c_driver wm8753_i2c_driver = {
69e169da 1696 .driver = {
f0fba2ad
LG		 1697 .name = "wm8753-codec",
1698 .owner = THIS_MODULE,
69e169da 1699 },
f0fba2ad
LG		 1700 .probe = wm8753_i2c_probe,
1701 .remove = __devexit_p(wm8753_i2c_remove),
1702 .id_table = wm8753_i2c_id,
69e169da
MB		 1703};
1704#endif
1705
c9b3a40f 1706static int __init wm8753_modinit(void)
64089b84 1707{
f0fba2ad 1708 int ret = 0;
c2bac160
MB		 1709#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1710 ret = i2c_add_driver(&wm8753_i2c_driver);
f0fba2ad
LG		 1711 if (ret != 0) {
1712 printk(KERN_ERR "Failed to register wm8753 I2C driver: %d\n",
1713 ret);
1714 }
c2bac160
MB		 1715#endif
1716#if defined(CONFIG_SPI_MASTER)
1717 ret = spi_register_driver(&wm8753_spi_driver);
f0fba2ad
LG		 1718 if (ret != 0) {
1719 printk(KERN_ERR "Failed to register wm8753 SPI driver: %d\n",
1720 ret);
1721 }
c2bac160 1722#endif
f0fba2ad 1723 return ret;
64089b84
MB		 1724}
1725module_init(wm8753_modinit);
1726
1727static void __exit wm8753_exit(void)
1728{
c2bac160
MB		 1729#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1730 i2c_del_driver(&wm8753_i2c_driver);
1731#endif
1732#if defined(CONFIG_SPI_MASTER)
1733 spi_unregister_driver(&wm8753_spi_driver);
1734#endif
64089b84
MB		 1735}
1736module_exit(wm8753_exit);
1737
1f53aee0
LG		 1738MODULE_DESCRIPTION("ASoC WM8753 driver");
1739MODULE_AUTHOR("Liam Girdwood");
1740MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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