projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 1f53aee0 LG |
1 | /* |
| 2 | * wm8753.h -- audio driver for WM8753 | |
| 3 | * | |
| 4 | * Copyright 2003 Wolfson Microelectronics PLC. | |
| 5 | * Author: Liam Girdwood | |
| 6 | * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify it | |
| 9 | * under the terms of the GNU General Public License as published by the | |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | |
| 11 | * option) any later version. | |
| 12 | * | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef _WM8753_H | |
| 16 | #define _WM8753_H | |
| 17 | ||
| 18 | /* WM8753 register space */ | |
| 19 | ||
| 20 | #define WM8753_DAC 0x01 | |
| 21 | #define WM8753_ADC 0x02 | |
| 22 | #define WM8753_PCM 0x03 | |
| 23 | #define WM8753_HIFI 0x04 | |
| 24 | #define WM8753_IOCTL 0x05 | |
| 25 | #define WM8753_SRATE1 0x06 | |
| 26 | #define WM8753_SRATE2 0x07 | |
| 27 | #define WM8753_LDAC 0x08 | |
| 28 | #define WM8753_RDAC 0x09 | |
| 29 | #define WM8753_BASS 0x0a | |
| 30 | #define WM8753_TREBLE 0x0b | |
| 31 | #define WM8753_ALC1 0x0c | |
| 32 | #define WM8753_ALC2 0x0d | |
| 33 | #define WM8753_ALC3 0x0e | |
| 34 | #define WM8753_NGATE 0x0f | |
| 35 | #define WM8753_LADC 0x10 | |
| 36 | #define WM8753_RADC 0x11 | |
| 37 | #define WM8753_ADCTL1 0x12 | |
| 38 | #define WM8753_3D 0x13 | |
| 39 | #define WM8753_PWR1 0x14 | |
| 40 | #define WM8753_PWR2 0x15 | |
| 41 | #define WM8753_PWR3 0x16 | |
| 42 | #define WM8753_PWR4 0x17 | |
| 43 | #define WM8753_ID 0x18 | |
| 44 | #define WM8753_INTPOL 0x19 | |
| 45 | #define WM8753_INTEN 0x1a | |
| 46 | #define WM8753_GPIO1 0x1b | |
| 47 | #define WM8753_GPIO2 0x1c | |
| 48 | #define WM8753_RESET 0x1f | |
| 49 | #define WM8753_RECMIX1 0x20 | |
| 50 | #define WM8753_RECMIX2 0x21 | |
| 51 | #define WM8753_LOUTM1 0x22 | |
| 52 | #define WM8753_LOUTM2 0x23 | |
| 53 | #define WM8753_ROUTM1 0x24 | |
| 54 | #define WM8753_ROUTM2 0x25 | |
| 55 | #define WM8753_MOUTM1 0x26 | |
| 56 | #define WM8753_MOUTM2 0x27 | |
| 57 | #define WM8753_LOUT1V 0x28 | |
| 58 | #define WM8753_ROUT1V 0x29 | |
| 59 | #define WM8753_LOUT2V 0x2a | |
| 60 | #define WM8753_ROUT2V 0x2b | |
| 61 | #define WM8753_MOUTV 0x2c | |
| 62 | #define WM8753_OUTCTL 0x2d | |
| 63 | #define WM8753_ADCIN 0x2e | |
| 64 | #define WM8753_INCTL1 0x2f | |
| 65 | #define WM8753_INCTL2 0x30 | |
| 66 | #define WM8753_LINVOL 0x31 | |
| 67 | #define WM8753_RINVOL 0x32 | |
| 68 | #define WM8753_MICBIAS 0x33 | |
| 69 | #define WM8753_CLOCK 0x34 | |
| 70 | #define WM8753_PLL1CTL1 0x35 | |
| 71 | #define WM8753_PLL1CTL2 0x36 | |
| 72 | #define WM8753_PLL1CTL3 0x37 | |
| 73 | #define WM8753_PLL1CTL4 0x38 | |
| 74 | #define WM8753_PLL2CTL1 0x39 | |
| 75 | #define WM8753_PLL2CTL2 0x3a | |
| 76 | #define WM8753_PLL2CTL3 0x3b | |
| 77 | #define WM8753_PLL2CTL4 0x3c | |
| 78 | #define WM8753_BIASCTL 0x3d | |
| 79 | #define WM8753_ADCTL2 0x3f | |
| 80 | ||
| 81 | struct wm8753_setup_data { | |
| 82 | unsigned short i2c_address; | |
| 83 | }; | |
| 84 | ||
| 85 | #define WM8753_PLL1 0 | |
| 86 | #define WM8753_PLL2 1 | |
| 87 | ||
| 88 | /* clock inputs */ | |
| 89 | #define WM8753_MCLK 0 | |
| 90 | #define WM8753_PCMCLK 1 | |
| 91 | ||
| 92 | /* clock divider id's */ | |
| 93 | #define WM8753_PCMDIV 0 | |
| 94 | #define WM8753_BCLKDIV 1 | |
| 95 | #define WM8753_VXCLKDIV 2 | |
| 96 | ||
| 97 | /* PCM clock dividers */ | |
| 98 | #define WM8753_PCM_DIV_1 (0 << 6) | |
| 99 | #define WM8753_PCM_DIV_3 (2 << 6) | |
| 100 | #define WM8753_PCM_DIV_5_5 (3 << 6) | |
| 101 | #define WM8753_PCM_DIV_2 (4 << 6) | |
| 102 | #define WM8753_PCM_DIV_4 (5 << 6) | |
| 103 | #define WM8753_PCM_DIV_6 (6 << 6) | |
| 104 | #define WM8753_PCM_DIV_8 (7 << 6) | |
| 105 | ||
| 106 | /* BCLK clock dividers */ | |
| 107 | #define WM8753_BCLK_DIV_1 (0 << 3) | |
| 108 | #define WM8753_BCLK_DIV_2 (1 << 3) | |
| 109 | #define WM8753_BCLK_DIV_4 (2 << 3) | |
| 110 | #define WM8753_BCLK_DIV_8 (3 << 3) | |
| 111 | #define WM8753_BCLK_DIV_16 (4 << 3) | |
| 112 | ||
| 113 | /* VXCLK clock dividers */ | |
| 114 | #define WM8753_VXCLK_DIV_1 (0 << 6) | |
| 115 | #define WM8753_VXCLK_DIV_2 (1 << 6) | |
| 116 | #define WM8753_VXCLK_DIV_4 (2 << 6) | |
| 117 | #define WM8753_VXCLK_DIV_8 (3 << 6) | |
| 118 | #define WM8753_VXCLK_DIV_16 (4 << 6) | |
| 119 | ||
| 120 | #define WM8753_DAI_HIFI 0 | |
| 121 | #define WM8753_DAI_VOICE 1 | |
| 122 | ||
| e550e17f | 123 | extern struct snd_soc_dai wm8753_dai[2]; |
| 1f53aee0 LG |
124 | extern struct snd_soc_codec_device soc_codec_dev_wm8753; |
| 125 | ||
| 126 | #endif |