projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'hwpoison' of git://git.kernel.org/pub/scm/linux/kernel/git/ak/linux...
[deliverable/linux.git] / sound / soc / codecs / wm8900.c
CommitLineData
0e0e16a8
MB		 1/*
2 * wm8900.c -- WM8900 ALSA Soc Audio driver
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - Tristating.
14 * - TDM.
15 * - Jack detect.
16 * - FLL source configuration, currently only MCLK is supported.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
0e0e16a8
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
35#include "wm8900.h"
36
37/* WM8900 register space */
38#define WM8900_REG_RESET 0x0
39#define WM8900_REG_ID 0x0
40#define WM8900_REG_POWER1 0x1
41#define WM8900_REG_POWER2 0x2
42#define WM8900_REG_POWER3 0x3
43#define WM8900_REG_AUDIO1 0x4
44#define WM8900_REG_AUDIO2 0x5
45#define WM8900_REG_CLOCKING1 0x6
46#define WM8900_REG_CLOCKING2 0x7
47#define WM8900_REG_AUDIO3 0x8
48#define WM8900_REG_AUDIO4 0x9
49#define WM8900_REG_DACCTRL 0xa
50#define WM8900_REG_LDAC_DV 0xb
51#define WM8900_REG_RDAC_DV 0xc
52#define WM8900_REG_SIDETONE 0xd
53#define WM8900_REG_ADCCTRL 0xe
54#define WM8900_REG_LADC_DV 0xf
55#define WM8900_REG_RADC_DV 0x10
56#define WM8900_REG_GPIO 0x12
57#define WM8900_REG_INCTL 0x15
58#define WM8900_REG_LINVOL 0x16
59#define WM8900_REG_RINVOL 0x17
60#define WM8900_REG_INBOOSTMIX1 0x18
61#define WM8900_REG_INBOOSTMIX2 0x19
62#define WM8900_REG_ADCPATH 0x1a
63#define WM8900_REG_AUXBOOST 0x1b
64#define WM8900_REG_ADDCTL 0x1e
65#define WM8900_REG_FLLCTL1 0x24
66#define WM8900_REG_FLLCTL2 0x25
67#define WM8900_REG_FLLCTL3 0x26
68#define WM8900_REG_FLLCTL4 0x27
69#define WM8900_REG_FLLCTL5 0x28
70#define WM8900_REG_FLLCTL6 0x29
71#define WM8900_REG_LOUTMIXCTL1 0x2c
72#define WM8900_REG_ROUTMIXCTL1 0x2d
73#define WM8900_REG_BYPASS1 0x2e
74#define WM8900_REG_BYPASS2 0x2f
75#define WM8900_REG_AUXOUT_CTL 0x30
76#define WM8900_REG_LOUT1CTL 0x33
77#define WM8900_REG_ROUT1CTL 0x34
78#define WM8900_REG_LOUT2CTL 0x35
79#define WM8900_REG_ROUT2CTL 0x36
80#define WM8900_REG_HPCTL1 0x3a
81#define WM8900_REG_OUTBIASCTL 0x73
82
83#define WM8900_MAXREG 0x80
84
85#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
86#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
87#define WM8900_REG_ADDCTL_VMID_DIS 0x20
88#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
89#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
90#define WM8900_REG_ADDCTL_TEMP_SD 0x02
91
92#define WM8900_REG_GPIO_TEMP_ENA 0x2
93
94#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
95#define WM8900_REG_POWER1_BIAS_ENA 0x0008
96#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
97#define WM8900_REG_POWER1_FLL_ENA 0x0040
98
99#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
100#define WM8900_REG_POWER2_ADCL_ENA 0x0002
101#define WM8900_REG_POWER2_ADCR_ENA 0x0001
102
103#define WM8900_REG_POWER3_DACL_ENA 0x0002
104#define WM8900_REG_POWER3_DACR_ENA 0x0001
105
106#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
107#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
108#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
109
110#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
111#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
112#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
113#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
114
115#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
116#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
117
118#define WM8900_REG_DACCTRL_MUTE 0x004
21002e20 119#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
0e0e16a8
MB		 120#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
121
122#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
123
124#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
125
126#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
127
128#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
129
130#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
131#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
132#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
133#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
134#define WM8900_REG_HPCTL1_HP_SHORT 0x08
135#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
136
137#define WM8900_LRC_MASK 0xfc00
138
139struct snd_soc_codec_device soc_codec_dev_wm8900;
140
141struct wm8900_priv {
78e19a39
MB		 142 struct snd_soc_codec codec;
143
144 u16 reg_cache[WM8900_MAXREG];
145
0e0e16a8
MB		 146 u32 fll_in; /* FLL input frequency */
147 u32 fll_out; /* FLL output frequency */
148};
149
150/*
151 * wm8900 register cache. We can't read the entire register space and we
152 * have slow control buses so we cache the registers.
153 */
154static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
155 0x8900, 0x0000,
156 0xc000, 0x0000,
157 0x4050, 0x4000,
158 0x0008, 0x0000,
159 0x0040, 0x0040,
160 0x1004, 0x00c0,
161 0x00c0, 0x0000,
162 0x0100, 0x00c0,
163 0x00c0, 0x0000,
164 0xb001, 0x0000,
165 0x0000, 0x0044,
166 0x004c, 0x004c,
167 0x0044, 0x0044,
168 0x0000, 0x0044,
169 0x0000, 0x0000,
170 0x0002, 0x0000,
171 0x0000, 0x0000,
172 0x0000, 0x0000,
173 0x0008, 0x0000,
174 0x0000, 0x0008,
175 0x0097, 0x0100,
176 0x0000, 0x0000,
177 0x0050, 0x0050,
178 0x0055, 0x0055,
179 0x0055, 0x0000,
180 0x0000, 0x0079,
181 0x0079, 0x0079,
182 0x0079, 0x0000,
183 /* Remaining registers all zero */
184};
185
8d50e447 186static int wm8900_volatile_register(unsigned int reg)
0e0e16a8
MB		 187{
188 switch (reg) {
189 case WM8900_REG_ID:
8d50e447
MB		 190 case WM8900_REG_POWER1:
191 return 1;
0e0e16a8 192 default:
8d50e447 193 return 0;
0e0e16a8
MB		 194 }
195}
196
197static void wm8900_reset(struct snd_soc_codec *codec)
198{
8d50e447 199 snd_soc_write(codec, WM8900_REG_RESET, 0);
0e0e16a8
MB		 200
201 memcpy(codec->reg_cache, wm8900_reg_defaults,
202 sizeof(codec->reg_cache));
203}
204
205static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
206 struct snd_kcontrol *kcontrol, int event)
207{
208 struct snd_soc_codec *codec = w->codec;
8d50e447 209 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
0e0e16a8
MB		 210
211 switch (event) {
212 case SND_SOC_DAPM_PRE_PMU:
213 /* Clamp headphone outputs */
214 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
215 WM8900_REG_HPCTL1_HP_CLAMP_OP;
8d50e447 216 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 217 break;
218
219 case SND_SOC_DAPM_POST_PMU:
220 /* Enable the input stage */
221 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
222 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
223 WM8900_REG_HPCTL1_HP_SHORT2 |
224 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 225 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 226
227 msleep(400);
228
229 /* Enable the output stage */
230 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
231 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 232 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 233
234 /* Remove the shorts */
235 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
8d50e447 236 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8 237 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 238 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 239 break;
240
241 case SND_SOC_DAPM_PRE_PMD:
242 /* Short the output */
243 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 244 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 245
246 /* Disable the output stage */
247 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 248 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 249
250 /* Clamp the outputs and power down input */
251 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
252 WM8900_REG_HPCTL1_HP_CLAMP_OP;
253 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 254 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 255 break;
256
257 case SND_SOC_DAPM_POST_PMD:
258 /* Disable everything */
8d50e447 259 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 260 break;
261
262 default:
263 BUG();
264 }
265
266 return 0;
267}
268
269static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
270
271static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
272
273static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
274
275static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
276
277static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
278
279static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
280
281static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
282
283static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
284
285static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
286
287static const struct soc_enum mic_bias_level =
288SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
289
290static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
291
292static const struct soc_enum dac_mute_rate =
293SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
294
295static const char *dac_deemphasis_txt[] = {
296 "Disabled", "32kHz", "44.1kHz", "48kHz"
297};
298
299static const struct soc_enum dac_deemphasis =
300SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
301
302static const char *adc_hpf_cut_txt[] = {
303 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
304};
305
306static const struct soc_enum adc_hpf_cut =
307SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
308
309static const char *lr_txt[] = {
310 "Left", "Right"
311};
312
313static const struct soc_enum aifl_src =
314SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
315
316static const struct soc_enum aifr_src =
317SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
318
319static const struct soc_enum dacl_src =
320SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
321
322static const struct soc_enum dacr_src =
323SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
324
325static const char *sidetone_txt[] = {
326 "Disabled", "Left ADC", "Right ADC"
327};
328
329static const struct soc_enum dacl_sidetone =
330SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
331
332static const struct soc_enum dacr_sidetone =
333SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
334
335static const struct snd_kcontrol_new wm8900_snd_controls[] = {
336SOC_ENUM("Mic Bias Level", mic_bias_level),
337
338SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
339 in_pga_tlv),
340SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
341SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
342
343SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
344 in_pga_tlv),
345SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
346SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
347
348SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
349SOC_ENUM("DAC Mute Rate", dac_mute_rate),
350SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
351SOC_ENUM("DAC Deemphasis", dac_deemphasis),
0e0e16a8
MB		 352SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
353 12, 1, 0),
354
355SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
356SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
357SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
358SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
359 adc_svol_tlv),
360SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
361 adc_svol_tlv),
362SOC_ENUM("Left Digital Audio Source", aifl_src),
363SOC_ENUM("Right Digital Audio Source", aifr_src),
364
365SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
366 dac_boost_tlv),
367SOC_ENUM("Left DAC Source", dacl_src),
368SOC_ENUM("Right DAC Source", dacr_src),
369SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
370SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
371SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
372
373SOC_DOUBLE_R_TLV("Digital Playback Volume",
374 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
375 1, 96, 0, dac_tlv),
376SOC_DOUBLE_R_TLV("Digital Capture Volume",
377 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
378
379SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
380 out_mix_tlv),
381SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
382 out_mix_tlv),
383SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
384 out_mix_tlv),
385SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
386 out_mix_tlv),
387
388SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
389 out_mix_tlv),
390SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
391 out_mix_tlv),
392SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
393 out_mix_tlv),
394SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
395 out_mix_tlv),
396
397SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
398 in_boost_tlv),
399SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
400 in_boost_tlv),
401SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
402 in_boost_tlv),
403SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
404 in_boost_tlv),
405SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
406 in_boost_tlv),
407SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
408 in_boost_tlv),
409
410SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
411 0, 63, 0, out_pga_tlv),
412SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
413 6, 1, 1),
414SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
415 7, 1, 0),
416
417SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
418 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
419 0, 63, 0, out_pga_tlv),
420SOC_DOUBLE_R("LINEOUT2 Switch",
421 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
422SOC_DOUBLE_R("LINEOUT2 ZC Switch",
423 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
424SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
425 0, 1, 1),
426
427};
428
0e0e16a8
MB		 429static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
430SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
431
432static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
433SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
434
435static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
436SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
437SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
438SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
439SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
440SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
441};
442
443static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
444SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
445SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
446SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
447SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
448SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
449};
450
451static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
452SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
453SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
454SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
455SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
456};
457
458static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
459SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
460SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
461SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
462SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
463};
464
465static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
466SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
467SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
468SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
469};
470
471static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
472SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
473SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
474SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
475};
476
477static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
478
479static const struct soc_enum wm8900_lineout2_lp_mux =
480SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
481
482static const struct snd_kcontrol_new wm8900_lineout2_lp =
483SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
484
485static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
486
487/* Externally visible pins */
488SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
489SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
490SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
491SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
492SND_SOC_DAPM_OUTPUT("HP_L"),
493SND_SOC_DAPM_OUTPUT("HP_R"),
494
495SND_SOC_DAPM_INPUT("RINPUT1"),
496SND_SOC_DAPM_INPUT("LINPUT1"),
497SND_SOC_DAPM_INPUT("RINPUT2"),
498SND_SOC_DAPM_INPUT("LINPUT2"),
499SND_SOC_DAPM_INPUT("RINPUT3"),
500SND_SOC_DAPM_INPUT("LINPUT3"),
501SND_SOC_DAPM_INPUT("AUX"),
502
503SND_SOC_DAPM_VMID("VMID"),
504
505/* Input */
506SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
507 wm8900_linpga_controls,
508 ARRAY_SIZE(wm8900_linpga_controls)),
509SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
510 wm8900_rinpga_controls,
511 ARRAY_SIZE(wm8900_rinpga_controls)),
512
513SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
514 wm8900_linmix_controls,
515 ARRAY_SIZE(wm8900_linmix_controls)),
516SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
517 wm8900_rinmix_controls,
518 ARRAY_SIZE(wm8900_rinmix_controls)),
519
520SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
521
522SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
523SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
524
525/* Output */
526SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
527SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
528
529SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
530 wm8900_hp_event,
531 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
532 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
533
534SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
535SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
536
537SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
538SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
539SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
540
541SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
542 wm8900_loutmix_controls,
543 ARRAY_SIZE(wm8900_loutmix_controls)),
544SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
545 wm8900_routmix_controls,
546 ARRAY_SIZE(wm8900_routmix_controls)),
547};
548
549/* Target, Path, Source */
550static const struct snd_soc_dapm_route audio_map[] = {
551/* Inputs */
552{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
553{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
554{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
555
556{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
557{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
558{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
559
560{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
561{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
562{"Left Input Mixer", "AUX Switch", "AUX"},
563{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
564
565{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
566{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
567{"Right Input Mixer", "AUX Switch", "AUX"},
568{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
569
570{"ADCL", NULL, "Left Input Mixer"},
571{"ADCR", NULL, "Right Input Mixer"},
572
573/* Outputs */
574{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
575{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
576{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
577{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
578
579{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
580{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
581{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
582{"LINEOUT2L", NULL, "LINEOUT2 LP"},
583
584{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
585{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
586{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
587{"LINEOUT2R", NULL, "LINEOUT2 LP"},
588
589{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
590{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
591{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
592{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
593{"Left Output Mixer", "DACL Switch", "DACL"},
594
595{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
596{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
597{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
598{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
599{"Right Output Mixer", "DACR Switch", "DACR"},
600
601/* Note that the headphone output stage needs to be connected
602 * externally to LINEOUT2 via DC blocking capacitors. Other
603 * configurations are not supported.
604 *
605 * Note also that left and right headphone paths are treated as a
606 * mono path.
607 */
608{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
609{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
610{"HP_L", NULL, "Headphone Amplifier"},
611{"HP_R", NULL, "Headphone Amplifier"},
612};
613
614static int wm8900_add_widgets(struct snd_soc_codec *codec)
615{
616 snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets,
617 ARRAY_SIZE(wm8900_dapm_widgets));
618
619 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
620
621 snd_soc_dapm_new_widgets(codec);
622
623 return 0;
624}
625
626static int wm8900_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 627 struct snd_pcm_hw_params *params,
628 struct snd_soc_dai *dai)
0e0e16a8
MB		 629{
630 struct snd_soc_pcm_runtime *rtd = substream->private_data;
631 struct snd_soc_device *socdev = rtd->socdev;
6627a653 632 struct snd_soc_codec *codec = socdev->card->codec;
0e0e16a8
MB		 633 u16 reg;
634
8d50e447 635 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
0e0e16a8
MB		 636
637 switch (params_format(params)) {
638 case SNDRV_PCM_FORMAT_S16_LE:
639 break;
640 case SNDRV_PCM_FORMAT_S20_3LE:
641 reg |= 0x20;
642 break;
643 case SNDRV_PCM_FORMAT_S24_LE:
644 reg |= 0x40;
645 break;
646 case SNDRV_PCM_FORMAT_S32_LE:
647 reg |= 0x60;
648 break;
649 default:
650 return -EINVAL;
651 }
652
8d50e447 653 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
0e0e16a8 654
21002e20 655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
8d50e447 656 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
21002e20
MB		 657
658 if (params_rate(params) <= 24000)
659 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
660 else
661 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
662
8d50e447 663 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
21002e20
MB		 664 }
665
0e0e16a8
MB		 666 return 0;
667}
668
669/* FLL divisors */
670struct _fll_div {
671 u16 fll_ratio;
672 u16 fllclk_div;
673 u16 fll_slow_lock_ref;
674 u16 n;
675 u16 k;
676};
677
678/* The size in bits of the FLL divide multiplied by 10
679 * to allow rounding later */
680#define FIXED_FLL_SIZE ((1 << 16) * 10)
681
682static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
683 unsigned int Fout)
684{
685 u64 Kpart;
686 unsigned int K, Ndiv, Nmod, target;
687 unsigned int div;
688
689 BUG_ON(!Fout);
690
691 /* The FLL must run at 90-100MHz which is then scaled down to
692 * the output value by FLLCLK_DIV. */
693 target = Fout;
694 div = 1;
695 while (target < 90000000) {
696 div *= 2;
697 target *= 2;
698 }
699
700 if (target > 100000000)
449bd54d
RK		 701 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
702 " Fout=%u\n", target, Fref, Fout);
0e0e16a8
MB		 703 if (div > 32) {
704 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
449bd54d 705 "Fref=%u, Fout=%u, target=%u\n",
0e0e16a8
MB		 706 div, Fref, Fout, target);
707 return -EINVAL;
708 }
709
710 fll_div->fllclk_div = div >> 2;
711
712 if (Fref < 48000)
713 fll_div->fll_slow_lock_ref = 1;
714 else
715 fll_div->fll_slow_lock_ref = 0;
716
717 Ndiv = target / Fref;
718
719 if (Fref < 1000000)
720 fll_div->fll_ratio = 8;
721 else
722 fll_div->fll_ratio = 1;
723
724 fll_div->n = Ndiv / fll_div->fll_ratio;
725 Nmod = (target / fll_div->fll_ratio) % Fref;
726
727 /* Calculate fractional part - scale up so we can round. */
728 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
729
730 do_div(Kpart, Fref);
731
732 K = Kpart & 0xFFFFFFFF;
733
734 if ((K % 10) >= 5)
735 K += 5;
736
737 /* Move down to proper range now rounding is done */
738 fll_div->k = K / 10;
739
740 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
741 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
742
743 return 0;
744}
745
746static int wm8900_set_fll(struct snd_soc_codec *codec,
747 int fll_id, unsigned int freq_in, unsigned int freq_out)
748{
749 struct wm8900_priv *wm8900 = codec->private_data;
750 struct _fll_div fll_div;
751 unsigned int reg;
752
753 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
754 return 0;
755
756 /* The digital side should be disabled during any change. */
8d50e447
MB		 757 reg = snd_soc_read(codec, WM8900_REG_POWER1);
758 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 759 reg & (~WM8900_REG_POWER1_FLL_ENA));
760
761 /* Disable the FLL? */
762 if (!freq_in || !freq_out) {
8d50e447
MB		 763 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
764 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 765 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
766
8d50e447
MB		 767 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
768 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 769 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
770
771 wm8900->fll_in = freq_in;
772 wm8900->fll_out = freq_out;
773
774 return 0;
775 }
776
777 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
778 goto reenable;
779
780 wm8900->fll_in = freq_in;
781 wm8900->fll_out = freq_out;
782
783 /* The osclilator *MUST* be enabled before we enable the
784 * digital circuit. */
8d50e447 785 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 786 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
787
8d50e447
MB		 788 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
789 snd_soc_write(codec, WM8900_REG_FLLCTL5,
0e0e16a8
MB		 790 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
791
792 if (fll_div.k) {
8d50e447 793 snd_soc_write(codec, WM8900_REG_FLLCTL2,
0e0e16a8 794 (fll_div.k >> 8) | 0x100);
8d50e447 795 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
0e0e16a8 796 } else
8d50e447 797 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
0e0e16a8
MB		 798
799 if (fll_div.fll_slow_lock_ref)
8d50e447 800 snd_soc_write(codec, WM8900_REG_FLLCTL6,
0e0e16a8
MB		 801 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
802 else
8d50e447 803 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
0e0e16a8 804
8d50e447
MB		 805 reg = snd_soc_read(codec, WM8900_REG_POWER1);
806 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 807 reg | WM8900_REG_POWER1_FLL_ENA);
808
809reenable:
8d50e447
MB		 810 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
811 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 812 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
813
814 return 0;
815}
816
817static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai,
818 int pll_id, unsigned int freq_in, unsigned int freq_out)
819{
820 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
821}
822
823static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
824 int div_id, int div)
825{
826 struct snd_soc_codec *codec = codec_dai->codec;
827 unsigned int reg;
828
829 switch (div_id) {
830 case WM8900_BCLK_DIV:
8d50e447
MB		 831 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
832 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 833 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
834 break;
835 case WM8900_OPCLK_DIV:
8d50e447
MB		 836 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
837 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 838 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
839 break;
840 case WM8900_DAC_LRCLK:
8d50e447
MB		 841 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
842 snd_soc_write(codec, WM8900_REG_AUDIO4,
0e0e16a8
MB		 843 div | (reg & WM8900_LRC_MASK));
844 break;
845 case WM8900_ADC_LRCLK:
8d50e447
MB		 846 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
847 snd_soc_write(codec, WM8900_REG_AUDIO3,
0e0e16a8
MB		 848 div | (reg & WM8900_LRC_MASK));
849 break;
850 case WM8900_DAC_CLKDIV:
8d50e447
MB		 851 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
852 snd_soc_write(codec, WM8900_REG_CLOCKING2,
0e0e16a8
MB		 853 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
854 break;
855 case WM8900_ADC_CLKDIV:
8d50e447
MB		 856 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
857 snd_soc_write(codec, WM8900_REG_CLOCKING2,
0e0e16a8
MB		 858 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
859 break;
860 case WM8900_LRCLK_MODE:
8d50e447
MB		 861 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
862 snd_soc_write(codec, WM8900_REG_DACCTRL,
0e0e16a8
MB		 863 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
864 break;
865 default:
866 return -EINVAL;
867 }
868
869 return 0;
870}
871
872
873static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
874 unsigned int fmt)
875{
876 struct snd_soc_codec *codec = codec_dai->codec;
877 unsigned int clocking1, aif1, aif3, aif4;
878
8d50e447
MB		 879 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
880 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
881 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
882 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
0e0e16a8
MB		 883
884 /* set master/slave audio interface */
885 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
886 case SND_SOC_DAIFMT_CBS_CFS:
887 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
888 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
889 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
890 break;
891 case SND_SOC_DAIFMT_CBS_CFM:
892 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
893 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
894 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
895 break;
896 case SND_SOC_DAIFMT_CBM_CFM:
897 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
898 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
899 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
900 break;
901 case SND_SOC_DAIFMT_CBM_CFS:
902 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
903 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
904 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
905 break;
906 default:
907 return -EINVAL;
908 }
909
910 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
911 case SND_SOC_DAIFMT_DSP_A:
912 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
913 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
914 break;
915 case SND_SOC_DAIFMT_DSP_B:
916 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
917 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
918 break;
919 case SND_SOC_DAIFMT_I2S:
920 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
921 aif1 |= 0x10;
922 break;
923 case SND_SOC_DAIFMT_RIGHT_J:
924 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
925 break;
926 case SND_SOC_DAIFMT_LEFT_J:
927 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
928 aif1 |= 0x8;
929 break;
930 default:
931 return -EINVAL;
932 }
933
934 /* Clock inversion */
935 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
936 case SND_SOC_DAIFMT_DSP_A:
937 case SND_SOC_DAIFMT_DSP_B:
938 /* frame inversion not valid for DSP modes */
939 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
940 case SND_SOC_DAIFMT_NB_NF:
941 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
942 break;
943 case SND_SOC_DAIFMT_IB_NF:
944 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
945 break;
946 default:
947 return -EINVAL;
948 }
949 break;
950 case SND_SOC_DAIFMT_I2S:
951 case SND_SOC_DAIFMT_RIGHT_J:
952 case SND_SOC_DAIFMT_LEFT_J:
953 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
954 case SND_SOC_DAIFMT_NB_NF:
955 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
956 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
957 break;
958 case SND_SOC_DAIFMT_IB_IF:
959 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
960 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
961 break;
962 case SND_SOC_DAIFMT_IB_NF:
963 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
964 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
965 break;
966 case SND_SOC_DAIFMT_NB_IF:
967 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
968 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
969 break;
970 default:
971 return -EINVAL;
972 }
973 break;
974 default:
975 return -EINVAL;
976 }
977
8d50e447
MB		 978 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
979 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
980 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
981 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
0e0e16a8
MB		 982
983 return 0;
984}
985
986static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
987{
988 struct snd_soc_codec *codec = codec_dai->codec;
989 u16 reg;
990
8d50e447 991 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
0e0e16a8
MB		 992
993 if (mute)
994 reg |= WM8900_REG_DACCTRL_MUTE;
995 else
996 reg &= ~WM8900_REG_DACCTRL_MUTE;
997
8d50e447 998 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
0e0e16a8
MB		 999
1000 return 0;
1001}
1002
1003#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1004 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1005 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1006
1007#define WM8900_PCM_FORMATS \
1008 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1009 SNDRV_PCM_FORMAT_S24_LE)
1010
6335d055
EM		 1011static struct snd_soc_dai_ops wm8900_dai_ops = {
1012 .hw_params = wm8900_hw_params,
1013 .set_clkdiv = wm8900_set_dai_clkdiv,
1014 .set_pll = wm8900_set_dai_pll,
1015 .set_fmt = wm8900_set_dai_fmt,
1016 .digital_mute = wm8900_digital_mute,
1017};
1018
0e0e16a8
MB		 1019struct snd_soc_dai wm8900_dai = {
1020 .name = "WM8900 HiFi",
1021 .playback = {
1022 .stream_name = "HiFi Playback",
1023 .channels_min = 1,
1024 .channels_max = 2,
1025 .rates = WM8900_RATES,
1026 .formats = WM8900_PCM_FORMATS,
1027 },
1028 .capture = {
1029 .stream_name = "HiFi Capture",
1030 .channels_min = 1,
1031 .channels_max = 2,
1032 .rates = WM8900_RATES,
1033 .formats = WM8900_PCM_FORMATS,
1034 },
6335d055 1035 .ops = &wm8900_dai_ops,
0e0e16a8
MB		 1036};
1037EXPORT_SYMBOL_GPL(wm8900_dai);
1038
1039static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1040 enum snd_soc_bias_level level)
1041{
1042 u16 reg;
1043
1044 switch (level) {
1045 case SND_SOC_BIAS_ON:
1046 /* Enable thermal shutdown */
8d50e447
MB		 1047 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1048 snd_soc_write(codec, WM8900_REG_GPIO,
0e0e16a8 1049 reg | WM8900_REG_GPIO_TEMP_ENA);
8d50e447
MB		 1050 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1051 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1052 reg | WM8900_REG_ADDCTL_TEMP_SD);
1053 break;
1054
1055 case SND_SOC_BIAS_PREPARE:
1056 break;
1057
1058 case SND_SOC_BIAS_STANDBY:
1059 /* Charge capacitors if initial power up */
1060 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1061 /* STARTUP_BIAS_ENA on */
8d50e447 1062 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1063 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1064
1065 /* Startup bias mode */
8d50e447 1066 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1067 WM8900_REG_ADDCTL_BIAS_SRC |
1068 WM8900_REG_ADDCTL_VMID_SOFTST);
1069
1070 /* VMID 2x50k */
8d50e447 1071 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1072 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1073
1074 /* Allow capacitors to charge */
1075 schedule_timeout_interruptible(msecs_to_jiffies(400));
1076
1077 /* Enable bias */
8d50e447 1078 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1079 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1080 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1081
8d50e447 1082 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
0e0e16a8 1083
8d50e447 1084 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1085 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1086 }
1087
8d50e447
MB		 1088 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1089 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1090 (reg & WM8900_REG_POWER1_FLL_ENA) |
1091 WM8900_REG_POWER1_BIAS_ENA | 0x1);
8d50e447 1092 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8 1093 WM8900_REG_POWER2_SYSCLK_ENA);
8d50e447 1094 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1095 break;
1096
1097 case SND_SOC_BIAS_OFF:
1098 /* Startup bias enable */
8d50e447
MB		 1099 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1100 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8 1101 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
8d50e447 1102 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1103 WM8900_REG_ADDCTL_BIAS_SRC |
1104 WM8900_REG_ADDCTL_VMID_SOFTST);
1105
1106 /* Discharge caps */
8d50e447 1107 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1108 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1109 schedule_timeout_interruptible(msecs_to_jiffies(500));
1110
1111 /* Remove clamp */
8d50e447 1112 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 1113
1114 /* Power down */
8d50e447
MB		 1115 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1116 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1117 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1118 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1119
1120 /* Need to let things settle before stopping the clock
1121 * to ensure that restart works, see "Stopping the
1122 * master clock" in the datasheet. */
1123 schedule_timeout_interruptible(msecs_to_jiffies(1));
8d50e447 1124 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8
MB		 1125 WM8900_REG_POWER2_SYSCLK_ENA);
1126 break;
1127 }
1128 codec->bias_level = level;
1129 return 0;
1130}
1131
1132static int wm8900_suspend(struct platform_device *pdev, pm_message_t state)
1133{
1134 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1135 struct snd_soc_codec *codec = socdev->card->codec;
0e0e16a8
MB		 1136 struct wm8900_priv *wm8900 = codec->private_data;
1137 int fll_out = wm8900->fll_out;
1138 int fll_in = wm8900->fll_in;
1139 int ret;
1140
1141 /* Stop the FLL in an orderly fashion */
1142 ret = wm8900_set_fll(codec, 0, 0, 0);
1143 if (ret != 0) {
1144 dev_err(&pdev->dev, "Failed to stop FLL\n");
1145 return ret;
1146 }
1147
1148 wm8900->fll_out = fll_out;
1149 wm8900->fll_in = fll_in;
1150
1151 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1152
1153 return 0;
1154}
1155
1156static int wm8900_resume(struct platform_device *pdev)
1157{
1158 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1159 struct snd_soc_codec *codec = socdev->card->codec;
0e0e16a8
MB		 1160 struct wm8900_priv *wm8900 = codec->private_data;
1161 u16 *cache;
1162 int i, ret;
1163
1164 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1165 GFP_KERNEL);
1166
1167 wm8900_reset(codec);
1168 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1169
1170 /* Restart the FLL? */
1171 if (wm8900->fll_out) {
1172 int fll_out = wm8900->fll_out;
1173 int fll_in = wm8900->fll_in;
1174
1175 wm8900->fll_in = 0;
1176 wm8900->fll_out = 0;
1177
1178 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1179 if (ret != 0) {
1180 dev_err(&pdev->dev, "Failed to restart FLL\n");
1181 return ret;
1182 }
1183 }
1184
1185 if (cache) {
1186 for (i = 0; i < WM8900_MAXREG; i++)
8d50e447 1187 snd_soc_write(codec, i, cache[i]);
0e0e16a8
MB		 1188 kfree(cache);
1189 } else
1190 dev_err(&pdev->dev, "Unable to allocate register cache\n");
1191
1192 return 0;
1193}
1194
78e19a39
MB		 1195static struct snd_soc_codec *wm8900_codec;
1196
c6f29811
MB		 1197static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1198 const struct i2c_device_id *id)
0e0e16a8 1199{
78e19a39
MB		 1200 struct wm8900_priv *wm8900;
1201 struct snd_soc_codec *codec;
0e0e16a8 1202 unsigned int reg;
78e19a39
MB		 1203 int ret;
1204
1205 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1206 if (wm8900 == NULL)
1207 return -ENOMEM;
1208
1209 codec = &wm8900->codec;
1210 codec->private_data = wm8900;
1211 codec->reg_cache = &wm8900->reg_cache[0];
1212 codec->reg_cache_size = WM8900_MAXREG;
1213
1214 mutex_init(&codec->mutex);
1215 INIT_LIST_HEAD(&codec->dapm_widgets);
1216 INIT_LIST_HEAD(&codec->dapm_paths);
0e0e16a8
MB		 1217
1218 codec->name = "WM8900";
1219 codec->owner = THIS_MODULE;
0e0e16a8
MB		 1220 codec->dai = &wm8900_dai;
1221 codec->num_dai = 1;
78e19a39
MB		 1222 codec->control_data = i2c;
1223 codec->set_bias_level = wm8900_set_bias_level;
8d50e447 1224 codec->volatile_register = wm8900_volatile_register;
78e19a39 1225 codec->dev = &i2c->dev;
0e0e16a8 1226
8d50e447
MB		 1227 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1228 if (ret != 0) {
1229 dev_err(&i2c->dev, "Failed to set cache I/O: %d\n", ret);
1230 goto err;
1231 }
1232
1233 reg = snd_soc_read(codec, WM8900_REG_ID);
0e0e16a8 1234 if (reg != 0x8900) {
78e19a39
MB		 1235 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg);
1236 ret = -ENODEV;
1237 goto err;
0e0e16a8
MB		 1238 }
1239
1240 /* Read back from the chip */
8d50e447 1241 reg = snd_soc_read(codec, WM8900_REG_POWER1);
0e0e16a8 1242 reg = (reg >> 12) & 0xf;
78e19a39 1243 dev_info(&i2c->dev, "WM8900 revision %d\n", reg);
0e0e16a8
MB		 1244
1245 wm8900_reset(codec);
1246
78e19a39
MB		 1247 /* Turn the chip on */
1248 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1249
0e0e16a8 1250 /* Latch the volume update bits */
8d50e447
MB		 1251 snd_soc_write(codec, WM8900_REG_LINVOL,
1252 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1253 snd_soc_write(codec, WM8900_REG_RINVOL,
1254 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1255 snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1256 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1257 snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1258 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1259 snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1260 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1261 snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1262 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1263 snd_soc_write(codec, WM8900_REG_LDAC_DV,
1264 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1265 snd_soc_write(codec, WM8900_REG_RDAC_DV,
1266 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1267 snd_soc_write(codec, WM8900_REG_LADC_DV,
1268 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1269 snd_soc_write(codec, WM8900_REG_RADC_DV,
1270 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
0e0e16a8
MB		 1271
1272 /* Set the DAC and mixer output bias */
8d50e447 1273 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
0e0e16a8 1274
78e19a39 1275 wm8900_dai.dev = &i2c->dev;
0e0e16a8 1276
78e19a39 1277 wm8900_codec = codec;
0e0e16a8 1278
78e19a39
MB		 1279 ret = snd_soc_register_codec(codec);
1280 if (ret != 0) {
1281 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1282 goto err;
1283 }
0e0e16a8 1284
78e19a39
MB		 1285 ret = snd_soc_register_dai(&wm8900_dai);
1286 if (ret != 0) {
1287 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1288 goto err_codec;
0e0e16a8 1289 }
0e0e16a8 1290
0e0e16a8 1291 return ret;
0e0e16a8 1292
78e19a39
MB		 1293err_codec:
1294 snd_soc_unregister_codec(codec);
1295err:
1296 kfree(wm8900);
1297 wm8900_codec = NULL;
1298 return ret;
0e0e16a8
MB		 1299}
1300
c6f29811 1301static __devexit int wm8900_i2c_remove(struct i2c_client *client)
0e0e16a8 1302{
f0752331 1303 snd_soc_unregister_dai(&wm8900_dai);
78e19a39
MB		 1304 snd_soc_unregister_codec(wm8900_codec);
1305
1306 wm8900_set_bias_level(wm8900_codec, SND_SOC_BIAS_OFF);
1307
f0752331 1308 wm8900_dai.dev = NULL;
78e19a39
MB		 1309 kfree(wm8900_codec->private_data);
1310 wm8900_codec = NULL;
1311
0e0e16a8
MB		 1312 return 0;
1313}
1314
b3b50b3f
MB		 1315#ifdef CONFIG_PM
1316static int wm8900_i2c_suspend(struct i2c_client *client, pm_message_t msg)
1317{
1318 return snd_soc_suspend_device(&client->dev);
1319}
1320
1321static int wm8900_i2c_resume(struct i2c_client *client)
1322{
1323 return snd_soc_resume_device(&client->dev);
1324}
1325#else
1326#define wm8900_i2c_suspend NULL
1327#define wm8900_i2c_resume NULL
1328#endif
1329
8ae6a552
JD		 1330static const struct i2c_device_id wm8900_i2c_id[] = {
1331 { "wm8900", 0 },
1332 { }
1333};
1334MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
0e0e16a8 1335
0e0e16a8
MB		 1336static struct i2c_driver wm8900_i2c_driver = {
1337 .driver = {
78e19a39 1338 .name = "WM8900",
0e0e16a8
MB		 1339 .owner = THIS_MODULE,
1340 },
8ae6a552 1341 .probe = wm8900_i2c_probe,
c6f29811 1342 .remove = __devexit_p(wm8900_i2c_remove),
b3b50b3f
MB		 1343 .suspend = wm8900_i2c_suspend,
1344 .resume = wm8900_i2c_resume,
8ae6a552 1345 .id_table = wm8900_i2c_id,
0e0e16a8
MB		 1346};
1347
0e0e16a8
MB		 1348static int wm8900_probe(struct platform_device *pdev)
1349{
1350 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
0e0e16a8
MB		 1351 struct snd_soc_codec *codec;
1352 int ret = 0;
1353
78e19a39 1354 if (!wm8900_codec) {
f0752331
MB		 1355 dev_err(&pdev->dev, "I2C client not yet instantiated\n");
1356 return -ENODEV;
1357 }
0e0e16a8 1358
78e19a39 1359 codec = wm8900_codec;
6627a653 1360 socdev->card->codec = codec;
0e0e16a8 1361
78e19a39
MB		 1362 /* Register pcms */
1363 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1364 if (ret < 0) {
1365 dev_err(&pdev->dev, "Failed to register new PCMs\n");
1366 goto pcm_err;
1367 }
0e0e16a8 1368
3e8e1952
IM		 1369 snd_soc_add_controls(codec, wm8900_snd_controls,
1370 ARRAY_SIZE(wm8900_snd_controls));
78e19a39
MB		 1371 wm8900_add_widgets(codec);
1372
1373 ret = snd_soc_init_card(socdev);
1374 if (ret < 0) {
1375 dev_err(&pdev->dev, "Failed to register card\n");
1376 goto card_err;
1377 }
f0752331 1378
78e19a39 1379 return ret;
f0752331 1380
78e19a39
MB		 1381card_err:
1382 snd_soc_free_pcms(socdev);
1383 snd_soc_dapm_free(socdev);
1384pcm_err:
0e0e16a8
MB		 1385 return ret;
1386}
1387
1388/* power down chip */
1389static int wm8900_remove(struct platform_device *pdev)
1390{
1391 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
0e0e16a8
MB		 1392
1393 snd_soc_free_pcms(socdev);
1394 snd_soc_dapm_free(socdev);
0e0e16a8
MB		 1395
1396 return 0;
1397}
1398
1399struct snd_soc_codec_device soc_codec_dev_wm8900 = {
1400 .probe = wm8900_probe,
1401 .remove = wm8900_remove,
1402 .suspend = wm8900_suspend,
1403 .resume = wm8900_resume,
1404};
1405EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900);
1406
c9b3a40f 1407static int __init wm8900_modinit(void)
64089b84 1408{
f0752331 1409 return i2c_add_driver(&wm8900_i2c_driver);
64089b84
MB		 1410}
1411module_init(wm8900_modinit);
1412
1413static void __exit wm8900_exit(void)
1414{
f0752331 1415 i2c_del_driver(&wm8900_i2c_driver);
64089b84
MB		 1416}
1417module_exit(wm8900_exit);
1418
0e0e16a8
MB		 1419MODULE_DESCRIPTION("ASoC WM8900 driver");
1420MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1421MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.119397 seconds and 5 git commands to generate.