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ASoC: soc-cache: Add support for default readable()/volatile() functions
[deliverable/linux.git] / sound / soc / codecs / wm8900.c
CommitLineData
0e0e16a8
MB		 1/*
2 * wm8900.c -- WM8900 ALSA Soc Audio driver
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - Tristating.
14 * - TDM.
15 * - Jack detect.
16 * - FLL source configuration, currently only MCLK is supported.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
0e0e16a8
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
f0fba2ad 26#include <linux/spi/spi.h>
0e0e16a8 27#include <linux/platform_device.h>
5a0e3ad6 28#include <linux/slab.h>
0e0e16a8
MB		 29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
0e0e16a8
MB		 33#include <sound/initval.h>
34#include <sound/tlv.h>
35
36#include "wm8900.h"
37
38/* WM8900 register space */
39#define WM8900_REG_RESET 0x0
40#define WM8900_REG_ID 0x0
41#define WM8900_REG_POWER1 0x1
42#define WM8900_REG_POWER2 0x2
43#define WM8900_REG_POWER3 0x3
44#define WM8900_REG_AUDIO1 0x4
45#define WM8900_REG_AUDIO2 0x5
46#define WM8900_REG_CLOCKING1 0x6
47#define WM8900_REG_CLOCKING2 0x7
48#define WM8900_REG_AUDIO3 0x8
49#define WM8900_REG_AUDIO4 0x9
50#define WM8900_REG_DACCTRL 0xa
51#define WM8900_REG_LDAC_DV 0xb
52#define WM8900_REG_RDAC_DV 0xc
53#define WM8900_REG_SIDETONE 0xd
54#define WM8900_REG_ADCCTRL 0xe
55#define WM8900_REG_LADC_DV 0xf
56#define WM8900_REG_RADC_DV 0x10
57#define WM8900_REG_GPIO 0x12
58#define WM8900_REG_INCTL 0x15
59#define WM8900_REG_LINVOL 0x16
60#define WM8900_REG_RINVOL 0x17
61#define WM8900_REG_INBOOSTMIX1 0x18
62#define WM8900_REG_INBOOSTMIX2 0x19
63#define WM8900_REG_ADCPATH 0x1a
64#define WM8900_REG_AUXBOOST 0x1b
65#define WM8900_REG_ADDCTL 0x1e
66#define WM8900_REG_FLLCTL1 0x24
67#define WM8900_REG_FLLCTL2 0x25
68#define WM8900_REG_FLLCTL3 0x26
69#define WM8900_REG_FLLCTL4 0x27
70#define WM8900_REG_FLLCTL5 0x28
71#define WM8900_REG_FLLCTL6 0x29
72#define WM8900_REG_LOUTMIXCTL1 0x2c
73#define WM8900_REG_ROUTMIXCTL1 0x2d
74#define WM8900_REG_BYPASS1 0x2e
75#define WM8900_REG_BYPASS2 0x2f
76#define WM8900_REG_AUXOUT_CTL 0x30
77#define WM8900_REG_LOUT1CTL 0x33
78#define WM8900_REG_ROUT1CTL 0x34
79#define WM8900_REG_LOUT2CTL 0x35
80#define WM8900_REG_ROUT2CTL 0x36
81#define WM8900_REG_HPCTL1 0x3a
82#define WM8900_REG_OUTBIASCTL 0x73
83
84#define WM8900_MAXREG 0x80
85
86#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
87#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
88#define WM8900_REG_ADDCTL_VMID_DIS 0x20
89#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
90#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
91#define WM8900_REG_ADDCTL_TEMP_SD 0x02
92
93#define WM8900_REG_GPIO_TEMP_ENA 0x2
94
95#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
96#define WM8900_REG_POWER1_BIAS_ENA 0x0008
97#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
98#define WM8900_REG_POWER1_FLL_ENA 0x0040
99
100#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
101#define WM8900_REG_POWER2_ADCL_ENA 0x0002
102#define WM8900_REG_POWER2_ADCR_ENA 0x0001
103
104#define WM8900_REG_POWER3_DACL_ENA 0x0002
105#define WM8900_REG_POWER3_DACR_ENA 0x0001
106
107#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
108#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
109#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
110
111#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
112#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
113#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
114#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
115
116#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
117#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
118
119#define WM8900_REG_DACCTRL_MUTE 0x004
21002e20 120#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
0e0e16a8
MB		 121#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
122
123#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
124
125#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
126
127#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
128
129#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
130
131#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
132#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
133#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
134#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
135#define WM8900_REG_HPCTL1_HP_SHORT 0x08
136#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
137
138#define WM8900_LRC_MASK 0xfc00
139
0e0e16a8 140struct wm8900_priv {
f0fba2ad 141 enum snd_soc_control_type control_type;
78e19a39 142
0e0e16a8
MB		 143 u32 fll_in; /* FLL input frequency */
144 u32 fll_out; /* FLL output frequency */
145};
146
147/*
148 * wm8900 register cache. We can't read the entire register space and we
149 * have slow control buses so we cache the registers.
150 */
151static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
152 0x8900, 0x0000,
153 0xc000, 0x0000,
154 0x4050, 0x4000,
155 0x0008, 0x0000,
156 0x0040, 0x0040,
157 0x1004, 0x00c0,
158 0x00c0, 0x0000,
159 0x0100, 0x00c0,
160 0x00c0, 0x0000,
161 0xb001, 0x0000,
162 0x0000, 0x0044,
163 0x004c, 0x004c,
164 0x0044, 0x0044,
165 0x0000, 0x0044,
166 0x0000, 0x0000,
167 0x0002, 0x0000,
168 0x0000, 0x0000,
169 0x0000, 0x0000,
170 0x0008, 0x0000,
171 0x0000, 0x0008,
172 0x0097, 0x0100,
173 0x0000, 0x0000,
174 0x0050, 0x0050,
175 0x0055, 0x0055,
176 0x0055, 0x0000,
177 0x0000, 0x0079,
178 0x0079, 0x0079,
179 0x0079, 0x0000,
180 /* Remaining registers all zero */
181};
182
8d50e447 183static int wm8900_volatile_register(unsigned int reg)
0e0e16a8
MB		 184{
185 switch (reg) {
186 case WM8900_REG_ID:
8d50e447 187 return 1;
0e0e16a8 188 default:
8d50e447 189 return 0;
0e0e16a8
MB		 190 }
191}
192
193static void wm8900_reset(struct snd_soc_codec *codec)
194{
8d50e447 195 snd_soc_write(codec, WM8900_REG_RESET, 0);
0e0e16a8
MB		 196
197 memcpy(codec->reg_cache, wm8900_reg_defaults,
bc258006 198 sizeof(wm8900_reg_defaults));
0e0e16a8
MB		 199}
200
201static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
202 struct snd_kcontrol *kcontrol, int event)
203{
204 struct snd_soc_codec *codec = w->codec;
8d50e447 205 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
0e0e16a8
MB		 206
207 switch (event) {
208 case SND_SOC_DAPM_PRE_PMU:
209 /* Clamp headphone outputs */
210 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
211 WM8900_REG_HPCTL1_HP_CLAMP_OP;
8d50e447 212 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 213 break;
214
215 case SND_SOC_DAPM_POST_PMU:
216 /* Enable the input stage */
217 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
218 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
219 WM8900_REG_HPCTL1_HP_SHORT2 |
220 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 221 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 222
223 msleep(400);
224
225 /* Enable the output stage */
226 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
227 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 228 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 229
230 /* Remove the shorts */
231 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
8d50e447 232 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8 233 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 234 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 235 break;
236
237 case SND_SOC_DAPM_PRE_PMD:
238 /* Short the output */
239 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 240 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 241
242 /* Disable the output stage */
243 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 244 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 245
246 /* Clamp the outputs and power down input */
247 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
248 WM8900_REG_HPCTL1_HP_CLAMP_OP;
249 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 250 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 251 break;
252
253 case SND_SOC_DAPM_POST_PMD:
254 /* Disable everything */
8d50e447 255 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 256 break;
257
258 default:
259 BUG();
260 }
261
262 return 0;
263}
264
265static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
266
267static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
268
269static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
270
271static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
272
273static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
274
275static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
276
277static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
278
279static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
280
281static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
282
283static const struct soc_enum mic_bias_level =
284SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
285
286static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
287
288static const struct soc_enum dac_mute_rate =
289SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
290
291static const char *dac_deemphasis_txt[] = {
292 "Disabled", "32kHz", "44.1kHz", "48kHz"
293};
294
295static const struct soc_enum dac_deemphasis =
296SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
297
298static const char *adc_hpf_cut_txt[] = {
299 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
300};
301
302static const struct soc_enum adc_hpf_cut =
303SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
304
305static const char *lr_txt[] = {
306 "Left", "Right"
307};
308
309static const struct soc_enum aifl_src =
310SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
311
312static const struct soc_enum aifr_src =
313SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
314
315static const struct soc_enum dacl_src =
316SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
317
318static const struct soc_enum dacr_src =
319SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
320
321static const char *sidetone_txt[] = {
322 "Disabled", "Left ADC", "Right ADC"
323};
324
325static const struct soc_enum dacl_sidetone =
326SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
327
328static const struct soc_enum dacr_sidetone =
329SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
330
331static const struct snd_kcontrol_new wm8900_snd_controls[] = {
332SOC_ENUM("Mic Bias Level", mic_bias_level),
333
334SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
335 in_pga_tlv),
336SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
337SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
338
339SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
340 in_pga_tlv),
341SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
342SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
343
344SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
345SOC_ENUM("DAC Mute Rate", dac_mute_rate),
346SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
347SOC_ENUM("DAC Deemphasis", dac_deemphasis),
0e0e16a8
MB		 348SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
349 12, 1, 0),
350
351SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
352SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
353SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
354SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
355 adc_svol_tlv),
356SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
357 adc_svol_tlv),
358SOC_ENUM("Left Digital Audio Source", aifl_src),
359SOC_ENUM("Right Digital Audio Source", aifr_src),
360
361SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
362 dac_boost_tlv),
363SOC_ENUM("Left DAC Source", dacl_src),
364SOC_ENUM("Right DAC Source", dacr_src),
365SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
366SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
367SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
368
369SOC_DOUBLE_R_TLV("Digital Playback Volume",
370 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
371 1, 96, 0, dac_tlv),
372SOC_DOUBLE_R_TLV("Digital Capture Volume",
373 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
374
375SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
376 out_mix_tlv),
377SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
378 out_mix_tlv),
379SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
380 out_mix_tlv),
381SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
382 out_mix_tlv),
383
384SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
385 out_mix_tlv),
386SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
387 out_mix_tlv),
388SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
389 out_mix_tlv),
390SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
391 out_mix_tlv),
392
393SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
394 in_boost_tlv),
395SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
396 in_boost_tlv),
397SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
398 in_boost_tlv),
399SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
400 in_boost_tlv),
401SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
402 in_boost_tlv),
403SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
404 in_boost_tlv),
405
406SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
407 0, 63, 0, out_pga_tlv),
408SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
409 6, 1, 1),
410SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
411 7, 1, 0),
412
413SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
414 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
415 0, 63, 0, out_pga_tlv),
416SOC_DOUBLE_R("LINEOUT2 Switch",
417 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
418SOC_DOUBLE_R("LINEOUT2 ZC Switch",
419 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
420SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
421 0, 1, 1),
422
423};
424
0e0e16a8
MB		 425static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
426SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
427
428static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
429SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
430
431static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
432SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
433SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
434SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
435SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
436SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
437};
438
439static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
440SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
441SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
442SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
443SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
444SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
445};
446
447static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
448SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
449SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
450SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
451SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
452};
453
454static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
455SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
456SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
457SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
458SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
459};
460
461static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
462SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
463SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
464SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
465};
466
467static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
468SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
469SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
470SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
471};
472
473static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
474
475static const struct soc_enum wm8900_lineout2_lp_mux =
476SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
477
478static const struct snd_kcontrol_new wm8900_lineout2_lp =
479SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
480
481static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
482
483/* Externally visible pins */
484SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
485SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
486SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
487SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
488SND_SOC_DAPM_OUTPUT("HP_L"),
489SND_SOC_DAPM_OUTPUT("HP_R"),
490
491SND_SOC_DAPM_INPUT("RINPUT1"),
492SND_SOC_DAPM_INPUT("LINPUT1"),
493SND_SOC_DAPM_INPUT("RINPUT2"),
494SND_SOC_DAPM_INPUT("LINPUT2"),
495SND_SOC_DAPM_INPUT("RINPUT3"),
496SND_SOC_DAPM_INPUT("LINPUT3"),
497SND_SOC_DAPM_INPUT("AUX"),
498
499SND_SOC_DAPM_VMID("VMID"),
500
501/* Input */
502SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
503 wm8900_linpga_controls,
504 ARRAY_SIZE(wm8900_linpga_controls)),
505SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
506 wm8900_rinpga_controls,
507 ARRAY_SIZE(wm8900_rinpga_controls)),
508
509SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
510 wm8900_linmix_controls,
511 ARRAY_SIZE(wm8900_linmix_controls)),
512SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
513 wm8900_rinmix_controls,
514 ARRAY_SIZE(wm8900_rinmix_controls)),
515
516SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
517
518SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
519SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
520
521/* Output */
522SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
523SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
524
525SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
526 wm8900_hp_event,
527 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
528 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
529
530SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
531SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
532
533SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
534SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
535SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
536
537SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
538 wm8900_loutmix_controls,
539 ARRAY_SIZE(wm8900_loutmix_controls)),
540SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
541 wm8900_routmix_controls,
542 ARRAY_SIZE(wm8900_routmix_controls)),
543};
544
545/* Target, Path, Source */
546static const struct snd_soc_dapm_route audio_map[] = {
547/* Inputs */
548{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
549{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
550{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
551
552{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
553{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
554{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
555
556{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
557{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
558{"Left Input Mixer", "AUX Switch", "AUX"},
559{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
560
561{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
562{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
563{"Right Input Mixer", "AUX Switch", "AUX"},
564{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
565
566{"ADCL", NULL, "Left Input Mixer"},
567{"ADCR", NULL, "Right Input Mixer"},
568
569/* Outputs */
570{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
571{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
572{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
573{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
574
575{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
576{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
577{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
578{"LINEOUT2L", NULL, "LINEOUT2 LP"},
579
580{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
581{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
582{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
583{"LINEOUT2R", NULL, "LINEOUT2 LP"},
584
585{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
586{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
587{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
588{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
589{"Left Output Mixer", "DACL Switch", "DACL"},
590
591{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
592{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
593{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
594{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
595{"Right Output Mixer", "DACR Switch", "DACR"},
596
597/* Note that the headphone output stage needs to be connected
598 * externally to LINEOUT2 via DC blocking capacitors. Other
599 * configurations are not supported.
600 *
601 * Note also that left and right headphone paths are treated as a
602 * mono path.
603 */
604{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
605{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
606{"HP_L", NULL, "Headphone Amplifier"},
607{"HP_R", NULL, "Headphone Amplifier"},
608};
609
610static int wm8900_add_widgets(struct snd_soc_codec *codec)
611{
ce6120cc 612 struct snd_soc_dapm_context *dapm = &codec->dapm;
0e0e16a8 613
ce6120cc
LG		 614 snd_soc_dapm_new_controls(dapm, wm8900_dapm_widgets,
615 ARRAY_SIZE(wm8900_dapm_widgets));
616 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
0e0e16a8 617
0e0e16a8
MB		 618 return 0;
619}
620
621static int wm8900_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 622 struct snd_pcm_hw_params *params,
623 struct snd_soc_dai *dai)
0e0e16a8
MB		 624{
625 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 626 struct snd_soc_codec *codec = rtd->codec;
0e0e16a8
MB		 627 u16 reg;
628
8d50e447 629 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
0e0e16a8
MB		 630
631 switch (params_format(params)) {
632 case SNDRV_PCM_FORMAT_S16_LE:
633 break;
634 case SNDRV_PCM_FORMAT_S20_3LE:
635 reg |= 0x20;
636 break;
637 case SNDRV_PCM_FORMAT_S24_LE:
638 reg |= 0x40;
639 break;
640 case SNDRV_PCM_FORMAT_S32_LE:
641 reg |= 0x60;
642 break;
643 default:
644 return -EINVAL;
645 }
646
8d50e447 647 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
0e0e16a8 648
21002e20 649 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
8d50e447 650 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
21002e20
MB		 651
652 if (params_rate(params) <= 24000)
653 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
654 else
655 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
656
8d50e447 657 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
21002e20
MB		 658 }
659
0e0e16a8
MB		 660 return 0;
661}
662
663/* FLL divisors */
664struct _fll_div {
665 u16 fll_ratio;
666 u16 fllclk_div;
667 u16 fll_slow_lock_ref;
668 u16 n;
669 u16 k;
670};
671
672/* The size in bits of the FLL divide multiplied by 10
673 * to allow rounding later */
674#define FIXED_FLL_SIZE ((1 << 16) * 10)
675
676static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
677 unsigned int Fout)
678{
679 u64 Kpart;
680 unsigned int K, Ndiv, Nmod, target;
681 unsigned int div;
682
683 BUG_ON(!Fout);
684
685 /* The FLL must run at 90-100MHz which is then scaled down to
686 * the output value by FLLCLK_DIV. */
687 target = Fout;
688 div = 1;
689 while (target < 90000000) {
690 div *= 2;
691 target *= 2;
692 }
693
694 if (target > 100000000)
449bd54d
RK		 695 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
696 " Fout=%u\n", target, Fref, Fout);
0e0e16a8
MB		 697 if (div > 32) {
698 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
449bd54d 699 "Fref=%u, Fout=%u, target=%u\n",
0e0e16a8
MB		 700 div, Fref, Fout, target);
701 return -EINVAL;
702 }
703
704 fll_div->fllclk_div = div >> 2;
705
706 if (Fref < 48000)
707 fll_div->fll_slow_lock_ref = 1;
708 else
709 fll_div->fll_slow_lock_ref = 0;
710
711 Ndiv = target / Fref;
712
713 if (Fref < 1000000)
714 fll_div->fll_ratio = 8;
715 else
716 fll_div->fll_ratio = 1;
717
718 fll_div->n = Ndiv / fll_div->fll_ratio;
719 Nmod = (target / fll_div->fll_ratio) % Fref;
720
721 /* Calculate fractional part - scale up so we can round. */
722 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
723
724 do_div(Kpart, Fref);
725
726 K = Kpart & 0xFFFFFFFF;
727
728 if ((K % 10) >= 5)
729 K += 5;
730
731 /* Move down to proper range now rounding is done */
732 fll_div->k = K / 10;
733
734 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
735 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
736
737 return 0;
738}
739
740static int wm8900_set_fll(struct snd_soc_codec *codec,
741 int fll_id, unsigned int freq_in, unsigned int freq_out)
742{
b2c812e2 743 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 744 struct _fll_div fll_div;
745 unsigned int reg;
746
747 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
748 return 0;
749
750 /* The digital side should be disabled during any change. */
8d50e447
MB		 751 reg = snd_soc_read(codec, WM8900_REG_POWER1);
752 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 753 reg & (~WM8900_REG_POWER1_FLL_ENA));
754
755 /* Disable the FLL? */
756 if (!freq_in || !freq_out) {
8d50e447
MB		 757 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
758 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 759 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
760
8d50e447
MB		 761 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
762 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 763 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
764
765 wm8900->fll_in = freq_in;
766 wm8900->fll_out = freq_out;
767
768 return 0;
769 }
770
771 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
772 goto reenable;
773
774 wm8900->fll_in = freq_in;
775 wm8900->fll_out = freq_out;
776
777 /* The osclilator *MUST* be enabled before we enable the
778 * digital circuit. */
8d50e447 779 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 780 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
781
8d50e447
MB		 782 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
783 snd_soc_write(codec, WM8900_REG_FLLCTL5,
0e0e16a8
MB		 784 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
785
786 if (fll_div.k) {
8d50e447 787 snd_soc_write(codec, WM8900_REG_FLLCTL2,
0e0e16a8 788 (fll_div.k >> 8) | 0x100);
8d50e447 789 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
0e0e16a8 790 } else
8d50e447 791 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
0e0e16a8
MB		 792
793 if (fll_div.fll_slow_lock_ref)
8d50e447 794 snd_soc_write(codec, WM8900_REG_FLLCTL6,
0e0e16a8
MB		 795 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
796 else
8d50e447 797 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
0e0e16a8 798
8d50e447
MB		 799 reg = snd_soc_read(codec, WM8900_REG_POWER1);
800 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 801 reg | WM8900_REG_POWER1_FLL_ENA);
802
803reenable:
8d50e447
MB		 804 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
805 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 806 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
807
808 return 0;
809}
810
85488037
MB		 811static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
812 int source, unsigned int freq_in, unsigned int freq_out)
0e0e16a8
MB		 813{
814 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
815}
816
817static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
818 int div_id, int div)
819{
820 struct snd_soc_codec *codec = codec_dai->codec;
821 unsigned int reg;
822
823 switch (div_id) {
824 case WM8900_BCLK_DIV:
8d50e447
MB		 825 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
826 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 827 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
828 break;
829 case WM8900_OPCLK_DIV:
8d50e447
MB		 830 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
831 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 832 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
833 break;
834 case WM8900_DAC_LRCLK:
8d50e447
MB		 835 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
836 snd_soc_write(codec, WM8900_REG_AUDIO4,
0e0e16a8
MB		 837 div | (reg & WM8900_LRC_MASK));
838 break;
839 case WM8900_ADC_LRCLK:
8d50e447
MB		 840 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
841 snd_soc_write(codec, WM8900_REG_AUDIO3,
0e0e16a8
MB		 842 div | (reg & WM8900_LRC_MASK));
843 break;
844 case WM8900_DAC_CLKDIV:
8d50e447
MB		 845 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
846 snd_soc_write(codec, WM8900_REG_CLOCKING2,
0e0e16a8
MB		 847 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
848 break;
849 case WM8900_ADC_CLKDIV:
8d50e447
MB		 850 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
851 snd_soc_write(codec, WM8900_REG_CLOCKING2,
0e0e16a8
MB		 852 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
853 break;
854 case WM8900_LRCLK_MODE:
8d50e447
MB		 855 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
856 snd_soc_write(codec, WM8900_REG_DACCTRL,
0e0e16a8
MB		 857 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
858 break;
859 default:
860 return -EINVAL;
861 }
862
863 return 0;
864}
865
866
867static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
868 unsigned int fmt)
869{
870 struct snd_soc_codec *codec = codec_dai->codec;
871 unsigned int clocking1, aif1, aif3, aif4;
872
8d50e447
MB		 873 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
874 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
875 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
876 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
0e0e16a8
MB		 877
878 /* set master/slave audio interface */
879 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
880 case SND_SOC_DAIFMT_CBS_CFS:
881 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
882 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
883 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
884 break;
885 case SND_SOC_DAIFMT_CBS_CFM:
886 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
887 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
888 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
889 break;
890 case SND_SOC_DAIFMT_CBM_CFM:
891 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
892 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
893 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
894 break;
895 case SND_SOC_DAIFMT_CBM_CFS:
896 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
897 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
898 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
899 break;
900 default:
901 return -EINVAL;
902 }
903
904 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
905 case SND_SOC_DAIFMT_DSP_A:
906 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
907 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
908 break;
909 case SND_SOC_DAIFMT_DSP_B:
910 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
911 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
912 break;
913 case SND_SOC_DAIFMT_I2S:
914 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
915 aif1 |= 0x10;
916 break;
917 case SND_SOC_DAIFMT_RIGHT_J:
918 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
919 break;
920 case SND_SOC_DAIFMT_LEFT_J:
921 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
922 aif1 |= 0x8;
923 break;
924 default:
925 return -EINVAL;
926 }
927
928 /* Clock inversion */
929 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
930 case SND_SOC_DAIFMT_DSP_A:
931 case SND_SOC_DAIFMT_DSP_B:
932 /* frame inversion not valid for DSP modes */
933 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
934 case SND_SOC_DAIFMT_NB_NF:
935 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
936 break;
937 case SND_SOC_DAIFMT_IB_NF:
938 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
939 break;
940 default:
941 return -EINVAL;
942 }
943 break;
944 case SND_SOC_DAIFMT_I2S:
945 case SND_SOC_DAIFMT_RIGHT_J:
946 case SND_SOC_DAIFMT_LEFT_J:
947 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
948 case SND_SOC_DAIFMT_NB_NF:
949 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
950 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
951 break;
952 case SND_SOC_DAIFMT_IB_IF:
953 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
954 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
955 break;
956 case SND_SOC_DAIFMT_IB_NF:
957 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
958 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
959 break;
960 case SND_SOC_DAIFMT_NB_IF:
961 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
962 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
963 break;
964 default:
965 return -EINVAL;
966 }
967 break;
968 default:
969 return -EINVAL;
970 }
971
8d50e447
MB		 972 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
973 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
974 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
975 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
0e0e16a8
MB		 976
977 return 0;
978}
979
980static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
981{
982 struct snd_soc_codec *codec = codec_dai->codec;
983 u16 reg;
984
8d50e447 985 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
0e0e16a8
MB		 986
987 if (mute)
988 reg |= WM8900_REG_DACCTRL_MUTE;
989 else
990 reg &= ~WM8900_REG_DACCTRL_MUTE;
991
8d50e447 992 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
0e0e16a8
MB		 993
994 return 0;
995}
996
997#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
998 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
999 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1000
1001#define WM8900_PCM_FORMATS \
1002 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1003 SNDRV_PCM_FORMAT_S24_LE)
1004
6335d055
EM		 1005static struct snd_soc_dai_ops wm8900_dai_ops = {
1006 .hw_params = wm8900_hw_params,
1007 .set_clkdiv = wm8900_set_dai_clkdiv,
1008 .set_pll = wm8900_set_dai_pll,
1009 .set_fmt = wm8900_set_dai_fmt,
1010 .digital_mute = wm8900_digital_mute,
1011};
1012
f0fba2ad
LG		 1013static struct snd_soc_dai_driver wm8900_dai = {
1014 .name = "wm8900-hifi",
0e0e16a8
MB		 1015 .playback = {
1016 .stream_name = "HiFi Playback",
1017 .channels_min = 1,
1018 .channels_max = 2,
1019 .rates = WM8900_RATES,
1020 .formats = WM8900_PCM_FORMATS,
1021 },
1022 .capture = {
1023 .stream_name = "HiFi Capture",
1024 .channels_min = 1,
1025 .channels_max = 2,
1026 .rates = WM8900_RATES,
1027 .formats = WM8900_PCM_FORMATS,
1028 },
6335d055 1029 .ops = &wm8900_dai_ops,
0e0e16a8 1030};
0e0e16a8
MB		 1031
1032static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1033 enum snd_soc_bias_level level)
1034{
1035 u16 reg;
1036
1037 switch (level) {
1038 case SND_SOC_BIAS_ON:
1039 /* Enable thermal shutdown */
8d50e447
MB		 1040 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1041 snd_soc_write(codec, WM8900_REG_GPIO,
0e0e16a8 1042 reg | WM8900_REG_GPIO_TEMP_ENA);
8d50e447
MB		 1043 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1044 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1045 reg | WM8900_REG_ADDCTL_TEMP_SD);
1046 break;
1047
1048 case SND_SOC_BIAS_PREPARE:
1049 break;
1050
1051 case SND_SOC_BIAS_STANDBY:
1052 /* Charge capacitors if initial power up */
ce6120cc 1053 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0e0e16a8 1054 /* STARTUP_BIAS_ENA on */
8d50e447 1055 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1056 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1057
1058 /* Startup bias mode */
8d50e447 1059 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1060 WM8900_REG_ADDCTL_BIAS_SRC |
1061 WM8900_REG_ADDCTL_VMID_SOFTST);
1062
1063 /* VMID 2x50k */
8d50e447 1064 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1065 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1066
1067 /* Allow capacitors to charge */
1068 schedule_timeout_interruptible(msecs_to_jiffies(400));
1069
1070 /* Enable bias */
8d50e447 1071 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1072 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1073 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1074
8d50e447 1075 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
0e0e16a8 1076
8d50e447 1077 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1078 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1079 }
1080
8d50e447
MB		 1081 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1082 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1083 (reg & WM8900_REG_POWER1_FLL_ENA) |
1084 WM8900_REG_POWER1_BIAS_ENA | 0x1);
8d50e447 1085 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8 1086 WM8900_REG_POWER2_SYSCLK_ENA);
8d50e447 1087 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1088 break;
1089
1090 case SND_SOC_BIAS_OFF:
1091 /* Startup bias enable */
8d50e447
MB		 1092 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1093 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8 1094 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
8d50e447 1095 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1096 WM8900_REG_ADDCTL_BIAS_SRC |
1097 WM8900_REG_ADDCTL_VMID_SOFTST);
1098
1099 /* Discharge caps */
8d50e447 1100 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1101 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1102 schedule_timeout_interruptible(msecs_to_jiffies(500));
1103
1104 /* Remove clamp */
8d50e447 1105 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 1106
1107 /* Power down */
8d50e447
MB		 1108 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1109 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1110 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1111 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1112
1113 /* Need to let things settle before stopping the clock
1114 * to ensure that restart works, see "Stopping the
1115 * master clock" in the datasheet. */
1116 schedule_timeout_interruptible(msecs_to_jiffies(1));
8d50e447 1117 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8
MB		 1118 WM8900_REG_POWER2_SYSCLK_ENA);
1119 break;
1120 }
ce6120cc 1121 codec->dapm.bias_level = level;
0e0e16a8
MB		 1122 return 0;
1123}
1124
f0fba2ad 1125static int wm8900_suspend(struct snd_soc_codec *codec, pm_message_t state)
0e0e16a8 1126{
b2c812e2 1127 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 1128 int fll_out = wm8900->fll_out;
1129 int fll_in = wm8900->fll_in;
1130 int ret;
1131
1132 /* Stop the FLL in an orderly fashion */
1133 ret = wm8900_set_fll(codec, 0, 0, 0);
1134 if (ret != 0) {
f0fba2ad 1135 dev_err(codec->dev, "Failed to stop FLL\n");
0e0e16a8
MB		 1136 return ret;
1137 }
1138
1139 wm8900->fll_out = fll_out;
1140 wm8900->fll_in = fll_in;
1141
1142 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1143
1144 return 0;
1145}
1146
f0fba2ad 1147static int wm8900_resume(struct snd_soc_codec *codec)
0e0e16a8 1148{
b2c812e2 1149 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 1150 u16 *cache;
1151 int i, ret;
1152
1153 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1154 GFP_KERNEL);
1155
1156 wm8900_reset(codec);
1157 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1158
1159 /* Restart the FLL? */
1160 if (wm8900->fll_out) {
1161 int fll_out = wm8900->fll_out;
1162 int fll_in = wm8900->fll_in;
1163
1164 wm8900->fll_in = 0;
1165 wm8900->fll_out = 0;
1166
1167 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1168 if (ret != 0) {
f0fba2ad 1169 dev_err(codec->dev, "Failed to restart FLL\n");
0e0e16a8
MB		 1170 return ret;
1171 }
1172 }
1173
1174 if (cache) {
1175 for (i = 0; i < WM8900_MAXREG; i++)
8d50e447 1176 snd_soc_write(codec, i, cache[i]);
0e0e16a8
MB		 1177 kfree(cache);
1178 } else
f0fba2ad 1179 dev_err(codec->dev, "Unable to allocate register cache\n");
0e0e16a8
MB		 1180
1181 return 0;
1182}
1183
f0fba2ad 1184static int wm8900_probe(struct snd_soc_codec *codec)
0e0e16a8 1185{
f0fba2ad
LG		 1186 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1187 int ret = 0, reg;
78e19a39 1188
f0fba2ad 1189 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8900->control_type);
8d50e447 1190 if (ret != 0) {
f0fba2ad
LG		 1191 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1192 return ret;
8d50e447
MB		 1193 }
1194
1195 reg = snd_soc_read(codec, WM8900_REG_ID);
0e0e16a8 1196 if (reg != 0x8900) {
f0fba2ad
LG		 1197 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1198 return -ENODEV;
0e0e16a8
MB		 1199 }
1200
0e0e16a8
MB		 1201 wm8900_reset(codec);
1202
78e19a39
MB		 1203 /* Turn the chip on */
1204 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1205
0e0e16a8 1206 /* Latch the volume update bits */
8d50e447
MB		 1207 snd_soc_write(codec, WM8900_REG_LINVOL,
1208 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1209 snd_soc_write(codec, WM8900_REG_RINVOL,
1210 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1211 snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1212 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1213 snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1214 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1215 snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1216 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1217 snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1218 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1219 snd_soc_write(codec, WM8900_REG_LDAC_DV,
1220 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1221 snd_soc_write(codec, WM8900_REG_RDAC_DV,
1222 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1223 snd_soc_write(codec, WM8900_REG_LADC_DV,
1224 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1225 snd_soc_write(codec, WM8900_REG_RADC_DV,
1226 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
0e0e16a8
MB		 1227
1228 /* Set the DAC and mixer output bias */
8d50e447 1229 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
0e0e16a8 1230
f0fba2ad
LG		 1231 snd_soc_add_controls(codec, wm8900_snd_controls,
1232 ARRAY_SIZE(wm8900_snd_controls));
1233 wm8900_add_widgets(codec);
0e0e16a8 1234
f0fba2ad
LG		 1235 return 0;
1236}
0e0e16a8 1237
f0fba2ad
LG		 1238/* power down chip */
1239static int wm8900_remove(struct snd_soc_codec *codec)
1240{
1241 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1242 return 0;
1243}
0e0e16a8 1244
f0fba2ad
LG		 1245static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1246 .probe = wm8900_probe,
1247 .remove = wm8900_remove,
1248 .suspend = wm8900_suspend,
1249 .resume = wm8900_resume,
1250 .set_bias_level = wm8900_set_bias_level,
1251 .volatile_register = wm8900_volatile_register,
e5eec34c 1252 .reg_cache_size = ARRAY_SIZE(wm8900_reg_defaults),
f0fba2ad
LG		 1253 .reg_word_size = sizeof(u16),
1254 .reg_cache_default = wm8900_reg_defaults,
1255};
0e0e16a8 1256
f0fba2ad
LG		 1257#if defined(CONFIG_SPI_MASTER)
1258static int __devinit wm8900_spi_probe(struct spi_device *spi)
1259{
1260 struct wm8900_priv *wm8900;
1261 int ret;
1262
1263 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1264 if (wm8900 == NULL)
1265 return -ENOMEM;
0e0e16a8 1266
f0fba2ad
LG		 1267 wm8900->control_type = SND_SOC_SPI;
1268 spi_set_drvdata(spi, wm8900);
1269
1270 ret = snd_soc_register_codec(&spi->dev,
1271 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1272 if (ret < 0)
1273 kfree(wm8900);
78e19a39 1274 return ret;
0e0e16a8
MB		 1275}
1276
f0fba2ad 1277static int __devexit wm8900_spi_remove(struct spi_device *spi)
0e0e16a8 1278{
f0fba2ad
LG		 1279 snd_soc_unregister_codec(&spi->dev);
1280 kfree(spi_get_drvdata(spi));
1281 return 0;
1282}
78e19a39 1283
f0fba2ad
LG		 1284static struct spi_driver wm8900_spi_driver = {
1285 .driver = {
1286 .name = "wm8900-codec",
f0fba2ad
LG		 1287 .owner = THIS_MODULE,
1288 },
1289 .probe = wm8900_spi_probe,
1290 .remove = __devexit_p(wm8900_spi_remove),
1291};
1292#endif /* CONFIG_SPI_MASTER */
1293
1294#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1295static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1296 const struct i2c_device_id *id)
1297{
1298 struct wm8900_priv *wm8900;
1299 int ret;
1300
1301 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1302 if (wm8900 == NULL)
1303 return -ENOMEM;
1304
1305 i2c_set_clientdata(i2c, wm8900);
f0fba2ad 1306 wm8900->control_type = SND_SOC_I2C;
78e19a39 1307
f0fba2ad
LG		 1308 ret = snd_soc_register_codec(&i2c->dev,
1309 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1310 if (ret < 0)
1311 kfree(wm8900);
1312 return ret;
1313}
78e19a39 1314
f0fba2ad
LG		 1315static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1316{
1317 snd_soc_unregister_codec(&client->dev);
1318 kfree(i2c_get_clientdata(client));
0e0e16a8
MB		 1319 return 0;
1320}
1321
8ae6a552
JD		 1322static const struct i2c_device_id wm8900_i2c_id[] = {
1323 { "wm8900", 0 },
1324 { }
1325};
1326MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
0e0e16a8 1327
0e0e16a8
MB		 1328static struct i2c_driver wm8900_i2c_driver = {
1329 .driver = {
f0fba2ad 1330 .name = "wm8900-codec",
0e0e16a8
MB		 1331 .owner = THIS_MODULE,
1332 },
f0fba2ad
LG		 1333 .probe = wm8900_i2c_probe,
1334 .remove = __devexit_p(wm8900_i2c_remove),
8ae6a552 1335 .id_table = wm8900_i2c_id,
0e0e16a8 1336};
f0fba2ad 1337#endif
0e0e16a8 1338
f0fba2ad 1339static int __init wm8900_modinit(void)
0e0e16a8 1340{
0e0e16a8 1341 int ret = 0;
f0fba2ad
LG		 1342#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1343 ret = i2c_add_driver(&wm8900_i2c_driver);
1344 if (ret != 0) {
1345 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1346 ret);
f0752331 1347 }
f0fba2ad
LG		 1348#endif
1349#if defined(CONFIG_SPI_MASTER)
1350 ret = spi_register_driver(&wm8900_spi_driver);
1351 if (ret != 0) {
1352 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1353 ret);
78e19a39 1354 }
f0fba2ad 1355#endif
0e0e16a8
MB		 1356 return ret;
1357}
64089b84
MB		 1358module_init(wm8900_modinit);
1359
1360static void __exit wm8900_exit(void)
1361{
f0fba2ad 1362#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
f0752331 1363 i2c_del_driver(&wm8900_i2c_driver);
f0fba2ad
LG		 1364#endif
1365#if defined(CONFIG_SPI_MASTER)
1366 spi_unregister_driver(&wm8900_spi_driver);
1367#endif
64089b84
MB		 1368}
1369module_exit(wm8900_exit);
1370
0e0e16a8
MB		 1371MODULE_DESCRIPTION("ASoC WM8900 driver");
1372MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1373MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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