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ASoC: Automatically manage WM8900 sloping stopband filter
[deliverable/linux.git] / sound / soc / codecs / wm8900.c
CommitLineData
0e0e16a8
MB		 1/*
2 * wm8900.c -- WM8900 ALSA Soc Audio driver
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - Tristating.
14 * - TDM.
15 * - Jack detect.
16 * - FLL source configuration, currently only MCLK is supported.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
0e0e16a8
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/initval.h>
33#include <sound/tlv.h>
34
35#include "wm8900.h"
36
37/* WM8900 register space */
38#define WM8900_REG_RESET 0x0
39#define WM8900_REG_ID 0x0
40#define WM8900_REG_POWER1 0x1
41#define WM8900_REG_POWER2 0x2
42#define WM8900_REG_POWER3 0x3
43#define WM8900_REG_AUDIO1 0x4
44#define WM8900_REG_AUDIO2 0x5
45#define WM8900_REG_CLOCKING1 0x6
46#define WM8900_REG_CLOCKING2 0x7
47#define WM8900_REG_AUDIO3 0x8
48#define WM8900_REG_AUDIO4 0x9
49#define WM8900_REG_DACCTRL 0xa
50#define WM8900_REG_LDAC_DV 0xb
51#define WM8900_REG_RDAC_DV 0xc
52#define WM8900_REG_SIDETONE 0xd
53#define WM8900_REG_ADCCTRL 0xe
54#define WM8900_REG_LADC_DV 0xf
55#define WM8900_REG_RADC_DV 0x10
56#define WM8900_REG_GPIO 0x12
57#define WM8900_REG_INCTL 0x15
58#define WM8900_REG_LINVOL 0x16
59#define WM8900_REG_RINVOL 0x17
60#define WM8900_REG_INBOOSTMIX1 0x18
61#define WM8900_REG_INBOOSTMIX2 0x19
62#define WM8900_REG_ADCPATH 0x1a
63#define WM8900_REG_AUXBOOST 0x1b
64#define WM8900_REG_ADDCTL 0x1e
65#define WM8900_REG_FLLCTL1 0x24
66#define WM8900_REG_FLLCTL2 0x25
67#define WM8900_REG_FLLCTL3 0x26
68#define WM8900_REG_FLLCTL4 0x27
69#define WM8900_REG_FLLCTL5 0x28
70#define WM8900_REG_FLLCTL6 0x29
71#define WM8900_REG_LOUTMIXCTL1 0x2c
72#define WM8900_REG_ROUTMIXCTL1 0x2d
73#define WM8900_REG_BYPASS1 0x2e
74#define WM8900_REG_BYPASS2 0x2f
75#define WM8900_REG_AUXOUT_CTL 0x30
76#define WM8900_REG_LOUT1CTL 0x33
77#define WM8900_REG_ROUT1CTL 0x34
78#define WM8900_REG_LOUT2CTL 0x35
79#define WM8900_REG_ROUT2CTL 0x36
80#define WM8900_REG_HPCTL1 0x3a
81#define WM8900_REG_OUTBIASCTL 0x73
82
83#define WM8900_MAXREG 0x80
84
85#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
86#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
87#define WM8900_REG_ADDCTL_VMID_DIS 0x20
88#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
89#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
90#define WM8900_REG_ADDCTL_TEMP_SD 0x02
91
92#define WM8900_REG_GPIO_TEMP_ENA 0x2
93
94#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
95#define WM8900_REG_POWER1_BIAS_ENA 0x0008
96#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
97#define WM8900_REG_POWER1_FLL_ENA 0x0040
98
99#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
100#define WM8900_REG_POWER2_ADCL_ENA 0x0002
101#define WM8900_REG_POWER2_ADCR_ENA 0x0001
102
103#define WM8900_REG_POWER3_DACL_ENA 0x0002
104#define WM8900_REG_POWER3_DACR_ENA 0x0001
105
106#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
107#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
108#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
109
110#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
111#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
112#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
113#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
114
115#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
116#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
117
118#define WM8900_REG_DACCTRL_MUTE 0x004
21002e20 119#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
0e0e16a8
MB		 120#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
121
122#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
123
124#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
125
126#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
127
128#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
129
130#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
131#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
132#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
133#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
134#define WM8900_REG_HPCTL1_HP_SHORT 0x08
135#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
136
137#define WM8900_LRC_MASK 0xfc00
138
139struct snd_soc_codec_device soc_codec_dev_wm8900;
140
141struct wm8900_priv {
78e19a39
MB		 142 struct snd_soc_codec codec;
143
144 u16 reg_cache[WM8900_MAXREG];
145
0e0e16a8
MB		 146 u32 fll_in; /* FLL input frequency */
147 u32 fll_out; /* FLL output frequency */
148};
149
150/*
151 * wm8900 register cache. We can't read the entire register space and we
152 * have slow control buses so we cache the registers.
153 */
154static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
155 0x8900, 0x0000,
156 0xc000, 0x0000,
157 0x4050, 0x4000,
158 0x0008, 0x0000,
159 0x0040, 0x0040,
160 0x1004, 0x00c0,
161 0x00c0, 0x0000,
162 0x0100, 0x00c0,
163 0x00c0, 0x0000,
164 0xb001, 0x0000,
165 0x0000, 0x0044,
166 0x004c, 0x004c,
167 0x0044, 0x0044,
168 0x0000, 0x0044,
169 0x0000, 0x0000,
170 0x0002, 0x0000,
171 0x0000, 0x0000,
172 0x0000, 0x0000,
173 0x0008, 0x0000,
174 0x0000, 0x0008,
175 0x0097, 0x0100,
176 0x0000, 0x0000,
177 0x0050, 0x0050,
178 0x0055, 0x0055,
179 0x0055, 0x0000,
180 0x0000, 0x0079,
181 0x0079, 0x0079,
182 0x0079, 0x0000,
183 /* Remaining registers all zero */
184};
185
186/*
187 * read wm8900 register cache
188 */
189static inline unsigned int wm8900_read_reg_cache(struct snd_soc_codec *codec,
190 unsigned int reg)
191{
192 u16 *cache = codec->reg_cache;
193
194 BUG_ON(reg >= WM8900_MAXREG);
195
196 if (reg == WM8900_REG_ID)
197 return 0;
198
199 return cache[reg];
200}
201
202/*
203 * write wm8900 register cache
204 */
205static inline void wm8900_write_reg_cache(struct snd_soc_codec *codec,
206 u16 reg, unsigned int value)
207{
208 u16 *cache = codec->reg_cache;
209
210 BUG_ON(reg >= WM8900_MAXREG);
211
212 cache[reg] = value;
213}
214
215/*
216 * write to the WM8900 register space
217 */
218static int wm8900_write(struct snd_soc_codec *codec, unsigned int reg,
219 unsigned int value)
220{
221 u8 data[3];
222
223 if (value == wm8900_read_reg_cache(codec, reg))
224 return 0;
225
226 /* data is
227 * D15..D9 WM8900 register offset
228 * D8...D0 register data
229 */
230 data[0] = reg;
231 data[1] = value >> 8;
232 data[2] = value & 0x00ff;
233
234 wm8900_write_reg_cache(codec, reg, value);
235 if (codec->hw_write(codec->control_data, data, 3) == 3)
236 return 0;
237 else
238 return -EIO;
239}
240
241/*
242 * Read from the wm8900.
243 */
244static unsigned int wm8900_chip_read(struct snd_soc_codec *codec, u8 reg)
245{
246 struct i2c_msg xfer[2];
247 u16 data;
248 int ret;
249 struct i2c_client *client = codec->control_data;
250
251 BUG_ON(reg != WM8900_REG_ID && reg != WM8900_REG_POWER1);
252
253 /* Write register */
254 xfer[0].addr = client->addr;
255 xfer[0].flags = 0;
256 xfer[0].len = 1;
257 xfer[0].buf = &reg;
258
259 /* Read data */
260 xfer[1].addr = client->addr;
261 xfer[1].flags = I2C_M_RD;
262 xfer[1].len = 2;
263 xfer[1].buf = (u8 *)&data;
264
265 ret = i2c_transfer(client->adapter, xfer, 2);
266 if (ret != 2) {
267 printk(KERN_CRIT "i2c_transfer returned %d\n", ret);
268 return 0;
269 }
270
271 return (data >> 8) | ((data & 0xff) << 8);
272}
273
274/*
275 * Read from the WM8900 register space. Most registers can't be read
276 * and are therefore supplied from cache.
277 */
278static unsigned int wm8900_read(struct snd_soc_codec *codec, unsigned int reg)
279{
280 switch (reg) {
281 case WM8900_REG_ID:
282 return wm8900_chip_read(codec, reg);
283 default:
284 return wm8900_read_reg_cache(codec, reg);
285 }
286}
287
288static void wm8900_reset(struct snd_soc_codec *codec)
289{
290 wm8900_write(codec, WM8900_REG_RESET, 0);
291
292 memcpy(codec->reg_cache, wm8900_reg_defaults,
293 sizeof(codec->reg_cache));
294}
295
296static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
297 struct snd_kcontrol *kcontrol, int event)
298{
299 struct snd_soc_codec *codec = w->codec;
300 u16 hpctl1 = wm8900_read(codec, WM8900_REG_HPCTL1);
301
302 switch (event) {
303 case SND_SOC_DAPM_PRE_PMU:
304 /* Clamp headphone outputs */
305 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
306 WM8900_REG_HPCTL1_HP_CLAMP_OP;
307 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
308 break;
309
310 case SND_SOC_DAPM_POST_PMU:
311 /* Enable the input stage */
312 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
313 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
314 WM8900_REG_HPCTL1_HP_SHORT2 |
315 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
316 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
317
318 msleep(400);
319
320 /* Enable the output stage */
321 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
322 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
323 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
324
325 /* Remove the shorts */
326 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
327 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
328 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
329 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
330 break;
331
332 case SND_SOC_DAPM_PRE_PMD:
333 /* Short the output */
334 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
335 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
336
337 /* Disable the output stage */
338 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
339 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
340
341 /* Clamp the outputs and power down input */
342 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
343 WM8900_REG_HPCTL1_HP_CLAMP_OP;
344 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
345 wm8900_write(codec, WM8900_REG_HPCTL1, hpctl1);
346 break;
347
348 case SND_SOC_DAPM_POST_PMD:
349 /* Disable everything */
350 wm8900_write(codec, WM8900_REG_HPCTL1, 0);
351 break;
352
353 default:
354 BUG();
355 }
356
357 return 0;
358}
359
360static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
361
362static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
363
364static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
365
366static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
367
368static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
369
370static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
371
372static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
373
374static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
375
376static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
377
378static const struct soc_enum mic_bias_level =
379SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
380
381static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
382
383static const struct soc_enum dac_mute_rate =
384SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
385
386static const char *dac_deemphasis_txt[] = {
387 "Disabled", "32kHz", "44.1kHz", "48kHz"
388};
389
390static const struct soc_enum dac_deemphasis =
391SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
392
393static const char *adc_hpf_cut_txt[] = {
394 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
395};
396
397static const struct soc_enum adc_hpf_cut =
398SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
399
400static const char *lr_txt[] = {
401 "Left", "Right"
402};
403
404static const struct soc_enum aifl_src =
405SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
406
407static const struct soc_enum aifr_src =
408SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
409
410static const struct soc_enum dacl_src =
411SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
412
413static const struct soc_enum dacr_src =
414SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
415
416static const char *sidetone_txt[] = {
417 "Disabled", "Left ADC", "Right ADC"
418};
419
420static const struct soc_enum dacl_sidetone =
421SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
422
423static const struct soc_enum dacr_sidetone =
424SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
425
426static const struct snd_kcontrol_new wm8900_snd_controls[] = {
427SOC_ENUM("Mic Bias Level", mic_bias_level),
428
429SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
430 in_pga_tlv),
431SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
432SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
433
434SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
435 in_pga_tlv),
436SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
437SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
438
439SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
440SOC_ENUM("DAC Mute Rate", dac_mute_rate),
441SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
442SOC_ENUM("DAC Deemphasis", dac_deemphasis),
0e0e16a8
MB		 443SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
444 12, 1, 0),
445
446SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
447SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
448SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
449SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
450 adc_svol_tlv),
451SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
452 adc_svol_tlv),
453SOC_ENUM("Left Digital Audio Source", aifl_src),
454SOC_ENUM("Right Digital Audio Source", aifr_src),
455
456SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
457 dac_boost_tlv),
458SOC_ENUM("Left DAC Source", dacl_src),
459SOC_ENUM("Right DAC Source", dacr_src),
460SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
461SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
462SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
463
464SOC_DOUBLE_R_TLV("Digital Playback Volume",
465 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
466 1, 96, 0, dac_tlv),
467SOC_DOUBLE_R_TLV("Digital Capture Volume",
468 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
469
470SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
471 out_mix_tlv),
472SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
473 out_mix_tlv),
474SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
475 out_mix_tlv),
476SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
477 out_mix_tlv),
478
479SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
480 out_mix_tlv),
481SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
482 out_mix_tlv),
483SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
484 out_mix_tlv),
485SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
486 out_mix_tlv),
487
488SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
489 in_boost_tlv),
490SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
491 in_boost_tlv),
492SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
493 in_boost_tlv),
494SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
495 in_boost_tlv),
496SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
497 in_boost_tlv),
498SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
499 in_boost_tlv),
500
501SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
502 0, 63, 0, out_pga_tlv),
503SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
504 6, 1, 1),
505SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
506 7, 1, 0),
507
508SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
509 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
510 0, 63, 0, out_pga_tlv),
511SOC_DOUBLE_R("LINEOUT2 Switch",
512 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
513SOC_DOUBLE_R("LINEOUT2 ZC Switch",
514 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
515SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
516 0, 1, 1),
517
518};
519
0e0e16a8
MB		 520static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
521SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
522
523static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
524SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
525
526static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
527SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
528SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
529SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
530SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
531SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
532};
533
534static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
535SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
536SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
537SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
538SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
539SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
540};
541
542static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
543SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
544SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
545SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
546SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
547};
548
549static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
550SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
551SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
552SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
553SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
554};
555
556static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
557SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
558SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
559SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
560};
561
562static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
563SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
564SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
565SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
566};
567
568static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
569
570static const struct soc_enum wm8900_lineout2_lp_mux =
571SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
572
573static const struct snd_kcontrol_new wm8900_lineout2_lp =
574SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
575
576static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
577
578/* Externally visible pins */
579SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
580SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
581SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
582SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
583SND_SOC_DAPM_OUTPUT("HP_L"),
584SND_SOC_DAPM_OUTPUT("HP_R"),
585
586SND_SOC_DAPM_INPUT("RINPUT1"),
587SND_SOC_DAPM_INPUT("LINPUT1"),
588SND_SOC_DAPM_INPUT("RINPUT2"),
589SND_SOC_DAPM_INPUT("LINPUT2"),
590SND_SOC_DAPM_INPUT("RINPUT3"),
591SND_SOC_DAPM_INPUT("LINPUT3"),
592SND_SOC_DAPM_INPUT("AUX"),
593
594SND_SOC_DAPM_VMID("VMID"),
595
596/* Input */
597SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
598 wm8900_linpga_controls,
599 ARRAY_SIZE(wm8900_linpga_controls)),
600SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
601 wm8900_rinpga_controls,
602 ARRAY_SIZE(wm8900_rinpga_controls)),
603
604SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
605 wm8900_linmix_controls,
606 ARRAY_SIZE(wm8900_linmix_controls)),
607SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
608 wm8900_rinmix_controls,
609 ARRAY_SIZE(wm8900_rinmix_controls)),
610
611SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
612
613SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
614SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
615
616/* Output */
617SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
618SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
619
620SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
621 wm8900_hp_event,
622 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
623 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
624
625SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
626SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
627
628SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
629SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
630SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
631
632SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
633 wm8900_loutmix_controls,
634 ARRAY_SIZE(wm8900_loutmix_controls)),
635SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
636 wm8900_routmix_controls,
637 ARRAY_SIZE(wm8900_routmix_controls)),
638};
639
640/* Target, Path, Source */
641static const struct snd_soc_dapm_route audio_map[] = {
642/* Inputs */
643{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
644{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
645{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
646
647{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
648{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
649{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
650
651{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
652{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
653{"Left Input Mixer", "AUX Switch", "AUX"},
654{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
655
656{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
657{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
658{"Right Input Mixer", "AUX Switch", "AUX"},
659{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
660
661{"ADCL", NULL, "Left Input Mixer"},
662{"ADCR", NULL, "Right Input Mixer"},
663
664/* Outputs */
665{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
666{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
667{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
668{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
669
670{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
671{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
672{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
673{"LINEOUT2L", NULL, "LINEOUT2 LP"},
674
675{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
676{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
677{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
678{"LINEOUT2R", NULL, "LINEOUT2 LP"},
679
680{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
681{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
682{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
683{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
684{"Left Output Mixer", "DACL Switch", "DACL"},
685
686{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
687{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
688{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
689{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
690{"Right Output Mixer", "DACR Switch", "DACR"},
691
692/* Note that the headphone output stage needs to be connected
693 * externally to LINEOUT2 via DC blocking capacitors. Other
694 * configurations are not supported.
695 *
696 * Note also that left and right headphone paths are treated as a
697 * mono path.
698 */
699{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
700{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
701{"HP_L", NULL, "Headphone Amplifier"},
702{"HP_R", NULL, "Headphone Amplifier"},
703};
704
705static int wm8900_add_widgets(struct snd_soc_codec *codec)
706{
707 snd_soc_dapm_new_controls(codec, wm8900_dapm_widgets,
708 ARRAY_SIZE(wm8900_dapm_widgets));
709
710 snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
711
712 snd_soc_dapm_new_widgets(codec);
713
714 return 0;
715}
716
717static int wm8900_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 718 struct snd_pcm_hw_params *params,
719 struct snd_soc_dai *dai)
0e0e16a8
MB		 720{
721 struct snd_soc_pcm_runtime *rtd = substream->private_data;
722 struct snd_soc_device *socdev = rtd->socdev;
6627a653 723 struct snd_soc_codec *codec = socdev->card->codec;
0e0e16a8
MB		 724 u16 reg;
725
726 reg = wm8900_read(codec, WM8900_REG_AUDIO1) & ~0x60;
727
728 switch (params_format(params)) {
729 case SNDRV_PCM_FORMAT_S16_LE:
730 break;
731 case SNDRV_PCM_FORMAT_S20_3LE:
732 reg |= 0x20;
733 break;
734 case SNDRV_PCM_FORMAT_S24_LE:
735 reg |= 0x40;
736 break;
737 case SNDRV_PCM_FORMAT_S32_LE:
738 reg |= 0x60;
739 break;
740 default:
741 return -EINVAL;
742 }
743
744 wm8900_write(codec, WM8900_REG_AUDIO1, reg);
745
21002e20
MB		 746 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
747 reg = wm8900_read(codec, WM8900_REG_DACCTRL);
748
749 if (params_rate(params) <= 24000)
750 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
751 else
752 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
753
754 wm8900_write(codec, WM8900_REG_DACCTRL, reg);
755 }
756
0e0e16a8
MB		 757 return 0;
758}
759
760/* FLL divisors */
761struct _fll_div {
762 u16 fll_ratio;
763 u16 fllclk_div;
764 u16 fll_slow_lock_ref;
765 u16 n;
766 u16 k;
767};
768
769/* The size in bits of the FLL divide multiplied by 10
770 * to allow rounding later */
771#define FIXED_FLL_SIZE ((1 << 16) * 10)
772
773static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
774 unsigned int Fout)
775{
776 u64 Kpart;
777 unsigned int K, Ndiv, Nmod, target;
778 unsigned int div;
779
780 BUG_ON(!Fout);
781
782 /* The FLL must run at 90-100MHz which is then scaled down to
783 * the output value by FLLCLK_DIV. */
784 target = Fout;
785 div = 1;
786 while (target < 90000000) {
787 div *= 2;
788 target *= 2;
789 }
790
791 if (target > 100000000)
449bd54d
RK		 792 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
793 " Fout=%u\n", target, Fref, Fout);
0e0e16a8
MB		 794 if (div > 32) {
795 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
449bd54d 796 "Fref=%u, Fout=%u, target=%u\n",
0e0e16a8
MB		 797 div, Fref, Fout, target);
798 return -EINVAL;
799 }
800
801 fll_div->fllclk_div = div >> 2;
802
803 if (Fref < 48000)
804 fll_div->fll_slow_lock_ref = 1;
805 else
806 fll_div->fll_slow_lock_ref = 0;
807
808 Ndiv = target / Fref;
809
810 if (Fref < 1000000)
811 fll_div->fll_ratio = 8;
812 else
813 fll_div->fll_ratio = 1;
814
815 fll_div->n = Ndiv / fll_div->fll_ratio;
816 Nmod = (target / fll_div->fll_ratio) % Fref;
817
818 /* Calculate fractional part - scale up so we can round. */
819 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
820
821 do_div(Kpart, Fref);
822
823 K = Kpart & 0xFFFFFFFF;
824
825 if ((K % 10) >= 5)
826 K += 5;
827
828 /* Move down to proper range now rounding is done */
829 fll_div->k = K / 10;
830
831 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
832 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
833
834 return 0;
835}
836
837static int wm8900_set_fll(struct snd_soc_codec *codec,
838 int fll_id, unsigned int freq_in, unsigned int freq_out)
839{
840 struct wm8900_priv *wm8900 = codec->private_data;
841 struct _fll_div fll_div;
842 unsigned int reg;
843
844 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
845 return 0;
846
847 /* The digital side should be disabled during any change. */
848 reg = wm8900_read(codec, WM8900_REG_POWER1);
849 wm8900_write(codec, WM8900_REG_POWER1,
850 reg & (~WM8900_REG_POWER1_FLL_ENA));
851
852 /* Disable the FLL? */
853 if (!freq_in || !freq_out) {
854 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
855 wm8900_write(codec, WM8900_REG_CLOCKING1,
856 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
857
858 reg = wm8900_read(codec, WM8900_REG_FLLCTL1);
859 wm8900_write(codec, WM8900_REG_FLLCTL1,
860 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
861
862 wm8900->fll_in = freq_in;
863 wm8900->fll_out = freq_out;
864
865 return 0;
866 }
867
868 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
869 goto reenable;
870
871 wm8900->fll_in = freq_in;
872 wm8900->fll_out = freq_out;
873
874 /* The osclilator *MUST* be enabled before we enable the
875 * digital circuit. */
876 wm8900_write(codec, WM8900_REG_FLLCTL1,
877 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
878
879 wm8900_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
880 wm8900_write(codec, WM8900_REG_FLLCTL5,
881 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
882
883 if (fll_div.k) {
884 wm8900_write(codec, WM8900_REG_FLLCTL2,
885 (fll_div.k >> 8) | 0x100);
886 wm8900_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
887 } else
888 wm8900_write(codec, WM8900_REG_FLLCTL2, 0);
889
890 if (fll_div.fll_slow_lock_ref)
891 wm8900_write(codec, WM8900_REG_FLLCTL6,
892 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
893 else
894 wm8900_write(codec, WM8900_REG_FLLCTL6, 0);
895
896 reg = wm8900_read(codec, WM8900_REG_POWER1);
897 wm8900_write(codec, WM8900_REG_POWER1,
898 reg | WM8900_REG_POWER1_FLL_ENA);
899
900reenable:
901 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
902 wm8900_write(codec, WM8900_REG_CLOCKING1,
903 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
904
905 return 0;
906}
907
908static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai,
909 int pll_id, unsigned int freq_in, unsigned int freq_out)
910{
911 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
912}
913
914static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
915 int div_id, int div)
916{
917 struct snd_soc_codec *codec = codec_dai->codec;
918 unsigned int reg;
919
920 switch (div_id) {
921 case WM8900_BCLK_DIV:
922 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
923 wm8900_write(codec, WM8900_REG_CLOCKING1,
924 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
925 break;
926 case WM8900_OPCLK_DIV:
927 reg = wm8900_read(codec, WM8900_REG_CLOCKING1);
928 wm8900_write(codec, WM8900_REG_CLOCKING1,
929 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
930 break;
931 case WM8900_DAC_LRCLK:
932 reg = wm8900_read(codec, WM8900_REG_AUDIO4);
933 wm8900_write(codec, WM8900_REG_AUDIO4,
934 div | (reg & WM8900_LRC_MASK));
935 break;
936 case WM8900_ADC_LRCLK:
937 reg = wm8900_read(codec, WM8900_REG_AUDIO3);
938 wm8900_write(codec, WM8900_REG_AUDIO3,
939 div | (reg & WM8900_LRC_MASK));
940 break;
941 case WM8900_DAC_CLKDIV:
942 reg = wm8900_read(codec, WM8900_REG_CLOCKING2);
943 wm8900_write(codec, WM8900_REG_CLOCKING2,
944 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
945 break;
946 case WM8900_ADC_CLKDIV:
947 reg = wm8900_read(codec, WM8900_REG_CLOCKING2);
948 wm8900_write(codec, WM8900_REG_CLOCKING2,
949 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
950 break;
951 case WM8900_LRCLK_MODE:
952 reg = wm8900_read(codec, WM8900_REG_DACCTRL);
953 wm8900_write(codec, WM8900_REG_DACCTRL,
954 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
955 break;
956 default:
957 return -EINVAL;
958 }
959
960 return 0;
961}
962
963
964static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
965 unsigned int fmt)
966{
967 struct snd_soc_codec *codec = codec_dai->codec;
968 unsigned int clocking1, aif1, aif3, aif4;
969
970 clocking1 = wm8900_read(codec, WM8900_REG_CLOCKING1);
971 aif1 = wm8900_read(codec, WM8900_REG_AUDIO1);
972 aif3 = wm8900_read(codec, WM8900_REG_AUDIO3);
973 aif4 = wm8900_read(codec, WM8900_REG_AUDIO4);
974
975 /* set master/slave audio interface */
976 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
977 case SND_SOC_DAIFMT_CBS_CFS:
978 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
979 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
980 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
981 break;
982 case SND_SOC_DAIFMT_CBS_CFM:
983 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
984 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
985 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
986 break;
987 case SND_SOC_DAIFMT_CBM_CFM:
988 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
989 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
990 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
991 break;
992 case SND_SOC_DAIFMT_CBM_CFS:
993 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
994 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
995 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
996 break;
997 default:
998 return -EINVAL;
999 }
1000
1001 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1002 case SND_SOC_DAIFMT_DSP_A:
1003 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
1004 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1005 break;
1006 case SND_SOC_DAIFMT_DSP_B:
1007 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
1008 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1009 break;
1010 case SND_SOC_DAIFMT_I2S:
1011 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
1012 aif1 |= 0x10;
1013 break;
1014 case SND_SOC_DAIFMT_RIGHT_J:
1015 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
1016 break;
1017 case SND_SOC_DAIFMT_LEFT_J:
1018 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
1019 aif1 |= 0x8;
1020 break;
1021 default:
1022 return -EINVAL;
1023 }
1024
1025 /* Clock inversion */
1026 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1027 case SND_SOC_DAIFMT_DSP_A:
1028 case SND_SOC_DAIFMT_DSP_B:
1029 /* frame inversion not valid for DSP modes */
1030 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1031 case SND_SOC_DAIFMT_NB_NF:
1032 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1033 break;
1034 case SND_SOC_DAIFMT_IB_NF:
1035 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1036 break;
1037 default:
1038 return -EINVAL;
1039 }
1040 break;
1041 case SND_SOC_DAIFMT_I2S:
1042 case SND_SOC_DAIFMT_RIGHT_J:
1043 case SND_SOC_DAIFMT_LEFT_J:
1044 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1045 case SND_SOC_DAIFMT_NB_NF:
1046 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1047 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1048 break;
1049 case SND_SOC_DAIFMT_IB_IF:
1050 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1051 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1052 break;
1053 case SND_SOC_DAIFMT_IB_NF:
1054 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
1055 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
1056 break;
1057 case SND_SOC_DAIFMT_NB_IF:
1058 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
1059 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
1060 break;
1061 default:
1062 return -EINVAL;
1063 }
1064 break;
1065 default:
1066 return -EINVAL;
1067 }
1068
1069 wm8900_write(codec, WM8900_REG_CLOCKING1, clocking1);
1070 wm8900_write(codec, WM8900_REG_AUDIO1, aif1);
1071 wm8900_write(codec, WM8900_REG_AUDIO3, aif3);
1072 wm8900_write(codec, WM8900_REG_AUDIO4, aif4);
1073
1074 return 0;
1075}
1076
1077static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1078{
1079 struct snd_soc_codec *codec = codec_dai->codec;
1080 u16 reg;
1081
1082 reg = wm8900_read(codec, WM8900_REG_DACCTRL);
1083
1084 if (mute)
1085 reg |= WM8900_REG_DACCTRL_MUTE;
1086 else
1087 reg &= ~WM8900_REG_DACCTRL_MUTE;
1088
1089 wm8900_write(codec, WM8900_REG_DACCTRL, reg);
1090
1091 return 0;
1092}
1093
1094#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1095 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1096 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1097
1098#define WM8900_PCM_FORMATS \
1099 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1100 SNDRV_PCM_FORMAT_S24_LE)
1101
6335d055
EM		 1102static struct snd_soc_dai_ops wm8900_dai_ops = {
1103 .hw_params = wm8900_hw_params,
1104 .set_clkdiv = wm8900_set_dai_clkdiv,
1105 .set_pll = wm8900_set_dai_pll,
1106 .set_fmt = wm8900_set_dai_fmt,
1107 .digital_mute = wm8900_digital_mute,
1108};
1109
0e0e16a8
MB		 1110struct snd_soc_dai wm8900_dai = {
1111 .name = "WM8900 HiFi",
1112 .playback = {
1113 .stream_name = "HiFi Playback",
1114 .channels_min = 1,
1115 .channels_max = 2,
1116 .rates = WM8900_RATES,
1117 .formats = WM8900_PCM_FORMATS,
1118 },
1119 .capture = {
1120 .stream_name = "HiFi Capture",
1121 .channels_min = 1,
1122 .channels_max = 2,
1123 .rates = WM8900_RATES,
1124 .formats = WM8900_PCM_FORMATS,
1125 },
6335d055 1126 .ops = &wm8900_dai_ops,
0e0e16a8
MB		 1127};
1128EXPORT_SYMBOL_GPL(wm8900_dai);
1129
1130static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1131 enum snd_soc_bias_level level)
1132{
1133 u16 reg;
1134
1135 switch (level) {
1136 case SND_SOC_BIAS_ON:
1137 /* Enable thermal shutdown */
1138 reg = wm8900_read(codec, WM8900_REG_GPIO);
1139 wm8900_write(codec, WM8900_REG_GPIO,
1140 reg | WM8900_REG_GPIO_TEMP_ENA);
1141 reg = wm8900_read(codec, WM8900_REG_ADDCTL);
1142 wm8900_write(codec, WM8900_REG_ADDCTL,
1143 reg | WM8900_REG_ADDCTL_TEMP_SD);
1144 break;
1145
1146 case SND_SOC_BIAS_PREPARE:
1147 break;
1148
1149 case SND_SOC_BIAS_STANDBY:
1150 /* Charge capacitors if initial power up */
1151 if (codec->bias_level == SND_SOC_BIAS_OFF) {
1152 /* STARTUP_BIAS_ENA on */
1153 wm8900_write(codec, WM8900_REG_POWER1,
1154 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1155
1156 /* Startup bias mode */
1157 wm8900_write(codec, WM8900_REG_ADDCTL,
1158 WM8900_REG_ADDCTL_BIAS_SRC |
1159 WM8900_REG_ADDCTL_VMID_SOFTST);
1160
1161 /* VMID 2x50k */
1162 wm8900_write(codec, WM8900_REG_POWER1,
1163 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1164
1165 /* Allow capacitors to charge */
1166 schedule_timeout_interruptible(msecs_to_jiffies(400));
1167
1168 /* Enable bias */
1169 wm8900_write(codec, WM8900_REG_POWER1,
1170 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1171 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1172
1173 wm8900_write(codec, WM8900_REG_ADDCTL, 0);
1174
1175 wm8900_write(codec, WM8900_REG_POWER1,
1176 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1177 }
1178
1179 reg = wm8900_read(codec, WM8900_REG_POWER1);
1180 wm8900_write(codec, WM8900_REG_POWER1,
1181 (reg & WM8900_REG_POWER1_FLL_ENA) |
1182 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1183 wm8900_write(codec, WM8900_REG_POWER2,
1184 WM8900_REG_POWER2_SYSCLK_ENA);
1185 wm8900_write(codec, WM8900_REG_POWER3, 0);
1186 break;
1187
1188 case SND_SOC_BIAS_OFF:
1189 /* Startup bias enable */
1190 reg = wm8900_read(codec, WM8900_REG_POWER1);
1191 wm8900_write(codec, WM8900_REG_POWER1,
1192 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1193 wm8900_write(codec, WM8900_REG_ADDCTL,
1194 WM8900_REG_ADDCTL_BIAS_SRC |
1195 WM8900_REG_ADDCTL_VMID_SOFTST);
1196
1197 /* Discharge caps */
1198 wm8900_write(codec, WM8900_REG_POWER1,
1199 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1200 schedule_timeout_interruptible(msecs_to_jiffies(500));
1201
1202 /* Remove clamp */
1203 wm8900_write(codec, WM8900_REG_HPCTL1, 0);
1204
1205 /* Power down */
1206 wm8900_write(codec, WM8900_REG_ADDCTL, 0);
1207 wm8900_write(codec, WM8900_REG_POWER1, 0);
1208 wm8900_write(codec, WM8900_REG_POWER2, 0);
1209 wm8900_write(codec, WM8900_REG_POWER3, 0);
1210
1211 /* Need to let things settle before stopping the clock
1212 * to ensure that restart works, see "Stopping the
1213 * master clock" in the datasheet. */
1214 schedule_timeout_interruptible(msecs_to_jiffies(1));
1215 wm8900_write(codec, WM8900_REG_POWER2,
1216 WM8900_REG_POWER2_SYSCLK_ENA);
1217 break;
1218 }
1219 codec->bias_level = level;
1220 return 0;
1221}
1222
1223static int wm8900_suspend(struct platform_device *pdev, pm_message_t state)
1224{
1225 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1226 struct snd_soc_codec *codec = socdev->card->codec;
0e0e16a8
MB		 1227 struct wm8900_priv *wm8900 = codec->private_data;
1228 int fll_out = wm8900->fll_out;
1229 int fll_in = wm8900->fll_in;
1230 int ret;
1231
1232 /* Stop the FLL in an orderly fashion */
1233 ret = wm8900_set_fll(codec, 0, 0, 0);
1234 if (ret != 0) {
1235 dev_err(&pdev->dev, "Failed to stop FLL\n");
1236 return ret;
1237 }
1238
1239 wm8900->fll_out = fll_out;
1240 wm8900->fll_in = fll_in;
1241
1242 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1243
1244 return 0;
1245}
1246
1247static int wm8900_resume(struct platform_device *pdev)
1248{
1249 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1250 struct snd_soc_codec *codec = socdev->card->codec;
0e0e16a8
MB		 1251 struct wm8900_priv *wm8900 = codec->private_data;
1252 u16 *cache;
1253 int i, ret;
1254
1255 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1256 GFP_KERNEL);
1257
1258 wm8900_reset(codec);
1259 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1260
1261 /* Restart the FLL? */
1262 if (wm8900->fll_out) {
1263 int fll_out = wm8900->fll_out;
1264 int fll_in = wm8900->fll_in;
1265
1266 wm8900->fll_in = 0;
1267 wm8900->fll_out = 0;
1268
1269 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1270 if (ret != 0) {
1271 dev_err(&pdev->dev, "Failed to restart FLL\n");
1272 return ret;
1273 }
1274 }
1275
1276 if (cache) {
1277 for (i = 0; i < WM8900_MAXREG; i++)
1278 wm8900_write(codec, i, cache[i]);
1279 kfree(cache);
1280 } else
1281 dev_err(&pdev->dev, "Unable to allocate register cache\n");
1282
1283 return 0;
1284}
1285
78e19a39
MB		 1286static struct snd_soc_codec *wm8900_codec;
1287
c6f29811
MB		 1288static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1289 const struct i2c_device_id *id)
0e0e16a8 1290{
78e19a39
MB		 1291 struct wm8900_priv *wm8900;
1292 struct snd_soc_codec *codec;
0e0e16a8 1293 unsigned int reg;
78e19a39
MB		 1294 int ret;
1295
1296 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1297 if (wm8900 == NULL)
1298 return -ENOMEM;
1299
1300 codec = &wm8900->codec;
1301 codec->private_data = wm8900;
1302 codec->reg_cache = &wm8900->reg_cache[0];
1303 codec->reg_cache_size = WM8900_MAXREG;
1304
1305 mutex_init(&codec->mutex);
1306 INIT_LIST_HEAD(&codec->dapm_widgets);
1307 INIT_LIST_HEAD(&codec->dapm_paths);
0e0e16a8
MB		 1308
1309 codec->name = "WM8900";
1310 codec->owner = THIS_MODULE;
1311 codec->read = wm8900_read;
1312 codec->write = wm8900_write;
1313 codec->dai = &wm8900_dai;
1314 codec->num_dai = 1;
78e19a39
MB		 1315 codec->hw_write = (hw_write_t)i2c_master_send;
1316 codec->control_data = i2c;
1317 codec->set_bias_level = wm8900_set_bias_level;
1318 codec->dev = &i2c->dev;
0e0e16a8
MB		 1319
1320 reg = wm8900_read(codec, WM8900_REG_ID);
1321 if (reg != 0x8900) {
78e19a39
MB		 1322 dev_err(&i2c->dev, "Device is not a WM8900 - ID %x\n", reg);
1323 ret = -ENODEV;
1324 goto err;
0e0e16a8
MB		 1325 }
1326
1327 /* Read back from the chip */
1328 reg = wm8900_chip_read(codec, WM8900_REG_POWER1);
1329 reg = (reg >> 12) & 0xf;
78e19a39 1330 dev_info(&i2c->dev, "WM8900 revision %d\n", reg);
0e0e16a8
MB		 1331
1332 wm8900_reset(codec);
1333
78e19a39
MB		 1334 /* Turn the chip on */
1335 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1336
0e0e16a8
MB		 1337 /* Latch the volume update bits */
1338 wm8900_write(codec, WM8900_REG_LINVOL,
1339 wm8900_read(codec, WM8900_REG_LINVOL) | 0x100);
1340 wm8900_write(codec, WM8900_REG_RINVOL,
1341 wm8900_read(codec, WM8900_REG_RINVOL) | 0x100);
1342 wm8900_write(codec, WM8900_REG_LOUT1CTL,
1343 wm8900_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1344 wm8900_write(codec, WM8900_REG_ROUT1CTL,
1345 wm8900_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1346 wm8900_write(codec, WM8900_REG_LOUT2CTL,
1347 wm8900_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1348 wm8900_write(codec, WM8900_REG_ROUT2CTL,
1349 wm8900_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1350 wm8900_write(codec, WM8900_REG_LDAC_DV,
1351 wm8900_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1352 wm8900_write(codec, WM8900_REG_RDAC_DV,
1353 wm8900_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1354 wm8900_write(codec, WM8900_REG_LADC_DV,
1355 wm8900_read(codec, WM8900_REG_LADC_DV) | 0x100);
1356 wm8900_write(codec, WM8900_REG_RADC_DV,
1357 wm8900_read(codec, WM8900_REG_RADC_DV) | 0x100);
1358
1359 /* Set the DAC and mixer output bias */
1360 wm8900_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
1361
78e19a39 1362 wm8900_dai.dev = &i2c->dev;
0e0e16a8 1363
78e19a39 1364 wm8900_codec = codec;
0e0e16a8 1365
78e19a39
MB		 1366 ret = snd_soc_register_codec(codec);
1367 if (ret != 0) {
1368 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1369 goto err;
1370 }
0e0e16a8 1371
78e19a39
MB		 1372 ret = snd_soc_register_dai(&wm8900_dai);
1373 if (ret != 0) {
1374 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1375 goto err_codec;
0e0e16a8 1376 }
0e0e16a8 1377
0e0e16a8 1378 return ret;
0e0e16a8 1379
78e19a39
MB		 1380err_codec:
1381 snd_soc_unregister_codec(codec);
1382err:
1383 kfree(wm8900);
1384 wm8900_codec = NULL;
1385 return ret;
0e0e16a8
MB		 1386}
1387
c6f29811 1388static __devexit int wm8900_i2c_remove(struct i2c_client *client)
0e0e16a8 1389{
f0752331 1390 snd_soc_unregister_dai(&wm8900_dai);
78e19a39
MB		 1391 snd_soc_unregister_codec(wm8900_codec);
1392
1393 wm8900_set_bias_level(wm8900_codec, SND_SOC_BIAS_OFF);
1394
f0752331 1395 wm8900_dai.dev = NULL;
78e19a39
MB		 1396 kfree(wm8900_codec->private_data);
1397 wm8900_codec = NULL;
1398
0e0e16a8
MB		 1399 return 0;
1400}
1401
8ae6a552
JD		 1402static const struct i2c_device_id wm8900_i2c_id[] = {
1403 { "wm8900", 0 },
1404 { }
1405};
1406MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
0e0e16a8 1407
0e0e16a8
MB		 1408static struct i2c_driver wm8900_i2c_driver = {
1409 .driver = {
78e19a39 1410 .name = "WM8900",
0e0e16a8
MB		 1411 .owner = THIS_MODULE,
1412 },
8ae6a552 1413 .probe = wm8900_i2c_probe,
c6f29811 1414 .remove = __devexit_p(wm8900_i2c_remove),
8ae6a552 1415 .id_table = wm8900_i2c_id,
0e0e16a8
MB		 1416};
1417
0e0e16a8
MB		 1418static int wm8900_probe(struct platform_device *pdev)
1419{
1420 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
0e0e16a8
MB		 1421 struct snd_soc_codec *codec;
1422 int ret = 0;
1423
78e19a39 1424 if (!wm8900_codec) {
f0752331
MB		 1425 dev_err(&pdev->dev, "I2C client not yet instantiated\n");
1426 return -ENODEV;
1427 }
0e0e16a8 1428
78e19a39 1429 codec = wm8900_codec;
6627a653 1430 socdev->card->codec = codec;
0e0e16a8 1431
78e19a39
MB		 1432 /* Register pcms */
1433 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1434 if (ret < 0) {
1435 dev_err(&pdev->dev, "Failed to register new PCMs\n");
1436 goto pcm_err;
1437 }
0e0e16a8 1438
3e8e1952
IM		 1439 snd_soc_add_controls(codec, wm8900_snd_controls,
1440 ARRAY_SIZE(wm8900_snd_controls));
78e19a39
MB		 1441 wm8900_add_widgets(codec);
1442
1443 ret = snd_soc_init_card(socdev);
1444 if (ret < 0) {
1445 dev_err(&pdev->dev, "Failed to register card\n");
1446 goto card_err;
1447 }
f0752331 1448
78e19a39 1449 return ret;
f0752331 1450
78e19a39
MB		 1451card_err:
1452 snd_soc_free_pcms(socdev);
1453 snd_soc_dapm_free(socdev);
1454pcm_err:
0e0e16a8
MB		 1455 return ret;
1456}
1457
1458/* power down chip */
1459static int wm8900_remove(struct platform_device *pdev)
1460{
1461 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
0e0e16a8
MB		 1462
1463 snd_soc_free_pcms(socdev);
1464 snd_soc_dapm_free(socdev);
0e0e16a8
MB		 1465
1466 return 0;
1467}
1468
1469struct snd_soc_codec_device soc_codec_dev_wm8900 = {
1470 .probe = wm8900_probe,
1471 .remove = wm8900_remove,
1472 .suspend = wm8900_suspend,
1473 .resume = wm8900_resume,
1474};
1475EXPORT_SYMBOL_GPL(soc_codec_dev_wm8900);
1476
c9b3a40f 1477static int __init wm8900_modinit(void)
64089b84 1478{
f0752331 1479 return i2c_add_driver(&wm8900_i2c_driver);
64089b84
MB		 1480}
1481module_init(wm8900_modinit);
1482
1483static void __exit wm8900_exit(void)
1484{
f0752331 1485 i2c_del_driver(&wm8900_i2c_driver);
64089b84
MB		 1486}
1487module_exit(wm8900_exit);
1488
0e0e16a8
MB		 1489MODULE_DESCRIPTION("ASoC WM8900 driver");
1490MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1491MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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