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ASoC: WM8903: Create default platform data structure
[deliverable/linux.git] / sound / soc / codecs / wm8900.c
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0e0e16a8
MB		 1/*
2 * wm8900.c -- WM8900 ALSA Soc Audio driver
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - Tristating.
14 * - TDM.
15 * - Jack detect.
16 * - FLL source configuration, currently only MCLK is supported.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
0e0e16a8
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
f0fba2ad 26#include <linux/spi/spi.h>
5a0e3ad6 27#include <linux/slab.h>
0e0e16a8
MB		 28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/soc.h>
0e0e16a8
MB		 32#include <sound/initval.h>
33#include <sound/tlv.h>
34
35#include "wm8900.h"
36
37/* WM8900 register space */
38#define WM8900_REG_RESET 0x0
39#define WM8900_REG_ID 0x0
40#define WM8900_REG_POWER1 0x1
41#define WM8900_REG_POWER2 0x2
42#define WM8900_REG_POWER3 0x3
43#define WM8900_REG_AUDIO1 0x4
44#define WM8900_REG_AUDIO2 0x5
45#define WM8900_REG_CLOCKING1 0x6
46#define WM8900_REG_CLOCKING2 0x7
47#define WM8900_REG_AUDIO3 0x8
48#define WM8900_REG_AUDIO4 0x9
49#define WM8900_REG_DACCTRL 0xa
50#define WM8900_REG_LDAC_DV 0xb
51#define WM8900_REG_RDAC_DV 0xc
52#define WM8900_REG_SIDETONE 0xd
53#define WM8900_REG_ADCCTRL 0xe
54#define WM8900_REG_LADC_DV 0xf
55#define WM8900_REG_RADC_DV 0x10
56#define WM8900_REG_GPIO 0x12
57#define WM8900_REG_INCTL 0x15
58#define WM8900_REG_LINVOL 0x16
59#define WM8900_REG_RINVOL 0x17
60#define WM8900_REG_INBOOSTMIX1 0x18
61#define WM8900_REG_INBOOSTMIX2 0x19
62#define WM8900_REG_ADCPATH 0x1a
63#define WM8900_REG_AUXBOOST 0x1b
64#define WM8900_REG_ADDCTL 0x1e
65#define WM8900_REG_FLLCTL1 0x24
66#define WM8900_REG_FLLCTL2 0x25
67#define WM8900_REG_FLLCTL3 0x26
68#define WM8900_REG_FLLCTL4 0x27
69#define WM8900_REG_FLLCTL5 0x28
70#define WM8900_REG_FLLCTL6 0x29
71#define WM8900_REG_LOUTMIXCTL1 0x2c
72#define WM8900_REG_ROUTMIXCTL1 0x2d
73#define WM8900_REG_BYPASS1 0x2e
74#define WM8900_REG_BYPASS2 0x2f
75#define WM8900_REG_AUXOUT_CTL 0x30
76#define WM8900_REG_LOUT1CTL 0x33
77#define WM8900_REG_ROUT1CTL 0x34
78#define WM8900_REG_LOUT2CTL 0x35
79#define WM8900_REG_ROUT2CTL 0x36
80#define WM8900_REG_HPCTL1 0x3a
81#define WM8900_REG_OUTBIASCTL 0x73
82
83#define WM8900_MAXREG 0x80
84
85#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
86#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
87#define WM8900_REG_ADDCTL_VMID_DIS 0x20
88#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
89#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
90#define WM8900_REG_ADDCTL_TEMP_SD 0x02
91
92#define WM8900_REG_GPIO_TEMP_ENA 0x2
93
94#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
95#define WM8900_REG_POWER1_BIAS_ENA 0x0008
96#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
97#define WM8900_REG_POWER1_FLL_ENA 0x0040
98
99#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
100#define WM8900_REG_POWER2_ADCL_ENA 0x0002
101#define WM8900_REG_POWER2_ADCR_ENA 0x0001
102
103#define WM8900_REG_POWER3_DACL_ENA 0x0002
104#define WM8900_REG_POWER3_DACR_ENA 0x0001
105
106#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
107#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
108#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
109
110#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
111#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
de5035b1
AL		 112#define WM8900_REG_CLOCKING1_BCLK_MASK 0x01e
113#define WM8900_REG_CLOCKING1_OPCLK_MASK 0x7000
0e0e16a8
MB		 114
115#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
116#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
117
118#define WM8900_REG_DACCTRL_MUTE 0x004
21002e20 119#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
0e0e16a8
MB		 120#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
121
122#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
123
124#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
125
126#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
127
128#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
129
130#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
131#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
132#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
133#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
134#define WM8900_REG_HPCTL1_HP_SHORT 0x08
135#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
136
de5035b1 137#define WM8900_LRC_MASK 0x03ff
0e0e16a8 138
0e0e16a8 139struct wm8900_priv {
f0fba2ad 140 enum snd_soc_control_type control_type;
78e19a39 141
0e0e16a8
MB		 142 u32 fll_in; /* FLL input frequency */
143 u32 fll_out; /* FLL output frequency */
144};
145
146/*
147 * wm8900 register cache. We can't read the entire register space and we
148 * have slow control buses so we cache the registers.
149 */
150static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
151 0x8900, 0x0000,
152 0xc000, 0x0000,
153 0x4050, 0x4000,
154 0x0008, 0x0000,
155 0x0040, 0x0040,
156 0x1004, 0x00c0,
157 0x00c0, 0x0000,
158 0x0100, 0x00c0,
159 0x00c0, 0x0000,
160 0xb001, 0x0000,
161 0x0000, 0x0044,
162 0x004c, 0x004c,
163 0x0044, 0x0044,
164 0x0000, 0x0044,
165 0x0000, 0x0000,
166 0x0002, 0x0000,
167 0x0000, 0x0000,
168 0x0000, 0x0000,
169 0x0008, 0x0000,
170 0x0000, 0x0008,
171 0x0097, 0x0100,
172 0x0000, 0x0000,
173 0x0050, 0x0050,
174 0x0055, 0x0055,
175 0x0055, 0x0000,
176 0x0000, 0x0079,
177 0x0079, 0x0079,
178 0x0079, 0x0000,
179 /* Remaining registers all zero */
180};
181
d4754ec9 182static int wm8900_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
0e0e16a8
MB		 183{
184 switch (reg) {
185 case WM8900_REG_ID:
8d50e447 186 return 1;
0e0e16a8 187 default:
8d50e447 188 return 0;
0e0e16a8
MB		 189 }
190}
191
192static void wm8900_reset(struct snd_soc_codec *codec)
193{
8d50e447 194 snd_soc_write(codec, WM8900_REG_RESET, 0);
0e0e16a8
MB		 195
196 memcpy(codec->reg_cache, wm8900_reg_defaults,
bc258006 197 sizeof(wm8900_reg_defaults));
0e0e16a8
MB		 198}
199
200static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
201 struct snd_kcontrol *kcontrol, int event)
202{
203 struct snd_soc_codec *codec = w->codec;
8d50e447 204 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
0e0e16a8
MB		 205
206 switch (event) {
207 case SND_SOC_DAPM_PRE_PMU:
208 /* Clamp headphone outputs */
209 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
210 WM8900_REG_HPCTL1_HP_CLAMP_OP;
8d50e447 211 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 212 break;
213
214 case SND_SOC_DAPM_POST_PMU:
215 /* Enable the input stage */
216 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
217 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
218 WM8900_REG_HPCTL1_HP_SHORT2 |
219 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 220 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 221
222 msleep(400);
223
224 /* Enable the output stage */
225 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
226 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 227 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 228
229 /* Remove the shorts */
230 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
8d50e447 231 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8 232 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 233 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 234 break;
235
236 case SND_SOC_DAPM_PRE_PMD:
237 /* Short the output */
238 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 239 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 240
241 /* Disable the output stage */
242 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 243 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 244
245 /* Clamp the outputs and power down input */
246 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
247 WM8900_REG_HPCTL1_HP_CLAMP_OP;
248 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 249 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 250 break;
251
252 case SND_SOC_DAPM_POST_PMD:
253 /* Disable everything */
8d50e447 254 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 255 break;
256
257 default:
258 BUG();
259 }
260
261 return 0;
262}
263
264static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
265
266static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
267
268static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
269
270static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
271
272static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
273
274static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
275
276static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
277
278static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
279
280static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
281
282static const struct soc_enum mic_bias_level =
283SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
284
285static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
286
287static const struct soc_enum dac_mute_rate =
288SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
289
290static const char *dac_deemphasis_txt[] = {
291 "Disabled", "32kHz", "44.1kHz", "48kHz"
292};
293
294static const struct soc_enum dac_deemphasis =
295SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
296
297static const char *adc_hpf_cut_txt[] = {
298 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
299};
300
301static const struct soc_enum adc_hpf_cut =
302SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
303
304static const char *lr_txt[] = {
305 "Left", "Right"
306};
307
308static const struct soc_enum aifl_src =
309SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
310
311static const struct soc_enum aifr_src =
312SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
313
314static const struct soc_enum dacl_src =
315SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
316
317static const struct soc_enum dacr_src =
318SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
319
320static const char *sidetone_txt[] = {
321 "Disabled", "Left ADC", "Right ADC"
322};
323
324static const struct soc_enum dacl_sidetone =
325SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
326
327static const struct soc_enum dacr_sidetone =
328SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
329
330static const struct snd_kcontrol_new wm8900_snd_controls[] = {
331SOC_ENUM("Mic Bias Level", mic_bias_level),
332
333SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
334 in_pga_tlv),
335SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
336SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
337
338SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
339 in_pga_tlv),
340SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
341SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
342
343SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
344SOC_ENUM("DAC Mute Rate", dac_mute_rate),
345SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
346SOC_ENUM("DAC Deemphasis", dac_deemphasis),
0e0e16a8
MB		 347SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
348 12, 1, 0),
349
350SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
351SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
352SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
353SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
354 adc_svol_tlv),
355SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
356 adc_svol_tlv),
357SOC_ENUM("Left Digital Audio Source", aifl_src),
358SOC_ENUM("Right Digital Audio Source", aifr_src),
359
360SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
361 dac_boost_tlv),
362SOC_ENUM("Left DAC Source", dacl_src),
363SOC_ENUM("Right DAC Source", dacr_src),
364SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
365SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
366SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
367
368SOC_DOUBLE_R_TLV("Digital Playback Volume",
369 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
370 1, 96, 0, dac_tlv),
371SOC_DOUBLE_R_TLV("Digital Capture Volume",
372 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
373
374SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
375 out_mix_tlv),
376SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
377 out_mix_tlv),
378SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
379 out_mix_tlv),
380SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
381 out_mix_tlv),
382
383SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
384 out_mix_tlv),
385SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
386 out_mix_tlv),
387SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
388 out_mix_tlv),
389SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
390 out_mix_tlv),
391
392SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
393 in_boost_tlv),
394SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
395 in_boost_tlv),
396SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
397 in_boost_tlv),
398SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
399 in_boost_tlv),
400SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
401 in_boost_tlv),
402SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
403 in_boost_tlv),
404
405SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
406 0, 63, 0, out_pga_tlv),
407SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
408 6, 1, 1),
409SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
410 7, 1, 0),
411
412SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
413 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
414 0, 63, 0, out_pga_tlv),
415SOC_DOUBLE_R("LINEOUT2 Switch",
416 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
417SOC_DOUBLE_R("LINEOUT2 ZC Switch",
418 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
419SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
420 0, 1, 1),
421
422};
423
0e0e16a8
MB		 424static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
425SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
426
427static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
428SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
429
430static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
431SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
432SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
433SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
434SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
435SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
436};
437
438static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
439SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
440SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
441SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
442SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
443SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
444};
445
446static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
447SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
448SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
449SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
450SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
451};
452
453static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
454SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
455SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
456SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
457SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
458};
459
460static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
461SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
462SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
463SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
464};
465
466static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
467SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
468SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
469SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
470};
471
472static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
473
474static const struct soc_enum wm8900_lineout2_lp_mux =
475SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
476
477static const struct snd_kcontrol_new wm8900_lineout2_lp =
478SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
479
480static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
481
482/* Externally visible pins */
483SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
484SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
485SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
486SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
487SND_SOC_DAPM_OUTPUT("HP_L"),
488SND_SOC_DAPM_OUTPUT("HP_R"),
489
490SND_SOC_DAPM_INPUT("RINPUT1"),
491SND_SOC_DAPM_INPUT("LINPUT1"),
492SND_SOC_DAPM_INPUT("RINPUT2"),
493SND_SOC_DAPM_INPUT("LINPUT2"),
494SND_SOC_DAPM_INPUT("RINPUT3"),
495SND_SOC_DAPM_INPUT("LINPUT3"),
496SND_SOC_DAPM_INPUT("AUX"),
497
498SND_SOC_DAPM_VMID("VMID"),
499
500/* Input */
501SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
502 wm8900_linpga_controls,
503 ARRAY_SIZE(wm8900_linpga_controls)),
504SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
505 wm8900_rinpga_controls,
506 ARRAY_SIZE(wm8900_rinpga_controls)),
507
508SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
509 wm8900_linmix_controls,
510 ARRAY_SIZE(wm8900_linmix_controls)),
511SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
512 wm8900_rinmix_controls,
513 ARRAY_SIZE(wm8900_rinmix_controls)),
514
8a709d92 515SND_SOC_DAPM_SUPPLY("Mic Bias", WM8900_REG_POWER1, 4, 0, NULL, 0),
0e0e16a8
MB		 516
517SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
518SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
519
520/* Output */
521SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
522SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
523
524SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
525 wm8900_hp_event,
526 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
527 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
528
529SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
530SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
531
532SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
533SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
534SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
535
536SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
537 wm8900_loutmix_controls,
538 ARRAY_SIZE(wm8900_loutmix_controls)),
539SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
540 wm8900_routmix_controls,
541 ARRAY_SIZE(wm8900_routmix_controls)),
542};
543
544/* Target, Path, Source */
545static const struct snd_soc_dapm_route audio_map[] = {
546/* Inputs */
547{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
548{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
549{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
550
551{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
552{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
553{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
554
555{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
556{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
557{"Left Input Mixer", "AUX Switch", "AUX"},
558{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
559
560{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
561{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
562{"Right Input Mixer", "AUX Switch", "AUX"},
563{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
564
565{"ADCL", NULL, "Left Input Mixer"},
566{"ADCR", NULL, "Right Input Mixer"},
567
568/* Outputs */
569{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
570{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
571{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
572{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
573
574{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
575{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
576{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
577{"LINEOUT2L", NULL, "LINEOUT2 LP"},
578
579{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
580{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
581{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
582{"LINEOUT2R", NULL, "LINEOUT2 LP"},
583
584{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
585{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
586{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
587{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
588{"Left Output Mixer", "DACL Switch", "DACL"},
589
590{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
591{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
592{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
593{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
594{"Right Output Mixer", "DACR Switch", "DACR"},
595
596/* Note that the headphone output stage needs to be connected
597 * externally to LINEOUT2 via DC blocking capacitors. Other
598 * configurations are not supported.
599 *
600 * Note also that left and right headphone paths are treated as a
601 * mono path.
602 */
603{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
604{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
605{"HP_L", NULL, "Headphone Amplifier"},
606{"HP_R", NULL, "Headphone Amplifier"},
607};
608
609static int wm8900_add_widgets(struct snd_soc_codec *codec)
610{
ce6120cc 611 struct snd_soc_dapm_context *dapm = &codec->dapm;
0e0e16a8 612
ce6120cc
LG		 613 snd_soc_dapm_new_controls(dapm, wm8900_dapm_widgets,
614 ARRAY_SIZE(wm8900_dapm_widgets));
615 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
0e0e16a8 616
0e0e16a8
MB		 617 return 0;
618}
619
620static int wm8900_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 621 struct snd_pcm_hw_params *params,
622 struct snd_soc_dai *dai)
0e0e16a8
MB		 623{
624 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 625 struct snd_soc_codec *codec = rtd->codec;
0e0e16a8
MB		 626 u16 reg;
627
8d50e447 628 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
0e0e16a8
MB		 629
630 switch (params_format(params)) {
631 case SNDRV_PCM_FORMAT_S16_LE:
632 break;
633 case SNDRV_PCM_FORMAT_S20_3LE:
634 reg |= 0x20;
635 break;
636 case SNDRV_PCM_FORMAT_S24_LE:
637 reg |= 0x40;
638 break;
639 case SNDRV_PCM_FORMAT_S32_LE:
640 reg |= 0x60;
641 break;
642 default:
643 return -EINVAL;
644 }
645
8d50e447 646 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
0e0e16a8 647
21002e20 648 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
8d50e447 649 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
21002e20
MB		 650
651 if (params_rate(params) <= 24000)
652 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
653 else
654 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
655
8d50e447 656 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
21002e20
MB		 657 }
658
0e0e16a8
MB		 659 return 0;
660}
661
662/* FLL divisors */
663struct _fll_div {
664 u16 fll_ratio;
665 u16 fllclk_div;
666 u16 fll_slow_lock_ref;
667 u16 n;
668 u16 k;
669};
670
671/* The size in bits of the FLL divide multiplied by 10
672 * to allow rounding later */
673#define FIXED_FLL_SIZE ((1 << 16) * 10)
674
675static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
676 unsigned int Fout)
677{
678 u64 Kpart;
679 unsigned int K, Ndiv, Nmod, target;
680 unsigned int div;
681
682 BUG_ON(!Fout);
683
684 /* The FLL must run at 90-100MHz which is then scaled down to
685 * the output value by FLLCLK_DIV. */
686 target = Fout;
687 div = 1;
688 while (target < 90000000) {
689 div *= 2;
690 target *= 2;
691 }
692
693 if (target > 100000000)
449bd54d
RK		 694 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
695 " Fout=%u\n", target, Fref, Fout);
0e0e16a8
MB		 696 if (div > 32) {
697 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
449bd54d 698 "Fref=%u, Fout=%u, target=%u\n",
0e0e16a8
MB		 699 div, Fref, Fout, target);
700 return -EINVAL;
701 }
702
703 fll_div->fllclk_div = div >> 2;
704
705 if (Fref < 48000)
706 fll_div->fll_slow_lock_ref = 1;
707 else
708 fll_div->fll_slow_lock_ref = 0;
709
710 Ndiv = target / Fref;
711
712 if (Fref < 1000000)
713 fll_div->fll_ratio = 8;
714 else
715 fll_div->fll_ratio = 1;
716
717 fll_div->n = Ndiv / fll_div->fll_ratio;
718 Nmod = (target / fll_div->fll_ratio) % Fref;
719
720 /* Calculate fractional part - scale up so we can round. */
721 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
722
723 do_div(Kpart, Fref);
724
725 K = Kpart & 0xFFFFFFFF;
726
727 if ((K % 10) >= 5)
728 K += 5;
729
730 /* Move down to proper range now rounding is done */
731 fll_div->k = K / 10;
732
733 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
734 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
735
736 return 0;
737}
738
739static int wm8900_set_fll(struct snd_soc_codec *codec,
740 int fll_id, unsigned int freq_in, unsigned int freq_out)
741{
b2c812e2 742 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8 743 struct _fll_div fll_div;
0e0e16a8
MB		 744
745 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
746 return 0;
747
748 /* The digital side should be disabled during any change. */
29c6a01d
AL		 749 snd_soc_update_bits(codec, WM8900_REG_POWER1,
750 WM8900_REG_POWER1_FLL_ENA, 0);
0e0e16a8
MB		 751
752 /* Disable the FLL? */
753 if (!freq_in || !freq_out) {
29c6a01d
AL		 754 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
755 WM8900_REG_CLOCKING1_MCLK_SRC, 0);
756 snd_soc_update_bits(codec, WM8900_REG_FLLCTL1,
757 WM8900_REG_FLLCTL1_OSC_ENA, 0);
0e0e16a8
MB		 758 wm8900->fll_in = freq_in;
759 wm8900->fll_out = freq_out;
760
761 return 0;
762 }
763
764 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
765 goto reenable;
766
767 wm8900->fll_in = freq_in;
768 wm8900->fll_out = freq_out;
769
770 /* The osclilator *MUST* be enabled before we enable the
771 * digital circuit. */
8d50e447 772 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 773 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
774
8d50e447
MB		 775 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
776 snd_soc_write(codec, WM8900_REG_FLLCTL5,
0e0e16a8
MB		 777 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
778
779 if (fll_div.k) {
8d50e447 780 snd_soc_write(codec, WM8900_REG_FLLCTL2,
0e0e16a8 781 (fll_div.k >> 8) | 0x100);
8d50e447 782 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
0e0e16a8 783 } else
8d50e447 784 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
0e0e16a8
MB		 785
786 if (fll_div.fll_slow_lock_ref)
8d50e447 787 snd_soc_write(codec, WM8900_REG_FLLCTL6,
0e0e16a8
MB		 788 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
789 else
8d50e447 790 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
0e0e16a8 791
29c6a01d
AL		 792 snd_soc_update_bits(codec, WM8900_REG_POWER1,
793 WM8900_REG_POWER1_FLL_ENA,
794 WM8900_REG_POWER1_FLL_ENA);
0e0e16a8
MB		 795
796reenable:
29c6a01d
AL		 797 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
798 WM8900_REG_CLOCKING1_MCLK_SRC,
799 WM8900_REG_CLOCKING1_MCLK_SRC);
0e0e16a8
MB		 800 return 0;
801}
802
85488037
MB		 803static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
804 int source, unsigned int freq_in, unsigned int freq_out)
0e0e16a8
MB		 805{
806 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
807}
808
809static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
810 int div_id, int div)
811{
812 struct snd_soc_codec *codec = codec_dai->codec;
0e0e16a8
MB		 813
814 switch (div_id) {
815 case WM8900_BCLK_DIV:
29c6a01d
AL		 816 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
817 WM8900_REG_CLOCKING1_BCLK_MASK, div);
0e0e16a8
MB		 818 break;
819 case WM8900_OPCLK_DIV:
29c6a01d
AL		 820 snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
821 WM8900_REG_CLOCKING1_OPCLK_MASK, div);
0e0e16a8
MB		 822 break;
823 case WM8900_DAC_LRCLK:
29c6a01d
AL		 824 snd_soc_update_bits(codec, WM8900_REG_AUDIO4,
825 WM8900_LRC_MASK, div);
0e0e16a8
MB		 826 break;
827 case WM8900_ADC_LRCLK:
29c6a01d
AL		 828 snd_soc_update_bits(codec, WM8900_REG_AUDIO3,
829 WM8900_LRC_MASK, div);
0e0e16a8
MB		 830 break;
831 case WM8900_DAC_CLKDIV:
29c6a01d
AL		 832 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
833 WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
0e0e16a8
MB		 834 break;
835 case WM8900_ADC_CLKDIV:
29c6a01d
AL		 836 snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
837 WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
0e0e16a8
MB		 838 break;
839 case WM8900_LRCLK_MODE:
29c6a01d
AL		 840 snd_soc_update_bits(codec, WM8900_REG_DACCTRL,
841 WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
0e0e16a8
MB		 842 break;
843 default:
844 return -EINVAL;
845 }
846
847 return 0;
848}
849
850
851static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
852 unsigned int fmt)
853{
854 struct snd_soc_codec *codec = codec_dai->codec;
855 unsigned int clocking1, aif1, aif3, aif4;
856
8d50e447
MB		 857 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
858 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
859 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
860 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
0e0e16a8
MB		 861
862 /* set master/slave audio interface */
863 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
864 case SND_SOC_DAIFMT_CBS_CFS:
865 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
866 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
867 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
868 break;
869 case SND_SOC_DAIFMT_CBS_CFM:
870 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
871 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
872 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
873 break;
874 case SND_SOC_DAIFMT_CBM_CFM:
875 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
876 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
877 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
878 break;
879 case SND_SOC_DAIFMT_CBM_CFS:
880 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
881 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
882 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
883 break;
884 default:
885 return -EINVAL;
886 }
887
888 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
889 case SND_SOC_DAIFMT_DSP_A:
890 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
891 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
892 break;
893 case SND_SOC_DAIFMT_DSP_B:
894 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
895 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
896 break;
897 case SND_SOC_DAIFMT_I2S:
898 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
899 aif1 |= 0x10;
900 break;
901 case SND_SOC_DAIFMT_RIGHT_J:
902 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
903 break;
904 case SND_SOC_DAIFMT_LEFT_J:
905 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
906 aif1 |= 0x8;
907 break;
908 default:
909 return -EINVAL;
910 }
911
912 /* Clock inversion */
913 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
914 case SND_SOC_DAIFMT_DSP_A:
915 case SND_SOC_DAIFMT_DSP_B:
916 /* frame inversion not valid for DSP modes */
917 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
918 case SND_SOC_DAIFMT_NB_NF:
919 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
920 break;
921 case SND_SOC_DAIFMT_IB_NF:
922 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
923 break;
924 default:
925 return -EINVAL;
926 }
927 break;
928 case SND_SOC_DAIFMT_I2S:
929 case SND_SOC_DAIFMT_RIGHT_J:
930 case SND_SOC_DAIFMT_LEFT_J:
931 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
932 case SND_SOC_DAIFMT_NB_NF:
933 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
934 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
935 break;
936 case SND_SOC_DAIFMT_IB_IF:
937 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
938 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
939 break;
940 case SND_SOC_DAIFMT_IB_NF:
941 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
942 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
943 break;
944 case SND_SOC_DAIFMT_NB_IF:
945 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
946 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
947 break;
948 default:
949 return -EINVAL;
950 }
951 break;
952 default:
953 return -EINVAL;
954 }
955
8d50e447
MB		 956 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
957 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
958 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
959 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
0e0e16a8
MB		 960
961 return 0;
962}
963
964static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
965{
966 struct snd_soc_codec *codec = codec_dai->codec;
967 u16 reg;
968
8d50e447 969 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
0e0e16a8
MB		 970
971 if (mute)
972 reg |= WM8900_REG_DACCTRL_MUTE;
973 else
974 reg &= ~WM8900_REG_DACCTRL_MUTE;
975
8d50e447 976 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
0e0e16a8
MB		 977
978 return 0;
979}
980
981#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
982 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
983 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
984
985#define WM8900_PCM_FORMATS \
986 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
987 SNDRV_PCM_FORMAT_S24_LE)
988
85e7652d 989static const struct snd_soc_dai_ops wm8900_dai_ops = {
6335d055
EM		 990 .hw_params = wm8900_hw_params,
991 .set_clkdiv = wm8900_set_dai_clkdiv,
992 .set_pll = wm8900_set_dai_pll,
993 .set_fmt = wm8900_set_dai_fmt,
994 .digital_mute = wm8900_digital_mute,
995};
996
f0fba2ad
LG		 997static struct snd_soc_dai_driver wm8900_dai = {
998 .name = "wm8900-hifi",
0e0e16a8
MB		 999 .playback = {
1000 .stream_name = "HiFi Playback",
1001 .channels_min = 1,
1002 .channels_max = 2,
1003 .rates = WM8900_RATES,
1004 .formats = WM8900_PCM_FORMATS,
1005 },
1006 .capture = {
1007 .stream_name = "HiFi Capture",
1008 .channels_min = 1,
1009 .channels_max = 2,
1010 .rates = WM8900_RATES,
1011 .formats = WM8900_PCM_FORMATS,
1012 },
6335d055 1013 .ops = &wm8900_dai_ops,
0e0e16a8 1014};
0e0e16a8
MB		 1015
1016static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1017 enum snd_soc_bias_level level)
1018{
1019 u16 reg;
1020
1021 switch (level) {
1022 case SND_SOC_BIAS_ON:
1023 /* Enable thermal shutdown */
29c6a01d
AL		 1024 snd_soc_update_bits(codec, WM8900_REG_GPIO,
1025 WM8900_REG_GPIO_TEMP_ENA,
1026 WM8900_REG_GPIO_TEMP_ENA);
1027 snd_soc_update_bits(codec, WM8900_REG_ADDCTL,
1028 WM8900_REG_ADDCTL_TEMP_SD,
1029 WM8900_REG_ADDCTL_TEMP_SD);
0e0e16a8
MB		 1030 break;
1031
1032 case SND_SOC_BIAS_PREPARE:
1033 break;
1034
1035 case SND_SOC_BIAS_STANDBY:
1036 /* Charge capacitors if initial power up */
ce6120cc 1037 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0e0e16a8 1038 /* STARTUP_BIAS_ENA on */
8d50e447 1039 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1040 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1041
1042 /* Startup bias mode */
8d50e447 1043 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1044 WM8900_REG_ADDCTL_BIAS_SRC |
1045 WM8900_REG_ADDCTL_VMID_SOFTST);
1046
1047 /* VMID 2x50k */
8d50e447 1048 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1049 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1050
1051 /* Allow capacitors to charge */
1052 schedule_timeout_interruptible(msecs_to_jiffies(400));
1053
1054 /* Enable bias */
8d50e447 1055 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1056 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1057 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1058
8d50e447 1059 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
0e0e16a8 1060
8d50e447 1061 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1062 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1063 }
1064
8d50e447
MB		 1065 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1066 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1067 (reg & WM8900_REG_POWER1_FLL_ENA) |
1068 WM8900_REG_POWER1_BIAS_ENA | 0x1);
8d50e447 1069 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8 1070 WM8900_REG_POWER2_SYSCLK_ENA);
8d50e447 1071 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1072 break;
1073
1074 case SND_SOC_BIAS_OFF:
1075 /* Startup bias enable */
8d50e447
MB		 1076 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1077 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8 1078 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
8d50e447 1079 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1080 WM8900_REG_ADDCTL_BIAS_SRC |
1081 WM8900_REG_ADDCTL_VMID_SOFTST);
1082
1083 /* Discharge caps */
8d50e447 1084 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1085 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1086 schedule_timeout_interruptible(msecs_to_jiffies(500));
1087
1088 /* Remove clamp */
8d50e447 1089 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 1090
1091 /* Power down */
8d50e447
MB		 1092 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1093 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1094 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1095 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1096
1097 /* Need to let things settle before stopping the clock
1098 * to ensure that restart works, see "Stopping the
1099 * master clock" in the datasheet. */
1100 schedule_timeout_interruptible(msecs_to_jiffies(1));
8d50e447 1101 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8
MB		 1102 WM8900_REG_POWER2_SYSCLK_ENA);
1103 break;
1104 }
ce6120cc 1105 codec->dapm.bias_level = level;
0e0e16a8
MB		 1106 return 0;
1107}
1108
84b315ee 1109static int wm8900_suspend(struct snd_soc_codec *codec)
0e0e16a8 1110{
b2c812e2 1111 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 1112 int fll_out = wm8900->fll_out;
1113 int fll_in = wm8900->fll_in;
1114 int ret;
1115
1116 /* Stop the FLL in an orderly fashion */
1117 ret = wm8900_set_fll(codec, 0, 0, 0);
1118 if (ret != 0) {
f0fba2ad 1119 dev_err(codec->dev, "Failed to stop FLL\n");
0e0e16a8
MB		 1120 return ret;
1121 }
1122
1123 wm8900->fll_out = fll_out;
1124 wm8900->fll_in = fll_in;
1125
1126 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1127
1128 return 0;
1129}
1130
f0fba2ad 1131static int wm8900_resume(struct snd_soc_codec *codec)
0e0e16a8 1132{
b2c812e2 1133 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 1134 u16 *cache;
1135 int i, ret;
1136
1137 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1138 GFP_KERNEL);
1139
1140 wm8900_reset(codec);
1141 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1142
1143 /* Restart the FLL? */
1144 if (wm8900->fll_out) {
1145 int fll_out = wm8900->fll_out;
1146 int fll_in = wm8900->fll_in;
1147
1148 wm8900->fll_in = 0;
1149 wm8900->fll_out = 0;
1150
1151 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1152 if (ret != 0) {
f0fba2ad 1153 dev_err(codec->dev, "Failed to restart FLL\n");
58499906 1154 kfree(cache);
0e0e16a8
MB		 1155 return ret;
1156 }
1157 }
1158
1159 if (cache) {
1160 for (i = 0; i < WM8900_MAXREG; i++)
8d50e447 1161 snd_soc_write(codec, i, cache[i]);
0e0e16a8
MB		 1162 kfree(cache);
1163 } else
f0fba2ad 1164 dev_err(codec->dev, "Unable to allocate register cache\n");
0e0e16a8
MB		 1165
1166 return 0;
1167}
1168
f0fba2ad 1169static int wm8900_probe(struct snd_soc_codec *codec)
0e0e16a8 1170{
f0fba2ad
LG		 1171 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1172 int ret = 0, reg;
78e19a39 1173
f0fba2ad 1174 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8900->control_type);
8d50e447 1175 if (ret != 0) {
f0fba2ad
LG		 1176 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1177 return ret;
8d50e447
MB		 1178 }
1179
1180 reg = snd_soc_read(codec, WM8900_REG_ID);
0e0e16a8 1181 if (reg != 0x8900) {
f0fba2ad
LG		 1182 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1183 return -ENODEV;
0e0e16a8
MB		 1184 }
1185
0e0e16a8
MB		 1186 wm8900_reset(codec);
1187
78e19a39
MB		 1188 /* Turn the chip on */
1189 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1190
0e0e16a8 1191 /* Latch the volume update bits */
29c6a01d
AL		 1192 snd_soc_update_bits(codec, WM8900_REG_LINVOL, 0x100, 0x100);
1193 snd_soc_update_bits(codec, WM8900_REG_RINVOL, 0x100, 0x100);
1194 snd_soc_update_bits(codec, WM8900_REG_LOUT1CTL, 0x100, 0x100);
1195 snd_soc_update_bits(codec, WM8900_REG_ROUT1CTL, 0x100, 0x100);
1196 snd_soc_update_bits(codec, WM8900_REG_LOUT2CTL, 0x100, 0x100);
1197 snd_soc_update_bits(codec, WM8900_REG_ROUT2CTL, 0x100, 0x100);
1198 snd_soc_update_bits(codec, WM8900_REG_LDAC_DV, 0x100, 0x100);
1199 snd_soc_update_bits(codec, WM8900_REG_RDAC_DV, 0x100, 0x100);
1200 snd_soc_update_bits(codec, WM8900_REG_LADC_DV, 0x100, 0x100);
1201 snd_soc_update_bits(codec, WM8900_REG_RADC_DV, 0x100, 0x100);
0e0e16a8
MB		 1202
1203 /* Set the DAC and mixer output bias */
8d50e447 1204 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
0e0e16a8 1205
f0fba2ad
LG		 1206 snd_soc_add_controls(codec, wm8900_snd_controls,
1207 ARRAY_SIZE(wm8900_snd_controls));
1208 wm8900_add_widgets(codec);
0e0e16a8 1209
f0fba2ad
LG		 1210 return 0;
1211}
0e0e16a8 1212
f0fba2ad
LG		 1213/* power down chip */
1214static int wm8900_remove(struct snd_soc_codec *codec)
1215{
1216 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1217 return 0;
1218}
0e0e16a8 1219
f0fba2ad
LG		 1220static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1221 .probe = wm8900_probe,
1222 .remove = wm8900_remove,
1223 .suspend = wm8900_suspend,
1224 .resume = wm8900_resume,
1225 .set_bias_level = wm8900_set_bias_level,
1226 .volatile_register = wm8900_volatile_register,
e5eec34c 1227 .reg_cache_size = ARRAY_SIZE(wm8900_reg_defaults),
f0fba2ad
LG		 1228 .reg_word_size = sizeof(u16),
1229 .reg_cache_default = wm8900_reg_defaults,
1230};
0e0e16a8 1231
f0fba2ad
LG		 1232#if defined(CONFIG_SPI_MASTER)
1233static int __devinit wm8900_spi_probe(struct spi_device *spi)
1234{
1235 struct wm8900_priv *wm8900;
1236 int ret;
1237
1238 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1239 if (wm8900 == NULL)
1240 return -ENOMEM;
0e0e16a8 1241
f0fba2ad
LG		 1242 wm8900->control_type = SND_SOC_SPI;
1243 spi_set_drvdata(spi, wm8900);
1244
1245 ret = snd_soc_register_codec(&spi->dev,
1246 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1247 if (ret < 0)
1248 kfree(wm8900);
78e19a39 1249 return ret;
0e0e16a8
MB		 1250}
1251
f0fba2ad 1252static int __devexit wm8900_spi_remove(struct spi_device *spi)
0e0e16a8 1253{
f0fba2ad
LG		 1254 snd_soc_unregister_codec(&spi->dev);
1255 kfree(spi_get_drvdata(spi));
1256 return 0;
1257}
78e19a39 1258
f0fba2ad
LG		 1259static struct spi_driver wm8900_spi_driver = {
1260 .driver = {
1261 .name = "wm8900-codec",
f0fba2ad
LG		 1262 .owner = THIS_MODULE,
1263 },
1264 .probe = wm8900_spi_probe,
1265 .remove = __devexit_p(wm8900_spi_remove),
1266};
1267#endif /* CONFIG_SPI_MASTER */
1268
1269#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1270static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1271 const struct i2c_device_id *id)
1272{
1273 struct wm8900_priv *wm8900;
1274 int ret;
1275
1276 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1277 if (wm8900 == NULL)
1278 return -ENOMEM;
1279
1280 i2c_set_clientdata(i2c, wm8900);
f0fba2ad 1281 wm8900->control_type = SND_SOC_I2C;
78e19a39 1282
f0fba2ad
LG		 1283 ret = snd_soc_register_codec(&i2c->dev,
1284 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1285 if (ret < 0)
1286 kfree(wm8900);
1287 return ret;
1288}
78e19a39 1289
f0fba2ad
LG		 1290static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1291{
1292 snd_soc_unregister_codec(&client->dev);
1293 kfree(i2c_get_clientdata(client));
0e0e16a8
MB		 1294 return 0;
1295}
1296
8ae6a552
JD		 1297static const struct i2c_device_id wm8900_i2c_id[] = {
1298 { "wm8900", 0 },
1299 { }
1300};
1301MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
0e0e16a8 1302
0e0e16a8
MB		 1303static struct i2c_driver wm8900_i2c_driver = {
1304 .driver = {
f0fba2ad 1305 .name = "wm8900-codec",
0e0e16a8
MB		 1306 .owner = THIS_MODULE,
1307 },
f0fba2ad
LG		 1308 .probe = wm8900_i2c_probe,
1309 .remove = __devexit_p(wm8900_i2c_remove),
8ae6a552 1310 .id_table = wm8900_i2c_id,
0e0e16a8 1311};
f0fba2ad 1312#endif
0e0e16a8 1313
f0fba2ad 1314static int __init wm8900_modinit(void)
0e0e16a8 1315{
0e0e16a8 1316 int ret = 0;
f0fba2ad
LG		 1317#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1318 ret = i2c_add_driver(&wm8900_i2c_driver);
1319 if (ret != 0) {
1320 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1321 ret);
f0752331 1322 }
f0fba2ad
LG		 1323#endif
1324#if defined(CONFIG_SPI_MASTER)
1325 ret = spi_register_driver(&wm8900_spi_driver);
1326 if (ret != 0) {
1327 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1328 ret);
78e19a39 1329 }
f0fba2ad 1330#endif
0e0e16a8
MB		 1331 return ret;
1332}
64089b84
MB		 1333module_init(wm8900_modinit);
1334
1335static void __exit wm8900_exit(void)
1336{
f0fba2ad 1337#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
f0752331 1338 i2c_del_driver(&wm8900_i2c_driver);
f0fba2ad
LG		 1339#endif
1340#if defined(CONFIG_SPI_MASTER)
1341 spi_unregister_driver(&wm8900_spi_driver);
1342#endif
64089b84
MB		 1343}
1344module_exit(wm8900_exit);
1345
0e0e16a8
MB		 1346MODULE_DESCRIPTION("ASoC WM8900 driver");
1347MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1348MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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