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ASoC: Decouple DAPM from CODECs
[deliverable/linux.git] / sound / soc / codecs / wm8900.c
CommitLineData
0e0e16a8
MB		 1/*
2 * wm8900.c -- WM8900 ALSA Soc Audio driver
3 *
4 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - Tristating.
14 * - TDM.
15 * - Jack detect.
16 * - FLL source configuration, currently only MCLK is supported.
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
0e0e16a8
MB		 21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/delay.h>
24#include <linux/pm.h>
25#include <linux/i2c.h>
f0fba2ad 26#include <linux/spi/spi.h>
0e0e16a8 27#include <linux/platform_device.h>
5a0e3ad6 28#include <linux/slab.h>
0e0e16a8
MB		 29#include <sound/core.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
33#include <sound/soc-dapm.h>
34#include <sound/initval.h>
35#include <sound/tlv.h>
36
37#include "wm8900.h"
38
39/* WM8900 register space */
40#define WM8900_REG_RESET 0x0
41#define WM8900_REG_ID 0x0
42#define WM8900_REG_POWER1 0x1
43#define WM8900_REG_POWER2 0x2
44#define WM8900_REG_POWER3 0x3
45#define WM8900_REG_AUDIO1 0x4
46#define WM8900_REG_AUDIO2 0x5
47#define WM8900_REG_CLOCKING1 0x6
48#define WM8900_REG_CLOCKING2 0x7
49#define WM8900_REG_AUDIO3 0x8
50#define WM8900_REG_AUDIO4 0x9
51#define WM8900_REG_DACCTRL 0xa
52#define WM8900_REG_LDAC_DV 0xb
53#define WM8900_REG_RDAC_DV 0xc
54#define WM8900_REG_SIDETONE 0xd
55#define WM8900_REG_ADCCTRL 0xe
56#define WM8900_REG_LADC_DV 0xf
57#define WM8900_REG_RADC_DV 0x10
58#define WM8900_REG_GPIO 0x12
59#define WM8900_REG_INCTL 0x15
60#define WM8900_REG_LINVOL 0x16
61#define WM8900_REG_RINVOL 0x17
62#define WM8900_REG_INBOOSTMIX1 0x18
63#define WM8900_REG_INBOOSTMIX2 0x19
64#define WM8900_REG_ADCPATH 0x1a
65#define WM8900_REG_AUXBOOST 0x1b
66#define WM8900_REG_ADDCTL 0x1e
67#define WM8900_REG_FLLCTL1 0x24
68#define WM8900_REG_FLLCTL2 0x25
69#define WM8900_REG_FLLCTL3 0x26
70#define WM8900_REG_FLLCTL4 0x27
71#define WM8900_REG_FLLCTL5 0x28
72#define WM8900_REG_FLLCTL6 0x29
73#define WM8900_REG_LOUTMIXCTL1 0x2c
74#define WM8900_REG_ROUTMIXCTL1 0x2d
75#define WM8900_REG_BYPASS1 0x2e
76#define WM8900_REG_BYPASS2 0x2f
77#define WM8900_REG_AUXOUT_CTL 0x30
78#define WM8900_REG_LOUT1CTL 0x33
79#define WM8900_REG_ROUT1CTL 0x34
80#define WM8900_REG_LOUT2CTL 0x35
81#define WM8900_REG_ROUT2CTL 0x36
82#define WM8900_REG_HPCTL1 0x3a
83#define WM8900_REG_OUTBIASCTL 0x73
84
85#define WM8900_MAXREG 0x80
86
87#define WM8900_REG_ADDCTL_OUT1_DIS 0x80
88#define WM8900_REG_ADDCTL_OUT2_DIS 0x40
89#define WM8900_REG_ADDCTL_VMID_DIS 0x20
90#define WM8900_REG_ADDCTL_BIAS_SRC 0x10
91#define WM8900_REG_ADDCTL_VMID_SOFTST 0x04
92#define WM8900_REG_ADDCTL_TEMP_SD 0x02
93
94#define WM8900_REG_GPIO_TEMP_ENA 0x2
95
96#define WM8900_REG_POWER1_STARTUP_BIAS_ENA 0x0100
97#define WM8900_REG_POWER1_BIAS_ENA 0x0008
98#define WM8900_REG_POWER1_VMID_BUF_ENA 0x0004
99#define WM8900_REG_POWER1_FLL_ENA 0x0040
100
101#define WM8900_REG_POWER2_SYSCLK_ENA 0x8000
102#define WM8900_REG_POWER2_ADCL_ENA 0x0002
103#define WM8900_REG_POWER2_ADCR_ENA 0x0001
104
105#define WM8900_REG_POWER3_DACL_ENA 0x0002
106#define WM8900_REG_POWER3_DACR_ENA 0x0001
107
108#define WM8900_REG_AUDIO1_AIF_FMT_MASK 0x0018
109#define WM8900_REG_AUDIO1_LRCLK_INV 0x0080
110#define WM8900_REG_AUDIO1_BCLK_INV 0x0100
111
112#define WM8900_REG_CLOCKING1_BCLK_DIR 0x1
113#define WM8900_REG_CLOCKING1_MCLK_SRC 0x100
114#define WM8900_REG_CLOCKING1_BCLK_MASK (~0x01e)
115#define WM8900_REG_CLOCKING1_OPCLK_MASK (~0x7000)
116
117#define WM8900_REG_CLOCKING2_ADC_CLKDIV 0xe0
118#define WM8900_REG_CLOCKING2_DAC_CLKDIV 0x1c
119
120#define WM8900_REG_DACCTRL_MUTE 0x004
21002e20 121#define WM8900_REG_DACCTRL_DAC_SB_FILT 0x100
0e0e16a8
MB		 122#define WM8900_REG_DACCTRL_AIF_LRCLKRATE 0x400
123
124#define WM8900_REG_AUDIO3_ADCLRC_DIR 0x0800
125
126#define WM8900_REG_AUDIO4_DACLRC_DIR 0x0800
127
128#define WM8900_REG_FLLCTL1_OSC_ENA 0x100
129
130#define WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF 0x100
131
132#define WM8900_REG_HPCTL1_HP_IPSTAGE_ENA 0x80
133#define WM8900_REG_HPCTL1_HP_OPSTAGE_ENA 0x40
134#define WM8900_REG_HPCTL1_HP_CLAMP_IP 0x20
135#define WM8900_REG_HPCTL1_HP_CLAMP_OP 0x10
136#define WM8900_REG_HPCTL1_HP_SHORT 0x08
137#define WM8900_REG_HPCTL1_HP_SHORT2 0x04
138
139#define WM8900_LRC_MASK 0xfc00
140
0e0e16a8 141struct wm8900_priv {
f0fba2ad 142 enum snd_soc_control_type control_type;
78e19a39
MB		 143 u16 reg_cache[WM8900_MAXREG];
144
0e0e16a8
MB		 145 u32 fll_in; /* FLL input frequency */
146 u32 fll_out; /* FLL output frequency */
147};
148
149/*
150 * wm8900 register cache. We can't read the entire register space and we
151 * have slow control buses so we cache the registers.
152 */
153static const u16 wm8900_reg_defaults[WM8900_MAXREG] = {
154 0x8900, 0x0000,
155 0xc000, 0x0000,
156 0x4050, 0x4000,
157 0x0008, 0x0000,
158 0x0040, 0x0040,
159 0x1004, 0x00c0,
160 0x00c0, 0x0000,
161 0x0100, 0x00c0,
162 0x00c0, 0x0000,
163 0xb001, 0x0000,
164 0x0000, 0x0044,
165 0x004c, 0x004c,
166 0x0044, 0x0044,
167 0x0000, 0x0044,
168 0x0000, 0x0000,
169 0x0002, 0x0000,
170 0x0000, 0x0000,
171 0x0000, 0x0000,
172 0x0008, 0x0000,
173 0x0000, 0x0008,
174 0x0097, 0x0100,
175 0x0000, 0x0000,
176 0x0050, 0x0050,
177 0x0055, 0x0055,
178 0x0055, 0x0000,
179 0x0000, 0x0079,
180 0x0079, 0x0079,
181 0x0079, 0x0000,
182 /* Remaining registers all zero */
183};
184
8d50e447 185static int wm8900_volatile_register(unsigned int reg)
0e0e16a8
MB		 186{
187 switch (reg) {
188 case WM8900_REG_ID:
8d50e447 189 return 1;
0e0e16a8 190 default:
8d50e447 191 return 0;
0e0e16a8
MB		 192 }
193}
194
195static void wm8900_reset(struct snd_soc_codec *codec)
196{
8d50e447 197 snd_soc_write(codec, WM8900_REG_RESET, 0);
0e0e16a8
MB		 198
199 memcpy(codec->reg_cache, wm8900_reg_defaults,
bc258006 200 sizeof(wm8900_reg_defaults));
0e0e16a8
MB		 201}
202
203static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
204 struct snd_kcontrol *kcontrol, int event)
205{
206 struct snd_soc_codec *codec = w->codec;
8d50e447 207 u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
0e0e16a8
MB		 208
209 switch (event) {
210 case SND_SOC_DAPM_PRE_PMU:
211 /* Clamp headphone outputs */
212 hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
213 WM8900_REG_HPCTL1_HP_CLAMP_OP;
8d50e447 214 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 215 break;
216
217 case SND_SOC_DAPM_POST_PMU:
218 /* Enable the input stage */
219 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_IP;
220 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
221 WM8900_REG_HPCTL1_HP_SHORT2 |
222 WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 223 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 224
225 msleep(400);
226
227 /* Enable the output stage */
228 hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
229 hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 230 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 231
232 /* Remove the shorts */
233 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
8d50e447 234 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8 235 hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 236 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 237 break;
238
239 case SND_SOC_DAPM_PRE_PMD:
240 /* Short the output */
241 hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
8d50e447 242 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 243
244 /* Disable the output stage */
245 hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
8d50e447 246 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 247
248 /* Clamp the outputs and power down input */
249 hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
250 WM8900_REG_HPCTL1_HP_CLAMP_OP;
251 hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
8d50e447 252 snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
0e0e16a8
MB		 253 break;
254
255 case SND_SOC_DAPM_POST_PMD:
256 /* Disable everything */
8d50e447 257 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 258 break;
259
260 default:
261 BUG();
262 }
263
264 return 0;
265}
266
267static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 100, 0);
268
269static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 0);
270
271static const DECLARE_TLV_DB_SCALE(in_boost_tlv, -1200, 600, 0);
272
273static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1200, 100, 0);
274
275static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
276
277static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
278
279static const DECLARE_TLV_DB_SCALE(adc_svol_tlv, -3600, 300, 0);
280
281static const DECLARE_TLV_DB_SCALE(adc_tlv, -7200, 75, 1);
282
283static const char *mic_bias_level_txt[] = { "0.9*AVDD", "0.65*AVDD" };
284
285static const struct soc_enum mic_bias_level =
286SOC_ENUM_SINGLE(WM8900_REG_INCTL, 8, 2, mic_bias_level_txt);
287
288static const char *dac_mute_rate_txt[] = { "Fast", "Slow" };
289
290static const struct soc_enum dac_mute_rate =
291SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 7, 2, dac_mute_rate_txt);
292
293static const char *dac_deemphasis_txt[] = {
294 "Disabled", "32kHz", "44.1kHz", "48kHz"
295};
296
297static const struct soc_enum dac_deemphasis =
298SOC_ENUM_SINGLE(WM8900_REG_DACCTRL, 4, 4, dac_deemphasis_txt);
299
300static const char *adc_hpf_cut_txt[] = {
301 "Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"
302};
303
304static const struct soc_enum adc_hpf_cut =
305SOC_ENUM_SINGLE(WM8900_REG_ADCCTRL, 5, 4, adc_hpf_cut_txt);
306
307static const char *lr_txt[] = {
308 "Left", "Right"
309};
310
311static const struct soc_enum aifl_src =
312SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 15, 2, lr_txt);
313
314static const struct soc_enum aifr_src =
315SOC_ENUM_SINGLE(WM8900_REG_AUDIO1, 14, 2, lr_txt);
316
317static const struct soc_enum dacl_src =
318SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 15, 2, lr_txt);
319
320static const struct soc_enum dacr_src =
321SOC_ENUM_SINGLE(WM8900_REG_AUDIO2, 14, 2, lr_txt);
322
323static const char *sidetone_txt[] = {
324 "Disabled", "Left ADC", "Right ADC"
325};
326
327static const struct soc_enum dacl_sidetone =
328SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 2, 3, sidetone_txt);
329
330static const struct soc_enum dacr_sidetone =
331SOC_ENUM_SINGLE(WM8900_REG_SIDETONE, 0, 3, sidetone_txt);
332
333static const struct snd_kcontrol_new wm8900_snd_controls[] = {
334SOC_ENUM("Mic Bias Level", mic_bias_level),
335
336SOC_SINGLE_TLV("Left Input PGA Volume", WM8900_REG_LINVOL, 0, 31, 0,
337 in_pga_tlv),
338SOC_SINGLE("Left Input PGA Switch", WM8900_REG_LINVOL, 6, 1, 1),
339SOC_SINGLE("Left Input PGA ZC Switch", WM8900_REG_LINVOL, 7, 1, 0),
340
341SOC_SINGLE_TLV("Right Input PGA Volume", WM8900_REG_RINVOL, 0, 31, 0,
342 in_pga_tlv),
343SOC_SINGLE("Right Input PGA Switch", WM8900_REG_RINVOL, 6, 1, 1),
344SOC_SINGLE("Right Input PGA ZC Switch", WM8900_REG_RINVOL, 7, 1, 0),
345
346SOC_SINGLE("DAC Soft Mute Switch", WM8900_REG_DACCTRL, 6, 1, 1),
347SOC_ENUM("DAC Mute Rate", dac_mute_rate),
348SOC_SINGLE("DAC Mono Switch", WM8900_REG_DACCTRL, 9, 1, 0),
349SOC_ENUM("DAC Deemphasis", dac_deemphasis),
0e0e16a8
MB		 350SOC_SINGLE("DAC Sigma-Delta Modulator Clock Switch", WM8900_REG_DACCTRL,
351 12, 1, 0),
352
353SOC_SINGLE("ADC HPF Switch", WM8900_REG_ADCCTRL, 8, 1, 0),
354SOC_ENUM("ADC HPF Cut-Off", adc_hpf_cut),
355SOC_DOUBLE("ADC Invert Switch", WM8900_REG_ADCCTRL, 1, 0, 1, 0),
356SOC_SINGLE_TLV("Left ADC Sidetone Volume", WM8900_REG_SIDETONE, 9, 12, 0,
357 adc_svol_tlv),
358SOC_SINGLE_TLV("Right ADC Sidetone Volume", WM8900_REG_SIDETONE, 5, 12, 0,
359 adc_svol_tlv),
360SOC_ENUM("Left Digital Audio Source", aifl_src),
361SOC_ENUM("Right Digital Audio Source", aifr_src),
362
363SOC_SINGLE_TLV("DAC Input Boost Volume", WM8900_REG_AUDIO2, 10, 4, 0,
364 dac_boost_tlv),
365SOC_ENUM("Left DAC Source", dacl_src),
366SOC_ENUM("Right DAC Source", dacr_src),
367SOC_ENUM("Left DAC Sidetone", dacl_sidetone),
368SOC_ENUM("Right DAC Sidetone", dacr_sidetone),
369SOC_DOUBLE("DAC Invert Switch", WM8900_REG_DACCTRL, 1, 0, 1, 0),
370
371SOC_DOUBLE_R_TLV("Digital Playback Volume",
372 WM8900_REG_LDAC_DV, WM8900_REG_RDAC_DV,
373 1, 96, 0, dac_tlv),
374SOC_DOUBLE_R_TLV("Digital Capture Volume",
375 WM8900_REG_LADC_DV, WM8900_REG_RADC_DV, 1, 119, 0, adc_tlv),
376
377SOC_SINGLE_TLV("LINPUT3 Bypass Volume", WM8900_REG_LOUTMIXCTL1, 4, 7, 0,
378 out_mix_tlv),
379SOC_SINGLE_TLV("RINPUT3 Bypass Volume", WM8900_REG_ROUTMIXCTL1, 4, 7, 0,
380 out_mix_tlv),
381SOC_SINGLE_TLV("Left AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 4, 7, 0,
382 out_mix_tlv),
383SOC_SINGLE_TLV("Right AUX Bypass Volume", WM8900_REG_AUXOUT_CTL, 0, 7, 0,
384 out_mix_tlv),
385
386SOC_SINGLE_TLV("LeftIn to RightOut Mixer Volume", WM8900_REG_BYPASS1, 0, 7, 0,
387 out_mix_tlv),
388SOC_SINGLE_TLV("LeftIn to LeftOut Mixer Volume", WM8900_REG_BYPASS1, 4, 7, 0,
389 out_mix_tlv),
390SOC_SINGLE_TLV("RightIn to LeftOut Mixer Volume", WM8900_REG_BYPASS2, 0, 7, 0,
391 out_mix_tlv),
392SOC_SINGLE_TLV("RightIn to RightOut Mixer Volume", WM8900_REG_BYPASS2, 4, 7, 0,
393 out_mix_tlv),
394
395SOC_SINGLE_TLV("IN2L Boost Volume", WM8900_REG_INBOOSTMIX1, 0, 3, 0,
396 in_boost_tlv),
397SOC_SINGLE_TLV("IN3L Boost Volume", WM8900_REG_INBOOSTMIX1, 4, 3, 0,
398 in_boost_tlv),
399SOC_SINGLE_TLV("IN2R Boost Volume", WM8900_REG_INBOOSTMIX2, 0, 3, 0,
400 in_boost_tlv),
401SOC_SINGLE_TLV("IN3R Boost Volume", WM8900_REG_INBOOSTMIX2, 4, 3, 0,
402 in_boost_tlv),
403SOC_SINGLE_TLV("Left AUX Boost Volume", WM8900_REG_AUXBOOST, 4, 3, 0,
404 in_boost_tlv),
405SOC_SINGLE_TLV("Right AUX Boost Volume", WM8900_REG_AUXBOOST, 0, 3, 0,
406 in_boost_tlv),
407
408SOC_DOUBLE_R_TLV("LINEOUT1 Volume", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
409 0, 63, 0, out_pga_tlv),
410SOC_DOUBLE_R("LINEOUT1 Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
411 6, 1, 1),
412SOC_DOUBLE_R("LINEOUT1 ZC Switch", WM8900_REG_LOUT1CTL, WM8900_REG_ROUT1CTL,
413 7, 1, 0),
414
415SOC_DOUBLE_R_TLV("LINEOUT2 Volume",
416 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL,
417 0, 63, 0, out_pga_tlv),
418SOC_DOUBLE_R("LINEOUT2 Switch",
419 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 6, 1, 1),
420SOC_DOUBLE_R("LINEOUT2 ZC Switch",
421 WM8900_REG_LOUT2CTL, WM8900_REG_ROUT2CTL, 7, 1, 0),
422SOC_SINGLE("LINEOUT2 LP -12dB", WM8900_REG_LOUTMIXCTL1,
423 0, 1, 1),
424
425};
426
0e0e16a8
MB		 427static const struct snd_kcontrol_new wm8900_dapm_loutput2_control =
428SOC_DAPM_SINGLE("LINEOUT2L Switch", WM8900_REG_POWER3, 6, 1, 0);
429
430static const struct snd_kcontrol_new wm8900_dapm_routput2_control =
431SOC_DAPM_SINGLE("LINEOUT2R Switch", WM8900_REG_POWER3, 5, 1, 0);
432
433static const struct snd_kcontrol_new wm8900_loutmix_controls[] = {
434SOC_DAPM_SINGLE("LINPUT3 Bypass Switch", WM8900_REG_LOUTMIXCTL1, 7, 1, 0),
435SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 7, 1, 0),
436SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 7, 1, 0),
437SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 3, 1, 0),
438SOC_DAPM_SINGLE("DACL Switch", WM8900_REG_LOUTMIXCTL1, 8, 1, 0),
439};
440
441static const struct snd_kcontrol_new wm8900_routmix_controls[] = {
442SOC_DAPM_SINGLE("RINPUT3 Bypass Switch", WM8900_REG_ROUTMIXCTL1, 7, 1, 0),
443SOC_DAPM_SINGLE("AUX Bypass Switch", WM8900_REG_AUXOUT_CTL, 3, 1, 0),
444SOC_DAPM_SINGLE("Left Input Mixer Switch", WM8900_REG_BYPASS1, 3, 1, 0),
445SOC_DAPM_SINGLE("Right Input Mixer Switch", WM8900_REG_BYPASS2, 7, 1, 0),
446SOC_DAPM_SINGLE("DACR Switch", WM8900_REG_ROUTMIXCTL1, 8, 1, 0),
447};
448
449static const struct snd_kcontrol_new wm8900_linmix_controls[] = {
450SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INBOOSTMIX1, 2, 1, 1),
451SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INBOOSTMIX1, 6, 1, 1),
452SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 6, 1, 1),
453SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 6, 1, 0),
454};
455
456static const struct snd_kcontrol_new wm8900_rinmix_controls[] = {
457SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INBOOSTMIX2, 2, 1, 1),
458SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INBOOSTMIX2, 6, 1, 1),
459SOC_DAPM_SINGLE("AUX Switch", WM8900_REG_AUXBOOST, 2, 1, 1),
460SOC_DAPM_SINGLE("Input PGA Switch", WM8900_REG_ADCPATH, 2, 1, 0),
461};
462
463static const struct snd_kcontrol_new wm8900_linpga_controls[] = {
464SOC_DAPM_SINGLE("LINPUT1 Switch", WM8900_REG_INCTL, 6, 1, 0),
465SOC_DAPM_SINGLE("LINPUT2 Switch", WM8900_REG_INCTL, 5, 1, 0),
466SOC_DAPM_SINGLE("LINPUT3 Switch", WM8900_REG_INCTL, 4, 1, 0),
467};
468
469static const struct snd_kcontrol_new wm8900_rinpga_controls[] = {
470SOC_DAPM_SINGLE("RINPUT1 Switch", WM8900_REG_INCTL, 2, 1, 0),
471SOC_DAPM_SINGLE("RINPUT2 Switch", WM8900_REG_INCTL, 1, 1, 0),
472SOC_DAPM_SINGLE("RINPUT3 Switch", WM8900_REG_INCTL, 0, 1, 0),
473};
474
475static const char *wm9700_lp_mux[] = { "Disabled", "Enabled" };
476
477static const struct soc_enum wm8900_lineout2_lp_mux =
478SOC_ENUM_SINGLE(WM8900_REG_LOUTMIXCTL1, 1, 2, wm9700_lp_mux);
479
480static const struct snd_kcontrol_new wm8900_lineout2_lp =
481SOC_DAPM_ENUM("Route", wm8900_lineout2_lp_mux);
482
483static const struct snd_soc_dapm_widget wm8900_dapm_widgets[] = {
484
485/* Externally visible pins */
486SND_SOC_DAPM_OUTPUT("LINEOUT1L"),
487SND_SOC_DAPM_OUTPUT("LINEOUT1R"),
488SND_SOC_DAPM_OUTPUT("LINEOUT2L"),
489SND_SOC_DAPM_OUTPUT("LINEOUT2R"),
490SND_SOC_DAPM_OUTPUT("HP_L"),
491SND_SOC_DAPM_OUTPUT("HP_R"),
492
493SND_SOC_DAPM_INPUT("RINPUT1"),
494SND_SOC_DAPM_INPUT("LINPUT1"),
495SND_SOC_DAPM_INPUT("RINPUT2"),
496SND_SOC_DAPM_INPUT("LINPUT2"),
497SND_SOC_DAPM_INPUT("RINPUT3"),
498SND_SOC_DAPM_INPUT("LINPUT3"),
499SND_SOC_DAPM_INPUT("AUX"),
500
501SND_SOC_DAPM_VMID("VMID"),
502
503/* Input */
504SND_SOC_DAPM_MIXER("Left Input PGA", WM8900_REG_POWER2, 3, 0,
505 wm8900_linpga_controls,
506 ARRAY_SIZE(wm8900_linpga_controls)),
507SND_SOC_DAPM_MIXER("Right Input PGA", WM8900_REG_POWER2, 2, 0,
508 wm8900_rinpga_controls,
509 ARRAY_SIZE(wm8900_rinpga_controls)),
510
511SND_SOC_DAPM_MIXER("Left Input Mixer", WM8900_REG_POWER2, 5, 0,
512 wm8900_linmix_controls,
513 ARRAY_SIZE(wm8900_linmix_controls)),
514SND_SOC_DAPM_MIXER("Right Input Mixer", WM8900_REG_POWER2, 4, 0,
515 wm8900_rinmix_controls,
516 ARRAY_SIZE(wm8900_rinmix_controls)),
517
518SND_SOC_DAPM_MICBIAS("Mic Bias", WM8900_REG_POWER1, 4, 0),
519
520SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8900_REG_POWER2, 1, 0),
521SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
522
523/* Output */
524SND_SOC_DAPM_DAC("DACL", "Left HiFi Playback", WM8900_REG_POWER3, 1, 0),
525SND_SOC_DAPM_DAC("DACR", "Right HiFi Playback", WM8900_REG_POWER3, 0, 0),
526
527SND_SOC_DAPM_PGA_E("Headphone Amplifier", WM8900_REG_POWER3, 7, 0, NULL, 0,
528 wm8900_hp_event,
529 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
530 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
531
532SND_SOC_DAPM_PGA("LINEOUT1L PGA", WM8900_REG_POWER2, 8, 0, NULL, 0),
533SND_SOC_DAPM_PGA("LINEOUT1R PGA", WM8900_REG_POWER2, 7, 0, NULL, 0),
534
535SND_SOC_DAPM_MUX("LINEOUT2 LP", SND_SOC_NOPM, 0, 0, &wm8900_lineout2_lp),
536SND_SOC_DAPM_PGA("LINEOUT2L PGA", WM8900_REG_POWER3, 6, 0, NULL, 0),
537SND_SOC_DAPM_PGA("LINEOUT2R PGA", WM8900_REG_POWER3, 5, 0, NULL, 0),
538
539SND_SOC_DAPM_MIXER("Left Output Mixer", WM8900_REG_POWER3, 3, 0,
540 wm8900_loutmix_controls,
541 ARRAY_SIZE(wm8900_loutmix_controls)),
542SND_SOC_DAPM_MIXER("Right Output Mixer", WM8900_REG_POWER3, 2, 0,
543 wm8900_routmix_controls,
544 ARRAY_SIZE(wm8900_routmix_controls)),
545};
546
547/* Target, Path, Source */
548static const struct snd_soc_dapm_route audio_map[] = {
549/* Inputs */
550{"Left Input PGA", "LINPUT1 Switch", "LINPUT1"},
551{"Left Input PGA", "LINPUT2 Switch", "LINPUT2"},
552{"Left Input PGA", "LINPUT3 Switch", "LINPUT3"},
553
554{"Right Input PGA", "RINPUT1 Switch", "RINPUT1"},
555{"Right Input PGA", "RINPUT2 Switch", "RINPUT2"},
556{"Right Input PGA", "RINPUT3 Switch", "RINPUT3"},
557
558{"Left Input Mixer", "LINPUT2 Switch", "LINPUT2"},
559{"Left Input Mixer", "LINPUT3 Switch", "LINPUT3"},
560{"Left Input Mixer", "AUX Switch", "AUX"},
561{"Left Input Mixer", "Input PGA Switch", "Left Input PGA"},
562
563{"Right Input Mixer", "RINPUT2 Switch", "RINPUT2"},
564{"Right Input Mixer", "RINPUT3 Switch", "RINPUT3"},
565{"Right Input Mixer", "AUX Switch", "AUX"},
566{"Right Input Mixer", "Input PGA Switch", "Right Input PGA"},
567
568{"ADCL", NULL, "Left Input Mixer"},
569{"ADCR", NULL, "Right Input Mixer"},
570
571/* Outputs */
572{"LINEOUT1L", NULL, "LINEOUT1L PGA"},
573{"LINEOUT1L PGA", NULL, "Left Output Mixer"},
574{"LINEOUT1R", NULL, "LINEOUT1R PGA"},
575{"LINEOUT1R PGA", NULL, "Right Output Mixer"},
576
577{"LINEOUT2L PGA", NULL, "Left Output Mixer"},
578{"LINEOUT2 LP", "Disabled", "LINEOUT2L PGA"},
579{"LINEOUT2 LP", "Enabled", "Left Output Mixer"},
580{"LINEOUT2L", NULL, "LINEOUT2 LP"},
581
582{"LINEOUT2R PGA", NULL, "Right Output Mixer"},
583{"LINEOUT2 LP", "Disabled", "LINEOUT2R PGA"},
584{"LINEOUT2 LP", "Enabled", "Right Output Mixer"},
585{"LINEOUT2R", NULL, "LINEOUT2 LP"},
586
587{"Left Output Mixer", "LINPUT3 Bypass Switch", "LINPUT3"},
588{"Left Output Mixer", "AUX Bypass Switch", "AUX"},
589{"Left Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
590{"Left Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
591{"Left Output Mixer", "DACL Switch", "DACL"},
592
593{"Right Output Mixer", "RINPUT3 Bypass Switch", "RINPUT3"},
594{"Right Output Mixer", "AUX Bypass Switch", "AUX"},
595{"Right Output Mixer", "Left Input Mixer Switch", "Left Input Mixer"},
596{"Right Output Mixer", "Right Input Mixer Switch", "Right Input Mixer"},
597{"Right Output Mixer", "DACR Switch", "DACR"},
598
599/* Note that the headphone output stage needs to be connected
600 * externally to LINEOUT2 via DC blocking capacitors. Other
601 * configurations are not supported.
602 *
603 * Note also that left and right headphone paths are treated as a
604 * mono path.
605 */
606{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
607{"Headphone Amplifier", NULL, "LINEOUT2 LP"},
608{"HP_L", NULL, "Headphone Amplifier"},
609{"HP_R", NULL, "Headphone Amplifier"},
610};
611
612static int wm8900_add_widgets(struct snd_soc_codec *codec)
613{
ce6120cc 614 struct snd_soc_dapm_context *dapm = &codec->dapm;
0e0e16a8 615
ce6120cc
LG		 616 snd_soc_dapm_new_controls(dapm, wm8900_dapm_widgets,
617 ARRAY_SIZE(wm8900_dapm_widgets));
618 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
0e0e16a8 619
0e0e16a8
MB		 620 return 0;
621}
622
623static int wm8900_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 624 struct snd_pcm_hw_params *params,
625 struct snd_soc_dai *dai)
0e0e16a8
MB		 626{
627 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 628 struct snd_soc_codec *codec = rtd->codec;
0e0e16a8
MB		 629 u16 reg;
630
8d50e447 631 reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
0e0e16a8
MB		 632
633 switch (params_format(params)) {
634 case SNDRV_PCM_FORMAT_S16_LE:
635 break;
636 case SNDRV_PCM_FORMAT_S20_3LE:
637 reg |= 0x20;
638 break;
639 case SNDRV_PCM_FORMAT_S24_LE:
640 reg |= 0x40;
641 break;
642 case SNDRV_PCM_FORMAT_S32_LE:
643 reg |= 0x60;
644 break;
645 default:
646 return -EINVAL;
647 }
648
8d50e447 649 snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
0e0e16a8 650
21002e20 651 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
8d50e447 652 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
21002e20
MB		 653
654 if (params_rate(params) <= 24000)
655 reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
656 else
657 reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
658
8d50e447 659 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
21002e20
MB		 660 }
661
0e0e16a8
MB		 662 return 0;
663}
664
665/* FLL divisors */
666struct _fll_div {
667 u16 fll_ratio;
668 u16 fllclk_div;
669 u16 fll_slow_lock_ref;
670 u16 n;
671 u16 k;
672};
673
674/* The size in bits of the FLL divide multiplied by 10
675 * to allow rounding later */
676#define FIXED_FLL_SIZE ((1 << 16) * 10)
677
678static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
679 unsigned int Fout)
680{
681 u64 Kpart;
682 unsigned int K, Ndiv, Nmod, target;
683 unsigned int div;
684
685 BUG_ON(!Fout);
686
687 /* The FLL must run at 90-100MHz which is then scaled down to
688 * the output value by FLLCLK_DIV. */
689 target = Fout;
690 div = 1;
691 while (target < 90000000) {
692 div *= 2;
693 target *= 2;
694 }
695
696 if (target > 100000000)
449bd54d
RK		 697 printk(KERN_WARNING "wm8900: FLL rate %u out of range, Fref=%u"
698 " Fout=%u\n", target, Fref, Fout);
0e0e16a8
MB		 699 if (div > 32) {
700 printk(KERN_ERR "wm8900: Invalid FLL division rate %u, "
449bd54d 701 "Fref=%u, Fout=%u, target=%u\n",
0e0e16a8
MB		 702 div, Fref, Fout, target);
703 return -EINVAL;
704 }
705
706 fll_div->fllclk_div = div >> 2;
707
708 if (Fref < 48000)
709 fll_div->fll_slow_lock_ref = 1;
710 else
711 fll_div->fll_slow_lock_ref = 0;
712
713 Ndiv = target / Fref;
714
715 if (Fref < 1000000)
716 fll_div->fll_ratio = 8;
717 else
718 fll_div->fll_ratio = 1;
719
720 fll_div->n = Ndiv / fll_div->fll_ratio;
721 Nmod = (target / fll_div->fll_ratio) % Fref;
722
723 /* Calculate fractional part - scale up so we can round. */
724 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
725
726 do_div(Kpart, Fref);
727
728 K = Kpart & 0xFFFFFFFF;
729
730 if ((K % 10) >= 5)
731 K += 5;
732
733 /* Move down to proper range now rounding is done */
734 fll_div->k = K / 10;
735
736 BUG_ON(target != Fout * (fll_div->fllclk_div << 2));
737 BUG_ON(!K && target != Fref * fll_div->fll_ratio * fll_div->n);
738
739 return 0;
740}
741
742static int wm8900_set_fll(struct snd_soc_codec *codec,
743 int fll_id, unsigned int freq_in, unsigned int freq_out)
744{
b2c812e2 745 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 746 struct _fll_div fll_div;
747 unsigned int reg;
748
749 if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
750 return 0;
751
752 /* The digital side should be disabled during any change. */
8d50e447
MB		 753 reg = snd_soc_read(codec, WM8900_REG_POWER1);
754 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 755 reg & (~WM8900_REG_POWER1_FLL_ENA));
756
757 /* Disable the FLL? */
758 if (!freq_in || !freq_out) {
8d50e447
MB		 759 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
760 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 761 reg & (~WM8900_REG_CLOCKING1_MCLK_SRC));
762
8d50e447
MB		 763 reg = snd_soc_read(codec, WM8900_REG_FLLCTL1);
764 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 765 reg & (~WM8900_REG_FLLCTL1_OSC_ENA));
766
767 wm8900->fll_in = freq_in;
768 wm8900->fll_out = freq_out;
769
770 return 0;
771 }
772
773 if (fll_factors(&fll_div, freq_in, freq_out) != 0)
774 goto reenable;
775
776 wm8900->fll_in = freq_in;
777 wm8900->fll_out = freq_out;
778
779 /* The osclilator *MUST* be enabled before we enable the
780 * digital circuit. */
8d50e447 781 snd_soc_write(codec, WM8900_REG_FLLCTL1,
0e0e16a8
MB		 782 fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
783
8d50e447
MB		 784 snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
785 snd_soc_write(codec, WM8900_REG_FLLCTL5,
0e0e16a8
MB		 786 (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
787
788 if (fll_div.k) {
8d50e447 789 snd_soc_write(codec, WM8900_REG_FLLCTL2,
0e0e16a8 790 (fll_div.k >> 8) | 0x100);
8d50e447 791 snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
0e0e16a8 792 } else
8d50e447 793 snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
0e0e16a8
MB		 794
795 if (fll_div.fll_slow_lock_ref)
8d50e447 796 snd_soc_write(codec, WM8900_REG_FLLCTL6,
0e0e16a8
MB		 797 WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
798 else
8d50e447 799 snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
0e0e16a8 800
8d50e447
MB		 801 reg = snd_soc_read(codec, WM8900_REG_POWER1);
802 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 803 reg | WM8900_REG_POWER1_FLL_ENA);
804
805reenable:
8d50e447
MB		 806 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
807 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 808 reg | WM8900_REG_CLOCKING1_MCLK_SRC);
809
810 return 0;
811}
812
85488037
MB		 813static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
814 int source, unsigned int freq_in, unsigned int freq_out)
0e0e16a8
MB		 815{
816 return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
817}
818
819static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
820 int div_id, int div)
821{
822 struct snd_soc_codec *codec = codec_dai->codec;
823 unsigned int reg;
824
825 switch (div_id) {
826 case WM8900_BCLK_DIV:
8d50e447
MB		 827 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
828 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 829 div | (reg & WM8900_REG_CLOCKING1_BCLK_MASK));
830 break;
831 case WM8900_OPCLK_DIV:
8d50e447
MB		 832 reg = snd_soc_read(codec, WM8900_REG_CLOCKING1);
833 snd_soc_write(codec, WM8900_REG_CLOCKING1,
0e0e16a8
MB		 834 div | (reg & WM8900_REG_CLOCKING1_OPCLK_MASK));
835 break;
836 case WM8900_DAC_LRCLK:
8d50e447
MB		 837 reg = snd_soc_read(codec, WM8900_REG_AUDIO4);
838 snd_soc_write(codec, WM8900_REG_AUDIO4,
0e0e16a8
MB		 839 div | (reg & WM8900_LRC_MASK));
840 break;
841 case WM8900_ADC_LRCLK:
8d50e447
MB		 842 reg = snd_soc_read(codec, WM8900_REG_AUDIO3);
843 snd_soc_write(codec, WM8900_REG_AUDIO3,
0e0e16a8
MB		 844 div | (reg & WM8900_LRC_MASK));
845 break;
846 case WM8900_DAC_CLKDIV:
8d50e447
MB		 847 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
848 snd_soc_write(codec, WM8900_REG_CLOCKING2,
0e0e16a8
MB		 849 div | (reg & WM8900_REG_CLOCKING2_DAC_CLKDIV));
850 break;
851 case WM8900_ADC_CLKDIV:
8d50e447
MB		 852 reg = snd_soc_read(codec, WM8900_REG_CLOCKING2);
853 snd_soc_write(codec, WM8900_REG_CLOCKING2,
0e0e16a8
MB		 854 div | (reg & WM8900_REG_CLOCKING2_ADC_CLKDIV));
855 break;
856 case WM8900_LRCLK_MODE:
8d50e447
MB		 857 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
858 snd_soc_write(codec, WM8900_REG_DACCTRL,
0e0e16a8
MB		 859 div | (reg & WM8900_REG_DACCTRL_AIF_LRCLKRATE));
860 break;
861 default:
862 return -EINVAL;
863 }
864
865 return 0;
866}
867
868
869static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
870 unsigned int fmt)
871{
872 struct snd_soc_codec *codec = codec_dai->codec;
873 unsigned int clocking1, aif1, aif3, aif4;
874
8d50e447
MB		 875 clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
876 aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
877 aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
878 aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
0e0e16a8
MB		 879
880 /* set master/slave audio interface */
881 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
882 case SND_SOC_DAIFMT_CBS_CFS:
883 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
884 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
885 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
886 break;
887 case SND_SOC_DAIFMT_CBS_CFM:
888 clocking1 &= ~WM8900_REG_CLOCKING1_BCLK_DIR;
889 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
890 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
891 break;
892 case SND_SOC_DAIFMT_CBM_CFM:
893 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
894 aif3 |= WM8900_REG_AUDIO3_ADCLRC_DIR;
895 aif4 |= WM8900_REG_AUDIO4_DACLRC_DIR;
896 break;
897 case SND_SOC_DAIFMT_CBM_CFS:
898 clocking1 |= WM8900_REG_CLOCKING1_BCLK_DIR;
899 aif3 &= ~WM8900_REG_AUDIO3_ADCLRC_DIR;
900 aif4 &= ~WM8900_REG_AUDIO4_DACLRC_DIR;
901 break;
902 default:
903 return -EINVAL;
904 }
905
906 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
907 case SND_SOC_DAIFMT_DSP_A:
908 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
909 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
910 break;
911 case SND_SOC_DAIFMT_DSP_B:
912 aif1 |= WM8900_REG_AUDIO1_AIF_FMT_MASK;
913 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
914 break;
915 case SND_SOC_DAIFMT_I2S:
916 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
917 aif1 |= 0x10;
918 break;
919 case SND_SOC_DAIFMT_RIGHT_J:
920 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
921 break;
922 case SND_SOC_DAIFMT_LEFT_J:
923 aif1 &= ~WM8900_REG_AUDIO1_AIF_FMT_MASK;
924 aif1 |= 0x8;
925 break;
926 default:
927 return -EINVAL;
928 }
929
930 /* Clock inversion */
931 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
932 case SND_SOC_DAIFMT_DSP_A:
933 case SND_SOC_DAIFMT_DSP_B:
934 /* frame inversion not valid for DSP modes */
935 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
936 case SND_SOC_DAIFMT_NB_NF:
937 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
938 break;
939 case SND_SOC_DAIFMT_IB_NF:
940 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
941 break;
942 default:
943 return -EINVAL;
944 }
945 break;
946 case SND_SOC_DAIFMT_I2S:
947 case SND_SOC_DAIFMT_RIGHT_J:
948 case SND_SOC_DAIFMT_LEFT_J:
949 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
950 case SND_SOC_DAIFMT_NB_NF:
951 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
952 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
953 break;
954 case SND_SOC_DAIFMT_IB_IF:
955 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
956 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
957 break;
958 case SND_SOC_DAIFMT_IB_NF:
959 aif1 |= WM8900_REG_AUDIO1_BCLK_INV;
960 aif1 &= ~WM8900_REG_AUDIO1_LRCLK_INV;
961 break;
962 case SND_SOC_DAIFMT_NB_IF:
963 aif1 &= ~WM8900_REG_AUDIO1_BCLK_INV;
964 aif1 |= WM8900_REG_AUDIO1_LRCLK_INV;
965 break;
966 default:
967 return -EINVAL;
968 }
969 break;
970 default:
971 return -EINVAL;
972 }
973
8d50e447
MB		 974 snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
975 snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
976 snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
977 snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
0e0e16a8
MB		 978
979 return 0;
980}
981
982static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
983{
984 struct snd_soc_codec *codec = codec_dai->codec;
985 u16 reg;
986
8d50e447 987 reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
0e0e16a8
MB		 988
989 if (mute)
990 reg |= WM8900_REG_DACCTRL_MUTE;
991 else
992 reg &= ~WM8900_REG_DACCTRL_MUTE;
993
8d50e447 994 snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
0e0e16a8
MB		 995
996 return 0;
997}
998
999#define WM8900_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
1000 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
1001 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
1002
1003#define WM8900_PCM_FORMATS \
1004 (SNDRV_PCM_FORMAT_S16_LE | SNDRV_PCM_FORMAT_S20_3LE | \
1005 SNDRV_PCM_FORMAT_S24_LE)
1006
6335d055
EM		 1007static struct snd_soc_dai_ops wm8900_dai_ops = {
1008 .hw_params = wm8900_hw_params,
1009 .set_clkdiv = wm8900_set_dai_clkdiv,
1010 .set_pll = wm8900_set_dai_pll,
1011 .set_fmt = wm8900_set_dai_fmt,
1012 .digital_mute = wm8900_digital_mute,
1013};
1014
f0fba2ad
LG		 1015static struct snd_soc_dai_driver wm8900_dai = {
1016 .name = "wm8900-hifi",
0e0e16a8
MB		 1017 .playback = {
1018 .stream_name = "HiFi Playback",
1019 .channels_min = 1,
1020 .channels_max = 2,
1021 .rates = WM8900_RATES,
1022 .formats = WM8900_PCM_FORMATS,
1023 },
1024 .capture = {
1025 .stream_name = "HiFi Capture",
1026 .channels_min = 1,
1027 .channels_max = 2,
1028 .rates = WM8900_RATES,
1029 .formats = WM8900_PCM_FORMATS,
1030 },
6335d055 1031 .ops = &wm8900_dai_ops,
0e0e16a8 1032};
0e0e16a8
MB		 1033
1034static int wm8900_set_bias_level(struct snd_soc_codec *codec,
1035 enum snd_soc_bias_level level)
1036{
1037 u16 reg;
1038
1039 switch (level) {
1040 case SND_SOC_BIAS_ON:
1041 /* Enable thermal shutdown */
8d50e447
MB		 1042 reg = snd_soc_read(codec, WM8900_REG_GPIO);
1043 snd_soc_write(codec, WM8900_REG_GPIO,
0e0e16a8 1044 reg | WM8900_REG_GPIO_TEMP_ENA);
8d50e447
MB		 1045 reg = snd_soc_read(codec, WM8900_REG_ADDCTL);
1046 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1047 reg | WM8900_REG_ADDCTL_TEMP_SD);
1048 break;
1049
1050 case SND_SOC_BIAS_PREPARE:
1051 break;
1052
1053 case SND_SOC_BIAS_STANDBY:
1054 /* Charge capacitors if initial power up */
ce6120cc 1055 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
0e0e16a8 1056 /* STARTUP_BIAS_ENA on */
8d50e447 1057 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1058 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1059
1060 /* Startup bias mode */
8d50e447 1061 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1062 WM8900_REG_ADDCTL_BIAS_SRC |
1063 WM8900_REG_ADDCTL_VMID_SOFTST);
1064
1065 /* VMID 2x50k */
8d50e447 1066 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1067 WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
1068
1069 /* Allow capacitors to charge */
1070 schedule_timeout_interruptible(msecs_to_jiffies(400));
1071
1072 /* Enable bias */
8d50e447 1073 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1074 WM8900_REG_POWER1_STARTUP_BIAS_ENA |
1075 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1076
8d50e447 1077 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
0e0e16a8 1078
8d50e447 1079 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1080 WM8900_REG_POWER1_BIAS_ENA | 0x1);
1081 }
1082
8d50e447
MB		 1083 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1084 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1085 (reg & WM8900_REG_POWER1_FLL_ENA) |
1086 WM8900_REG_POWER1_BIAS_ENA | 0x1);
8d50e447 1087 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8 1088 WM8900_REG_POWER2_SYSCLK_ENA);
8d50e447 1089 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1090 break;
1091
1092 case SND_SOC_BIAS_OFF:
1093 /* Startup bias enable */
8d50e447
MB		 1094 reg = snd_soc_read(codec, WM8900_REG_POWER1);
1095 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8 1096 reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
8d50e447 1097 snd_soc_write(codec, WM8900_REG_ADDCTL,
0e0e16a8
MB		 1098 WM8900_REG_ADDCTL_BIAS_SRC |
1099 WM8900_REG_ADDCTL_VMID_SOFTST);
1100
1101 /* Discharge caps */
8d50e447 1102 snd_soc_write(codec, WM8900_REG_POWER1,
0e0e16a8
MB		 1103 WM8900_REG_POWER1_STARTUP_BIAS_ENA);
1104 schedule_timeout_interruptible(msecs_to_jiffies(500));
1105
1106 /* Remove clamp */
8d50e447 1107 snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
0e0e16a8
MB		 1108
1109 /* Power down */
8d50e447
MB		 1110 snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
1111 snd_soc_write(codec, WM8900_REG_POWER1, 0);
1112 snd_soc_write(codec, WM8900_REG_POWER2, 0);
1113 snd_soc_write(codec, WM8900_REG_POWER3, 0);
0e0e16a8
MB		 1114
1115 /* Need to let things settle before stopping the clock
1116 * to ensure that restart works, see "Stopping the
1117 * master clock" in the datasheet. */
1118 schedule_timeout_interruptible(msecs_to_jiffies(1));
8d50e447 1119 snd_soc_write(codec, WM8900_REG_POWER2,
0e0e16a8
MB		 1120 WM8900_REG_POWER2_SYSCLK_ENA);
1121 break;
1122 }
ce6120cc 1123 codec->dapm.bias_level = level;
0e0e16a8
MB		 1124 return 0;
1125}
1126
f0fba2ad 1127static int wm8900_suspend(struct snd_soc_codec *codec, pm_message_t state)
0e0e16a8 1128{
b2c812e2 1129 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 1130 int fll_out = wm8900->fll_out;
1131 int fll_in = wm8900->fll_in;
1132 int ret;
1133
1134 /* Stop the FLL in an orderly fashion */
1135 ret = wm8900_set_fll(codec, 0, 0, 0);
1136 if (ret != 0) {
f0fba2ad 1137 dev_err(codec->dev, "Failed to stop FLL\n");
0e0e16a8
MB		 1138 return ret;
1139 }
1140
1141 wm8900->fll_out = fll_out;
1142 wm8900->fll_in = fll_in;
1143
1144 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1145
1146 return 0;
1147}
1148
f0fba2ad 1149static int wm8900_resume(struct snd_soc_codec *codec)
0e0e16a8 1150{
b2c812e2 1151 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
0e0e16a8
MB		 1152 u16 *cache;
1153 int i, ret;
1154
1155 cache = kmemdup(codec->reg_cache, sizeof(wm8900_reg_defaults),
1156 GFP_KERNEL);
1157
1158 wm8900_reset(codec);
1159 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1160
1161 /* Restart the FLL? */
1162 if (wm8900->fll_out) {
1163 int fll_out = wm8900->fll_out;
1164 int fll_in = wm8900->fll_in;
1165
1166 wm8900->fll_in = 0;
1167 wm8900->fll_out = 0;
1168
1169 ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
1170 if (ret != 0) {
f0fba2ad 1171 dev_err(codec->dev, "Failed to restart FLL\n");
0e0e16a8
MB		 1172 return ret;
1173 }
1174 }
1175
1176 if (cache) {
1177 for (i = 0; i < WM8900_MAXREG; i++)
8d50e447 1178 snd_soc_write(codec, i, cache[i]);
0e0e16a8
MB		 1179 kfree(cache);
1180 } else
f0fba2ad 1181 dev_err(codec->dev, "Unable to allocate register cache\n");
0e0e16a8
MB		 1182
1183 return 0;
1184}
1185
f0fba2ad 1186static int wm8900_probe(struct snd_soc_codec *codec)
0e0e16a8 1187{
f0fba2ad
LG		 1188 struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
1189 int ret = 0, reg;
78e19a39 1190
f0fba2ad 1191 ret = snd_soc_codec_set_cache_io(codec, 8, 16, wm8900->control_type);
8d50e447 1192 if (ret != 0) {
f0fba2ad
LG		 1193 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1194 return ret;
8d50e447
MB		 1195 }
1196
1197 reg = snd_soc_read(codec, WM8900_REG_ID);
0e0e16a8 1198 if (reg != 0x8900) {
f0fba2ad
LG		 1199 dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
1200 return -ENODEV;
0e0e16a8
MB		 1201 }
1202
0e0e16a8
MB		 1203 wm8900_reset(codec);
1204
78e19a39
MB		 1205 /* Turn the chip on */
1206 wm8900_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1207
0e0e16a8 1208 /* Latch the volume update bits */
8d50e447
MB		 1209 snd_soc_write(codec, WM8900_REG_LINVOL,
1210 snd_soc_read(codec, WM8900_REG_LINVOL) | 0x100);
1211 snd_soc_write(codec, WM8900_REG_RINVOL,
1212 snd_soc_read(codec, WM8900_REG_RINVOL) | 0x100);
1213 snd_soc_write(codec, WM8900_REG_LOUT1CTL,
1214 snd_soc_read(codec, WM8900_REG_LOUT1CTL) | 0x100);
1215 snd_soc_write(codec, WM8900_REG_ROUT1CTL,
1216 snd_soc_read(codec, WM8900_REG_ROUT1CTL) | 0x100);
1217 snd_soc_write(codec, WM8900_REG_LOUT2CTL,
1218 snd_soc_read(codec, WM8900_REG_LOUT2CTL) | 0x100);
1219 snd_soc_write(codec, WM8900_REG_ROUT2CTL,
1220 snd_soc_read(codec, WM8900_REG_ROUT2CTL) | 0x100);
1221 snd_soc_write(codec, WM8900_REG_LDAC_DV,
1222 snd_soc_read(codec, WM8900_REG_LDAC_DV) | 0x100);
1223 snd_soc_write(codec, WM8900_REG_RDAC_DV,
1224 snd_soc_read(codec, WM8900_REG_RDAC_DV) | 0x100);
1225 snd_soc_write(codec, WM8900_REG_LADC_DV,
1226 snd_soc_read(codec, WM8900_REG_LADC_DV) | 0x100);
1227 snd_soc_write(codec, WM8900_REG_RADC_DV,
1228 snd_soc_read(codec, WM8900_REG_RADC_DV) | 0x100);
0e0e16a8
MB		 1229
1230 /* Set the DAC and mixer output bias */
8d50e447 1231 snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
0e0e16a8 1232
f0fba2ad
LG		 1233 snd_soc_add_controls(codec, wm8900_snd_controls,
1234 ARRAY_SIZE(wm8900_snd_controls));
1235 wm8900_add_widgets(codec);
0e0e16a8 1236
f0fba2ad
LG		 1237 return 0;
1238}
0e0e16a8 1239
f0fba2ad
LG		 1240/* power down chip */
1241static int wm8900_remove(struct snd_soc_codec *codec)
1242{
1243 wm8900_set_bias_level(codec, SND_SOC_BIAS_OFF);
1244 return 0;
1245}
0e0e16a8 1246
f0fba2ad
LG		 1247static struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
1248 .probe = wm8900_probe,
1249 .remove = wm8900_remove,
1250 .suspend = wm8900_suspend,
1251 .resume = wm8900_resume,
1252 .set_bias_level = wm8900_set_bias_level,
1253 .volatile_register = wm8900_volatile_register,
e5eec34c 1254 .reg_cache_size = ARRAY_SIZE(wm8900_reg_defaults),
f0fba2ad
LG		 1255 .reg_word_size = sizeof(u16),
1256 .reg_cache_default = wm8900_reg_defaults,
1257};
0e0e16a8 1258
f0fba2ad
LG		 1259#if defined(CONFIG_SPI_MASTER)
1260static int __devinit wm8900_spi_probe(struct spi_device *spi)
1261{
1262 struct wm8900_priv *wm8900;
1263 int ret;
1264
1265 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1266 if (wm8900 == NULL)
1267 return -ENOMEM;
0e0e16a8 1268
f0fba2ad
LG		 1269 wm8900->control_type = SND_SOC_SPI;
1270 spi_set_drvdata(spi, wm8900);
1271
1272 ret = snd_soc_register_codec(&spi->dev,
1273 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1274 if (ret < 0)
1275 kfree(wm8900);
78e19a39 1276 return ret;
0e0e16a8
MB		 1277}
1278
f0fba2ad 1279static int __devexit wm8900_spi_remove(struct spi_device *spi)
0e0e16a8 1280{
f0fba2ad
LG		 1281 snd_soc_unregister_codec(&spi->dev);
1282 kfree(spi_get_drvdata(spi));
1283 return 0;
1284}
78e19a39 1285
f0fba2ad
LG		 1286static struct spi_driver wm8900_spi_driver = {
1287 .driver = {
1288 .name = "wm8900-codec",
f0fba2ad
LG		 1289 .owner = THIS_MODULE,
1290 },
1291 .probe = wm8900_spi_probe,
1292 .remove = __devexit_p(wm8900_spi_remove),
1293};
1294#endif /* CONFIG_SPI_MASTER */
1295
1296#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1297static __devinit int wm8900_i2c_probe(struct i2c_client *i2c,
1298 const struct i2c_device_id *id)
1299{
1300 struct wm8900_priv *wm8900;
1301 int ret;
1302
1303 wm8900 = kzalloc(sizeof(struct wm8900_priv), GFP_KERNEL);
1304 if (wm8900 == NULL)
1305 return -ENOMEM;
1306
1307 i2c_set_clientdata(i2c, wm8900);
f0fba2ad 1308 wm8900->control_type = SND_SOC_I2C;
78e19a39 1309
f0fba2ad
LG		 1310 ret = snd_soc_register_codec(&i2c->dev,
1311 &soc_codec_dev_wm8900, &wm8900_dai, 1);
1312 if (ret < 0)
1313 kfree(wm8900);
1314 return ret;
1315}
78e19a39 1316
f0fba2ad
LG		 1317static __devexit int wm8900_i2c_remove(struct i2c_client *client)
1318{
1319 snd_soc_unregister_codec(&client->dev);
1320 kfree(i2c_get_clientdata(client));
0e0e16a8
MB		 1321 return 0;
1322}
1323
8ae6a552
JD		 1324static const struct i2c_device_id wm8900_i2c_id[] = {
1325 { "wm8900", 0 },
1326 { }
1327};
1328MODULE_DEVICE_TABLE(i2c, wm8900_i2c_id);
0e0e16a8 1329
0e0e16a8
MB		 1330static struct i2c_driver wm8900_i2c_driver = {
1331 .driver = {
f0fba2ad 1332 .name = "wm8900-codec",
0e0e16a8
MB		 1333 .owner = THIS_MODULE,
1334 },
f0fba2ad
LG		 1335 .probe = wm8900_i2c_probe,
1336 .remove = __devexit_p(wm8900_i2c_remove),
8ae6a552 1337 .id_table = wm8900_i2c_id,
0e0e16a8 1338};
f0fba2ad 1339#endif
0e0e16a8 1340
f0fba2ad 1341static int __init wm8900_modinit(void)
0e0e16a8 1342{
0e0e16a8 1343 int ret = 0;
f0fba2ad
LG		 1344#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1345 ret = i2c_add_driver(&wm8900_i2c_driver);
1346 if (ret != 0) {
1347 printk(KERN_ERR "Failed to register wm8900 I2C driver: %d\n",
1348 ret);
f0752331 1349 }
f0fba2ad
LG		 1350#endif
1351#if defined(CONFIG_SPI_MASTER)
1352 ret = spi_register_driver(&wm8900_spi_driver);
1353 if (ret != 0) {
1354 printk(KERN_ERR "Failed to register wm8900 SPI driver: %d\n",
1355 ret);
78e19a39 1356 }
f0fba2ad 1357#endif
0e0e16a8
MB		 1358 return ret;
1359}
64089b84
MB		 1360module_init(wm8900_modinit);
1361
1362static void __exit wm8900_exit(void)
1363{
f0fba2ad 1364#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
f0752331 1365 i2c_del_driver(&wm8900_i2c_driver);
f0fba2ad
LG		 1366#endif
1367#if defined(CONFIG_SPI_MASTER)
1368 spi_unregister_driver(&wm8900_spi_driver);
1369#endif
64089b84
MB		 1370}
1371module_exit(wm8900_exit);
1372
0e0e16a8
MB		 1373MODULE_DESCRIPTION("ASoC WM8900 driver");
1374MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfonmicro.com>");
1375MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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