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ASoC: wm8903: Move the deemph lock to the driver level
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
20c5fd39 4 * Copyright 2008-12 Wolfson Microelectronics
0bf79ef2 5 * Copyright 2011-2012 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
ee244ce4 26#include <linux/regmap.h>
5a0e3ad6 27#include <linux/slab.h>
9d35f3e1 28#include <linux/irq.h>
78660af7 29#include <linux/mutex.h>
f1c0a02f 30#include <sound/core.h>
7245387e 31#include <sound/jack.h>
f1c0a02f
MB		 32#include <sound/pcm.h>
33#include <sound/pcm_params.h>
34#include <sound/tlv.h>
35#include <sound/soc.h>
f1c0a02f 36#include <sound/initval.h>
8abd16a6 37#include <sound/wm8903.h>
2bbb5d66 38#include <trace/events/asoc.h>
f1c0a02f
MB		 39
40#include "wm8903.h"
41
f1c0a02f 42/* Register defaults at reset */
ee244ce4
MB		 43static const struct reg_default wm8903_reg_defaults[] = {
44 { 4, 0x0018 }, /* R4 - Bias Control 0 */
45 { 5, 0x0000 }, /* R5 - VMID Control 0 */
46 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
47 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
48 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
49 { 12, 0x0000 }, /* R12 - Power Management 0 */
50 { 13, 0x0000 }, /* R13 - Power Management 1 */
51 { 14, 0x0000 }, /* R14 - Power Management 2 */
52 { 15, 0x0000 }, /* R15 - Power Management 3 */
53 { 16, 0x0000 }, /* R16 - Power Management 4 */
54 { 17, 0x0000 }, /* R17 - Power Management 5 */
55 { 18, 0x0000 }, /* R18 - Power Management 6 */
56 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
57 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
58 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
59 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
60 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
61 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
62 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
63 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
64 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
65 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
66 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
67 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
68 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
69 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
70 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
71 { 40, 0x09BF }, /* R40 - DRC 0 */
72 { 41, 0x3241 }, /* R41 - DRC 1 */
73 { 42, 0x0020 }, /* R42 - DRC 2 */
74 { 43, 0x0000 }, /* R43 - DRC 3 */
75 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
76 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
77 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
78 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
79 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
80 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
81 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
82 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
83 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
84 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
85 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
86 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
87 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
88 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
89 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
90 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
91 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
92 { 67, 0x0010 }, /* R67 - DC Servo 0 */
93 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
94 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
95 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
96 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
97 { 104, 0x0000 }, /* R104 - Class W 0 */
98 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
99 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
100 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
101 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
102 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
103 { 114, 0x0000 }, /* R114 - Control Interface */
104 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
105 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
106 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
107 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
108 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
109 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
110 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
111 { 126, 0x0000 }, /* R126 - Interrupt Control */
112 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
113 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
114 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
115 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
f1c0a02f
MB		 116};
117
d58d5d55 118struct wm8903_priv {
c0eb27cf 119 struct wm8903_platform_data *pdata;
0bf79ef2 120 struct device *dev;
7cfe5617 121 struct snd_soc_codec *codec;
ee244ce4 122 struct regmap *regmap;
f0fba2ad 123
d58d5d55 124 int sysclk;
f0fba2ad 125 int irq;
d58d5d55 126
78660af7 127 struct mutex lock;
69fff9bb
MB		 128 int fs;
129 int deemph;
130
c5b6a9fe
MB		 131 int dcs_pending;
132 int dcs_cache[4];
133
f2c1fe09 134 /* Reference count */
d58d5d55 135 int class_w_users;
d58d5d55 136
7245387e
MB		 137 struct snd_soc_jack *mic_jack;
138 int mic_det;
139 int mic_short;
140 int mic_last_report;
141 int mic_delay;
7cfe5617
SW		 142
143#ifdef CONFIG_GPIOLIB
144 struct gpio_chip gpio_chip;
145#endif
d58d5d55
MB		 146};
147
ee244ce4
MB		 148static bool wm8903_readable_register(struct device *dev, unsigned int reg)
149{
150 switch (reg) {
151 case WM8903_SW_RESET_AND_ID:
152 case WM8903_REVISION_NUMBER:
153 case WM8903_BIAS_CONTROL_0:
154 case WM8903_VMID_CONTROL_0:
155 case WM8903_MIC_BIAS_CONTROL_0:
156 case WM8903_ANALOGUE_DAC_0:
157 case WM8903_ANALOGUE_ADC_0:
158 case WM8903_POWER_MANAGEMENT_0:
159 case WM8903_POWER_MANAGEMENT_1:
160 case WM8903_POWER_MANAGEMENT_2:
161 case WM8903_POWER_MANAGEMENT_3:
162 case WM8903_POWER_MANAGEMENT_4:
163 case WM8903_POWER_MANAGEMENT_5:
164 case WM8903_POWER_MANAGEMENT_6:
165 case WM8903_CLOCK_RATES_0:
166 case WM8903_CLOCK_RATES_1:
167 case WM8903_CLOCK_RATES_2:
168 case WM8903_AUDIO_INTERFACE_0:
169 case WM8903_AUDIO_INTERFACE_1:
170 case WM8903_AUDIO_INTERFACE_2:
171 case WM8903_AUDIO_INTERFACE_3:
172 case WM8903_DAC_DIGITAL_VOLUME_LEFT:
173 case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
174 case WM8903_DAC_DIGITAL_0:
175 case WM8903_DAC_DIGITAL_1:
176 case WM8903_ADC_DIGITAL_VOLUME_LEFT:
177 case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
178 case WM8903_ADC_DIGITAL_0:
179 case WM8903_DIGITAL_MICROPHONE_0:
180 case WM8903_DRC_0:
181 case WM8903_DRC_1:
182 case WM8903_DRC_2:
183 case WM8903_DRC_3:
184 case WM8903_ANALOGUE_LEFT_INPUT_0:
185 case WM8903_ANALOGUE_RIGHT_INPUT_0:
186 case WM8903_ANALOGUE_LEFT_INPUT_1:
187 case WM8903_ANALOGUE_RIGHT_INPUT_1:
188 case WM8903_ANALOGUE_LEFT_MIX_0:
189 case WM8903_ANALOGUE_RIGHT_MIX_0:
190 case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
191 case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
192 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
193 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
194 case WM8903_ANALOGUE_OUT1_LEFT:
195 case WM8903_ANALOGUE_OUT1_RIGHT:
196 case WM8903_ANALOGUE_OUT2_LEFT:
197 case WM8903_ANALOGUE_OUT2_RIGHT:
198 case WM8903_ANALOGUE_OUT3_LEFT:
199 case WM8903_ANALOGUE_OUT3_RIGHT:
200 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
201 case WM8903_DC_SERVO_0:
202 case WM8903_DC_SERVO_2:
203 case WM8903_DC_SERVO_READBACK_1:
204 case WM8903_DC_SERVO_READBACK_2:
205 case WM8903_DC_SERVO_READBACK_3:
206 case WM8903_DC_SERVO_READBACK_4:
207 case WM8903_ANALOGUE_HP_0:
208 case WM8903_ANALOGUE_LINEOUT_0:
209 case WM8903_CHARGE_PUMP_0:
210 case WM8903_CLASS_W_0:
211 case WM8903_WRITE_SEQUENCER_0:
212 case WM8903_WRITE_SEQUENCER_1:
213 case WM8903_WRITE_SEQUENCER_2:
214 case WM8903_WRITE_SEQUENCER_3:
215 case WM8903_WRITE_SEQUENCER_4:
216 case WM8903_CONTROL_INTERFACE:
217 case WM8903_GPIO_CONTROL_1:
218 case WM8903_GPIO_CONTROL_2:
219 case WM8903_GPIO_CONTROL_3:
220 case WM8903_GPIO_CONTROL_4:
221 case WM8903_GPIO_CONTROL_5:
222 case WM8903_INTERRUPT_STATUS_1:
223 case WM8903_INTERRUPT_STATUS_1_MASK:
224 case WM8903_INTERRUPT_POLARITY_1:
225 case WM8903_INTERRUPT_CONTROL:
226 case WM8903_CLOCK_RATE_TEST_4:
227 case WM8903_ANALOGUE_OUTPUT_BIAS_0:
228 return true;
229 default:
230 return false;
231 }
232}
233
234static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
f1c0a02f
MB		 235{
236 switch (reg) {
237 case WM8903_SW_RESET_AND_ID:
238 case WM8903_REVISION_NUMBER:
239 case WM8903_INTERRUPT_STATUS_1:
240 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 241 case WM8903_DC_SERVO_READBACK_1:
242 case WM8903_DC_SERVO_READBACK_2:
243 case WM8903_DC_SERVO_READBACK_3:
244 case WM8903_DC_SERVO_READBACK_4:
8d50e447 245 return 1;
f1c0a02f
MB		 246
247 default:
f1c0a02f 248 return 0;
8d50e447 249 }
f1c0a02f
MB		 250}
251
42768a12
MB		 252static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
253 struct snd_kcontrol *kcontrol, int event)
254{
255 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
256 mdelay(4);
257
258 return 0;
259}
260
c5b6a9fe
MB		 261static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
262 struct snd_kcontrol *kcontrol, int event)
263{
264 struct snd_soc_codec *codec = w->codec;
265 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
266
267 switch (event) {
268 case SND_SOC_DAPM_POST_PMU:
269 wm8903->dcs_pending |= 1 << w->shift;
270 break;
271 case SND_SOC_DAPM_PRE_PMD:
272 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
273 1 << w->shift, 0);
274 break;
275 }
276
277 return 0;
278}
279
280#define WM8903_DCS_MODE_WRITE_STOP 0
281#define WM8903_DCS_MODE_START_STOP 2
282
283static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
284 enum snd_soc_dapm_type event, int subseq)
285{
e73a2571 286 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
c5b6a9fe
MB		 287 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
288 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
289 int i, val;
290
291 /* Complete any pending DC servo starts */
292 if (wm8903->dcs_pending) {
293 dev_dbg(codec->dev, "Starting DC servo for %x\n",
294 wm8903->dcs_pending);
295
296 /* If we've no cached values then we need to do startup */
297 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
298 if (!(wm8903->dcs_pending & (1 << i)))
299 continue;
300
301 if (wm8903->dcs_cache[i]) {
302 dev_dbg(codec->dev,
303 "Restore DC servo %d value %x\n",
304 3 - i, wm8903->dcs_cache[i]);
305
306 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
307 wm8903->dcs_cache[i] & 0xff);
308 } else {
309 dev_dbg(codec->dev,
310 "Calibrate DC servo %d\n", 3 - i);
311 dcs_mode = WM8903_DCS_MODE_START_STOP;
312 }
313 }
314
315 /* Don't trust the cache for analogue */
316 if (wm8903->class_w_users)
317 dcs_mode = WM8903_DCS_MODE_START_STOP;
318
319 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
320 WM8903_DCS_MODE_MASK, dcs_mode);
321
322 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
323 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
324
325 switch (dcs_mode) {
326 case WM8903_DCS_MODE_WRITE_STOP:
327 break;
328
329 case WM8903_DCS_MODE_START_STOP:
330 msleep(270);
331
332 /* Cache the measured offsets for digital */
333 if (wm8903->class_w_users)
334 break;
335
336 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
337 if (!(wm8903->dcs_pending & (1 << i)))
338 continue;
339
340 val = snd_soc_read(codec,
341 WM8903_DC_SERVO_READBACK_1 + i);
342 dev_dbg(codec->dev, "DC servo %d: %x\n",
343 3 - i, val);
344 wm8903->dcs_cache[i] = val;
345 }
346 break;
347
348 default:
349 pr_warn("DCS mode %d delay not set\n", dcs_mode);
350 break;
351 }
352
353 wm8903->dcs_pending = 0;
354 }
355}
356
f1c0a02f
MB		 357/*
358 * When used with DAC outputs only the WM8903 charge pump supports
359 * operation in class W mode, providing very low power consumption
360 * when used with digital sources. Enable and disable this mode
361 * automatically depending on the mixer configuration.
362 *
363 * All the relevant controls are simple switches.
364 */
365static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
366 struct snd_ctl_elem_value *ucontrol)
367{
eee5d7f9 368 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
b2c812e2 369 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 370 u16 reg;
371 int ret;
372
8d50e447 373 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 374
375 /* Turn it off if we're about to enable bypass */
376 if (ucontrol->value.integer.value[0]) {
377 if (wm8903->class_w_users == 0) {
f0fba2ad 378 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 379 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 380 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
381 }
382 wm8903->class_w_users++;
383 }
384
385 /* Implement the change */
386 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
387
388 /* If we've just disabled the last bypass path turn Class W on */
389 if (!ucontrol->value.integer.value[0]) {
390 if (wm8903->class_w_users == 1) {
f0fba2ad 391 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 392 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 393 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
394 }
395 wm8903->class_w_users--;
396 }
397
f0fba2ad 398 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 399 wm8903->class_w_users);
400
401 return ret;
402}
403
404#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
ea3583d0
LPC		 405 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
406 snd_soc_dapm_get_volsw, wm8903_class_w_put)
f1c0a02f
MB		 407
408
69fff9bb
MB		 409static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
410
411static int wm8903_set_deemph(struct snd_soc_codec *codec)
412{
413 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
414 int val, i, best;
415
416 /* If we're using deemphasis select the nearest available sample
417 * rate.
418 */
419 if (wm8903->deemph) {
420 best = 1;
421 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
422 if (abs(wm8903_deemph[i] - wm8903->fs) <
423 abs(wm8903_deemph[best] - wm8903->fs))
424 best = i;
425 }
426
427 val = best << WM8903_DEEMPH_SHIFT;
428 } else {
429 best = 0;
430 val = 0;
431 }
432
433 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
434 best, wm8903_deemph[best]);
435
436 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
437 WM8903_DEEMPH_MASK, val);
438}
439
440static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
441 struct snd_ctl_elem_value *ucontrol)
442{
ea53bf77 443 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
69fff9bb
MB		 444 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
445
446 ucontrol->value.enumerated.item[0] = wm8903->deemph;
447
448 return 0;
449}
450
451static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
452 struct snd_ctl_elem_value *ucontrol)
453{
ea53bf77 454 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
69fff9bb
MB		 455 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
456 int deemph = ucontrol->value.enumerated.item[0];
457 int ret = 0;
458
459 if (deemph > 1)
460 return -EINVAL;
461
78660af7 462 mutex_lock(&wm8903->lock);
69fff9bb
MB		 463 if (wm8903->deemph != deemph) {
464 wm8903->deemph = deemph;
465
466 wm8903_set_deemph(codec);
467
468 ret = 1;
469 }
78660af7 470 mutex_unlock(&wm8903->lock);
69fff9bb
MB		 471
472 return ret;
473}
474
f1c0a02f
MB		 475/* ALSA can only do steps of .01dB */
476static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
477
00aa0fac
AB		 478static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
479
291ce18c 480static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 481static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
482
483static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
484static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
485static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
486static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
487static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
488
460f4aae
MB		 489static const char *hpf_mode_text[] = {
490 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
491};
492
a21bc5c5
TI		 493static SOC_ENUM_SINGLE_DECL(hpf_mode,
494 WM8903_ADC_DIGITAL_0, 5, hpf_mode_text);
460f4aae 495
dcf9ada3
MB		 496static const char *osr_text[] = {
497 "Low power", "High performance"
498};
499
a21bc5c5
TI		 500static SOC_ENUM_SINGLE_DECL(adc_osr,
501 WM8903_ANALOGUE_ADC_0, 0, osr_text);
dcf9ada3 502
a21bc5c5
TI		 503static SOC_ENUM_SINGLE_DECL(dac_osr,
504 WM8903_DAC_DIGITAL_1, 0, osr_text);
dcf9ada3 505
f1c0a02f
MB		 506static const char *drc_slope_text[] = {
507 "1", "1/2", "1/4", "1/8", "1/16", "0"
508};
509
a21bc5c5
TI		 510static SOC_ENUM_SINGLE_DECL(drc_slope_r0,
511 WM8903_DRC_2, 3, drc_slope_text);
f1c0a02f 512
a21bc5c5
TI		 513static SOC_ENUM_SINGLE_DECL(drc_slope_r1,
514 WM8903_DRC_2, 0, drc_slope_text);
f1c0a02f
MB		 515
516static const char *drc_attack_text[] = {
517 "instantaneous",
518 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
519 "46.4ms", "92.8ms", "185.6ms"
520};
521
a21bc5c5
TI		 522static SOC_ENUM_SINGLE_DECL(drc_attack,
523 WM8903_DRC_1, 12, drc_attack_text);
f1c0a02f
MB		 524
525static const char *drc_decay_text[] = {
526 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
527 "23.87s", "47.56s"
528};
529
a21bc5c5
TI		 530static SOC_ENUM_SINGLE_DECL(drc_decay,
531 WM8903_DRC_1, 8, drc_decay_text);
f1c0a02f
MB		 532
533static const char *drc_ff_delay_text[] = {
534 "5 samples", "9 samples"
535};
536
a21bc5c5
TI		 537static SOC_ENUM_SINGLE_DECL(drc_ff_delay,
538 WM8903_DRC_0, 5, drc_ff_delay_text);
f1c0a02f
MB		 539
540static const char *drc_qr_decay_text[] = {
541 "0.725ms", "1.45ms", "5.8ms"
542};
543
a21bc5c5
TI		 544static SOC_ENUM_SINGLE_DECL(drc_qr_decay,
545 WM8903_DRC_1, 4, drc_qr_decay_text);
f1c0a02f
MB		 546
547static const char *drc_smoothing_text[] = {
548 "Low", "Medium", "High"
549};
550
a21bc5c5
TI		 551static SOC_ENUM_SINGLE_DECL(drc_smoothing,
552 WM8903_DRC_0, 11, drc_smoothing_text);
f1c0a02f
MB		 553
554static const char *soft_mute_text[] = {
555 "Fast (fs/2)", "Slow (fs/32)"
556};
557
a21bc5c5
TI		 558static SOC_ENUM_SINGLE_DECL(soft_mute,
559 WM8903_DAC_DIGITAL_1, 10, soft_mute_text);
f1c0a02f
MB		 560
561static const char *mute_mode_text[] = {
562 "Hard", "Soft"
563};
564
a21bc5c5
TI		 565static SOC_ENUM_SINGLE_DECL(mute_mode,
566 WM8903_DAC_DIGITAL_1, 9, mute_mode_text);
f1c0a02f 567
f1c0a02f
MB		 568static const char *companding_text[] = {
569 "ulaw", "alaw"
570};
571
a21bc5c5
TI		 572static SOC_ENUM_SINGLE_DECL(dac_companding,
573 WM8903_AUDIO_INTERFACE_0, 0, companding_text);
f1c0a02f 574
a21bc5c5
TI		 575static SOC_ENUM_SINGLE_DECL(adc_companding,
576 WM8903_AUDIO_INTERFACE_0, 2, companding_text);
f1c0a02f
MB		 577
578static const char *input_mode_text[] = {
579 "Single-Ended", "Differential Line", "Differential Mic"
580};
581
a21bc5c5
TI		 582static SOC_ENUM_SINGLE_DECL(linput_mode_enum,
583 WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text);
f1c0a02f 584
a21bc5c5
TI		 585static SOC_ENUM_SINGLE_DECL(rinput_mode_enum,
586 WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text);
f1c0a02f
MB		 587
588static const char *linput_mux_text[] = {
589 "IN1L", "IN2L", "IN3L"
590};
591
a21bc5c5
TI		 592static SOC_ENUM_SINGLE_DECL(linput_enum,
593 WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text);
f1c0a02f 594
a21bc5c5
TI		 595static SOC_ENUM_SINGLE_DECL(linput_inv_enum,
596 WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text);
f1c0a02f
MB		 597
598static const char *rinput_mux_text[] = {
599 "IN1R", "IN2R", "IN3R"
600};
601
a21bc5c5
TI		 602static SOC_ENUM_SINGLE_DECL(rinput_enum,
603 WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text);
f1c0a02f 604
a21bc5c5
TI		 605static SOC_ENUM_SINGLE_DECL(rinput_inv_enum,
606 WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text);
f1c0a02f
MB		 607
608
291ce18c
MB		 609static const char *sidetone_text[] = {
610 "None", "Left", "Right"
611};
612
a21bc5c5
TI		 613static SOC_ENUM_SINGLE_DECL(lsidetone_enum,
614 WM8903_DAC_DIGITAL_0, 2, sidetone_text);
291ce18c 615
a21bc5c5
TI		 616static SOC_ENUM_SINGLE_DECL(rsidetone_enum,
617 WM8903_DAC_DIGITAL_0, 0, sidetone_text);
291ce18c 618
97945c46
SW		 619static const char *adcinput_text[] = {
620 "ADC", "DMIC"
621};
622
a21bc5c5
TI		 623static SOC_ENUM_SINGLE_DECL(adcinput_enum,
624 WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text);
97945c46 625
1e113bf9
MB		 626static const char *aif_text[] = {
627 "Left", "Right"
628};
629
a21bc5c5
TI		 630static SOC_ENUM_SINGLE_DECL(lcapture_enum,
631 WM8903_AUDIO_INTERFACE_0, 7, aif_text);
1e113bf9 632
a21bc5c5
TI		 633static SOC_ENUM_SINGLE_DECL(rcapture_enum,
634 WM8903_AUDIO_INTERFACE_0, 6, aif_text);
1e113bf9 635
a21bc5c5
TI		 636static SOC_ENUM_SINGLE_DECL(lplay_enum,
637 WM8903_AUDIO_INTERFACE_0, 5, aif_text);
1e113bf9 638
a21bc5c5
TI		 639static SOC_ENUM_SINGLE_DECL(rplay_enum,
640 WM8903_AUDIO_INTERFACE_0, 4, aif_text);
1e113bf9 641
f1c0a02f
MB		 642static const struct snd_kcontrol_new wm8903_snd_controls[] = {
643
644/* Input PGAs - No TLV since the scale depends on PGA mode */
645SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 646 7, 1, 1),
f1c0a02f
MB		 647SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
648 0, 31, 0),
649SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
650 6, 1, 0),
651
652SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 653 7, 1, 1),
f1c0a02f
MB		 654SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
655 0, 31, 0),
656SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
657 6, 1, 0),
658
659/* ADCs */
dcf9ada3 660SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 661SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
662SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 663SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
664SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
665SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 666SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 667 drc_tlv_thresh),
668SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
669SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
670SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
671SOC_ENUM("DRC Attack Rate", drc_attack),
672SOC_ENUM("DRC Decay Rate", drc_decay),
673SOC_ENUM("DRC FF Delay", drc_ff_delay),
674SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
675SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 676SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 677SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
678SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
679SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 680SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 681SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
682
683SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
61bf35b9 684 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
f1c0a02f
MB		 685SOC_ENUM("ADC Companding Mode", adc_companding),
686SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
687
291ce18c
MB		 688SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
689 12, 0, digital_sidetone_tlv),
690
f1c0a02f 691/* DAC */
dcf9ada3 692SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 693SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
694 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
695SOC_ENUM("DAC Soft Mute Rate", soft_mute),
696SOC_ENUM("DAC Mute Mode", mute_mode),
697SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 698SOC_ENUM("DAC Companding Mode", dac_companding),
699SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
00aa0fac
AB		 700SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0,
701 dac_boost_tlv),
69fff9bb
MB		 702SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
703 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 704
705/* Headphones */
706SOC_DOUBLE_R("Headphone Switch",
707 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
708 8, 1, 1),
709SOC_DOUBLE_R("Headphone ZC Switch",
710 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
711 6, 1, 0),
712SOC_DOUBLE_R_TLV("Headphone Volume",
713 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
714 0, 63, 0, out_tlv),
715
716/* Line out */
717SOC_DOUBLE_R("Line Out Switch",
718 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
719 8, 1, 1),
720SOC_DOUBLE_R("Line Out ZC Switch",
721 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
722 6, 1, 0),
723SOC_DOUBLE_R_TLV("Line Out Volume",
724 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
725 0, 63, 0, out_tlv),
726
727/* Speaker */
728SOC_DOUBLE_R("Speaker Switch",
729 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
730SOC_DOUBLE_R("Speaker ZC Switch",
731 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
732SOC_DOUBLE_R_TLV("Speaker Volume",
733 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
734 0, 63, 0, out_tlv),
735};
736
f1c0a02f
MB		 737static const struct snd_kcontrol_new linput_mode_mux =
738 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
739
740static const struct snd_kcontrol_new rinput_mode_mux =
741 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
742
743static const struct snd_kcontrol_new linput_mux =
744 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
745
746static const struct snd_kcontrol_new linput_inv_mux =
747 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
748
749static const struct snd_kcontrol_new rinput_mux =
750 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
751
752static const struct snd_kcontrol_new rinput_inv_mux =
753 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
754
291ce18c
MB		 755static const struct snd_kcontrol_new lsidetone_mux =
756 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
757
758static const struct snd_kcontrol_new rsidetone_mux =
759 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
760
97945c46
SW		 761static const struct snd_kcontrol_new adcinput_mux =
762 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
763
1e113bf9
MB		 764static const struct snd_kcontrol_new lcapture_mux =
765 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
766
767static const struct snd_kcontrol_new rcapture_mux =
768 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
769
770static const struct snd_kcontrol_new lplay_mux =
771 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
772
773static const struct snd_kcontrol_new rplay_mux =
774 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
775
f1c0a02f
MB		 776static const struct snd_kcontrol_new left_output_mixer[] = {
777SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
778SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
779SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 780SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 781};
782
783static const struct snd_kcontrol_new right_output_mixer[] = {
784SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
785SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
786SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 787SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 788};
789
790static const struct snd_kcontrol_new left_speaker_mixer[] = {
791SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
792SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
793SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
794SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 795 0, 1, 0),
f1c0a02f
MB		 796};
797
798static const struct snd_kcontrol_new right_speaker_mixer[] = {
799SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
800SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
801SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
802 1, 1, 0),
803SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 804 0, 1, 0),
f1c0a02f
MB		 805};
806
807static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
808SND_SOC_DAPM_INPUT("IN1L"),
809SND_SOC_DAPM_INPUT("IN1R"),
810SND_SOC_DAPM_INPUT("IN2L"),
811SND_SOC_DAPM_INPUT("IN2R"),
812SND_SOC_DAPM_INPUT("IN3L"),
813SND_SOC_DAPM_INPUT("IN3R"),
97945c46 814SND_SOC_DAPM_INPUT("DMICDAT"),
f1c0a02f
MB		 815
816SND_SOC_DAPM_OUTPUT("HPOUTL"),
817SND_SOC_DAPM_OUTPUT("HPOUTR"),
818SND_SOC_DAPM_OUTPUT("LINEOUTL"),
819SND_SOC_DAPM_OUTPUT("LINEOUTR"),
820SND_SOC_DAPM_OUTPUT("LOP"),
821SND_SOC_DAPM_OUTPUT("LON"),
822SND_SOC_DAPM_OUTPUT("ROP"),
823SND_SOC_DAPM_OUTPUT("RON"),
824
5032dc34 825SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
f1c0a02f
MB		 826
827SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
828SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
829 &linput_inv_mux),
830SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
831
832SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
833SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
834 &rinput_inv_mux),
835SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
836
837SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
838SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
839
97945c46
SW		 840SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
841SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
842
1e113bf9
MB		 843SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
844SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
845
846SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
847SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
848
849SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
850SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 851
291ce18c
MB		 852SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
853SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
854
1e113bf9
MB		 855SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
856SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
857
858SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
859SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
860
861SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
862SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 863
864SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
865 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
866SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
867 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
868
869SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
870 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
871SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
872 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
873
1b877cb5
DL		 874SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
875 1, 0, NULL, 0),
876SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 877 0, 0, NULL, 0),
878
1b877cb5 879SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 880 NULL, 0),
1b877cb5 881SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 882 NULL, 0),
883
884SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
885SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 886SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
887SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 888SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
889SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 890SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
891SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 892
893SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
894 NULL, 0),
895SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
896 NULL, 0),
1b877cb5
DL		 897SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
898 NULL, 0),
899SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 900 NULL, 0),
901SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
902 NULL, 0),
903SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
904 NULL, 0),
1b877cb5
DL		 905SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
906 NULL, 0),
907SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 908 NULL, 0),
909
c5b6a9fe
MB		 910SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
911SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
912 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
913SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
914 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
915SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
916 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
917SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
918 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 919
920SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
921 NULL, 0),
922SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
923 NULL, 0),
924
42768a12
MB		 925SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
926 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 927SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 928SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 929};
930
ecd01512 931static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 932
2c8be5a2 933 { "CLK_DSP", NULL, "CLK_SYS" },
5032dc34 934 { "MICBIAS", NULL, "CLK_SYS" },
2c8be5a2
MB		 935 { "HPL_DCS", NULL, "CLK_SYS" },
936 { "HPR_DCS", NULL, "CLK_SYS" },
937 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
938 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
939
f1c0a02f
MB		 940 { "Left Input Mux", "IN1L", "IN1L" },
941 { "Left Input Mux", "IN2L", "IN2L" },
942 { "Left Input Mux", "IN3L", "IN3L" },
943
944 { "Left Input Inverting Mux", "IN1L", "IN1L" },
945 { "Left Input Inverting Mux", "IN2L", "IN2L" },
946 { "Left Input Inverting Mux", "IN3L", "IN3L" },
947
948 { "Right Input Mux", "IN1R", "IN1R" },
949 { "Right Input Mux", "IN2R", "IN2R" },
950 { "Right Input Mux", "IN3R", "IN3R" },
951
952 { "Right Input Inverting Mux", "IN1R", "IN1R" },
953 { "Right Input Inverting Mux", "IN2R", "IN2R" },
954 { "Right Input Inverting Mux", "IN3R", "IN3R" },
955
956 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
957 { "Left Input Mode Mux", "Differential Line",
958 "Left Input Mux" },
959 { "Left Input Mode Mux", "Differential Line",
960 "Left Input Inverting Mux" },
961 { "Left Input Mode Mux", "Differential Mic",
962 "Left Input Mux" },
963 { "Left Input Mode Mux", "Differential Mic",
964 "Left Input Inverting Mux" },
965
966 { "Right Input Mode Mux", "Single-Ended",
967 "Right Input Inverting Mux" },
968 { "Right Input Mode Mux", "Differential Line",
969 "Right Input Mux" },
970 { "Right Input Mode Mux", "Differential Line",
971 "Right Input Inverting Mux" },
972 { "Right Input Mode Mux", "Differential Mic",
973 "Right Input Mux" },
974 { "Right Input Mode Mux", "Differential Mic",
975 "Right Input Inverting Mux" },
976
977 { "Left Input PGA", NULL, "Left Input Mode Mux" },
978 { "Right Input PGA", NULL, "Right Input Mode Mux" },
979
97945c46
SW		 980 { "Left ADC Input", "ADC", "Left Input PGA" },
981 { "Left ADC Input", "DMIC", "DMICDAT" },
982 { "Right ADC Input", "ADC", "Right Input PGA" },
983 { "Right ADC Input", "DMIC", "DMICDAT" },
984
1e113bf9
MB		 985 { "Left Capture Mux", "Left", "ADCL" },
986 { "Left Capture Mux", "Right", "ADCR" },
987
988 { "Right Capture Mux", "Left", "ADCL" },
989 { "Right Capture Mux", "Right", "ADCR" },
990
991 { "AIFTXL", NULL, "Left Capture Mux" },
992 { "AIFTXR", NULL, "Right Capture Mux" },
993
97945c46 994 { "ADCL", NULL, "Left ADC Input" },
c2aef4ff 995 { "ADCL", NULL, "CLK_DSP" },
97945c46 996 { "ADCR", NULL, "Right ADC Input" },
c2aef4ff
MB		 997 { "ADCR", NULL, "CLK_DSP" },
998
1e113bf9
MB		 999 { "Left Playback Mux", "Left", "AIFRXL" },
1000 { "Left Playback Mux", "Right", "AIFRXR" },
1001
1002 { "Right Playback Mux", "Left", "AIFRXL" },
1003 { "Right Playback Mux", "Right", "AIFRXR" },
1004
291ce18c
MB		 1005 { "DACL Sidetone", "Left", "ADCL" },
1006 { "DACL Sidetone", "Right", "ADCR" },
1007 { "DACR Sidetone", "Left", "ADCL" },
1008 { "DACR Sidetone", "Right", "ADCR" },
1009
1e113bf9 1010 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1011 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1012 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1013
1014 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1015 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1016 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1017
1018 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1019 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1020 { "Left Output Mixer", "DACL Switch", "DACL" },
1021 { "Left Output Mixer", "DACR Switch", "DACR" },
1022
1023 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1024 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1025 { "Right Output Mixer", "DACL Switch", "DACL" },
1026 { "Right Output Mixer", "DACR Switch", "DACR" },
1027
1028 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1029 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1030 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1031 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1032
1033 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1034 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1035 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1036 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1037
1038 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1039 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1040
1041 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1042 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1043
1044 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1045 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1046
1b877cb5
DL		 1047 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1048 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1049 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1050 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1051 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1052 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1053 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1054 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1055
c5b6a9fe
MB		 1056 { "HPL_DCS", NULL, "DCS Master" },
1057 { "HPR_DCS", NULL, "DCS Master" },
1058 { "LINEOUTL_DCS", NULL, "DCS Master" },
1059 { "LINEOUTR_DCS", NULL, "DCS Master" },
1060
13a9983e
MB		 1061 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1062 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1063 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1064 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1065
1066 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1067 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1068 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1069 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1070
1071 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1072 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1073 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1074 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1075
1076 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1077 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1078 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1079 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1080
1081 { "LOP", NULL, "Left Speaker PGA" },
1082 { "LON", NULL, "Left Speaker PGA" },
1083
1084 { "ROP", NULL, "Right Speaker PGA" },
1085 { "RON", NULL, "Right Speaker PGA" },
42768a12 1086
f1ca493b
AB		 1087 { "Charge Pump", NULL, "CLK_DSP" },
1088
42768a12
MB		 1089 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1090 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1091 { "Left Line Output PGA", NULL, "Charge Pump" },
1092 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1093};
1094
f1c0a02f
MB		 1095static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1096 enum snd_soc_bias_level level)
1097{
f1c0a02f
MB		 1098 switch (level) {
1099 case SND_SOC_BIAS_ON:
66daaa59 1100 break;
22f226dd 1101
f1c0a02f 1102 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1103 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1104 WM8903_VMID_RES_MASK,
1105 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1106 break;
1107
1108 case SND_SOC_BIAS_STANDBY:
ce6120cc 1109 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1110 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1111 WM8903_POBCTRL | WM8903_ISEL_MASK |
1112 WM8903_STARTUP_BIAS_ENA |
1113 WM8903_BIAS_ENA,
1114 WM8903_POBCTRL |
1115 (2 << WM8903_ISEL_SHIFT) |
1116 WM8903_STARTUP_BIAS_ENA);
1117
1118 snd_soc_update_bits(codec,
1119 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1120 WM8903_SPK_DISCHARGE,
1121 WM8903_SPK_DISCHARGE);
1122
1123 msleep(33);
1124
1125 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1126 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1127 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1128
1129 snd_soc_update_bits(codec,
1130 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1131 WM8903_SPK_DISCHARGE, 0);
1132
1133 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1134 WM8903_VMID_TIE_ENA |
1135 WM8903_BUFIO_ENA |
1136 WM8903_VMID_IO_ENA |
1137 WM8903_VMID_SOFT_MASK |
1138 WM8903_VMID_RES_MASK |
1139 WM8903_VMID_BUF_ENA,
1140 WM8903_VMID_TIE_ENA |
1141 WM8903_BUFIO_ENA |
1142 WM8903_VMID_IO_ENA |
1143 (2 << WM8903_VMID_SOFT_SHIFT) |
1144 WM8903_VMID_RES_250K |
1145 WM8903_VMID_BUF_ENA);
1146
1147 msleep(129);
1148
1149 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1150 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1151 0);
1152
1153 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1154 WM8903_VMID_SOFT_MASK, 0);
1155
1156 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1157 WM8903_VMID_RES_MASK,
1158 WM8903_VMID_RES_50K);
1159
1160 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1161 WM8903_BIAS_ENA | WM8903_POBCTRL,
1162 WM8903_BIAS_ENA);
f1c0a02f 1163
f1c0a02f
MB		 1164 /* By default no bypass paths are enabled so
1165 * enable Class W support.
1166 */
f0fba2ad 1167 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1168 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1169 WM8903_CP_DYN_FREQ |
1170 WM8903_CP_DYN_V,
1171 WM8903_CP_DYN_FREQ |
1172 WM8903_CP_DYN_V);
f1c0a02f
MB		 1173 }
1174
66daaa59
MB		 1175 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1176 WM8903_VMID_RES_MASK,
1177 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1178 break;
1179
1180 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1181 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1182 WM8903_BIAS_ENA, 0);
1183
1184 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1185 WM8903_VMID_SOFT_MASK,
1186 2 << WM8903_VMID_SOFT_SHIFT);
1187
1188 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1189 WM8903_VMID_BUF_ENA, 0);
1190
1191 msleep(290);
1192
1193 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1194 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1195 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1196 WM8903_VMID_SOFT_MASK |
1197 WM8903_VMID_BUF_ENA, 0);
1198
1199 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1200 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1201 break;
1202 }
1203
ce6120cc 1204 codec->dapm.bias_level = level;
f1c0a02f
MB		 1205
1206 return 0;
1207}
1208
1209static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1210 int clk_id, unsigned int freq, int dir)
1211{
1212 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1213 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1214
1215 wm8903->sysclk = freq;
1216
1217 return 0;
1218}
1219
1220static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1221 unsigned int fmt)
1222{
1223 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1224 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1225
1226 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1227 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1228
1229 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1230 case SND_SOC_DAIFMT_CBS_CFS:
1231 break;
1232 case SND_SOC_DAIFMT_CBS_CFM:
1233 aif1 |= WM8903_LRCLK_DIR;
1234 break;
1235 case SND_SOC_DAIFMT_CBM_CFM:
1236 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1237 break;
1238 case SND_SOC_DAIFMT_CBM_CFS:
1239 aif1 |= WM8903_BCLK_DIR;
1240 break;
1241 default:
1242 return -EINVAL;
1243 }
1244
1245 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1246 case SND_SOC_DAIFMT_DSP_A:
1247 aif1 |= 0x3;
1248 break;
1249 case SND_SOC_DAIFMT_DSP_B:
1250 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1251 break;
1252 case SND_SOC_DAIFMT_I2S:
1253 aif1 |= 0x2;
1254 break;
1255 case SND_SOC_DAIFMT_RIGHT_J:
1256 aif1 |= 0x1;
1257 break;
1258 case SND_SOC_DAIFMT_LEFT_J:
1259 break;
1260 default:
1261 return -EINVAL;
1262 }
1263
1264 /* Clock inversion */
1265 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1266 case SND_SOC_DAIFMT_DSP_A:
1267 case SND_SOC_DAIFMT_DSP_B:
1268 /* frame inversion not valid for DSP modes */
1269 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1270 case SND_SOC_DAIFMT_NB_NF:
1271 break;
1272 case SND_SOC_DAIFMT_IB_NF:
1273 aif1 |= WM8903_AIF_BCLK_INV;
1274 break;
1275 default:
1276 return -EINVAL;
1277 }
1278 break;
1279 case SND_SOC_DAIFMT_I2S:
1280 case SND_SOC_DAIFMT_RIGHT_J:
1281 case SND_SOC_DAIFMT_LEFT_J:
1282 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1283 case SND_SOC_DAIFMT_NB_NF:
1284 break;
1285 case SND_SOC_DAIFMT_IB_IF:
1286 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1287 break;
1288 case SND_SOC_DAIFMT_IB_NF:
1289 aif1 |= WM8903_AIF_BCLK_INV;
1290 break;
1291 case SND_SOC_DAIFMT_NB_IF:
1292 aif1 |= WM8903_AIF_LRCLK_INV;
1293 break;
1294 default:
1295 return -EINVAL;
1296 }
1297 break;
1298 default:
1299 return -EINVAL;
1300 }
1301
8d50e447 1302 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1303
1304 return 0;
1305}
1306
1307static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1308{
1309 struct snd_soc_codec *codec = codec_dai->codec;
1310 u16 reg;
1311
8d50e447 1312 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1313
1314 if (mute)
1315 reg |= WM8903_DAC_MUTE;
1316 else
1317 reg &= ~WM8903_DAC_MUTE;
1318
8d50e447 1319 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1320
1321 return 0;
1322}
1323
1324/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1325 * for optimal performance so we list the lower rates first and match
1326 * on the last match we find. */
1327static struct {
1328 int div;
1329 int rate;
1330 int mode;
1331 int mclk_div;
1332} clk_sys_ratios[] = {
1333 { 64, 0x0, 0x0, 1 },
1334 { 68, 0x0, 0x1, 1 },
1335 { 125, 0x0, 0x2, 1 },
1336 { 128, 0x1, 0x0, 1 },
1337 { 136, 0x1, 0x1, 1 },
1338 { 192, 0x2, 0x0, 1 },
1339 { 204, 0x2, 0x1, 1 },
1340
1341 { 64, 0x0, 0x0, 2 },
1342 { 68, 0x0, 0x1, 2 },
1343 { 125, 0x0, 0x2, 2 },
1344 { 128, 0x1, 0x0, 2 },
1345 { 136, 0x1, 0x1, 2 },
1346 { 192, 0x2, 0x0, 2 },
1347 { 204, 0x2, 0x1, 2 },
1348
1349 { 250, 0x2, 0x2, 1 },
1350 { 256, 0x3, 0x0, 1 },
1351 { 272, 0x3, 0x1, 1 },
1352 { 384, 0x4, 0x0, 1 },
1353 { 408, 0x4, 0x1, 1 },
1354 { 375, 0x4, 0x2, 1 },
1355 { 512, 0x5, 0x0, 1 },
1356 { 544, 0x5, 0x1, 1 },
1357 { 500, 0x5, 0x2, 1 },
1358 { 768, 0x6, 0x0, 1 },
1359 { 816, 0x6, 0x1, 1 },
1360 { 750, 0x6, 0x2, 1 },
1361 { 1024, 0x7, 0x0, 1 },
1362 { 1088, 0x7, 0x1, 1 },
1363 { 1000, 0x7, 0x2, 1 },
1364 { 1408, 0x8, 0x0, 1 },
1365 { 1496, 0x8, 0x1, 1 },
1366 { 1536, 0x9, 0x0, 1 },
1367 { 1632, 0x9, 0x1, 1 },
1368 { 1500, 0x9, 0x2, 1 },
1369
1370 { 250, 0x2, 0x2, 2 },
1371 { 256, 0x3, 0x0, 2 },
1372 { 272, 0x3, 0x1, 2 },
1373 { 384, 0x4, 0x0, 2 },
1374 { 408, 0x4, 0x1, 2 },
1375 { 375, 0x4, 0x2, 2 },
1376 { 512, 0x5, 0x0, 2 },
1377 { 544, 0x5, 0x1, 2 },
1378 { 500, 0x5, 0x2, 2 },
1379 { 768, 0x6, 0x0, 2 },
1380 { 816, 0x6, 0x1, 2 },
1381 { 750, 0x6, 0x2, 2 },
1382 { 1024, 0x7, 0x0, 2 },
1383 { 1088, 0x7, 0x1, 2 },
1384 { 1000, 0x7, 0x2, 2 },
1385 { 1408, 0x8, 0x0, 2 },
1386 { 1496, 0x8, 0x1, 2 },
1387 { 1536, 0x9, 0x0, 2 },
1388 { 1632, 0x9, 0x1, 2 },
1389 { 1500, 0x9, 0x2, 2 },
1390};
1391
1392/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1393static struct {
1394 int ratio;
1395 int div;
1396} bclk_divs[] = {
1397 { 10, 0 },
f1c0a02f
MB		 1398 { 20, 2 },
1399 { 30, 3 },
1400 { 40, 4 },
1401 { 50, 5 },
f1c0a02f
MB		 1402 { 60, 7 },
1403 { 80, 8 },
1404 { 100, 9 },
f1c0a02f
MB		 1405 { 120, 11 },
1406 { 160, 12 },
1407 { 200, 13 },
1408 { 220, 14 },
1409 { 240, 15 },
f1c0a02f
MB		 1410 { 300, 17 },
1411 { 320, 18 },
1412 { 440, 19 },
1413 { 480, 20 },
1414};
1415
1416/* Sample rates for DSP */
1417static struct {
1418 int rate;
1419 int value;
1420} sample_rates[] = {
1421 { 8000, 0 },
1422 { 11025, 1 },
1423 { 12000, 2 },
1424 { 16000, 3 },
1425 { 22050, 4 },
1426 { 24000, 5 },
1427 { 32000, 6 },
1428 { 44100, 7 },
1429 { 48000, 8 },
1430 { 88200, 9 },
1431 { 96000, 10 },
1432 { 0, 0 },
1433};
1434
f1c0a02f 1435static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1436 struct snd_pcm_hw_params *params,
1437 struct snd_soc_dai *dai)
f1c0a02f 1438{
e6968a17 1439 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1440 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1441 int fs = params_rate(params);
1442 int bclk;
1443 int bclk_div;
1444 int i;
1445 int dsp_config;
1446 int clk_config;
1447 int best_val;
1448 int cur_val;
1449 int clk_sys;
1450
8d50e447
MB		 1451 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1452 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1453 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1454 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1455 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1456 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1457
9e79261f
MB		 1458 /* Enable sloping stopband filter for low sample rates */
1459 if (fs <= 24000)
1460 dac_digital1 |= WM8903_DAC_SB_FILT;
1461 else
1462 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1463
f1c0a02f
MB		 1464 /* Configure sample rate logic for DSP - choose nearest rate */
1465 dsp_config = 0;
1466 best_val = abs(sample_rates[dsp_config].rate - fs);
1467 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1468 cur_val = abs(sample_rates[i].rate - fs);
1469 if (cur_val <= best_val) {
1470 dsp_config = i;
1471 best_val = cur_val;
1472 }
1473 }
1474
f0fba2ad 1475 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1476 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1477 clock1 |= sample_rates[dsp_config].value;
1478
1479 aif1 &= ~WM8903_AIF_WL_MASK;
1480 bclk = 2 * fs;
6139ea27
MB		 1481 switch (params_width(params)) {
1482 case 16:
f1c0a02f
MB		 1483 bclk *= 16;
1484 break;
6139ea27 1485 case 20:
f1c0a02f
MB		 1486 bclk *= 20;
1487 aif1 |= 0x4;
1488 break;
6139ea27 1489 case 24:
f1c0a02f
MB		 1490 bclk *= 24;
1491 aif1 |= 0x8;
1492 break;
6139ea27 1493 case 32:
f1c0a02f
MB		 1494 bclk *= 32;
1495 aif1 |= 0xc;
1496 break;
1497 default:
1498 return -EINVAL;
1499 }
1500
f0fba2ad 1501 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1502 wm8903->sysclk, fs);
1503
1504 /* We may not have an MCLK which allows us to generate exactly
1505 * the clock we want, particularly with USB derived inputs, so
1506 * approximate.
1507 */
1508 clk_config = 0;
1509 best_val = abs((wm8903->sysclk /
1510 (clk_sys_ratios[0].mclk_div *
1511 clk_sys_ratios[0].div)) - fs);
1512 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1513 cur_val = abs((wm8903->sysclk /
1514 (clk_sys_ratios[i].mclk_div *
1515 clk_sys_ratios[i].div)) - fs);
1516
1517 if (cur_val <= best_val) {
1518 clk_config = i;
1519 best_val = cur_val;
1520 }
1521 }
1522
1523 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1524 clock0 |= WM8903_MCLKDIV2;
1525 clk_sys = wm8903->sysclk / 2;
1526 } else {
1527 clock0 &= ~WM8903_MCLKDIV2;
1528 clk_sys = wm8903->sysclk;
1529 }
1530
1531 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1532 WM8903_CLK_SYS_MODE_MASK);
1533 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1534 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1535
f0fba2ad 1536 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1537 clk_sys_ratios[clk_config].rate,
1538 clk_sys_ratios[clk_config].mode,
1539 clk_sys_ratios[clk_config].div);
1540
f0fba2ad 1541 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1542
1543 /* We may not get quite the right frequency if using
1544 * approximate clocks so look for the closest match that is
1545 * higher than the target (we need to ensure that there enough
1546 * BCLKs to clock out the samples).
1547 */
1548 bclk_div = 0;
1549 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1550 i = 1;
1551 while (i < ARRAY_SIZE(bclk_divs)) {
1552 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1553 if (cur_val < 0) /* BCLK table is sorted */
1554 break;
1555 bclk_div = i;
1556 best_val = cur_val;
1557 i++;
1558 }
1559
1560 aif2 &= ~WM8903_BCLK_DIV_MASK;
1561 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1562
f0fba2ad 1563 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1564 bclk_divs[bclk_div].ratio / 10, bclk,
1565 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1566
1567 aif2 |= bclk_divs[bclk_div].div;
1568 aif3 |= bclk / fs;
1569
69fff9bb
MB		 1570 wm8903->fs = params_rate(params);
1571 wm8903_set_deemph(codec);
1572
8d50e447
MB		 1573 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1574 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1575 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1576 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1577 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1578 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1579
1580 return 0;
1581}
1582
7245387e
MB		 1583/**
1584 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1585 *
1586 * @codec: WM8903 codec
1587 * @jack: jack to report detection events on
1588 * @det: value to report for presence detection
1589 * @shrt: value to report for short detection
1590 *
1591 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1592 * being used to bring out signals to the processor then only platform
1593 * data configuration is needed for WM8903 and processor GPIOs should
1594 * be configured using snd_soc_jack_add_gpios() instead.
1595 *
1596 * The current threasholds for detection should be configured using
1597 * micdet_cfg in the platform data. Using this function will force on
1598 * the microphone bias for the device.
1599 */
1600int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1601 int det, int shrt)
1602{
b2c812e2 1603 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1604 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1605
1606 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1607 det, shrt);
1608
1609 /* Store the configuration */
1610 wm8903->mic_jack = jack;
1611 wm8903->mic_det = det;
1612 wm8903->mic_short = shrt;
1613
1614 /* Enable interrupts we've got a report configured for */
1615 if (det)
1616 irq_mask &= ~WM8903_MICDET_EINT;
1617 if (shrt)
1618 irq_mask &= ~WM8903_MICSHRT_EINT;
1619
1620 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1621 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1622 irq_mask);
1623
3088e3b4 1624 if (det || shrt) {
69266866
MB		 1625 /* Enable mic detection, this may not have been set through
1626 * platform data (eg, if the defaults are OK). */
1627 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1628 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1629 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1630 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1631 } else {
1632 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1633 WM8903_MICDET_ENA, 0);
1634 }
7245387e
MB		 1635
1636 return 0;
1637}
1638EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1639
8abd16a6
MB		 1640static irqreturn_t wm8903_irq(int irq, void *data)
1641{
e373cbfb
MB		 1642 struct wm8903_priv *wm8903 = data;
1643 int mic_report, ret;
1644 unsigned int int_val, mask, int_pol;
8abd16a6 1645
e373cbfb
MB		 1646 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK,
1647 &mask);
1648 if (ret != 0) {
1649 dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret);
1650 return IRQ_NONE;
1651 }
1652
1653 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val);
1654 if (ret != 0) {
1655 dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret);
1656 return IRQ_NONE;
1657 }
1658
1659 int_val &= ~mask;
8abd16a6 1660
7245387e 1661 if (int_val & WM8903_WSEQ_BUSY_EINT) {
e373cbfb 1662 dev_warn(wm8903->dev, "Write sequencer done\n");
8abd16a6
MB		 1663 }
1664
7245387e
MB		 1665 /*
1666 * The rest is microphone jack detection. We need to manually
1667 * invert the polarity of the interrupt after each event - to
1668 * simplify the code keep track of the last state we reported
1669 * and just invert the relevant bits in both the report and
1670 * the polarity register.
1671 */
1672 mic_report = wm8903->mic_last_report;
e373cbfb
MB		 1673 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1674 &int_pol);
1675 if (ret != 0) {
1676 dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n",
1677 ret);
1678 return IRQ_HANDLED;
1679 }
7245387e 1680
1435b940 1681#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66 1682 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
e373cbfb 1683 trace_snd_soc_jack_irq(dev_name(wm8903->dev));
1435b940 1684#endif
2bbb5d66 1685
7245387e 1686 if (int_val & WM8903_MICSHRT_EINT) {
e373cbfb 1687 dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol);
7245387e
MB		 1688
1689 mic_report ^= wm8903->mic_short;
1690 int_pol ^= WM8903_MICSHRT_INV;
1691 }
1692
1693 if (int_val & WM8903_MICDET_EINT) {
e373cbfb 1694 dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol);
7245387e
MB		 1695
1696 mic_report ^= wm8903->mic_det;
1697 int_pol ^= WM8903_MICDET_INV;
1698
1699 msleep(wm8903->mic_delay);
1700 }
1701
e373cbfb
MB		 1702 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1703 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
7245387e
MB		 1704
1705 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1706 wm8903->mic_short | wm8903->mic_det);
1707
1708 wm8903->mic_last_report = mic_report;
1709
8abd16a6
MB		 1710 return IRQ_HANDLED;
1711}
1712
f1c0a02f
MB		 1713#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1714 SNDRV_PCM_RATE_11025 | \
1715 SNDRV_PCM_RATE_16000 | \
1716 SNDRV_PCM_RATE_22050 | \
1717 SNDRV_PCM_RATE_32000 | \
1718 SNDRV_PCM_RATE_44100 | \
1719 SNDRV_PCM_RATE_48000 | \
1720 SNDRV_PCM_RATE_88200 | \
1721 SNDRV_PCM_RATE_96000)
1722
1723#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1724 SNDRV_PCM_RATE_11025 | \
1725 SNDRV_PCM_RATE_16000 | \
1726 SNDRV_PCM_RATE_22050 | \
1727 SNDRV_PCM_RATE_32000 | \
1728 SNDRV_PCM_RATE_44100 | \
1729 SNDRV_PCM_RATE_48000)
1730
1731#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1732 SNDRV_PCM_FMTBIT_S20_3LE |\
1733 SNDRV_PCM_FMTBIT_S24_LE)
1734
85e7652d 1735static const struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1736 .hw_params = wm8903_hw_params,
1737 .digital_mute = wm8903_digital_mute,
1738 .set_fmt = wm8903_set_dai_fmt,
1739 .set_sysclk = wm8903_set_dai_sysclk,
1740};
1741
f0fba2ad
LG		 1742static struct snd_soc_dai_driver wm8903_dai = {
1743 .name = "wm8903-hifi",
f1c0a02f
MB		 1744 .playback = {
1745 .stream_name = "Playback",
1746 .channels_min = 2,
1747 .channels_max = 2,
1748 .rates = WM8903_PLAYBACK_RATES,
1749 .formats = WM8903_FORMATS,
1750 },
1751 .capture = {
1752 .stream_name = "Capture",
1753 .channels_min = 2,
1754 .channels_max = 2,
1755 .rates = WM8903_CAPTURE_RATES,
1756 .formats = WM8903_FORMATS,
1757 },
6335d055 1758 .ops = &wm8903_dai_ops,
0d960e88 1759 .symmetric_rates = 1,
f1c0a02f 1760};
f1c0a02f 1761
84b315ee 1762static int wm8903_suspend(struct snd_soc_codec *codec)
f1c0a02f 1763{
f1c0a02f
MB		 1764 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1765
1766 return 0;
1767}
1768
f0fba2ad 1769static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1770{
45e96755 1771 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f 1772
ee244ce4 1773 regcache_sync(wm8903->regmap);
f1c0a02f 1774
45e96755 1775 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1776
1777 return 0;
1778}
1779
7cfe5617
SW		 1780#ifdef CONFIG_GPIOLIB
1781static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1782{
1783 return container_of(chip, struct wm8903_priv, gpio_chip);
1784}
1785
1786static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1787{
1788 if (offset >= WM8903_NUM_GPIO)
1789 return -EINVAL;
1790
1791 return 0;
1792}
1793
1794static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1795{
1796 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
7cfe5617 1797 unsigned int mask, val;
385bd937 1798 int ret;
7cfe5617
SW		 1799
1800 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1801 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1802 WM8903_GP1_DIR;
1803
0bf79ef2
SW		 1804 ret = regmap_update_bits(wm8903->regmap,
1805 WM8903_GPIO_CONTROL_1 + offset, mask, val);
385bd937
AL		 1806 if (ret < 0)
1807 return ret;
1808
1809 return 0;
7cfe5617
SW		 1810}
1811
1812static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1813{
1814 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
0bf79ef2 1815 unsigned int reg;
7cfe5617 1816
0bf79ef2 1817 regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, &reg);
7cfe5617
SW		 1818
1819 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1820}
1821
1822static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1823 unsigned offset, int value)
1824{
1825 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
7cfe5617 1826 unsigned int mask, val;
385bd937 1827 int ret;
7cfe5617
SW		 1828
1829 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1830 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1831 (value << WM8903_GP2_LVL_SHIFT);
1832
0bf79ef2
SW		 1833 ret = regmap_update_bits(wm8903->regmap,
1834 WM8903_GPIO_CONTROL_1 + offset, mask, val);
385bd937
AL		 1835 if (ret < 0)
1836 return ret;
1837
1838 return 0;
7cfe5617
SW		 1839}
1840
1841static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1842{
1843 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
7cfe5617 1844
0bf79ef2
SW		 1845 regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset,
1846 WM8903_GP1_LVL_MASK,
1847 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1848}
1849
1850static struct gpio_chip wm8903_template_chip = {
1851 .label = "wm8903",
1852 .owner = THIS_MODULE,
1853 .request = wm8903_gpio_request,
1854 .direction_input = wm8903_gpio_direction_in,
1855 .get = wm8903_gpio_get,
1856 .direction_output = wm8903_gpio_direction_out,
1857 .set = wm8903_gpio_set,
1858 .can_sleep = 1,
1859};
1860
0bf79ef2 1861static void wm8903_init_gpio(struct wm8903_priv *wm8903)
7cfe5617 1862{
c0eb27cf 1863 struct wm8903_platform_data *pdata = wm8903->pdata;
7cfe5617
SW		 1864 int ret;
1865
1866 wm8903->gpio_chip = wm8903_template_chip;
1867 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
0bf79ef2 1868 wm8903->gpio_chip.dev = wm8903->dev;
7cfe5617 1869
db817784 1870 if (pdata->gpio_base)
7cfe5617
SW		 1871 wm8903->gpio_chip.base = pdata->gpio_base;
1872 else
1873 wm8903->gpio_chip.base = -1;
1874
1875 ret = gpiochip_add(&wm8903->gpio_chip);
1876 if (ret != 0)
0bf79ef2 1877 dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret);
7cfe5617
SW		 1878}
1879
0bf79ef2 1880static void wm8903_free_gpio(struct wm8903_priv *wm8903)
7cfe5617 1881{
88d5e520 1882 gpiochip_remove(&wm8903->gpio_chip);
7cfe5617
SW		 1883}
1884#else
0bf79ef2 1885static void wm8903_init_gpio(struct wm8903_priv *wm8903)
7cfe5617
SW		 1886{
1887}
1888
0bf79ef2 1889static void wm8903_free_gpio(struct wm8903_priv *wm8903)
7cfe5617
SW		 1890{
1891}
1892#endif
1893
f0fba2ad 1894static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1895{
f0fba2ad 1896 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f 1897
7cfe5617 1898 wm8903->codec = codec;
8d50e447 1899
f1c0a02f
MB		 1900 /* power on device */
1901 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1902
5d6be5aa 1903 return 0;
f1c0a02f
MB		 1904}
1905
f0fba2ad
LG		 1906/* power down chip */
1907static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1908{
f0fba2ad 1909 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f99847a6 1910
f0fba2ad
LG		 1911 return 0;
1912}
f1c0a02f 1913
f0fba2ad
LG		 1914static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1915 .probe = wm8903_probe,
1916 .remove = wm8903_remove,
1917 .suspend = wm8903_suspend,
1918 .resume = wm8903_resume,
1919 .set_bias_level = wm8903_set_bias_level,
c5b6a9fe 1920 .seq_notifier = wm8903_seq_notifier,
f4a10837
MB		 1921 .controls = wm8903_snd_controls,
1922 .num_controls = ARRAY_SIZE(wm8903_snd_controls),
ecd01512
MB		 1923 .dapm_widgets = wm8903_dapm_widgets,
1924 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
1925 .dapm_routes = wm8903_intercon,
1926 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 1927};
f1c0a02f 1928
ee244ce4
MB		 1929static const struct regmap_config wm8903_regmap = {
1930 .reg_bits = 8,
1931 .val_bits = 16,
1932
1933 .max_register = WM8903_MAX_REGISTER,
1934 .volatile_reg = wm8903_volatile_register,
1935 .readable_reg = wm8903_readable_register,
1936
1937 .cache_type = REGCACHE_RBTREE,
1938 .reg_defaults = wm8903_reg_defaults,
1939 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
1940};
1941
9d35f3e1
SW		 1942static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c,
1943 struct wm8903_platform_data *pdata)
1944{
1945 struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
1946 if (!irq_data) {
1947 dev_err(&i2c->dev, "Invalid IRQ: %d\n",
1948 i2c->irq);
1949 return -EINVAL;
1950 }
1951
1952 switch (irqd_get_trigger_type(irq_data)) {
1953 case IRQ_TYPE_NONE:
6664ee11 1954 default:
9d35f3e1
SW		 1955 /*
1956 * We assume the controller imposes no restrictions,
1957 * so we are able to select active-high
1958 */
1959 /* Fall-through */
1960 case IRQ_TYPE_LEVEL_HIGH:
1961 pdata->irq_active_low = false;
1962 break;
1963 case IRQ_TYPE_LEVEL_LOW:
1964 pdata->irq_active_low = true;
1965 break;
9d35f3e1
SW		 1966 }
1967
1968 return 0;
1969}
1970
5d680b3a
SW		 1971static int wm8903_set_pdata_from_of(struct i2c_client *i2c,
1972 struct wm8903_platform_data *pdata)
1973{
1974 const struct device_node *np = i2c->dev.of_node;
1975 u32 val32;
1976 int i;
1977
1978 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0)
1979 pdata->micdet_cfg = val32;
1980
1981 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0)
1982 pdata->micdet_delay = val32;
1983
1984 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg,
1985 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) {
1986 /*
1987 * In device tree: 0 means "write 0",
1988 * 0xffffffff means "don't touch".
1989 *
1990 * In platform data: 0 means "don't touch",
1991 * 0x8000 means "write 0".
1992 *
1993 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
1994 *
1995 * Convert from DT to pdata representation here,
1996 * so no other code needs to change.
1997 */
1998 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1999 if (pdata->gpio_cfg[i] == 0) {
2000 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO;
2001 } else if (pdata->gpio_cfg[i] == 0xffffffff) {
2002 pdata->gpio_cfg[i] = 0;
2003 } else if (pdata->gpio_cfg[i] > 0x7fff) {
2004 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n",
2005 i, pdata->gpio_cfg[i]);
2006 return -EINVAL;
2007 }
2008 }
2009 }
2010
2011 return 0;
2012}
2013
7a79e94e
BP		 2014static int wm8903_i2c_probe(struct i2c_client *i2c,
2015 const struct i2c_device_id *id)
f0fba2ad 2016{
c0eb27cf 2017 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
f0fba2ad 2018 struct wm8903_priv *wm8903;
b7c95d91 2019 int trigger;
20c5fd39 2020 bool mic_gpio = false;
b7c95d91 2021 unsigned int val, irq_pol;
20c5fd39 2022 int ret, i;
f1c0a02f 2023
2950cd22
MB		 2024 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv),
2025 GFP_KERNEL);
f0fba2ad
LG		 2026 if (wm8903 == NULL)
2027 return -ENOMEM;
78660af7
LPC		 2028
2029 mutex_init(&wm8903->lock);
0bf79ef2 2030 wm8903->dev = &i2c->dev;
8abd16a6 2031
7d116684 2032 wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap);
ee244ce4
MB		 2033 if (IS_ERR(wm8903->regmap)) {
2034 ret = PTR_ERR(wm8903->regmap);
2035 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2036 ret);
2037 return ret;
2038 }
2039
f0fba2ad 2040 i2c_set_clientdata(i2c, wm8903);
d58d5d55 2041
c0eb27cf
SW		 2042 /* If no platform data was supplied, create storage for defaults */
2043 if (pdata) {
2044 wm8903->pdata = pdata;
2045 } else {
2046 wm8903->pdata = devm_kzalloc(&i2c->dev,
2047 sizeof(struct wm8903_platform_data),
2048 GFP_KERNEL);
2049 if (wm8903->pdata == NULL) {
2050 dev_err(&i2c->dev, "Failed to allocate pdata\n");
2051 return -ENOMEM;
2052 }
9d35f3e1
SW		 2053
2054 if (i2c->irq) {
2055 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata);
2056 if (ret != 0)
2057 return ret;
2058 }
5d680b3a
SW		 2059
2060 if (i2c->dev.of_node) {
2061 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata);
2062 if (ret != 0)
2063 return ret;
2064 }
c0eb27cf
SW		 2065 }
2066
20c5fd39
MB		 2067 pdata = wm8903->pdata;
2068
7d46a528
MB		 2069 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
2070 if (ret != 0) {
2071 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
2072 goto err;
2073 }
2074 if (val != 0x8903) {
2075 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
2076 ret = -ENODEV;
2077 goto err;
2078 }
2079
2080 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
2081 if (ret != 0) {
2082 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
2083 goto err;
2084 }
2085 dev_info(&i2c->dev, "WM8903 revision %c\n",
2086 (val & WM8903_CHIP_REV_MASK) + 'A');
2087
2088 /* Reset the device */
2089 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
2090
0bf79ef2
SW		 2091 wm8903_init_gpio(wm8903);
2092
20c5fd39
MB		 2093 /* Set up GPIO pin state, detect if any are MIC detect outputs */
2094 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
2095 if ((!pdata->gpio_cfg[i]) ||
2096 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))
2097 continue;
2098
2099 regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i,
2100 pdata->gpio_cfg[i] & 0x7fff);
2101
2102 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
2103 >> WM8903_GP1_FN_SHIFT;
2104
2105 switch (val) {
2106 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
2107 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
2108 mic_gpio = true;
2109 break;
2110 default:
2111 break;
2112 }
2113 }
2114
2115 /* Set up microphone detection */
2116 regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0,
2117 pdata->micdet_cfg);
2118
2119 /* Microphone detection needs the WSEQ clock */
2120 if (pdata->micdet_cfg)
2121 regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0,
2122 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
2123
2124 /* If microphone detection is enabled by pdata but
2125 * detected via IRQ then interrupts can be lost before
2126 * the machine driver has set up microphone detection
2127 * IRQs as the IRQs are clear on read. The detection
2128 * will be enabled when the machine driver configures.
2129 */
2130 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
2131
2132 wm8903->mic_delay = pdata->micdet_delay;
2133
b7c95d91
MB		 2134 if (i2c->irq) {
2135 if (pdata->irq_active_low) {
2136 trigger = IRQF_TRIGGER_LOW;
2137 irq_pol = WM8903_IRQ_POL;
2138 } else {
2139 trigger = IRQF_TRIGGER_HIGH;
2140 irq_pol = 0;
2141 }
2142
2143 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL,
2144 WM8903_IRQ_POL, irq_pol);
2145
2146 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
2147 trigger | IRQF_ONESHOT,
2148 "wm8903", wm8903);
2149 if (ret != 0) {
2150 dev_err(wm8903->dev, "Failed to request IRQ: %d\n",
2151 ret);
2152 return ret;
2153 }
2154
2155 /* Enable write sequencer interrupts */
2156 regmap_update_bits(wm8903->regmap,
2157 WM8903_INTERRUPT_STATUS_1_MASK,
2158 WM8903_IM_WSEQ_BUSY_EINT, 0);
2159 }
2160
a89c3e95
MB		 2161 /* Latch volume update bits */
2162 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT,
2163 WM8903_ADCVU, WM8903_ADCVU);
2164 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT,
2165 WM8903_ADCVU, WM8903_ADCVU);
2166
2167 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT,
2168 WM8903_DACVU, WM8903_DACVU);
2169 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT,
2170 WM8903_DACVU, WM8903_DACVU);
2171
2172 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT,
2173 WM8903_HPOUTVU, WM8903_HPOUTVU);
2174 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT,
2175 WM8903_HPOUTVU, WM8903_HPOUTVU);
2176
2177 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT,
2178 WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2179 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT,
2180 WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2181
2182 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT,
2183 WM8903_SPKVU, WM8903_SPKVU);
2184 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT,
2185 WM8903_SPKVU, WM8903_SPKVU);
2186
2187 /* Enable DAC soft mute by default */
2188 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1,
2189 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2190 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
2191
f0fba2ad
LG		 2192 ret = snd_soc_register_codec(&i2c->dev,
2193 &soc_codec_dev_wm8903, &wm8903_dai, 1);
ee244ce4
MB		 2194 if (ret != 0)
2195 goto err;
2950cd22 2196
ee244ce4
MB		 2197 return 0;
2198err:
f0fba2ad
LG		 2199 return ret;
2200}
f1c0a02f 2201
7a79e94e 2202static int wm8903_i2c_remove(struct i2c_client *client)
f0fba2ad 2203{
ee244ce4
MB		 2204 struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
2205
b7c95d91
MB		 2206 if (client->irq)
2207 free_irq(client->irq, wm8903);
0bf79ef2 2208 wm8903_free_gpio(wm8903);
f0fba2ad 2209 snd_soc_unregister_codec(&client->dev);
ee244ce4 2210
f1c0a02f
MB		 2211 return 0;
2212}
2213
f18b4e2e
SW		 2214static const struct of_device_id wm8903_of_match[] = {
2215 { .compatible = "wlf,wm8903", },
2216 {},
2217};
2218MODULE_DEVICE_TABLE(of, wm8903_of_match);
2219
f1c0a02f 2220static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2221 { "wm8903", 0 },
2222 { }
f1c0a02f
MB		 2223};
2224MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2225
2226static struct i2c_driver wm8903_i2c_driver = {
2227 .driver = {
4b592c91 2228 .name = "wm8903",
f1c0a02f 2229 .owner = THIS_MODULE,
f18b4e2e 2230 .of_match_table = wm8903_of_match,
f1c0a02f 2231 },
f0fba2ad 2232 .probe = wm8903_i2c_probe,
7a79e94e 2233 .remove = wm8903_i2c_remove,
f1c0a02f
MB		 2234 .id_table = wm8903_i2c_id,
2235};
2236
5c86ea44 2237module_i2c_driver(wm8903_i2c_driver);
64089b84 2238
f1c0a02f
MB		 2239MODULE_DESCRIPTION("ASoC WM8903 driver");
2240MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2241MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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