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ASoC: Display WM8903 chip revision alphabetically
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f
MB		 40/* Register defaults at reset */
41static u16 wm8903_reg_defaults[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
44 0x0000, /* R2 */
45 0x0000, /* R3 */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
49 0x0000, /* R7 */
50 0x0001, /* R8 - Analogue DAC 0 */
51 0x0000, /* R9 */
52 0x0001, /* R10 - Analogue ADC 0 */
53 0x0000, /* R11 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
61 0x0000, /* R19 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
65 0x0000, /* R23 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
70 0x0000, /* R28 */
71 0x0000, /* R29 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
76 0x0000, /* R34 */
77 0x0000, /* R35 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0000, /* R48 */
91 0x0000, /* R49 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
98 0x0000, /* R56 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
103 0x0100, /* R61 */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
106 0x0000, /* R64 */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
108 0x0000, /* R66 */
109 0x0010, /* R67 - DC Servo 0 */
110 0x0100, /* R68 */
111 0x00A4, /* R69 - DC Servo 2 */
112 0x0807, /* R70 */
113 0x0000, /* R71 */
114 0x0000, /* R72 */
115 0x0000, /* R73 */
116 0x0000, /* R74 */
117 0x0000, /* R75 */
118 0x0000, /* R76 */
119 0x0000, /* R77 */
120 0x0000, /* R78 */
121 0x000E, /* R79 */
122 0x0000, /* R80 */
123 0x0000, /* R81 */
124 0x0000, /* R82 */
125 0x0000, /* R83 */
126 0x0000, /* R84 */
127 0x0000, /* R85 */
128 0x0000, /* R86 */
129 0x0006, /* R87 */
130 0x0000, /* R88 */
131 0x0000, /* R89 */
132 0x0000, /* R90 - Analogue HP 0 */
133 0x0060, /* R91 */
134 0x0000, /* R92 */
135 0x0000, /* R93 */
136 0x0000, /* R94 - Analogue Lineout 0 */
137 0x0060, /* R95 */
138 0x0000, /* R96 */
139 0x0000, /* R97 */
140 0x0000, /* R98 - Charge Pump 0 */
141 0x1F25, /* R99 */
142 0x2B19, /* R100 */
143 0x01C0, /* R101 */
144 0x01EF, /* R102 */
145 0x2B00, /* R103 */
146 0x0000, /* R104 - Class W 0 */
147 0x01C0, /* R105 */
148 0x1C10, /* R106 */
149 0x0000, /* R107 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
155 0x0000, /* R113 */
156 0x0000, /* R114 - Control Interface */
157 0x0000, /* R115 */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R124 */
167 0x0003, /* R125 */
168 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R127 */
170 0x0005, /* R128 */
171 0x0000, /* R129 - Control Interface Test 1 */
172 0x0000, /* R130 */
173 0x0000, /* R131 */
174 0x0000, /* R132 */
175 0x0000, /* R133 */
176 0x0000, /* R134 */
177 0x03FF, /* R135 */
178 0x0007, /* R136 */
179 0x0040, /* R137 */
180 0x0000, /* R138 */
181 0x0000, /* R139 */
182 0x0000, /* R140 */
183 0x0000, /* R141 */
184 0x0000, /* R142 */
185 0x0000, /* R143 */
186 0x0000, /* R144 */
187 0x0000, /* R145 */
188 0x0000, /* R146 */
189 0x0000, /* R147 */
190 0x4000, /* R148 */
191 0x6810, /* R149 - Charge Pump Test 1 */
192 0x0004, /* R150 */
193 0x0000, /* R151 */
194 0x0000, /* R152 */
195 0x0000, /* R153 */
196 0x0000, /* R154 */
197 0x0000, /* R155 */
198 0x0000, /* R156 */
199 0x0000, /* R157 */
200 0x0000, /* R158 */
201 0x0000, /* R159 */
202 0x0000, /* R160 */
203 0x0000, /* R161 */
204 0x0000, /* R162 */
205 0x0000, /* R163 */
206 0x0028, /* R164 - Clock Rate Test 4 */
207 0x0004, /* R165 */
208 0x0000, /* R166 */
209 0x0060, /* R167 */
210 0x0000, /* R168 */
211 0x0000, /* R169 */
212 0x0000, /* R170 */
213 0x0000, /* R171 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
215};
216
d58d5d55 217struct wm8903_priv {
7cfe5617 218 struct snd_soc_codec *codec;
f0fba2ad 219
d58d5d55 220 int sysclk;
f0fba2ad 221 int irq;
d58d5d55 222
69fff9bb
MB		 223 int fs;
224 int deemph;
225
f2c1fe09 226 /* Reference count */
d58d5d55 227 int class_w_users;
d58d5d55 228
8abd16a6
MB		 229 struct completion wseq;
230
7245387e
MB		 231 struct snd_soc_jack *mic_jack;
232 int mic_det;
233 int mic_short;
234 int mic_last_report;
235 int mic_delay;
7cfe5617
SW		 236
237#ifdef CONFIG_GPIOLIB
238 struct gpio_chip gpio_chip;
239#endif
d58d5d55
MB		 240};
241
d4754ec9 242static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 243{
244 switch (reg) {
245 case WM8903_SW_RESET_AND_ID:
246 case WM8903_REVISION_NUMBER:
247 case WM8903_INTERRUPT_STATUS_1:
248 case WM8903_WRITE_SEQUENCER_4:
8d50e447 249 return 1;
f1c0a02f
MB		 250
251 default:
f1c0a02f 252 return 0;
8d50e447 253 }
f1c0a02f
MB		 254}
255
256static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
257{
258 u16 reg[5];
b2c812e2 259 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 260
261 BUG_ON(start > 48);
262
37f88e84 263 /* Enable the sequencer if it's not already on */
8d50e447 264 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 265 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
266 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 267
f0fba2ad 268 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 269
8d50e447 270 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 271 start | WM8903_WSEQ_START);
272
273 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 274 * that will break us out of the poll early.
f1c0a02f
MB		 275 */
276 do {
8abd16a6
MB		 277 wait_for_completion_timeout(&wm8903->wseq,
278 msecs_to_jiffies(10));
f1c0a02f 279
8d50e447 280 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 281 } while (reg[4] & WM8903_WSEQ_BUSY);
282
f0fba2ad 283 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 284
37f88e84
MB		 285 /* Disable the sequencer again if we enabled it */
286 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 287
288 return 0;
289}
290
291static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
292{
293 int i;
294
295 /* There really ought to be something better we can do here :/ */
296 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 297 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 298}
299
300static void wm8903_reset(struct snd_soc_codec *codec)
301{
8d50e447 302 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 303 memcpy(codec->reg_cache, wm8903_reg_defaults,
304 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 305}
306
307#define WM8903_OUTPUT_SHORT 0x8
308#define WM8903_OUTPUT_OUT 0x4
309#define WM8903_OUTPUT_INT 0x2
310#define WM8903_OUTPUT_IN 0x1
311
42768a12
MB		 312static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
313 struct snd_kcontrol *kcontrol, int event)
314{
315 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
316 mdelay(4);
317
318 return 0;
319}
320
f1c0a02f
MB		 321/*
322 * Event for headphone and line out amplifier power changes. Special
323 * power up/down sequences are required in order to maximise pop/click
324 * performance.
325 */
326static int wm8903_output_event(struct snd_soc_dapm_widget *w,
327 struct snd_kcontrol *kcontrol, int event)
328{
329 struct snd_soc_codec *codec = w->codec;
f1c0a02f 330 u16 val;
0bc286e2 331 u16 reg;
d7d5c547
MB		 332 u16 dcs_reg;
333 u16 dcs_bit;
0bc286e2 334 int shift;
f1c0a02f
MB		 335
336 switch (w->reg) {
337 case WM8903_POWER_MANAGEMENT_2:
338 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 339 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 340 break;
341 case WM8903_POWER_MANAGEMENT_3:
342 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 343 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 344 break;
345 default:
346 BUG();
1e297a19 347 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 348 }
349
350 switch (w->shift) {
351 case 0:
352 shift = 0;
353 break;
354 case 1:
355 shift = 4;
356 break;
357 default:
358 BUG();
1e297a19 359 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 360 }
361
362 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 363 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 364
365 /* Short the output */
366 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 367 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 368 }
369
370 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 371 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 372
373 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 374 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 375
376 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 377 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 378
379 /* Turn on the output ENA_OUTP */
380 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 381 snd_soc_write(codec, reg, val);
f1c0a02f 382
d7d5c547 383 /* Enable the DC servo */
8d50e447 384 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 385 dcs_reg |= dcs_bit;
8d50e447 386 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 387
f1c0a02f
MB		 388 /* Remove the short */
389 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 390 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 391 }
392
393 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 394 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 395
396 /* Short the output */
397 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 398 snd_soc_write(codec, reg, val);
f1c0a02f 399
d7d5c547 400 /* Disable the DC servo */
8d50e447 401 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 402 dcs_reg &= ~dcs_bit;
8d50e447 403 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 404
f1c0a02f
MB		 405 /* Then disable the intermediate and output stages */
406 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
407 WM8903_OUTPUT_IN) << shift);
8d50e447 408 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 409 }
410
f1c0a02f
MB		 411 return 0;
412}
413
414/*
415 * When used with DAC outputs only the WM8903 charge pump supports
416 * operation in class W mode, providing very low power consumption
417 * when used with digital sources. Enable and disable this mode
418 * automatically depending on the mixer configuration.
419 *
420 * All the relevant controls are simple switches.
421 */
422static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
423 struct snd_ctl_elem_value *ucontrol)
424{
425 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
426 struct snd_soc_codec *codec = widget->codec;
b2c812e2 427 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 428 u16 reg;
429 int ret;
430
8d50e447 431 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 432
433 /* Turn it off if we're about to enable bypass */
434 if (ucontrol->value.integer.value[0]) {
435 if (wm8903->class_w_users == 0) {
f0fba2ad 436 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 437 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 438 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
439 }
440 wm8903->class_w_users++;
441 }
442
443 /* Implement the change */
444 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
445
446 /* If we've just disabled the last bypass path turn Class W on */
447 if (!ucontrol->value.integer.value[0]) {
448 if (wm8903->class_w_users == 1) {
f0fba2ad 449 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 450 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 451 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
452 }
453 wm8903->class_w_users--;
454 }
455
f0fba2ad 456 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 457 wm8903->class_w_users);
458
459 return ret;
460}
461
462#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
463{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
464 .info = snd_soc_info_volsw, \
465 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
466 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
467
468
69fff9bb
MB		 469static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
470
471static int wm8903_set_deemph(struct snd_soc_codec *codec)
472{
473 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
474 int val, i, best;
475
476 /* If we're using deemphasis select the nearest available sample
477 * rate.
478 */
479 if (wm8903->deemph) {
480 best = 1;
481 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
482 if (abs(wm8903_deemph[i] - wm8903->fs) <
483 abs(wm8903_deemph[best] - wm8903->fs))
484 best = i;
485 }
486
487 val = best << WM8903_DEEMPH_SHIFT;
488 } else {
489 best = 0;
490 val = 0;
491 }
492
493 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
494 best, wm8903_deemph[best]);
495
496 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
497 WM8903_DEEMPH_MASK, val);
498}
499
500static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
501 struct snd_ctl_elem_value *ucontrol)
502{
503 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
504 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
505
506 ucontrol->value.enumerated.item[0] = wm8903->deemph;
507
508 return 0;
509}
510
511static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
512 struct snd_ctl_elem_value *ucontrol)
513{
514 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
515 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
516 int deemph = ucontrol->value.enumerated.item[0];
517 int ret = 0;
518
519 if (deemph > 1)
520 return -EINVAL;
521
522 mutex_lock(&codec->mutex);
523 if (wm8903->deemph != deemph) {
524 wm8903->deemph = deemph;
525
526 wm8903_set_deemph(codec);
527
528 ret = 1;
529 }
530 mutex_unlock(&codec->mutex);
531
532 return ret;
533}
534
f1c0a02f
MB		 535/* ALSA can only do steps of .01dB */
536static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
537
291ce18c 538static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 539static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
540
541static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
542static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
543static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
544static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
545static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
546
460f4aae
MB		 547static const char *hpf_mode_text[] = {
548 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
549};
550
551static const struct soc_enum hpf_mode =
552 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
553
dcf9ada3
MB		 554static const char *osr_text[] = {
555 "Low power", "High performance"
556};
557
558static const struct soc_enum adc_osr =
559 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
560
561static const struct soc_enum dac_osr =
562 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
563
f1c0a02f
MB		 564static const char *drc_slope_text[] = {
565 "1", "1/2", "1/4", "1/8", "1/16", "0"
566};
567
568static const struct soc_enum drc_slope_r0 =
569 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
570
571static const struct soc_enum drc_slope_r1 =
572 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
573
574static const char *drc_attack_text[] = {
575 "instantaneous",
576 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
577 "46.4ms", "92.8ms", "185.6ms"
578};
579
580static const struct soc_enum drc_attack =
581 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
582
583static const char *drc_decay_text[] = {
584 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
585 "23.87s", "47.56s"
586};
587
588static const struct soc_enum drc_decay =
589 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
590
591static const char *drc_ff_delay_text[] = {
592 "5 samples", "9 samples"
593};
594
595static const struct soc_enum drc_ff_delay =
596 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
597
598static const char *drc_qr_decay_text[] = {
599 "0.725ms", "1.45ms", "5.8ms"
600};
601
602static const struct soc_enum drc_qr_decay =
603 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
604
605static const char *drc_smoothing_text[] = {
606 "Low", "Medium", "High"
607};
608
609static const struct soc_enum drc_smoothing =
610 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
611
612static const char *soft_mute_text[] = {
613 "Fast (fs/2)", "Slow (fs/32)"
614};
615
616static const struct soc_enum soft_mute =
617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
618
619static const char *mute_mode_text[] = {
620 "Hard", "Soft"
621};
622
623static const struct soc_enum mute_mode =
624 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
625
f1c0a02f
MB		 626static const char *companding_text[] = {
627 "ulaw", "alaw"
628};
629
630static const struct soc_enum dac_companding =
631 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
632
633static const struct soc_enum adc_companding =
634 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
635
636static const char *input_mode_text[] = {
637 "Single-Ended", "Differential Line", "Differential Mic"
638};
639
640static const struct soc_enum linput_mode_enum =
641 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
642
643static const struct soc_enum rinput_mode_enum =
644 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
645
646static const char *linput_mux_text[] = {
647 "IN1L", "IN2L", "IN3L"
648};
649
650static const struct soc_enum linput_enum =
651 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
652
653static const struct soc_enum linput_inv_enum =
654 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
655
656static const char *rinput_mux_text[] = {
657 "IN1R", "IN2R", "IN3R"
658};
659
660static const struct soc_enum rinput_enum =
661 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
662
663static const struct soc_enum rinput_inv_enum =
664 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
665
666
291ce18c
MB		 667static const char *sidetone_text[] = {
668 "None", "Left", "Right"
669};
670
671static const struct soc_enum lsidetone_enum =
672 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
673
674static const struct soc_enum rsidetone_enum =
675 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
676
f1c0a02f
MB		 677static const struct snd_kcontrol_new wm8903_snd_controls[] = {
678
679/* Input PGAs - No TLV since the scale depends on PGA mode */
680SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 681 7, 1, 1),
f1c0a02f
MB		 682SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
683 0, 31, 0),
684SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
685 6, 1, 0),
686
687SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 688 7, 1, 1),
f1c0a02f
MB		 689SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
690 0, 31, 0),
691SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
692 6, 1, 0),
693
694/* ADCs */
dcf9ada3 695SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 696SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
697SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 698SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
699SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
700SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 701SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 702 drc_tlv_thresh),
703SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
704SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
705SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
706SOC_ENUM("DRC Attack Rate", drc_attack),
707SOC_ENUM("DRC Decay Rate", drc_decay),
708SOC_ENUM("DRC FF Delay", drc_ff_delay),
709SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
710SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 711SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 712SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
713SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
714SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 715SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 716SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
717
718SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
719 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
720SOC_ENUM("ADC Companding Mode", adc_companding),
721SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
722
291ce18c
MB		 723SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
724 12, 0, digital_sidetone_tlv),
725
f1c0a02f 726/* DAC */
dcf9ada3 727SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 728SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
729 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
730SOC_ENUM("DAC Soft Mute Rate", soft_mute),
731SOC_ENUM("DAC Mute Mode", mute_mode),
732SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 733SOC_ENUM("DAC Companding Mode", dac_companding),
734SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 735SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
736 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 737
738/* Headphones */
739SOC_DOUBLE_R("Headphone Switch",
740 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
741 8, 1, 1),
742SOC_DOUBLE_R("Headphone ZC Switch",
743 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
744 6, 1, 0),
745SOC_DOUBLE_R_TLV("Headphone Volume",
746 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
747 0, 63, 0, out_tlv),
748
749/* Line out */
750SOC_DOUBLE_R("Line Out Switch",
751 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
752 8, 1, 1),
753SOC_DOUBLE_R("Line Out ZC Switch",
754 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
755 6, 1, 0),
756SOC_DOUBLE_R_TLV("Line Out Volume",
757 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
758 0, 63, 0, out_tlv),
759
760/* Speaker */
761SOC_DOUBLE_R("Speaker Switch",
762 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
763SOC_DOUBLE_R("Speaker ZC Switch",
764 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
765SOC_DOUBLE_R_TLV("Speaker Volume",
766 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
767 0, 63, 0, out_tlv),
768};
769
f1c0a02f
MB		 770static const struct snd_kcontrol_new linput_mode_mux =
771 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
772
773static const struct snd_kcontrol_new rinput_mode_mux =
774 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
775
776static const struct snd_kcontrol_new linput_mux =
777 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
778
779static const struct snd_kcontrol_new linput_inv_mux =
780 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
781
782static const struct snd_kcontrol_new rinput_mux =
783 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
784
785static const struct snd_kcontrol_new rinput_inv_mux =
786 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
787
291ce18c
MB		 788static const struct snd_kcontrol_new lsidetone_mux =
789 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
790
791static const struct snd_kcontrol_new rsidetone_mux =
792 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
793
f1c0a02f
MB		 794static const struct snd_kcontrol_new left_output_mixer[] = {
795SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
796SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
797SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 798SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 799};
800
801static const struct snd_kcontrol_new right_output_mixer[] = {
802SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
803SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
804SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 805SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 806};
807
808static const struct snd_kcontrol_new left_speaker_mixer[] = {
809SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
810SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
811SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
812SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 813 0, 1, 0),
f1c0a02f
MB		 814};
815
816static const struct snd_kcontrol_new right_speaker_mixer[] = {
817SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
818SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
819SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
820 1, 1, 0),
821SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 822 0, 1, 0),
f1c0a02f
MB		 823};
824
825static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
826SND_SOC_DAPM_INPUT("IN1L"),
827SND_SOC_DAPM_INPUT("IN1R"),
828SND_SOC_DAPM_INPUT("IN2L"),
829SND_SOC_DAPM_INPUT("IN2R"),
830SND_SOC_DAPM_INPUT("IN3L"),
831SND_SOC_DAPM_INPUT("IN3R"),
832
833SND_SOC_DAPM_OUTPUT("HPOUTL"),
834SND_SOC_DAPM_OUTPUT("HPOUTR"),
835SND_SOC_DAPM_OUTPUT("LINEOUTL"),
836SND_SOC_DAPM_OUTPUT("LINEOUTR"),
837SND_SOC_DAPM_OUTPUT("LOP"),
838SND_SOC_DAPM_OUTPUT("LON"),
839SND_SOC_DAPM_OUTPUT("ROP"),
840SND_SOC_DAPM_OUTPUT("RON"),
841
842SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
843
844SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
845SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
846 &linput_inv_mux),
847SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
848
849SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
850SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
851 &rinput_inv_mux),
852SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
853
854SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
855SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
856
857SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
858SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
859
291ce18c
MB		 860SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
861SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
862
f1c0a02f
MB		 863SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
864SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
865
866SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
867 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
868SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
869 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
870
871SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
872 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
873SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
874 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
875
876SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
877 1, 0, NULL, 0, wm8903_output_event,
878 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 879 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 880SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
881 0, 0, NULL, 0, wm8903_output_event,
882 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 883 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 884
885SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
886 NULL, 0, wm8903_output_event,
887 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 888 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 889SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
890 NULL, 0, wm8903_output_event,
891 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 892 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 893
894SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
895 NULL, 0),
896SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
897 NULL, 0),
898
42768a12
MB		 899SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
900 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 901SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 902};
903
904static const struct snd_soc_dapm_route intercon[] = {
905
906 { "Left Input Mux", "IN1L", "IN1L" },
907 { "Left Input Mux", "IN2L", "IN2L" },
908 { "Left Input Mux", "IN3L", "IN3L" },
909
910 { "Left Input Inverting Mux", "IN1L", "IN1L" },
911 { "Left Input Inverting Mux", "IN2L", "IN2L" },
912 { "Left Input Inverting Mux", "IN3L", "IN3L" },
913
914 { "Right Input Mux", "IN1R", "IN1R" },
915 { "Right Input Mux", "IN2R", "IN2R" },
916 { "Right Input Mux", "IN3R", "IN3R" },
917
918 { "Right Input Inverting Mux", "IN1R", "IN1R" },
919 { "Right Input Inverting Mux", "IN2R", "IN2R" },
920 { "Right Input Inverting Mux", "IN3R", "IN3R" },
921
922 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
923 { "Left Input Mode Mux", "Differential Line",
924 "Left Input Mux" },
925 { "Left Input Mode Mux", "Differential Line",
926 "Left Input Inverting Mux" },
927 { "Left Input Mode Mux", "Differential Mic",
928 "Left Input Mux" },
929 { "Left Input Mode Mux", "Differential Mic",
930 "Left Input Inverting Mux" },
931
932 { "Right Input Mode Mux", "Single-Ended",
933 "Right Input Inverting Mux" },
934 { "Right Input Mode Mux", "Differential Line",
935 "Right Input Mux" },
936 { "Right Input Mode Mux", "Differential Line",
937 "Right Input Inverting Mux" },
938 { "Right Input Mode Mux", "Differential Mic",
939 "Right Input Mux" },
940 { "Right Input Mode Mux", "Differential Mic",
941 "Right Input Inverting Mux" },
942
943 { "Left Input PGA", NULL, "Left Input Mode Mux" },
944 { "Right Input PGA", NULL, "Right Input Mode Mux" },
945
946 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 947 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 948 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 949 { "ADCR", NULL, "CLK_DSP" },
950
291ce18c
MB		 951 { "DACL Sidetone", "Left", "ADCL" },
952 { "DACL Sidetone", "Right", "ADCR" },
953 { "DACR Sidetone", "Left", "ADCL" },
954 { "DACR Sidetone", "Right", "ADCR" },
955
956 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 957 { "DACL", NULL, "CLK_DSP" },
291ce18c 958 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 959 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 960
961 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
962 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
963 { "Left Output Mixer", "DACL Switch", "DACL" },
964 { "Left Output Mixer", "DACR Switch", "DACR" },
965
966 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
967 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
968 { "Right Output Mixer", "DACL Switch", "DACL" },
969 { "Right Output Mixer", "DACR Switch", "DACR" },
970
971 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
972 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
973 { "Left Speaker Mixer", "DACL Switch", "DACL" },
974 { "Left Speaker Mixer", "DACR Switch", "DACR" },
975
976 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
977 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
978 { "Right Speaker Mixer", "DACL Switch", "DACL" },
979 { "Right Speaker Mixer", "DACR Switch", "DACR" },
980
981 { "Left Line Output PGA", NULL, "Left Output Mixer" },
982 { "Right Line Output PGA", NULL, "Right Output Mixer" },
983
984 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
985 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
986
987 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
988 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
989
990 { "HPOUTL", NULL, "Left Headphone Output PGA" },
991 { "HPOUTR", NULL, "Right Headphone Output PGA" },
992
993 { "LINEOUTL", NULL, "Left Line Output PGA" },
994 { "LINEOUTR", NULL, "Right Line Output PGA" },
995
996 { "LOP", NULL, "Left Speaker PGA" },
997 { "LON", NULL, "Left Speaker PGA" },
998
999 { "ROP", NULL, "Right Speaker PGA" },
1000 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1001
1002 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1003 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1004 { "Left Line Output PGA", NULL, "Charge Pump" },
1005 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1006};
1007
1008static int wm8903_add_widgets(struct snd_soc_codec *codec)
1009{
ce6120cc 1010 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 1011
ce6120cc
LG		 1012 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1013 ARRAY_SIZE(wm8903_dapm_widgets));
1014 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 1015
f1c0a02f
MB		 1016 return 0;
1017}
1018
1019static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1020 enum snd_soc_bias_level level)
1021{
524d7692 1022 u16 reg;
f1c0a02f
MB		 1023
1024 switch (level) {
1025 case SND_SOC_BIAS_ON:
1026 case SND_SOC_BIAS_PREPARE:
8d50e447 1027 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1028 reg &= ~(WM8903_VMID_RES_MASK);
1029 reg |= WM8903_VMID_RES_50K;
8d50e447 1030 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1031 break;
1032
1033 case SND_SOC_BIAS_STANDBY:
ce6120cc 1034 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 1035 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 1036 WM8903_CLK_SYS_ENA);
1037
4dbfe809 1038 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 1039 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1040 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1041 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 1042
f1c0a02f
MB		 1043 wm8903_run_sequence(codec, 0);
1044 wm8903_sync_reg_cache(codec, codec->reg_cache);
1045
f1c0a02f
MB		 1046 /* By default no bypass paths are enabled so
1047 * enable Class W support.
1048 */
f0fba2ad 1049 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1050 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1051 WM8903_CP_DYN_FREQ |
1052 WM8903_CP_DYN_V,
1053 WM8903_CP_DYN_FREQ |
1054 WM8903_CP_DYN_V);
f1c0a02f
MB		 1055 }
1056
8d50e447 1057 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1058 reg &= ~(WM8903_VMID_RES_MASK);
1059 reg |= WM8903_VMID_RES_250K;
8d50e447 1060 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1061 break;
1062
1063 case SND_SOC_BIAS_OFF:
1064 wm8903_run_sequence(codec, 32);
8d50e447 1065 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 1066 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 1067 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1068 break;
1069 }
1070
ce6120cc 1071 codec->dapm.bias_level = level;
f1c0a02f
MB		 1072
1073 return 0;
1074}
1075
1076static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1077 int clk_id, unsigned int freq, int dir)
1078{
1079 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1080 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1081
1082 wm8903->sysclk = freq;
1083
1084 return 0;
1085}
1086
1087static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1088 unsigned int fmt)
1089{
1090 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1091 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1092
1093 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1094 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1095
1096 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1097 case SND_SOC_DAIFMT_CBS_CFS:
1098 break;
1099 case SND_SOC_DAIFMT_CBS_CFM:
1100 aif1 |= WM8903_LRCLK_DIR;
1101 break;
1102 case SND_SOC_DAIFMT_CBM_CFM:
1103 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1104 break;
1105 case SND_SOC_DAIFMT_CBM_CFS:
1106 aif1 |= WM8903_BCLK_DIR;
1107 break;
1108 default:
1109 return -EINVAL;
1110 }
1111
1112 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1113 case SND_SOC_DAIFMT_DSP_A:
1114 aif1 |= 0x3;
1115 break;
1116 case SND_SOC_DAIFMT_DSP_B:
1117 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1118 break;
1119 case SND_SOC_DAIFMT_I2S:
1120 aif1 |= 0x2;
1121 break;
1122 case SND_SOC_DAIFMT_RIGHT_J:
1123 aif1 |= 0x1;
1124 break;
1125 case SND_SOC_DAIFMT_LEFT_J:
1126 break;
1127 default:
1128 return -EINVAL;
1129 }
1130
1131 /* Clock inversion */
1132 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1133 case SND_SOC_DAIFMT_DSP_A:
1134 case SND_SOC_DAIFMT_DSP_B:
1135 /* frame inversion not valid for DSP modes */
1136 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1137 case SND_SOC_DAIFMT_NB_NF:
1138 break;
1139 case SND_SOC_DAIFMT_IB_NF:
1140 aif1 |= WM8903_AIF_BCLK_INV;
1141 break;
1142 default:
1143 return -EINVAL;
1144 }
1145 break;
1146 case SND_SOC_DAIFMT_I2S:
1147 case SND_SOC_DAIFMT_RIGHT_J:
1148 case SND_SOC_DAIFMT_LEFT_J:
1149 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1150 case SND_SOC_DAIFMT_NB_NF:
1151 break;
1152 case SND_SOC_DAIFMT_IB_IF:
1153 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1154 break;
1155 case SND_SOC_DAIFMT_IB_NF:
1156 aif1 |= WM8903_AIF_BCLK_INV;
1157 break;
1158 case SND_SOC_DAIFMT_NB_IF:
1159 aif1 |= WM8903_AIF_LRCLK_INV;
1160 break;
1161 default:
1162 return -EINVAL;
1163 }
1164 break;
1165 default:
1166 return -EINVAL;
1167 }
1168
8d50e447 1169 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1170
1171 return 0;
1172}
1173
1174static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1175{
1176 struct snd_soc_codec *codec = codec_dai->codec;
1177 u16 reg;
1178
8d50e447 1179 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1180
1181 if (mute)
1182 reg |= WM8903_DAC_MUTE;
1183 else
1184 reg &= ~WM8903_DAC_MUTE;
1185
8d50e447 1186 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1187
1188 return 0;
1189}
1190
1191/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1192 * for optimal performance so we list the lower rates first and match
1193 * on the last match we find. */
1194static struct {
1195 int div;
1196 int rate;
1197 int mode;
1198 int mclk_div;
1199} clk_sys_ratios[] = {
1200 { 64, 0x0, 0x0, 1 },
1201 { 68, 0x0, 0x1, 1 },
1202 { 125, 0x0, 0x2, 1 },
1203 { 128, 0x1, 0x0, 1 },
1204 { 136, 0x1, 0x1, 1 },
1205 { 192, 0x2, 0x0, 1 },
1206 { 204, 0x2, 0x1, 1 },
1207
1208 { 64, 0x0, 0x0, 2 },
1209 { 68, 0x0, 0x1, 2 },
1210 { 125, 0x0, 0x2, 2 },
1211 { 128, 0x1, 0x0, 2 },
1212 { 136, 0x1, 0x1, 2 },
1213 { 192, 0x2, 0x0, 2 },
1214 { 204, 0x2, 0x1, 2 },
1215
1216 { 250, 0x2, 0x2, 1 },
1217 { 256, 0x3, 0x0, 1 },
1218 { 272, 0x3, 0x1, 1 },
1219 { 384, 0x4, 0x0, 1 },
1220 { 408, 0x4, 0x1, 1 },
1221 { 375, 0x4, 0x2, 1 },
1222 { 512, 0x5, 0x0, 1 },
1223 { 544, 0x5, 0x1, 1 },
1224 { 500, 0x5, 0x2, 1 },
1225 { 768, 0x6, 0x0, 1 },
1226 { 816, 0x6, 0x1, 1 },
1227 { 750, 0x6, 0x2, 1 },
1228 { 1024, 0x7, 0x0, 1 },
1229 { 1088, 0x7, 0x1, 1 },
1230 { 1000, 0x7, 0x2, 1 },
1231 { 1408, 0x8, 0x0, 1 },
1232 { 1496, 0x8, 0x1, 1 },
1233 { 1536, 0x9, 0x0, 1 },
1234 { 1632, 0x9, 0x1, 1 },
1235 { 1500, 0x9, 0x2, 1 },
1236
1237 { 250, 0x2, 0x2, 2 },
1238 { 256, 0x3, 0x0, 2 },
1239 { 272, 0x3, 0x1, 2 },
1240 { 384, 0x4, 0x0, 2 },
1241 { 408, 0x4, 0x1, 2 },
1242 { 375, 0x4, 0x2, 2 },
1243 { 512, 0x5, 0x0, 2 },
1244 { 544, 0x5, 0x1, 2 },
1245 { 500, 0x5, 0x2, 2 },
1246 { 768, 0x6, 0x0, 2 },
1247 { 816, 0x6, 0x1, 2 },
1248 { 750, 0x6, 0x2, 2 },
1249 { 1024, 0x7, 0x0, 2 },
1250 { 1088, 0x7, 0x1, 2 },
1251 { 1000, 0x7, 0x2, 2 },
1252 { 1408, 0x8, 0x0, 2 },
1253 { 1496, 0x8, 0x1, 2 },
1254 { 1536, 0x9, 0x0, 2 },
1255 { 1632, 0x9, 0x1, 2 },
1256 { 1500, 0x9, 0x2, 2 },
1257};
1258
1259/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1260static struct {
1261 int ratio;
1262 int div;
1263} bclk_divs[] = {
1264 { 10, 0 },
f1c0a02f
MB		 1265 { 20, 2 },
1266 { 30, 3 },
1267 { 40, 4 },
1268 { 50, 5 },
f1c0a02f
MB		 1269 { 60, 7 },
1270 { 80, 8 },
1271 { 100, 9 },
f1c0a02f
MB		 1272 { 120, 11 },
1273 { 160, 12 },
1274 { 200, 13 },
1275 { 220, 14 },
1276 { 240, 15 },
f1c0a02f
MB		 1277 { 300, 17 },
1278 { 320, 18 },
1279 { 440, 19 },
1280 { 480, 20 },
1281};
1282
1283/* Sample rates for DSP */
1284static struct {
1285 int rate;
1286 int value;
1287} sample_rates[] = {
1288 { 8000, 0 },
1289 { 11025, 1 },
1290 { 12000, 2 },
1291 { 16000, 3 },
1292 { 22050, 4 },
1293 { 24000, 5 },
1294 { 32000, 6 },
1295 { 44100, 7 },
1296 { 48000, 8 },
1297 { 88200, 9 },
1298 { 96000, 10 },
1299 { 0, 0 },
1300};
1301
f1c0a02f 1302static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1303 struct snd_pcm_hw_params *params,
1304 struct snd_soc_dai *dai)
f1c0a02f
MB		 1305{
1306 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1307 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1308 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1309 int fs = params_rate(params);
1310 int bclk;
1311 int bclk_div;
1312 int i;
1313 int dsp_config;
1314 int clk_config;
1315 int best_val;
1316 int cur_val;
1317 int clk_sys;
1318
8d50e447
MB		 1319 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1320 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1321 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1322 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1323 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1324 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1325
9e79261f
MB		 1326 /* Enable sloping stopband filter for low sample rates */
1327 if (fs <= 24000)
1328 dac_digital1 |= WM8903_DAC_SB_FILT;
1329 else
1330 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1331
f1c0a02f
MB		 1332 /* Configure sample rate logic for DSP - choose nearest rate */
1333 dsp_config = 0;
1334 best_val = abs(sample_rates[dsp_config].rate - fs);
1335 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1336 cur_val = abs(sample_rates[i].rate - fs);
1337 if (cur_val <= best_val) {
1338 dsp_config = i;
1339 best_val = cur_val;
1340 }
1341 }
1342
f0fba2ad 1343 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1344 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1345 clock1 |= sample_rates[dsp_config].value;
1346
1347 aif1 &= ~WM8903_AIF_WL_MASK;
1348 bclk = 2 * fs;
1349 switch (params_format(params)) {
1350 case SNDRV_PCM_FORMAT_S16_LE:
1351 bclk *= 16;
1352 break;
1353 case SNDRV_PCM_FORMAT_S20_3LE:
1354 bclk *= 20;
1355 aif1 |= 0x4;
1356 break;
1357 case SNDRV_PCM_FORMAT_S24_LE:
1358 bclk *= 24;
1359 aif1 |= 0x8;
1360 break;
1361 case SNDRV_PCM_FORMAT_S32_LE:
1362 bclk *= 32;
1363 aif1 |= 0xc;
1364 break;
1365 default:
1366 return -EINVAL;
1367 }
1368
f0fba2ad 1369 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1370 wm8903->sysclk, fs);
1371
1372 /* We may not have an MCLK which allows us to generate exactly
1373 * the clock we want, particularly with USB derived inputs, so
1374 * approximate.
1375 */
1376 clk_config = 0;
1377 best_val = abs((wm8903->sysclk /
1378 (clk_sys_ratios[0].mclk_div *
1379 clk_sys_ratios[0].div)) - fs);
1380 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1381 cur_val = abs((wm8903->sysclk /
1382 (clk_sys_ratios[i].mclk_div *
1383 clk_sys_ratios[i].div)) - fs);
1384
1385 if (cur_val <= best_val) {
1386 clk_config = i;
1387 best_val = cur_val;
1388 }
1389 }
1390
1391 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1392 clock0 |= WM8903_MCLKDIV2;
1393 clk_sys = wm8903->sysclk / 2;
1394 } else {
1395 clock0 &= ~WM8903_MCLKDIV2;
1396 clk_sys = wm8903->sysclk;
1397 }
1398
1399 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1400 WM8903_CLK_SYS_MODE_MASK);
1401 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1402 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1403
f0fba2ad 1404 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1405 clk_sys_ratios[clk_config].rate,
1406 clk_sys_ratios[clk_config].mode,
1407 clk_sys_ratios[clk_config].div);
1408
f0fba2ad 1409 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1410
1411 /* We may not get quite the right frequency if using
1412 * approximate clocks so look for the closest match that is
1413 * higher than the target (we need to ensure that there enough
1414 * BCLKs to clock out the samples).
1415 */
1416 bclk_div = 0;
1417 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1418 i = 1;
1419 while (i < ARRAY_SIZE(bclk_divs)) {
1420 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1421 if (cur_val < 0) /* BCLK table is sorted */
1422 break;
1423 bclk_div = i;
1424 best_val = cur_val;
1425 i++;
1426 }
1427
1428 aif2 &= ~WM8903_BCLK_DIV_MASK;
1429 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1430
f0fba2ad 1431 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1432 bclk_divs[bclk_div].ratio / 10, bclk,
1433 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1434
1435 aif2 |= bclk_divs[bclk_div].div;
1436 aif3 |= bclk / fs;
1437
69fff9bb
MB		 1438 wm8903->fs = params_rate(params);
1439 wm8903_set_deemph(codec);
1440
8d50e447
MB		 1441 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1442 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1443 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1444 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1445 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1446 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1447
1448 return 0;
1449}
1450
7245387e
MB		 1451/**
1452 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1453 *
1454 * @codec: WM8903 codec
1455 * @jack: jack to report detection events on
1456 * @det: value to report for presence detection
1457 * @shrt: value to report for short detection
1458 *
1459 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1460 * being used to bring out signals to the processor then only platform
1461 * data configuration is needed for WM8903 and processor GPIOs should
1462 * be configured using snd_soc_jack_add_gpios() instead.
1463 *
1464 * The current threasholds for detection should be configured using
1465 * micdet_cfg in the platform data. Using this function will force on
1466 * the microphone bias for the device.
1467 */
1468int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1469 int det, int shrt)
1470{
b2c812e2 1471 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1472 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1473
1474 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1475 det, shrt);
1476
1477 /* Store the configuration */
1478 wm8903->mic_jack = jack;
1479 wm8903->mic_det = det;
1480 wm8903->mic_short = shrt;
1481
1482 /* Enable interrupts we've got a report configured for */
1483 if (det)
1484 irq_mask &= ~WM8903_MICDET_EINT;
1485 if (shrt)
1486 irq_mask &= ~WM8903_MICSHRT_EINT;
1487
1488 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1489 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1490 irq_mask);
1491
69266866
MB		 1492 if (det && shrt) {
1493 /* Enable mic detection, this may not have been set through
1494 * platform data (eg, if the defaults are OK). */
1495 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1496 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1497 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1498 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1499 } else {
1500 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1501 WM8903_MICDET_ENA, 0);
1502 }
7245387e
MB		 1503
1504 return 0;
1505}
1506EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1507
8abd16a6
MB		 1508static irqreturn_t wm8903_irq(int irq, void *data)
1509{
f0fba2ad
LG		 1510 struct snd_soc_codec *codec = data;
1511 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1512 int mic_report;
1513 int int_pol;
1514 int int_val = 0;
1515 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1516
7245387e 1517 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1518
7245387e 1519 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1520 dev_dbg(codec->dev, "Write sequencer done\n");
1521 complete(&wm8903->wseq);
1522 }
1523
7245387e
MB		 1524 /*
1525 * The rest is microphone jack detection. We need to manually
1526 * invert the polarity of the interrupt after each event - to
1527 * simplify the code keep track of the last state we reported
1528 * and just invert the relevant bits in both the report and
1529 * the polarity register.
1530 */
1531 mic_report = wm8903->mic_last_report;
1532 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1533
1435b940 1534#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1535 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1536 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1537#endif
2bbb5d66 1538
7245387e
MB		 1539 if (int_val & WM8903_MICSHRT_EINT) {
1540 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1541
1542 mic_report ^= wm8903->mic_short;
1543 int_pol ^= WM8903_MICSHRT_INV;
1544 }
1545
1546 if (int_val & WM8903_MICDET_EINT) {
1547 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1548
1549 mic_report ^= wm8903->mic_det;
1550 int_pol ^= WM8903_MICDET_INV;
1551
1552 msleep(wm8903->mic_delay);
1553 }
1554
1555 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1556 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1557
1558 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1559 wm8903->mic_short | wm8903->mic_det);
1560
1561 wm8903->mic_last_report = mic_report;
1562
8abd16a6
MB		 1563 return IRQ_HANDLED;
1564}
1565
f1c0a02f
MB		 1566#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1567 SNDRV_PCM_RATE_11025 | \
1568 SNDRV_PCM_RATE_16000 | \
1569 SNDRV_PCM_RATE_22050 | \
1570 SNDRV_PCM_RATE_32000 | \
1571 SNDRV_PCM_RATE_44100 | \
1572 SNDRV_PCM_RATE_48000 | \
1573 SNDRV_PCM_RATE_88200 | \
1574 SNDRV_PCM_RATE_96000)
1575
1576#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1577 SNDRV_PCM_RATE_11025 | \
1578 SNDRV_PCM_RATE_16000 | \
1579 SNDRV_PCM_RATE_22050 | \
1580 SNDRV_PCM_RATE_32000 | \
1581 SNDRV_PCM_RATE_44100 | \
1582 SNDRV_PCM_RATE_48000)
1583
1584#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1585 SNDRV_PCM_FMTBIT_S20_3LE |\
1586 SNDRV_PCM_FMTBIT_S24_LE)
1587
6335d055 1588static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1589 .hw_params = wm8903_hw_params,
1590 .digital_mute = wm8903_digital_mute,
1591 .set_fmt = wm8903_set_dai_fmt,
1592 .set_sysclk = wm8903_set_dai_sysclk,
1593};
1594
f0fba2ad
LG		 1595static struct snd_soc_dai_driver wm8903_dai = {
1596 .name = "wm8903-hifi",
f1c0a02f
MB		 1597 .playback = {
1598 .stream_name = "Playback",
1599 .channels_min = 2,
1600 .channels_max = 2,
1601 .rates = WM8903_PLAYBACK_RATES,
1602 .formats = WM8903_FORMATS,
1603 },
1604 .capture = {
1605 .stream_name = "Capture",
1606 .channels_min = 2,
1607 .channels_max = 2,
1608 .rates = WM8903_CAPTURE_RATES,
1609 .formats = WM8903_FORMATS,
1610 },
6335d055 1611 .ops = &wm8903_dai_ops,
0d960e88 1612 .symmetric_rates = 1,
f1c0a02f 1613};
f1c0a02f 1614
f0fba2ad 1615static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1616{
f1c0a02f
MB		 1617 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1618
1619 return 0;
1620}
1621
f0fba2ad 1622static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1623{
f1c0a02f
MB		 1624 int i;
1625 u16 *reg_cache = codec->reg_cache;
40aa7030 1626 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1627 GFP_KERNEL);
1628
1629 /* Bring the codec back up to standby first to minimise pop/clicks */
1630 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1631
1632 /* Sync back everything else */
1633 if (tmp_cache) {
1634 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1635 if (tmp_cache[i] != reg_cache[i])
8d50e447 1636 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1637 kfree(tmp_cache);
f1c0a02f 1638 } else {
f0fba2ad 1639 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1640 }
1641
1642 return 0;
1643}
1644
7cfe5617
SW		 1645#ifdef CONFIG_GPIOLIB
1646static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1647{
1648 return container_of(chip, struct wm8903_priv, gpio_chip);
1649}
1650
1651static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1652{
1653 if (offset >= WM8903_NUM_GPIO)
1654 return -EINVAL;
1655
1656 return 0;
1657}
1658
1659static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1660{
1661 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1662 struct snd_soc_codec *codec = wm8903->codec;
1663 unsigned int mask, val;
1664
1665 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1666 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1667 WM8903_GP1_DIR;
1668
1669 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1670 mask, val);
1671}
1672
1673static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1674{
1675 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1676 struct snd_soc_codec *codec = wm8903->codec;
1677 int reg;
1678
1679 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1680
1681 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1682}
1683
1684static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1685 unsigned offset, int value)
1686{
1687 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1688 struct snd_soc_codec *codec = wm8903->codec;
1689 unsigned int mask, val;
1690
1691 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1692 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1693 (value << WM8903_GP2_LVL_SHIFT);
1694
1695 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1696 mask, val);
1697}
1698
1699static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1700{
1701 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1702 struct snd_soc_codec *codec = wm8903->codec;
1703
1704 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1705 WM8903_GP1_LVL_MASK,
1706 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1707}
1708
1709static struct gpio_chip wm8903_template_chip = {
1710 .label = "wm8903",
1711 .owner = THIS_MODULE,
1712 .request = wm8903_gpio_request,
1713 .direction_input = wm8903_gpio_direction_in,
1714 .get = wm8903_gpio_get,
1715 .direction_output = wm8903_gpio_direction_out,
1716 .set = wm8903_gpio_set,
1717 .can_sleep = 1,
1718};
1719
1720static void wm8903_init_gpio(struct snd_soc_codec *codec)
1721{
1722 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1723 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1724 int ret;
1725
1726 wm8903->gpio_chip = wm8903_template_chip;
1727 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1728 wm8903->gpio_chip.dev = codec->dev;
1729
1730 if (pdata && pdata->gpio_base)
1731 wm8903->gpio_chip.base = pdata->gpio_base;
1732 else
1733 wm8903->gpio_chip.base = -1;
1734
1735 ret = gpiochip_add(&wm8903->gpio_chip);
1736 if (ret != 0)
1737 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1738}
1739
1740static void wm8903_free_gpio(struct snd_soc_codec *codec)
1741{
1742 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1743 int ret;
1744
1745 ret = gpiochip_remove(&wm8903->gpio_chip);
1746 if (ret != 0)
1747 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1748}
1749#else
1750static void wm8903_init_gpio(struct snd_soc_codec *codec)
1751{
1752}
1753
1754static void wm8903_free_gpio(struct snd_soc_codec *codec)
1755{
1756}
1757#endif
1758
f0fba2ad 1759static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1760{
f0fba2ad
LG		 1761 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1762 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1763 int ret, i;
8abd16a6 1764 int trigger, irq_pol;
f1c0a02f
MB		 1765 u16 val;
1766
7cfe5617 1767 wm8903->codec = codec;
8abd16a6 1768 init_completion(&wm8903->wseq);
d58d5d55 1769
8d50e447
MB		 1770 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1771 if (ret != 0) {
f0fba2ad
LG		 1772 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1773 return ret;
8d50e447
MB		 1774 }
1775
1776 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1777 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1778 dev_err(codec->dev,
d58d5d55
MB		 1779 "Device with ID register %x is not a WM8903\n", val);
1780 return -ENODEV;
f1c0a02f
MB		 1781 }
1782
8d50e447 1783 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1784 dev_info(codec->dev, "WM8903 revision %c\n",
1785 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1786
1787 wm8903_reset(codec);
1788
37f88e84 1789 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1790 if (pdata) {
1791 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
7cfe5617 1792 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
73b34ead
MB		 1793 continue;
1794
1795 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1796 pdata->gpio_cfg[i] & 0xffff);
1797 }
37f88e84
MB		 1798
1799 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1800 pdata->micdet_cfg);
1801
1802 /* Microphone detection needs the WSEQ clock */
1803 if (pdata->micdet_cfg)
1804 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1805 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1806
1807 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1808 }
8abd16a6 1809
f0fba2ad 1810 if (wm8903->irq) {
8abd16a6
MB		 1811 if (pdata && pdata->irq_active_low) {
1812 trigger = IRQF_TRIGGER_LOW;
1813 irq_pol = WM8903_IRQ_POL;
1814 } else {
1815 trigger = IRQF_TRIGGER_HIGH;
1816 irq_pol = 0;
1817 }
1818
1819 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1820 WM8903_IRQ_POL, irq_pol);
1821
f0fba2ad 1822 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1823 trigger | IRQF_ONESHOT,
f0fba2ad 1824 "wm8903", codec);
8abd16a6 1825 if (ret != 0) {
f0fba2ad 1826 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1827 ret);
f0fba2ad 1828 return ret;
8abd16a6
MB		 1829 }
1830
1831 /* Enable write sequencer interrupts */
1832 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1833 WM8903_IM_WSEQ_BUSY_EINT, 0);
1834 }
73b34ead 1835
f1c0a02f
MB		 1836 /* power on device */
1837 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1838
1839 /* Latch volume update bits */
8d50e447 1840 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1841 val |= WM8903_ADCVU;
8d50e447
MB		 1842 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1843 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1844
8d50e447 1845 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1846 val |= WM8903_DACVU;
8d50e447
MB		 1847 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1848 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1849
8d50e447 1850 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1851 val |= WM8903_HPOUTVU;
8d50e447
MB		 1852 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1853 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1854
8d50e447 1855 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1856 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1857 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1858 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1859
8d50e447 1860 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1861 val |= WM8903_SPKVU;
8d50e447
MB		 1862 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1863 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1864
1865 /* Enable DAC soft mute by default */
8d50e447 1866 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1867 val |= WM8903_DAC_MUTEMODE;
8d50e447 1868 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1869
f0fba2ad
LG		 1870 snd_soc_add_controls(codec, wm8903_snd_controls,
1871 ARRAY_SIZE(wm8903_snd_controls));
1872 wm8903_add_widgets(codec);
f1c0a02f 1873
7cfe5617
SW		 1874 wm8903_init_gpio(codec);
1875
f1c0a02f
MB		 1876 return ret;
1877}
1878
f0fba2ad
LG		 1879/* power down chip */
1880static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1881{
7cfe5617 1882 wm8903_free_gpio(codec);
f0fba2ad
LG		 1883 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1884 return 0;
1885}
f1c0a02f 1886
f0fba2ad
LG		 1887static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1888 .probe = wm8903_probe,
1889 .remove = wm8903_remove,
1890 .suspend = wm8903_suspend,
1891 .resume = wm8903_resume,
1892 .set_bias_level = wm8903_set_bias_level,
1893 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1894 .reg_word_size = sizeof(u16),
1895 .reg_cache_default = wm8903_reg_defaults,
1896 .volatile_register = wm8903_volatile_register,
1897};
f1c0a02f 1898
f0fba2ad
LG		 1899#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1900static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1901 const struct i2c_device_id *id)
1902{
1903 struct wm8903_priv *wm8903;
1904 int ret;
f1c0a02f 1905
f0fba2ad
LG		 1906 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1907 if (wm8903 == NULL)
1908 return -ENOMEM;
8abd16a6 1909
f0fba2ad 1910 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 1911 wm8903->irq = i2c->irq;
d58d5d55 1912
f0fba2ad
LG		 1913 ret = snd_soc_register_codec(&i2c->dev,
1914 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1915 if (ret < 0)
1916 kfree(wm8903);
1917 return ret;
1918}
f1c0a02f 1919
f0fba2ad
LG		 1920static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1921{
1922 snd_soc_unregister_codec(&client->dev);
1923 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 1924 return 0;
1925}
1926
f1c0a02f 1927static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 1928 { "wm8903", 0 },
1929 { }
f1c0a02f
MB		 1930};
1931MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1932
1933static struct i2c_driver wm8903_i2c_driver = {
1934 .driver = {
4b592c91 1935 .name = "wm8903",
f1c0a02f
MB		 1936 .owner = THIS_MODULE,
1937 },
f0fba2ad
LG		 1938 .probe = wm8903_i2c_probe,
1939 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1940 .id_table = wm8903_i2c_id,
1941};
f0fba2ad 1942#endif
f1c0a02f 1943
f0fba2ad 1944static int __init wm8903_modinit(void)
f1c0a02f 1945{
f1c0a02f 1946 int ret = 0;
f0fba2ad
LG		 1947#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1948 ret = i2c_add_driver(&wm8903_i2c_driver);
1949 if (ret != 0) {
1950 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1951 ret);
f1c0a02f 1952 }
f0fba2ad 1953#endif
f1c0a02f 1954 return ret;
64089b84
MB		 1955}
1956module_init(wm8903_modinit);
1957
1958static void __exit wm8903_exit(void)
1959{
f0fba2ad 1960#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 1961 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 1962#endif
64089b84
MB		 1963}
1964module_exit(wm8903_exit);
1965
f1c0a02f
MB		 1966MODULE_DESCRIPTION("ASoC WM8903 driver");
1967MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1968MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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