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ASoC: Add support for AIF channel muxing on WM8903
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f
MB		 40/* Register defaults at reset */
41static u16 wm8903_reg_defaults[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
44 0x0000, /* R2 */
45 0x0000, /* R3 */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
49 0x0000, /* R7 */
50 0x0001, /* R8 - Analogue DAC 0 */
51 0x0000, /* R9 */
52 0x0001, /* R10 - Analogue ADC 0 */
53 0x0000, /* R11 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
61 0x0000, /* R19 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
65 0x0000, /* R23 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
70 0x0000, /* R28 */
71 0x0000, /* R29 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
76 0x0000, /* R34 */
77 0x0000, /* R35 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0000, /* R48 */
91 0x0000, /* R49 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
98 0x0000, /* R56 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
103 0x0100, /* R61 */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
106 0x0000, /* R64 */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
108 0x0000, /* R66 */
109 0x0010, /* R67 - DC Servo 0 */
110 0x0100, /* R68 */
111 0x00A4, /* R69 - DC Servo 2 */
112 0x0807, /* R70 */
113 0x0000, /* R71 */
114 0x0000, /* R72 */
115 0x0000, /* R73 */
116 0x0000, /* R74 */
117 0x0000, /* R75 */
118 0x0000, /* R76 */
119 0x0000, /* R77 */
120 0x0000, /* R78 */
121 0x000E, /* R79 */
122 0x0000, /* R80 */
123 0x0000, /* R81 */
124 0x0000, /* R82 */
125 0x0000, /* R83 */
126 0x0000, /* R84 */
127 0x0000, /* R85 */
128 0x0000, /* R86 */
129 0x0006, /* R87 */
130 0x0000, /* R88 */
131 0x0000, /* R89 */
132 0x0000, /* R90 - Analogue HP 0 */
133 0x0060, /* R91 */
134 0x0000, /* R92 */
135 0x0000, /* R93 */
136 0x0000, /* R94 - Analogue Lineout 0 */
137 0x0060, /* R95 */
138 0x0000, /* R96 */
139 0x0000, /* R97 */
140 0x0000, /* R98 - Charge Pump 0 */
141 0x1F25, /* R99 */
142 0x2B19, /* R100 */
143 0x01C0, /* R101 */
144 0x01EF, /* R102 */
145 0x2B00, /* R103 */
146 0x0000, /* R104 - Class W 0 */
147 0x01C0, /* R105 */
148 0x1C10, /* R106 */
149 0x0000, /* R107 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
155 0x0000, /* R113 */
156 0x0000, /* R114 - Control Interface */
157 0x0000, /* R115 */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R124 */
167 0x0003, /* R125 */
168 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R127 */
170 0x0005, /* R128 */
171 0x0000, /* R129 - Control Interface Test 1 */
172 0x0000, /* R130 */
173 0x0000, /* R131 */
174 0x0000, /* R132 */
175 0x0000, /* R133 */
176 0x0000, /* R134 */
177 0x03FF, /* R135 */
178 0x0007, /* R136 */
179 0x0040, /* R137 */
180 0x0000, /* R138 */
181 0x0000, /* R139 */
182 0x0000, /* R140 */
183 0x0000, /* R141 */
184 0x0000, /* R142 */
185 0x0000, /* R143 */
186 0x0000, /* R144 */
187 0x0000, /* R145 */
188 0x0000, /* R146 */
189 0x0000, /* R147 */
190 0x4000, /* R148 */
191 0x6810, /* R149 - Charge Pump Test 1 */
192 0x0004, /* R150 */
193 0x0000, /* R151 */
194 0x0000, /* R152 */
195 0x0000, /* R153 */
196 0x0000, /* R154 */
197 0x0000, /* R155 */
198 0x0000, /* R156 */
199 0x0000, /* R157 */
200 0x0000, /* R158 */
201 0x0000, /* R159 */
202 0x0000, /* R160 */
203 0x0000, /* R161 */
204 0x0000, /* R162 */
205 0x0000, /* R163 */
206 0x0028, /* R164 - Clock Rate Test 4 */
207 0x0004, /* R165 */
208 0x0000, /* R166 */
209 0x0060, /* R167 */
210 0x0000, /* R168 */
211 0x0000, /* R169 */
212 0x0000, /* R170 */
213 0x0000, /* R171 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
215};
216
d58d5d55 217struct wm8903_priv {
7cfe5617 218 struct snd_soc_codec *codec;
f0fba2ad 219
d58d5d55 220 int sysclk;
f0fba2ad 221 int irq;
d58d5d55 222
69fff9bb
MB		 223 int fs;
224 int deemph;
225
f2c1fe09 226 /* Reference count */
d58d5d55 227 int class_w_users;
d58d5d55 228
8abd16a6
MB		 229 struct completion wseq;
230
7245387e
MB		 231 struct snd_soc_jack *mic_jack;
232 int mic_det;
233 int mic_short;
234 int mic_last_report;
235 int mic_delay;
7cfe5617
SW		 236
237#ifdef CONFIG_GPIOLIB
238 struct gpio_chip gpio_chip;
239#endif
d58d5d55
MB		 240};
241
d4754ec9 242static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 243{
244 switch (reg) {
245 case WM8903_SW_RESET_AND_ID:
246 case WM8903_REVISION_NUMBER:
247 case WM8903_INTERRUPT_STATUS_1:
248 case WM8903_WRITE_SEQUENCER_4:
8d50e447 249 return 1;
f1c0a02f
MB		 250
251 default:
f1c0a02f 252 return 0;
8d50e447 253 }
f1c0a02f
MB		 254}
255
256static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
257{
258 u16 reg[5];
b2c812e2 259 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 260
261 BUG_ON(start > 48);
262
37f88e84 263 /* Enable the sequencer if it's not already on */
8d50e447 264 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 265 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
266 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 267
f0fba2ad 268 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 269
8d50e447 270 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 271 start | WM8903_WSEQ_START);
272
273 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 274 * that will break us out of the poll early.
f1c0a02f
MB		 275 */
276 do {
8abd16a6
MB		 277 wait_for_completion_timeout(&wm8903->wseq,
278 msecs_to_jiffies(10));
f1c0a02f 279
8d50e447 280 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 281 } while (reg[4] & WM8903_WSEQ_BUSY);
282
f0fba2ad 283 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 284
37f88e84
MB		 285 /* Disable the sequencer again if we enabled it */
286 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 287
288 return 0;
289}
290
291static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
292{
293 int i;
294
295 /* There really ought to be something better we can do here :/ */
296 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 297 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 298}
299
300static void wm8903_reset(struct snd_soc_codec *codec)
301{
8d50e447 302 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 303 memcpy(codec->reg_cache, wm8903_reg_defaults,
304 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 305}
306
307#define WM8903_OUTPUT_SHORT 0x8
308#define WM8903_OUTPUT_OUT 0x4
309#define WM8903_OUTPUT_INT 0x2
310#define WM8903_OUTPUT_IN 0x1
311
42768a12
MB		 312static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
313 struct snd_kcontrol *kcontrol, int event)
314{
315 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
316 mdelay(4);
317
318 return 0;
319}
320
f1c0a02f
MB		 321/*
322 * Event for headphone and line out amplifier power changes. Special
323 * power up/down sequences are required in order to maximise pop/click
324 * performance.
325 */
326static int wm8903_output_event(struct snd_soc_dapm_widget *w,
327 struct snd_kcontrol *kcontrol, int event)
328{
329 struct snd_soc_codec *codec = w->codec;
f1c0a02f 330 u16 val;
0bc286e2 331 u16 reg;
d7d5c547
MB		 332 u16 dcs_reg;
333 u16 dcs_bit;
0bc286e2 334 int shift;
f1c0a02f
MB		 335
336 switch (w->reg) {
337 case WM8903_POWER_MANAGEMENT_2:
338 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 339 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 340 break;
341 case WM8903_POWER_MANAGEMENT_3:
342 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 343 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 344 break;
345 default:
346 BUG();
1e297a19 347 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 348 }
349
350 switch (w->shift) {
351 case 0:
352 shift = 0;
353 break;
354 case 1:
355 shift = 4;
356 break;
357 default:
358 BUG();
1e297a19 359 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 360 }
361
362 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 363 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 364
365 /* Short the output */
366 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 367 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 368 }
369
370 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 371 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 372
373 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 374 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 375
376 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 377 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 378
379 /* Turn on the output ENA_OUTP */
380 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 381 snd_soc_write(codec, reg, val);
f1c0a02f 382
d7d5c547 383 /* Enable the DC servo */
8d50e447 384 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 385 dcs_reg |= dcs_bit;
8d50e447 386 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 387
f1c0a02f
MB		 388 /* Remove the short */
389 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 390 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 391 }
392
393 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 394 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 395
396 /* Short the output */
397 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 398 snd_soc_write(codec, reg, val);
f1c0a02f 399
d7d5c547 400 /* Disable the DC servo */
8d50e447 401 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 402 dcs_reg &= ~dcs_bit;
8d50e447 403 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 404
f1c0a02f
MB		 405 /* Then disable the intermediate and output stages */
406 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
407 WM8903_OUTPUT_IN) << shift);
8d50e447 408 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 409 }
410
f1c0a02f
MB		 411 return 0;
412}
413
414/*
415 * When used with DAC outputs only the WM8903 charge pump supports
416 * operation in class W mode, providing very low power consumption
417 * when used with digital sources. Enable and disable this mode
418 * automatically depending on the mixer configuration.
419 *
420 * All the relevant controls are simple switches.
421 */
422static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
423 struct snd_ctl_elem_value *ucontrol)
424{
425 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
426 struct snd_soc_codec *codec = widget->codec;
b2c812e2 427 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 428 u16 reg;
429 int ret;
430
8d50e447 431 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 432
433 /* Turn it off if we're about to enable bypass */
434 if (ucontrol->value.integer.value[0]) {
435 if (wm8903->class_w_users == 0) {
f0fba2ad 436 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 437 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 438 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
439 }
440 wm8903->class_w_users++;
441 }
442
443 /* Implement the change */
444 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
445
446 /* If we've just disabled the last bypass path turn Class W on */
447 if (!ucontrol->value.integer.value[0]) {
448 if (wm8903->class_w_users == 1) {
f0fba2ad 449 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 450 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 451 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
452 }
453 wm8903->class_w_users--;
454 }
455
f0fba2ad 456 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 457 wm8903->class_w_users);
458
459 return ret;
460}
461
462#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
463{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
464 .info = snd_soc_info_volsw, \
465 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
466 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
467
468
69fff9bb
MB		 469static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
470
471static int wm8903_set_deemph(struct snd_soc_codec *codec)
472{
473 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
474 int val, i, best;
475
476 /* If we're using deemphasis select the nearest available sample
477 * rate.
478 */
479 if (wm8903->deemph) {
480 best = 1;
481 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
482 if (abs(wm8903_deemph[i] - wm8903->fs) <
483 abs(wm8903_deemph[best] - wm8903->fs))
484 best = i;
485 }
486
487 val = best << WM8903_DEEMPH_SHIFT;
488 } else {
489 best = 0;
490 val = 0;
491 }
492
493 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
494 best, wm8903_deemph[best]);
495
496 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
497 WM8903_DEEMPH_MASK, val);
498}
499
500static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
501 struct snd_ctl_elem_value *ucontrol)
502{
503 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
504 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
505
506 ucontrol->value.enumerated.item[0] = wm8903->deemph;
507
508 return 0;
509}
510
511static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
512 struct snd_ctl_elem_value *ucontrol)
513{
514 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
515 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
516 int deemph = ucontrol->value.enumerated.item[0];
517 int ret = 0;
518
519 if (deemph > 1)
520 return -EINVAL;
521
522 mutex_lock(&codec->mutex);
523 if (wm8903->deemph != deemph) {
524 wm8903->deemph = deemph;
525
526 wm8903_set_deemph(codec);
527
528 ret = 1;
529 }
530 mutex_unlock(&codec->mutex);
531
532 return ret;
533}
534
f1c0a02f
MB		 535/* ALSA can only do steps of .01dB */
536static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
537
291ce18c 538static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 539static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
540
541static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
542static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
543static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
544static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
545static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
546
460f4aae
MB		 547static const char *hpf_mode_text[] = {
548 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
549};
550
551static const struct soc_enum hpf_mode =
552 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
553
dcf9ada3
MB		 554static const char *osr_text[] = {
555 "Low power", "High performance"
556};
557
558static const struct soc_enum adc_osr =
559 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
560
561static const struct soc_enum dac_osr =
562 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
563
f1c0a02f
MB		 564static const char *drc_slope_text[] = {
565 "1", "1/2", "1/4", "1/8", "1/16", "0"
566};
567
568static const struct soc_enum drc_slope_r0 =
569 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
570
571static const struct soc_enum drc_slope_r1 =
572 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
573
574static const char *drc_attack_text[] = {
575 "instantaneous",
576 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
577 "46.4ms", "92.8ms", "185.6ms"
578};
579
580static const struct soc_enum drc_attack =
581 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
582
583static const char *drc_decay_text[] = {
584 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
585 "23.87s", "47.56s"
586};
587
588static const struct soc_enum drc_decay =
589 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
590
591static const char *drc_ff_delay_text[] = {
592 "5 samples", "9 samples"
593};
594
595static const struct soc_enum drc_ff_delay =
596 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
597
598static const char *drc_qr_decay_text[] = {
599 "0.725ms", "1.45ms", "5.8ms"
600};
601
602static const struct soc_enum drc_qr_decay =
603 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
604
605static const char *drc_smoothing_text[] = {
606 "Low", "Medium", "High"
607};
608
609static const struct soc_enum drc_smoothing =
610 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
611
612static const char *soft_mute_text[] = {
613 "Fast (fs/2)", "Slow (fs/32)"
614};
615
616static const struct soc_enum soft_mute =
617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
618
619static const char *mute_mode_text[] = {
620 "Hard", "Soft"
621};
622
623static const struct soc_enum mute_mode =
624 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
625
f1c0a02f
MB		 626static const char *companding_text[] = {
627 "ulaw", "alaw"
628};
629
630static const struct soc_enum dac_companding =
631 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
632
633static const struct soc_enum adc_companding =
634 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
635
636static const char *input_mode_text[] = {
637 "Single-Ended", "Differential Line", "Differential Mic"
638};
639
640static const struct soc_enum linput_mode_enum =
641 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
642
643static const struct soc_enum rinput_mode_enum =
644 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
645
646static const char *linput_mux_text[] = {
647 "IN1L", "IN2L", "IN3L"
648};
649
650static const struct soc_enum linput_enum =
651 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
652
653static const struct soc_enum linput_inv_enum =
654 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
655
656static const char *rinput_mux_text[] = {
657 "IN1R", "IN2R", "IN3R"
658};
659
660static const struct soc_enum rinput_enum =
661 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
662
663static const struct soc_enum rinput_inv_enum =
664 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
665
666
291ce18c
MB		 667static const char *sidetone_text[] = {
668 "None", "Left", "Right"
669};
670
671static const struct soc_enum lsidetone_enum =
672 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
673
674static const struct soc_enum rsidetone_enum =
675 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
676
1e113bf9
MB		 677static const char *aif_text[] = {
678 "Left", "Right"
679};
680
681static const struct soc_enum lcapture_enum =
682 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
683
684static const struct soc_enum rcapture_enum =
685 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
686
687static const struct soc_enum lplay_enum =
688 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
689
690static const struct soc_enum rplay_enum =
691 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
692
f1c0a02f
MB		 693static const struct snd_kcontrol_new wm8903_snd_controls[] = {
694
695/* Input PGAs - No TLV since the scale depends on PGA mode */
696SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 697 7, 1, 1),
f1c0a02f
MB		 698SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
699 0, 31, 0),
700SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
701 6, 1, 0),
702
703SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 704 7, 1, 1),
f1c0a02f
MB		 705SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
706 0, 31, 0),
707SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
708 6, 1, 0),
709
710/* ADCs */
dcf9ada3 711SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 712SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
713SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 714SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
715SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
716SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 717SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 718 drc_tlv_thresh),
719SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
720SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
721SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
722SOC_ENUM("DRC Attack Rate", drc_attack),
723SOC_ENUM("DRC Decay Rate", drc_decay),
724SOC_ENUM("DRC FF Delay", drc_ff_delay),
725SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
726SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 727SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 728SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
729SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
730SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 731SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 732SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
733
734SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
735 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
736SOC_ENUM("ADC Companding Mode", adc_companding),
737SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
738
291ce18c
MB		 739SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
740 12, 0, digital_sidetone_tlv),
741
f1c0a02f 742/* DAC */
dcf9ada3 743SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 744SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
745 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
746SOC_ENUM("DAC Soft Mute Rate", soft_mute),
747SOC_ENUM("DAC Mute Mode", mute_mode),
748SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 749SOC_ENUM("DAC Companding Mode", dac_companding),
750SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 751SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
752 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 753
754/* Headphones */
755SOC_DOUBLE_R("Headphone Switch",
756 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
757 8, 1, 1),
758SOC_DOUBLE_R("Headphone ZC Switch",
759 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
760 6, 1, 0),
761SOC_DOUBLE_R_TLV("Headphone Volume",
762 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
763 0, 63, 0, out_tlv),
764
765/* Line out */
766SOC_DOUBLE_R("Line Out Switch",
767 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
768 8, 1, 1),
769SOC_DOUBLE_R("Line Out ZC Switch",
770 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
771 6, 1, 0),
772SOC_DOUBLE_R_TLV("Line Out Volume",
773 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
774 0, 63, 0, out_tlv),
775
776/* Speaker */
777SOC_DOUBLE_R("Speaker Switch",
778 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
779SOC_DOUBLE_R("Speaker ZC Switch",
780 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
781SOC_DOUBLE_R_TLV("Speaker Volume",
782 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
783 0, 63, 0, out_tlv),
784};
785
f1c0a02f
MB		 786static const struct snd_kcontrol_new linput_mode_mux =
787 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
788
789static const struct snd_kcontrol_new rinput_mode_mux =
790 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
791
792static const struct snd_kcontrol_new linput_mux =
793 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
794
795static const struct snd_kcontrol_new linput_inv_mux =
796 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
797
798static const struct snd_kcontrol_new rinput_mux =
799 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
800
801static const struct snd_kcontrol_new rinput_inv_mux =
802 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
803
291ce18c
MB		 804static const struct snd_kcontrol_new lsidetone_mux =
805 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
806
807static const struct snd_kcontrol_new rsidetone_mux =
808 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
809
1e113bf9
MB		 810static const struct snd_kcontrol_new lcapture_mux =
811 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
812
813static const struct snd_kcontrol_new rcapture_mux =
814 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
815
816static const struct snd_kcontrol_new lplay_mux =
817 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
818
819static const struct snd_kcontrol_new rplay_mux =
820 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
821
f1c0a02f
MB		 822static const struct snd_kcontrol_new left_output_mixer[] = {
823SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
824SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
825SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 826SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 827};
828
829static const struct snd_kcontrol_new right_output_mixer[] = {
830SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
831SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
832SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 833SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 834};
835
836static const struct snd_kcontrol_new left_speaker_mixer[] = {
837SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
838SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
839SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
840SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 841 0, 1, 0),
f1c0a02f
MB		 842};
843
844static const struct snd_kcontrol_new right_speaker_mixer[] = {
845SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
846SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
847SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
848 1, 1, 0),
849SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 850 0, 1, 0),
f1c0a02f
MB		 851};
852
853static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
854SND_SOC_DAPM_INPUT("IN1L"),
855SND_SOC_DAPM_INPUT("IN1R"),
856SND_SOC_DAPM_INPUT("IN2L"),
857SND_SOC_DAPM_INPUT("IN2R"),
858SND_SOC_DAPM_INPUT("IN3L"),
859SND_SOC_DAPM_INPUT("IN3R"),
860
861SND_SOC_DAPM_OUTPUT("HPOUTL"),
862SND_SOC_DAPM_OUTPUT("HPOUTR"),
863SND_SOC_DAPM_OUTPUT("LINEOUTL"),
864SND_SOC_DAPM_OUTPUT("LINEOUTR"),
865SND_SOC_DAPM_OUTPUT("LOP"),
866SND_SOC_DAPM_OUTPUT("LON"),
867SND_SOC_DAPM_OUTPUT("ROP"),
868SND_SOC_DAPM_OUTPUT("RON"),
869
870SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
871
872SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
873SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
874 &linput_inv_mux),
875SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
876
877SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
878SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
879 &rinput_inv_mux),
880SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
881
882SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
883SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
884
1e113bf9
MB		 885SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
886SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
887
888SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
889SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
890
891SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
892SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 893
291ce18c
MB		 894SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
895SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
896
1e113bf9
MB		 897SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
898SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
899
900SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
901SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
902
903SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
904SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 905
906SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
907 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
908SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
909 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
910
911SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
912 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
913SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
914 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
915
916SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
917 1, 0, NULL, 0, wm8903_output_event,
918 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 919 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 920SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
921 0, 0, NULL, 0, wm8903_output_event,
922 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 923 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 924
925SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
926 NULL, 0, wm8903_output_event,
927 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 928 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 929SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
930 NULL, 0, wm8903_output_event,
931 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 932 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 933
934SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
935 NULL, 0),
936SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
937 NULL, 0),
938
42768a12
MB		 939SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
940 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 941SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 942};
943
944static const struct snd_soc_dapm_route intercon[] = {
945
946 { "Left Input Mux", "IN1L", "IN1L" },
947 { "Left Input Mux", "IN2L", "IN2L" },
948 { "Left Input Mux", "IN3L", "IN3L" },
949
950 { "Left Input Inverting Mux", "IN1L", "IN1L" },
951 { "Left Input Inverting Mux", "IN2L", "IN2L" },
952 { "Left Input Inverting Mux", "IN3L", "IN3L" },
953
954 { "Right Input Mux", "IN1R", "IN1R" },
955 { "Right Input Mux", "IN2R", "IN2R" },
956 { "Right Input Mux", "IN3R", "IN3R" },
957
958 { "Right Input Inverting Mux", "IN1R", "IN1R" },
959 { "Right Input Inverting Mux", "IN2R", "IN2R" },
960 { "Right Input Inverting Mux", "IN3R", "IN3R" },
961
962 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
963 { "Left Input Mode Mux", "Differential Line",
964 "Left Input Mux" },
965 { "Left Input Mode Mux", "Differential Line",
966 "Left Input Inverting Mux" },
967 { "Left Input Mode Mux", "Differential Mic",
968 "Left Input Mux" },
969 { "Left Input Mode Mux", "Differential Mic",
970 "Left Input Inverting Mux" },
971
972 { "Right Input Mode Mux", "Single-Ended",
973 "Right Input Inverting Mux" },
974 { "Right Input Mode Mux", "Differential Line",
975 "Right Input Mux" },
976 { "Right Input Mode Mux", "Differential Line",
977 "Right Input Inverting Mux" },
978 { "Right Input Mode Mux", "Differential Mic",
979 "Right Input Mux" },
980 { "Right Input Mode Mux", "Differential Mic",
981 "Right Input Inverting Mux" },
982
983 { "Left Input PGA", NULL, "Left Input Mode Mux" },
984 { "Right Input PGA", NULL, "Right Input Mode Mux" },
985
1e113bf9
MB		 986 { "Left Capture Mux", "Left", "ADCL" },
987 { "Left Capture Mux", "Right", "ADCR" },
988
989 { "Right Capture Mux", "Left", "ADCL" },
990 { "Right Capture Mux", "Right", "ADCR" },
991
992 { "AIFTXL", NULL, "Left Capture Mux" },
993 { "AIFTXR", NULL, "Right Capture Mux" },
994
f1c0a02f 995 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 996 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 997 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 998 { "ADCR", NULL, "CLK_DSP" },
999
1e113bf9
MB		 1000 { "Left Playback Mux", "Left", "AIFRXL" },
1001 { "Left Playback Mux", "Right", "AIFRXR" },
1002
1003 { "Right Playback Mux", "Left", "AIFRXL" },
1004 { "Right Playback Mux", "Right", "AIFRXR" },
1005
291ce18c
MB		 1006 { "DACL Sidetone", "Left", "ADCL" },
1007 { "DACL Sidetone", "Right", "ADCR" },
1008 { "DACR Sidetone", "Left", "ADCL" },
1009 { "DACR Sidetone", "Right", "ADCR" },
1010
1e113bf9 1011 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1012 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1013 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1014
1015 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1016 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1017 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1018
1019 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1020 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1021 { "Left Output Mixer", "DACL Switch", "DACL" },
1022 { "Left Output Mixer", "DACR Switch", "DACR" },
1023
1024 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1025 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1026 { "Right Output Mixer", "DACL Switch", "DACL" },
1027 { "Right Output Mixer", "DACR Switch", "DACR" },
1028
1029 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1030 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1031 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1032 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1033
1034 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1035 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1036 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1037 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1038
1039 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1040 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1041
1042 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1043 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1044
1045 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1046 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1047
1048 { "HPOUTL", NULL, "Left Headphone Output PGA" },
1049 { "HPOUTR", NULL, "Right Headphone Output PGA" },
1050
1051 { "LINEOUTL", NULL, "Left Line Output PGA" },
1052 { "LINEOUTR", NULL, "Right Line Output PGA" },
1053
1054 { "LOP", NULL, "Left Speaker PGA" },
1055 { "LON", NULL, "Left Speaker PGA" },
1056
1057 { "ROP", NULL, "Right Speaker PGA" },
1058 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1059
1060 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1061 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1062 { "Left Line Output PGA", NULL, "Charge Pump" },
1063 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1064};
1065
1066static int wm8903_add_widgets(struct snd_soc_codec *codec)
1067{
ce6120cc 1068 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 1069
ce6120cc
LG		 1070 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1071 ARRAY_SIZE(wm8903_dapm_widgets));
1072 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 1073
f1c0a02f
MB		 1074 return 0;
1075}
1076
1077static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1078 enum snd_soc_bias_level level)
1079{
524d7692 1080 u16 reg;
f1c0a02f
MB		 1081
1082 switch (level) {
1083 case SND_SOC_BIAS_ON:
1084 case SND_SOC_BIAS_PREPARE:
8d50e447 1085 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1086 reg &= ~(WM8903_VMID_RES_MASK);
1087 reg |= WM8903_VMID_RES_50K;
8d50e447 1088 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1089 break;
1090
1091 case SND_SOC_BIAS_STANDBY:
ce6120cc 1092 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 1093 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 1094 WM8903_CLK_SYS_ENA);
1095
4dbfe809 1096 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 1097 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1098 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1099 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 1100
f1c0a02f
MB		 1101 wm8903_run_sequence(codec, 0);
1102 wm8903_sync_reg_cache(codec, codec->reg_cache);
1103
f1c0a02f
MB		 1104 /* By default no bypass paths are enabled so
1105 * enable Class W support.
1106 */
f0fba2ad 1107 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1108 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1109 WM8903_CP_DYN_FREQ |
1110 WM8903_CP_DYN_V,
1111 WM8903_CP_DYN_FREQ |
1112 WM8903_CP_DYN_V);
f1c0a02f
MB		 1113 }
1114
8d50e447 1115 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1116 reg &= ~(WM8903_VMID_RES_MASK);
1117 reg |= WM8903_VMID_RES_250K;
8d50e447 1118 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1119 break;
1120
1121 case SND_SOC_BIAS_OFF:
1122 wm8903_run_sequence(codec, 32);
8d50e447 1123 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 1124 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 1125 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1126 break;
1127 }
1128
ce6120cc 1129 codec->dapm.bias_level = level;
f1c0a02f
MB		 1130
1131 return 0;
1132}
1133
1134static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1135 int clk_id, unsigned int freq, int dir)
1136{
1137 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1138 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1139
1140 wm8903->sysclk = freq;
1141
1142 return 0;
1143}
1144
1145static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1146 unsigned int fmt)
1147{
1148 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1149 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1150
1151 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1152 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1153
1154 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1155 case SND_SOC_DAIFMT_CBS_CFS:
1156 break;
1157 case SND_SOC_DAIFMT_CBS_CFM:
1158 aif1 |= WM8903_LRCLK_DIR;
1159 break;
1160 case SND_SOC_DAIFMT_CBM_CFM:
1161 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1162 break;
1163 case SND_SOC_DAIFMT_CBM_CFS:
1164 aif1 |= WM8903_BCLK_DIR;
1165 break;
1166 default:
1167 return -EINVAL;
1168 }
1169
1170 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1171 case SND_SOC_DAIFMT_DSP_A:
1172 aif1 |= 0x3;
1173 break;
1174 case SND_SOC_DAIFMT_DSP_B:
1175 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1176 break;
1177 case SND_SOC_DAIFMT_I2S:
1178 aif1 |= 0x2;
1179 break;
1180 case SND_SOC_DAIFMT_RIGHT_J:
1181 aif1 |= 0x1;
1182 break;
1183 case SND_SOC_DAIFMT_LEFT_J:
1184 break;
1185 default:
1186 return -EINVAL;
1187 }
1188
1189 /* Clock inversion */
1190 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1191 case SND_SOC_DAIFMT_DSP_A:
1192 case SND_SOC_DAIFMT_DSP_B:
1193 /* frame inversion not valid for DSP modes */
1194 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1195 case SND_SOC_DAIFMT_NB_NF:
1196 break;
1197 case SND_SOC_DAIFMT_IB_NF:
1198 aif1 |= WM8903_AIF_BCLK_INV;
1199 break;
1200 default:
1201 return -EINVAL;
1202 }
1203 break;
1204 case SND_SOC_DAIFMT_I2S:
1205 case SND_SOC_DAIFMT_RIGHT_J:
1206 case SND_SOC_DAIFMT_LEFT_J:
1207 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1208 case SND_SOC_DAIFMT_NB_NF:
1209 break;
1210 case SND_SOC_DAIFMT_IB_IF:
1211 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1212 break;
1213 case SND_SOC_DAIFMT_IB_NF:
1214 aif1 |= WM8903_AIF_BCLK_INV;
1215 break;
1216 case SND_SOC_DAIFMT_NB_IF:
1217 aif1 |= WM8903_AIF_LRCLK_INV;
1218 break;
1219 default:
1220 return -EINVAL;
1221 }
1222 break;
1223 default:
1224 return -EINVAL;
1225 }
1226
8d50e447 1227 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1228
1229 return 0;
1230}
1231
1232static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1233{
1234 struct snd_soc_codec *codec = codec_dai->codec;
1235 u16 reg;
1236
8d50e447 1237 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1238
1239 if (mute)
1240 reg |= WM8903_DAC_MUTE;
1241 else
1242 reg &= ~WM8903_DAC_MUTE;
1243
8d50e447 1244 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1245
1246 return 0;
1247}
1248
1249/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1250 * for optimal performance so we list the lower rates first and match
1251 * on the last match we find. */
1252static struct {
1253 int div;
1254 int rate;
1255 int mode;
1256 int mclk_div;
1257} clk_sys_ratios[] = {
1258 { 64, 0x0, 0x0, 1 },
1259 { 68, 0x0, 0x1, 1 },
1260 { 125, 0x0, 0x2, 1 },
1261 { 128, 0x1, 0x0, 1 },
1262 { 136, 0x1, 0x1, 1 },
1263 { 192, 0x2, 0x0, 1 },
1264 { 204, 0x2, 0x1, 1 },
1265
1266 { 64, 0x0, 0x0, 2 },
1267 { 68, 0x0, 0x1, 2 },
1268 { 125, 0x0, 0x2, 2 },
1269 { 128, 0x1, 0x0, 2 },
1270 { 136, 0x1, 0x1, 2 },
1271 { 192, 0x2, 0x0, 2 },
1272 { 204, 0x2, 0x1, 2 },
1273
1274 { 250, 0x2, 0x2, 1 },
1275 { 256, 0x3, 0x0, 1 },
1276 { 272, 0x3, 0x1, 1 },
1277 { 384, 0x4, 0x0, 1 },
1278 { 408, 0x4, 0x1, 1 },
1279 { 375, 0x4, 0x2, 1 },
1280 { 512, 0x5, 0x0, 1 },
1281 { 544, 0x5, 0x1, 1 },
1282 { 500, 0x5, 0x2, 1 },
1283 { 768, 0x6, 0x0, 1 },
1284 { 816, 0x6, 0x1, 1 },
1285 { 750, 0x6, 0x2, 1 },
1286 { 1024, 0x7, 0x0, 1 },
1287 { 1088, 0x7, 0x1, 1 },
1288 { 1000, 0x7, 0x2, 1 },
1289 { 1408, 0x8, 0x0, 1 },
1290 { 1496, 0x8, 0x1, 1 },
1291 { 1536, 0x9, 0x0, 1 },
1292 { 1632, 0x9, 0x1, 1 },
1293 { 1500, 0x9, 0x2, 1 },
1294
1295 { 250, 0x2, 0x2, 2 },
1296 { 256, 0x3, 0x0, 2 },
1297 { 272, 0x3, 0x1, 2 },
1298 { 384, 0x4, 0x0, 2 },
1299 { 408, 0x4, 0x1, 2 },
1300 { 375, 0x4, 0x2, 2 },
1301 { 512, 0x5, 0x0, 2 },
1302 { 544, 0x5, 0x1, 2 },
1303 { 500, 0x5, 0x2, 2 },
1304 { 768, 0x6, 0x0, 2 },
1305 { 816, 0x6, 0x1, 2 },
1306 { 750, 0x6, 0x2, 2 },
1307 { 1024, 0x7, 0x0, 2 },
1308 { 1088, 0x7, 0x1, 2 },
1309 { 1000, 0x7, 0x2, 2 },
1310 { 1408, 0x8, 0x0, 2 },
1311 { 1496, 0x8, 0x1, 2 },
1312 { 1536, 0x9, 0x0, 2 },
1313 { 1632, 0x9, 0x1, 2 },
1314 { 1500, 0x9, 0x2, 2 },
1315};
1316
1317/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1318static struct {
1319 int ratio;
1320 int div;
1321} bclk_divs[] = {
1322 { 10, 0 },
f1c0a02f
MB		 1323 { 20, 2 },
1324 { 30, 3 },
1325 { 40, 4 },
1326 { 50, 5 },
f1c0a02f
MB		 1327 { 60, 7 },
1328 { 80, 8 },
1329 { 100, 9 },
f1c0a02f
MB		 1330 { 120, 11 },
1331 { 160, 12 },
1332 { 200, 13 },
1333 { 220, 14 },
1334 { 240, 15 },
f1c0a02f
MB		 1335 { 300, 17 },
1336 { 320, 18 },
1337 { 440, 19 },
1338 { 480, 20 },
1339};
1340
1341/* Sample rates for DSP */
1342static struct {
1343 int rate;
1344 int value;
1345} sample_rates[] = {
1346 { 8000, 0 },
1347 { 11025, 1 },
1348 { 12000, 2 },
1349 { 16000, 3 },
1350 { 22050, 4 },
1351 { 24000, 5 },
1352 { 32000, 6 },
1353 { 44100, 7 },
1354 { 48000, 8 },
1355 { 88200, 9 },
1356 { 96000, 10 },
1357 { 0, 0 },
1358};
1359
f1c0a02f 1360static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1361 struct snd_pcm_hw_params *params,
1362 struct snd_soc_dai *dai)
f1c0a02f
MB		 1363{
1364 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1365 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1366 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1367 int fs = params_rate(params);
1368 int bclk;
1369 int bclk_div;
1370 int i;
1371 int dsp_config;
1372 int clk_config;
1373 int best_val;
1374 int cur_val;
1375 int clk_sys;
1376
8d50e447
MB		 1377 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1378 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1379 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1380 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1381 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1382 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1383
9e79261f
MB		 1384 /* Enable sloping stopband filter for low sample rates */
1385 if (fs <= 24000)
1386 dac_digital1 |= WM8903_DAC_SB_FILT;
1387 else
1388 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1389
f1c0a02f
MB		 1390 /* Configure sample rate logic for DSP - choose nearest rate */
1391 dsp_config = 0;
1392 best_val = abs(sample_rates[dsp_config].rate - fs);
1393 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1394 cur_val = abs(sample_rates[i].rate - fs);
1395 if (cur_val <= best_val) {
1396 dsp_config = i;
1397 best_val = cur_val;
1398 }
1399 }
1400
f0fba2ad 1401 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1402 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1403 clock1 |= sample_rates[dsp_config].value;
1404
1405 aif1 &= ~WM8903_AIF_WL_MASK;
1406 bclk = 2 * fs;
1407 switch (params_format(params)) {
1408 case SNDRV_PCM_FORMAT_S16_LE:
1409 bclk *= 16;
1410 break;
1411 case SNDRV_PCM_FORMAT_S20_3LE:
1412 bclk *= 20;
1413 aif1 |= 0x4;
1414 break;
1415 case SNDRV_PCM_FORMAT_S24_LE:
1416 bclk *= 24;
1417 aif1 |= 0x8;
1418 break;
1419 case SNDRV_PCM_FORMAT_S32_LE:
1420 bclk *= 32;
1421 aif1 |= 0xc;
1422 break;
1423 default:
1424 return -EINVAL;
1425 }
1426
f0fba2ad 1427 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1428 wm8903->sysclk, fs);
1429
1430 /* We may not have an MCLK which allows us to generate exactly
1431 * the clock we want, particularly with USB derived inputs, so
1432 * approximate.
1433 */
1434 clk_config = 0;
1435 best_val = abs((wm8903->sysclk /
1436 (clk_sys_ratios[0].mclk_div *
1437 clk_sys_ratios[0].div)) - fs);
1438 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1439 cur_val = abs((wm8903->sysclk /
1440 (clk_sys_ratios[i].mclk_div *
1441 clk_sys_ratios[i].div)) - fs);
1442
1443 if (cur_val <= best_val) {
1444 clk_config = i;
1445 best_val = cur_val;
1446 }
1447 }
1448
1449 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1450 clock0 |= WM8903_MCLKDIV2;
1451 clk_sys = wm8903->sysclk / 2;
1452 } else {
1453 clock0 &= ~WM8903_MCLKDIV2;
1454 clk_sys = wm8903->sysclk;
1455 }
1456
1457 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1458 WM8903_CLK_SYS_MODE_MASK);
1459 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1460 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1461
f0fba2ad 1462 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1463 clk_sys_ratios[clk_config].rate,
1464 clk_sys_ratios[clk_config].mode,
1465 clk_sys_ratios[clk_config].div);
1466
f0fba2ad 1467 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1468
1469 /* We may not get quite the right frequency if using
1470 * approximate clocks so look for the closest match that is
1471 * higher than the target (we need to ensure that there enough
1472 * BCLKs to clock out the samples).
1473 */
1474 bclk_div = 0;
1475 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1476 i = 1;
1477 while (i < ARRAY_SIZE(bclk_divs)) {
1478 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1479 if (cur_val < 0) /* BCLK table is sorted */
1480 break;
1481 bclk_div = i;
1482 best_val = cur_val;
1483 i++;
1484 }
1485
1486 aif2 &= ~WM8903_BCLK_DIV_MASK;
1487 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1488
f0fba2ad 1489 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1490 bclk_divs[bclk_div].ratio / 10, bclk,
1491 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1492
1493 aif2 |= bclk_divs[bclk_div].div;
1494 aif3 |= bclk / fs;
1495
69fff9bb
MB		 1496 wm8903->fs = params_rate(params);
1497 wm8903_set_deemph(codec);
1498
8d50e447
MB		 1499 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1500 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1501 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1502 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1503 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1504 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1505
1506 return 0;
1507}
1508
7245387e
MB		 1509/**
1510 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1511 *
1512 * @codec: WM8903 codec
1513 * @jack: jack to report detection events on
1514 * @det: value to report for presence detection
1515 * @shrt: value to report for short detection
1516 *
1517 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1518 * being used to bring out signals to the processor then only platform
1519 * data configuration is needed for WM8903 and processor GPIOs should
1520 * be configured using snd_soc_jack_add_gpios() instead.
1521 *
1522 * The current threasholds for detection should be configured using
1523 * micdet_cfg in the platform data. Using this function will force on
1524 * the microphone bias for the device.
1525 */
1526int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1527 int det, int shrt)
1528{
b2c812e2 1529 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1530 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1531
1532 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1533 det, shrt);
1534
1535 /* Store the configuration */
1536 wm8903->mic_jack = jack;
1537 wm8903->mic_det = det;
1538 wm8903->mic_short = shrt;
1539
1540 /* Enable interrupts we've got a report configured for */
1541 if (det)
1542 irq_mask &= ~WM8903_MICDET_EINT;
1543 if (shrt)
1544 irq_mask &= ~WM8903_MICSHRT_EINT;
1545
1546 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1547 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1548 irq_mask);
1549
69266866
MB		 1550 if (det && shrt) {
1551 /* Enable mic detection, this may not have been set through
1552 * platform data (eg, if the defaults are OK). */
1553 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1554 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1555 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1556 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1557 } else {
1558 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1559 WM8903_MICDET_ENA, 0);
1560 }
7245387e
MB		 1561
1562 return 0;
1563}
1564EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1565
8abd16a6
MB		 1566static irqreturn_t wm8903_irq(int irq, void *data)
1567{
f0fba2ad
LG		 1568 struct snd_soc_codec *codec = data;
1569 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1570 int mic_report;
1571 int int_pol;
1572 int int_val = 0;
1573 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1574
7245387e 1575 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1576
7245387e 1577 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1578 dev_dbg(codec->dev, "Write sequencer done\n");
1579 complete(&wm8903->wseq);
1580 }
1581
7245387e
MB		 1582 /*
1583 * The rest is microphone jack detection. We need to manually
1584 * invert the polarity of the interrupt after each event - to
1585 * simplify the code keep track of the last state we reported
1586 * and just invert the relevant bits in both the report and
1587 * the polarity register.
1588 */
1589 mic_report = wm8903->mic_last_report;
1590 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1591
1435b940 1592#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1593 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1594 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1595#endif
2bbb5d66 1596
7245387e
MB		 1597 if (int_val & WM8903_MICSHRT_EINT) {
1598 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1599
1600 mic_report ^= wm8903->mic_short;
1601 int_pol ^= WM8903_MICSHRT_INV;
1602 }
1603
1604 if (int_val & WM8903_MICDET_EINT) {
1605 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1606
1607 mic_report ^= wm8903->mic_det;
1608 int_pol ^= WM8903_MICDET_INV;
1609
1610 msleep(wm8903->mic_delay);
1611 }
1612
1613 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1614 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1615
1616 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1617 wm8903->mic_short | wm8903->mic_det);
1618
1619 wm8903->mic_last_report = mic_report;
1620
8abd16a6
MB		 1621 return IRQ_HANDLED;
1622}
1623
f1c0a02f
MB		 1624#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1625 SNDRV_PCM_RATE_11025 | \
1626 SNDRV_PCM_RATE_16000 | \
1627 SNDRV_PCM_RATE_22050 | \
1628 SNDRV_PCM_RATE_32000 | \
1629 SNDRV_PCM_RATE_44100 | \
1630 SNDRV_PCM_RATE_48000 | \
1631 SNDRV_PCM_RATE_88200 | \
1632 SNDRV_PCM_RATE_96000)
1633
1634#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1635 SNDRV_PCM_RATE_11025 | \
1636 SNDRV_PCM_RATE_16000 | \
1637 SNDRV_PCM_RATE_22050 | \
1638 SNDRV_PCM_RATE_32000 | \
1639 SNDRV_PCM_RATE_44100 | \
1640 SNDRV_PCM_RATE_48000)
1641
1642#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1643 SNDRV_PCM_FMTBIT_S20_3LE |\
1644 SNDRV_PCM_FMTBIT_S24_LE)
1645
6335d055 1646static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1647 .hw_params = wm8903_hw_params,
1648 .digital_mute = wm8903_digital_mute,
1649 .set_fmt = wm8903_set_dai_fmt,
1650 .set_sysclk = wm8903_set_dai_sysclk,
1651};
1652
f0fba2ad
LG		 1653static struct snd_soc_dai_driver wm8903_dai = {
1654 .name = "wm8903-hifi",
f1c0a02f
MB		 1655 .playback = {
1656 .stream_name = "Playback",
1657 .channels_min = 2,
1658 .channels_max = 2,
1659 .rates = WM8903_PLAYBACK_RATES,
1660 .formats = WM8903_FORMATS,
1661 },
1662 .capture = {
1663 .stream_name = "Capture",
1664 .channels_min = 2,
1665 .channels_max = 2,
1666 .rates = WM8903_CAPTURE_RATES,
1667 .formats = WM8903_FORMATS,
1668 },
6335d055 1669 .ops = &wm8903_dai_ops,
0d960e88 1670 .symmetric_rates = 1,
f1c0a02f 1671};
f1c0a02f 1672
f0fba2ad 1673static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1674{
f1c0a02f
MB		 1675 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1676
1677 return 0;
1678}
1679
f0fba2ad 1680static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1681{
f1c0a02f
MB		 1682 int i;
1683 u16 *reg_cache = codec->reg_cache;
40aa7030 1684 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1685 GFP_KERNEL);
1686
1687 /* Bring the codec back up to standby first to minimise pop/clicks */
1688 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1689
1690 /* Sync back everything else */
1691 if (tmp_cache) {
1692 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1693 if (tmp_cache[i] != reg_cache[i])
8d50e447 1694 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1695 kfree(tmp_cache);
f1c0a02f 1696 } else {
f0fba2ad 1697 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1698 }
1699
1700 return 0;
1701}
1702
7cfe5617
SW		 1703#ifdef CONFIG_GPIOLIB
1704static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1705{
1706 return container_of(chip, struct wm8903_priv, gpio_chip);
1707}
1708
1709static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1710{
1711 if (offset >= WM8903_NUM_GPIO)
1712 return -EINVAL;
1713
1714 return 0;
1715}
1716
1717static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1718{
1719 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1720 struct snd_soc_codec *codec = wm8903->codec;
1721 unsigned int mask, val;
1722
1723 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1724 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1725 WM8903_GP1_DIR;
1726
1727 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1728 mask, val);
1729}
1730
1731static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1732{
1733 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1734 struct snd_soc_codec *codec = wm8903->codec;
1735 int reg;
1736
1737 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1738
1739 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1740}
1741
1742static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1743 unsigned offset, int value)
1744{
1745 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1746 struct snd_soc_codec *codec = wm8903->codec;
1747 unsigned int mask, val;
1748
1749 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1750 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1751 (value << WM8903_GP2_LVL_SHIFT);
1752
1753 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1754 mask, val);
1755}
1756
1757static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1758{
1759 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1760 struct snd_soc_codec *codec = wm8903->codec;
1761
1762 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1763 WM8903_GP1_LVL_MASK,
1764 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1765}
1766
1767static struct gpio_chip wm8903_template_chip = {
1768 .label = "wm8903",
1769 .owner = THIS_MODULE,
1770 .request = wm8903_gpio_request,
1771 .direction_input = wm8903_gpio_direction_in,
1772 .get = wm8903_gpio_get,
1773 .direction_output = wm8903_gpio_direction_out,
1774 .set = wm8903_gpio_set,
1775 .can_sleep = 1,
1776};
1777
1778static void wm8903_init_gpio(struct snd_soc_codec *codec)
1779{
1780 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1781 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1782 int ret;
1783
1784 wm8903->gpio_chip = wm8903_template_chip;
1785 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1786 wm8903->gpio_chip.dev = codec->dev;
1787
1788 if (pdata && pdata->gpio_base)
1789 wm8903->gpio_chip.base = pdata->gpio_base;
1790 else
1791 wm8903->gpio_chip.base = -1;
1792
1793 ret = gpiochip_add(&wm8903->gpio_chip);
1794 if (ret != 0)
1795 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1796}
1797
1798static void wm8903_free_gpio(struct snd_soc_codec *codec)
1799{
1800 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1801 int ret;
1802
1803 ret = gpiochip_remove(&wm8903->gpio_chip);
1804 if (ret != 0)
1805 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1806}
1807#else
1808static void wm8903_init_gpio(struct snd_soc_codec *codec)
1809{
1810}
1811
1812static void wm8903_free_gpio(struct snd_soc_codec *codec)
1813{
1814}
1815#endif
1816
f0fba2ad 1817static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1818{
f0fba2ad
LG		 1819 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1820 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1821 int ret, i;
8abd16a6 1822 int trigger, irq_pol;
f1c0a02f
MB		 1823 u16 val;
1824
7cfe5617 1825 wm8903->codec = codec;
8abd16a6 1826 init_completion(&wm8903->wseq);
d58d5d55 1827
8d50e447
MB		 1828 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1829 if (ret != 0) {
f0fba2ad
LG		 1830 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1831 return ret;
8d50e447
MB		 1832 }
1833
1834 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1835 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1836 dev_err(codec->dev,
d58d5d55
MB		 1837 "Device with ID register %x is not a WM8903\n", val);
1838 return -ENODEV;
f1c0a02f
MB		 1839 }
1840
8d50e447 1841 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1842 dev_info(codec->dev, "WM8903 revision %c\n",
1843 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1844
1845 wm8903_reset(codec);
1846
37f88e84 1847 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1848 if (pdata) {
1849 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
7cfe5617 1850 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
73b34ead
MB		 1851 continue;
1852
1853 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1854 pdata->gpio_cfg[i] & 0xffff);
1855 }
37f88e84
MB		 1856
1857 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1858 pdata->micdet_cfg);
1859
1860 /* Microphone detection needs the WSEQ clock */
1861 if (pdata->micdet_cfg)
1862 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1863 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1864
1865 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1866 }
8abd16a6 1867
f0fba2ad 1868 if (wm8903->irq) {
8abd16a6
MB		 1869 if (pdata && pdata->irq_active_low) {
1870 trigger = IRQF_TRIGGER_LOW;
1871 irq_pol = WM8903_IRQ_POL;
1872 } else {
1873 trigger = IRQF_TRIGGER_HIGH;
1874 irq_pol = 0;
1875 }
1876
1877 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1878 WM8903_IRQ_POL, irq_pol);
1879
f0fba2ad 1880 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1881 trigger | IRQF_ONESHOT,
f0fba2ad 1882 "wm8903", codec);
8abd16a6 1883 if (ret != 0) {
f0fba2ad 1884 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1885 ret);
f0fba2ad 1886 return ret;
8abd16a6
MB		 1887 }
1888
1889 /* Enable write sequencer interrupts */
1890 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1891 WM8903_IM_WSEQ_BUSY_EINT, 0);
1892 }
73b34ead 1893
f1c0a02f
MB		 1894 /* power on device */
1895 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1896
1897 /* Latch volume update bits */
8d50e447 1898 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1899 val |= WM8903_ADCVU;
8d50e447
MB		 1900 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1901 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1902
8d50e447 1903 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1904 val |= WM8903_DACVU;
8d50e447
MB		 1905 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1906 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1907
8d50e447 1908 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1909 val |= WM8903_HPOUTVU;
8d50e447
MB		 1910 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1911 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1912
8d50e447 1913 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1914 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1915 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1916 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1917
8d50e447 1918 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1919 val |= WM8903_SPKVU;
8d50e447
MB		 1920 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1921 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1922
1923 /* Enable DAC soft mute by default */
8d50e447 1924 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1925 val |= WM8903_DAC_MUTEMODE;
8d50e447 1926 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1927
f0fba2ad
LG		 1928 snd_soc_add_controls(codec, wm8903_snd_controls,
1929 ARRAY_SIZE(wm8903_snd_controls));
1930 wm8903_add_widgets(codec);
f1c0a02f 1931
7cfe5617
SW		 1932 wm8903_init_gpio(codec);
1933
f1c0a02f
MB		 1934 return ret;
1935}
1936
f0fba2ad
LG		 1937/* power down chip */
1938static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1939{
7cfe5617 1940 wm8903_free_gpio(codec);
f0fba2ad
LG		 1941 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1942 return 0;
1943}
f1c0a02f 1944
f0fba2ad
LG		 1945static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1946 .probe = wm8903_probe,
1947 .remove = wm8903_remove,
1948 .suspend = wm8903_suspend,
1949 .resume = wm8903_resume,
1950 .set_bias_level = wm8903_set_bias_level,
1951 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1952 .reg_word_size = sizeof(u16),
1953 .reg_cache_default = wm8903_reg_defaults,
1954 .volatile_register = wm8903_volatile_register,
1955};
f1c0a02f 1956
f0fba2ad
LG		 1957#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1958static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1959 const struct i2c_device_id *id)
1960{
1961 struct wm8903_priv *wm8903;
1962 int ret;
f1c0a02f 1963
f0fba2ad
LG		 1964 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1965 if (wm8903 == NULL)
1966 return -ENOMEM;
8abd16a6 1967
f0fba2ad 1968 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 1969 wm8903->irq = i2c->irq;
d58d5d55 1970
f0fba2ad
LG		 1971 ret = snd_soc_register_codec(&i2c->dev,
1972 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1973 if (ret < 0)
1974 kfree(wm8903);
1975 return ret;
1976}
f1c0a02f 1977
f0fba2ad
LG		 1978static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1979{
1980 snd_soc_unregister_codec(&client->dev);
1981 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 1982 return 0;
1983}
1984
f1c0a02f 1985static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 1986 { "wm8903", 0 },
1987 { }
f1c0a02f
MB		 1988};
1989MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1990
1991static struct i2c_driver wm8903_i2c_driver = {
1992 .driver = {
4b592c91 1993 .name = "wm8903",
f1c0a02f
MB		 1994 .owner = THIS_MODULE,
1995 },
f0fba2ad
LG		 1996 .probe = wm8903_i2c_probe,
1997 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1998 .id_table = wm8903_i2c_id,
1999};
f0fba2ad 2000#endif
f1c0a02f 2001
f0fba2ad 2002static int __init wm8903_modinit(void)
f1c0a02f 2003{
f1c0a02f 2004 int ret = 0;
f0fba2ad
LG		 2005#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2006 ret = i2c_add_driver(&wm8903_i2c_driver);
2007 if (ret != 0) {
2008 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2009 ret);
f1c0a02f 2010 }
f0fba2ad 2011#endif
f1c0a02f 2012 return ret;
64089b84
MB		 2013}
2014module_init(wm8903_modinit);
2015
2016static void __exit wm8903_exit(void)
2017{
f0fba2ad 2018#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 2019 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 2020#endif
64089b84
MB		 2021}
2022module_exit(wm8903_exit);
2023
f1c0a02f
MB		 2024MODULE_DESCRIPTION("ASoC WM8903 driver");
2025MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2026MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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