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ASoC: Don't use write sequencer to power up WM8903
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
26#include <linux/platform_device.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f
MB		 40/* Register defaults at reset */
41static u16 wm8903_reg_defaults[] = {
42 0x8903, /* R0 - SW Reset and ID */
43 0x0000, /* R1 - Revision Number */
44 0x0000, /* R2 */
45 0x0000, /* R3 */
46 0x0018, /* R4 - Bias Control 0 */
47 0x0000, /* R5 - VMID Control 0 */
48 0x0000, /* R6 - Mic Bias Control 0 */
49 0x0000, /* R7 */
50 0x0001, /* R8 - Analogue DAC 0 */
51 0x0000, /* R9 */
52 0x0001, /* R10 - Analogue ADC 0 */
53 0x0000, /* R11 */
54 0x0000, /* R12 - Power Management 0 */
55 0x0000, /* R13 - Power Management 1 */
56 0x0000, /* R14 - Power Management 2 */
57 0x0000, /* R15 - Power Management 3 */
58 0x0000, /* R16 - Power Management 4 */
59 0x0000, /* R17 - Power Management 5 */
60 0x0000, /* R18 - Power Management 6 */
61 0x0000, /* R19 */
62 0x0400, /* R20 - Clock Rates 0 */
63 0x0D07, /* R21 - Clock Rates 1 */
64 0x0000, /* R22 - Clock Rates 2 */
65 0x0000, /* R23 */
66 0x0050, /* R24 - Audio Interface 0 */
67 0x0242, /* R25 - Audio Interface 1 */
68 0x0008, /* R26 - Audio Interface 2 */
69 0x0022, /* R27 - Audio Interface 3 */
70 0x0000, /* R28 */
71 0x0000, /* R29 */
72 0x00C0, /* R30 - DAC Digital Volume Left */
73 0x00C0, /* R31 - DAC Digital Volume Right */
74 0x0000, /* R32 - DAC Digital 0 */
75 0x0000, /* R33 - DAC Digital 1 */
76 0x0000, /* R34 */
77 0x0000, /* R35 */
78 0x00C0, /* R36 - ADC Digital Volume Left */
79 0x00C0, /* R37 - ADC Digital Volume Right */
80 0x0000, /* R38 - ADC Digital 0 */
81 0x0073, /* R39 - Digital Microphone 0 */
82 0x09BF, /* R40 - DRC 0 */
83 0x3241, /* R41 - DRC 1 */
84 0x0020, /* R42 - DRC 2 */
85 0x0000, /* R43 - DRC 3 */
86 0x0085, /* R44 - Analogue Left Input 0 */
87 0x0085, /* R45 - Analogue Right Input 0 */
88 0x0044, /* R46 - Analogue Left Input 1 */
89 0x0044, /* R47 - Analogue Right Input 1 */
90 0x0000, /* R48 */
91 0x0000, /* R49 */
92 0x0008, /* R50 - Analogue Left Mix 0 */
93 0x0004, /* R51 - Analogue Right Mix 0 */
94 0x0000, /* R52 - Analogue Spk Mix Left 0 */
95 0x0000, /* R53 - Analogue Spk Mix Left 1 */
96 0x0000, /* R54 - Analogue Spk Mix Right 0 */
97 0x0000, /* R55 - Analogue Spk Mix Right 1 */
98 0x0000, /* R56 */
99 0x002D, /* R57 - Analogue OUT1 Left */
100 0x002D, /* R58 - Analogue OUT1 Right */
101 0x0039, /* R59 - Analogue OUT2 Left */
102 0x0039, /* R60 - Analogue OUT2 Right */
103 0x0100, /* R61 */
104 0x0139, /* R62 - Analogue OUT3 Left */
105 0x0139, /* R63 - Analogue OUT3 Right */
106 0x0000, /* R64 */
107 0x0000, /* R65 - Analogue SPK Output Control 0 */
108 0x0000, /* R66 */
109 0x0010, /* R67 - DC Servo 0 */
110 0x0100, /* R68 */
111 0x00A4, /* R69 - DC Servo 2 */
112 0x0807, /* R70 */
113 0x0000, /* R71 */
114 0x0000, /* R72 */
115 0x0000, /* R73 */
116 0x0000, /* R74 */
117 0x0000, /* R75 */
118 0x0000, /* R76 */
119 0x0000, /* R77 */
120 0x0000, /* R78 */
121 0x000E, /* R79 */
122 0x0000, /* R80 */
123 0x0000, /* R81 */
124 0x0000, /* R82 */
125 0x0000, /* R83 */
126 0x0000, /* R84 */
127 0x0000, /* R85 */
128 0x0000, /* R86 */
129 0x0006, /* R87 */
130 0x0000, /* R88 */
131 0x0000, /* R89 */
132 0x0000, /* R90 - Analogue HP 0 */
133 0x0060, /* R91 */
134 0x0000, /* R92 */
135 0x0000, /* R93 */
136 0x0000, /* R94 - Analogue Lineout 0 */
137 0x0060, /* R95 */
138 0x0000, /* R96 */
139 0x0000, /* R97 */
140 0x0000, /* R98 - Charge Pump 0 */
141 0x1F25, /* R99 */
142 0x2B19, /* R100 */
143 0x01C0, /* R101 */
144 0x01EF, /* R102 */
145 0x2B00, /* R103 */
146 0x0000, /* R104 - Class W 0 */
147 0x01C0, /* R105 */
148 0x1C10, /* R106 */
149 0x0000, /* R107 */
150 0x0000, /* R108 - Write Sequencer 0 */
151 0x0000, /* R109 - Write Sequencer 1 */
152 0x0000, /* R110 - Write Sequencer 2 */
153 0x0000, /* R111 - Write Sequencer 3 */
154 0x0000, /* R112 - Write Sequencer 4 */
155 0x0000, /* R113 */
156 0x0000, /* R114 - Control Interface */
157 0x0000, /* R115 */
158 0x00A8, /* R116 - GPIO Control 1 */
159 0x00A8, /* R117 - GPIO Control 2 */
160 0x00A8, /* R118 - GPIO Control 3 */
161 0x0220, /* R119 - GPIO Control 4 */
162 0x01A0, /* R120 - GPIO Control 5 */
163 0x0000, /* R121 - Interrupt Status 1 */
164 0xFFFF, /* R122 - Interrupt Status 1 Mask */
165 0x0000, /* R123 - Interrupt Polarity 1 */
166 0x0000, /* R124 */
167 0x0003, /* R125 */
168 0x0000, /* R126 - Interrupt Control */
169 0x0000, /* R127 */
170 0x0005, /* R128 */
171 0x0000, /* R129 - Control Interface Test 1 */
172 0x0000, /* R130 */
173 0x0000, /* R131 */
174 0x0000, /* R132 */
175 0x0000, /* R133 */
176 0x0000, /* R134 */
177 0x03FF, /* R135 */
178 0x0007, /* R136 */
179 0x0040, /* R137 */
180 0x0000, /* R138 */
181 0x0000, /* R139 */
182 0x0000, /* R140 */
183 0x0000, /* R141 */
184 0x0000, /* R142 */
185 0x0000, /* R143 */
186 0x0000, /* R144 */
187 0x0000, /* R145 */
188 0x0000, /* R146 */
189 0x0000, /* R147 */
190 0x4000, /* R148 */
191 0x6810, /* R149 - Charge Pump Test 1 */
192 0x0004, /* R150 */
193 0x0000, /* R151 */
194 0x0000, /* R152 */
195 0x0000, /* R153 */
196 0x0000, /* R154 */
197 0x0000, /* R155 */
198 0x0000, /* R156 */
199 0x0000, /* R157 */
200 0x0000, /* R158 */
201 0x0000, /* R159 */
202 0x0000, /* R160 */
203 0x0000, /* R161 */
204 0x0000, /* R162 */
205 0x0000, /* R163 */
206 0x0028, /* R164 - Clock Rate Test 4 */
207 0x0004, /* R165 */
208 0x0000, /* R166 */
209 0x0060, /* R167 */
210 0x0000, /* R168 */
211 0x0000, /* R169 */
212 0x0000, /* R170 */
213 0x0000, /* R171 */
214 0x0000, /* R172 - Analogue Output Bias 0 */
215};
216
d58d5d55 217struct wm8903_priv {
7cfe5617 218 struct snd_soc_codec *codec;
f0fba2ad 219
d58d5d55 220 int sysclk;
f0fba2ad 221 int irq;
d58d5d55 222
69fff9bb
MB		 223 int fs;
224 int deemph;
225
c5b6a9fe
MB		 226 int dcs_pending;
227 int dcs_cache[4];
228
f2c1fe09 229 /* Reference count */
d58d5d55 230 int class_w_users;
d58d5d55 231
8abd16a6
MB		 232 struct completion wseq;
233
7245387e
MB		 234 struct snd_soc_jack *mic_jack;
235 int mic_det;
236 int mic_short;
237 int mic_last_report;
238 int mic_delay;
7cfe5617
SW		 239
240#ifdef CONFIG_GPIOLIB
241 struct gpio_chip gpio_chip;
242#endif
d58d5d55
MB		 243};
244
d4754ec9 245static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 246{
247 switch (reg) {
248 case WM8903_SW_RESET_AND_ID:
249 case WM8903_REVISION_NUMBER:
250 case WM8903_INTERRUPT_STATUS_1:
251 case WM8903_WRITE_SEQUENCER_4:
13a9983e
MB		 252 case WM8903_POWER_MANAGEMENT_3:
253 case WM8903_POWER_MANAGEMENT_2:
c5b6a9fe
MB		 254 case WM8903_DC_SERVO_READBACK_1:
255 case WM8903_DC_SERVO_READBACK_2:
256 case WM8903_DC_SERVO_READBACK_3:
257 case WM8903_DC_SERVO_READBACK_4:
8d50e447 258 return 1;
f1c0a02f
MB		 259
260 default:
f1c0a02f 261 return 0;
8d50e447 262 }
f1c0a02f
MB		 263}
264
265static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
266{
267 u16 reg[5];
b2c812e2 268 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 269
270 BUG_ON(start > 48);
271
37f88e84 272 /* Enable the sequencer if it's not already on */
8d50e447 273 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 274 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
275 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 276
f0fba2ad 277 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 278
8d50e447 279 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 280 start | WM8903_WSEQ_START);
281
282 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 283 * that will break us out of the poll early.
f1c0a02f
MB		 284 */
285 do {
8abd16a6
MB		 286 wait_for_completion_timeout(&wm8903->wseq,
287 msecs_to_jiffies(10));
f1c0a02f 288
8d50e447 289 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 290 } while (reg[4] & WM8903_WSEQ_BUSY);
291
f0fba2ad 292 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 293
37f88e84
MB		 294 /* Disable the sequencer again if we enabled it */
295 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 296
297 return 0;
298}
299
f1c0a02f
MB		 300static void wm8903_reset(struct snd_soc_codec *codec)
301{
8d50e447 302 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 303 memcpy(codec->reg_cache, wm8903_reg_defaults,
304 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 305}
306
42768a12
MB		 307static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
308 struct snd_kcontrol *kcontrol, int event)
309{
310 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
311 mdelay(4);
312
313 return 0;
314}
315
c5b6a9fe
MB		 316static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
317 struct snd_kcontrol *kcontrol, int event)
318{
319 struct snd_soc_codec *codec = w->codec;
320 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
321
322 switch (event) {
323 case SND_SOC_DAPM_POST_PMU:
324 wm8903->dcs_pending |= 1 << w->shift;
325 break;
326 case SND_SOC_DAPM_PRE_PMD:
327 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
328 1 << w->shift, 0);
329 break;
330 }
331
332 return 0;
333}
334
335#define WM8903_DCS_MODE_WRITE_STOP 0
336#define WM8903_DCS_MODE_START_STOP 2
337
338static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
339 enum snd_soc_dapm_type event, int subseq)
340{
341 struct snd_soc_codec *codec = container_of(dapm,
342 struct snd_soc_codec, dapm);
343 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
344 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
345 int i, val;
346
347 /* Complete any pending DC servo starts */
348 if (wm8903->dcs_pending) {
349 dev_dbg(codec->dev, "Starting DC servo for %x\n",
350 wm8903->dcs_pending);
351
352 /* If we've no cached values then we need to do startup */
353 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
354 if (!(wm8903->dcs_pending & (1 << i)))
355 continue;
356
357 if (wm8903->dcs_cache[i]) {
358 dev_dbg(codec->dev,
359 "Restore DC servo %d value %x\n",
360 3 - i, wm8903->dcs_cache[i]);
361
362 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
363 wm8903->dcs_cache[i] & 0xff);
364 } else {
365 dev_dbg(codec->dev,
366 "Calibrate DC servo %d\n", 3 - i);
367 dcs_mode = WM8903_DCS_MODE_START_STOP;
368 }
369 }
370
371 /* Don't trust the cache for analogue */
372 if (wm8903->class_w_users)
373 dcs_mode = WM8903_DCS_MODE_START_STOP;
374
375 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
376 WM8903_DCS_MODE_MASK, dcs_mode);
377
378 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
379 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
380
381 switch (dcs_mode) {
382 case WM8903_DCS_MODE_WRITE_STOP:
383 break;
384
385 case WM8903_DCS_MODE_START_STOP:
386 msleep(270);
387
388 /* Cache the measured offsets for digital */
389 if (wm8903->class_w_users)
390 break;
391
392 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
393 if (!(wm8903->dcs_pending & (1 << i)))
394 continue;
395
396 val = snd_soc_read(codec,
397 WM8903_DC_SERVO_READBACK_1 + i);
398 dev_dbg(codec->dev, "DC servo %d: %x\n",
399 3 - i, val);
400 wm8903->dcs_cache[i] = val;
401 }
402 break;
403
404 default:
405 pr_warn("DCS mode %d delay not set\n", dcs_mode);
406 break;
407 }
408
409 wm8903->dcs_pending = 0;
410 }
411}
412
f1c0a02f
MB		 413/*
414 * When used with DAC outputs only the WM8903 charge pump supports
415 * operation in class W mode, providing very low power consumption
416 * when used with digital sources. Enable and disable this mode
417 * automatically depending on the mixer configuration.
418 *
419 * All the relevant controls are simple switches.
420 */
421static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
422 struct snd_ctl_elem_value *ucontrol)
423{
424 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
425 struct snd_soc_codec *codec = widget->codec;
b2c812e2 426 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 427 u16 reg;
428 int ret;
429
8d50e447 430 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 431
432 /* Turn it off if we're about to enable bypass */
433 if (ucontrol->value.integer.value[0]) {
434 if (wm8903->class_w_users == 0) {
f0fba2ad 435 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 436 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 437 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
438 }
439 wm8903->class_w_users++;
440 }
441
442 /* Implement the change */
443 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
444
445 /* If we've just disabled the last bypass path turn Class W on */
446 if (!ucontrol->value.integer.value[0]) {
447 if (wm8903->class_w_users == 1) {
f0fba2ad 448 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 449 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 450 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
451 }
452 wm8903->class_w_users--;
453 }
454
f0fba2ad 455 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 456 wm8903->class_w_users);
457
458 return ret;
459}
460
461#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
462{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
463 .info = snd_soc_info_volsw, \
464 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
465 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
466
467
69fff9bb
MB		 468static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
469
470static int wm8903_set_deemph(struct snd_soc_codec *codec)
471{
472 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
473 int val, i, best;
474
475 /* If we're using deemphasis select the nearest available sample
476 * rate.
477 */
478 if (wm8903->deemph) {
479 best = 1;
480 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
481 if (abs(wm8903_deemph[i] - wm8903->fs) <
482 abs(wm8903_deemph[best] - wm8903->fs))
483 best = i;
484 }
485
486 val = best << WM8903_DEEMPH_SHIFT;
487 } else {
488 best = 0;
489 val = 0;
490 }
491
492 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
493 best, wm8903_deemph[best]);
494
495 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
496 WM8903_DEEMPH_MASK, val);
497}
498
499static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
500 struct snd_ctl_elem_value *ucontrol)
501{
502 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
503 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
504
505 ucontrol->value.enumerated.item[0] = wm8903->deemph;
506
507 return 0;
508}
509
510static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
511 struct snd_ctl_elem_value *ucontrol)
512{
513 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
514 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
515 int deemph = ucontrol->value.enumerated.item[0];
516 int ret = 0;
517
518 if (deemph > 1)
519 return -EINVAL;
520
521 mutex_lock(&codec->mutex);
522 if (wm8903->deemph != deemph) {
523 wm8903->deemph = deemph;
524
525 wm8903_set_deemph(codec);
526
527 ret = 1;
528 }
529 mutex_unlock(&codec->mutex);
530
531 return ret;
532}
533
f1c0a02f
MB		 534/* ALSA can only do steps of .01dB */
535static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
536
291ce18c 537static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 538static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
539
540static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
541static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
542static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
543static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
544static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
545
460f4aae
MB		 546static const char *hpf_mode_text[] = {
547 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
548};
549
550static const struct soc_enum hpf_mode =
551 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
552
dcf9ada3
MB		 553static const char *osr_text[] = {
554 "Low power", "High performance"
555};
556
557static const struct soc_enum adc_osr =
558 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
559
560static const struct soc_enum dac_osr =
561 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
562
f1c0a02f
MB		 563static const char *drc_slope_text[] = {
564 "1", "1/2", "1/4", "1/8", "1/16", "0"
565};
566
567static const struct soc_enum drc_slope_r0 =
568 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
569
570static const struct soc_enum drc_slope_r1 =
571 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
572
573static const char *drc_attack_text[] = {
574 "instantaneous",
575 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
576 "46.4ms", "92.8ms", "185.6ms"
577};
578
579static const struct soc_enum drc_attack =
580 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
581
582static const char *drc_decay_text[] = {
583 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
584 "23.87s", "47.56s"
585};
586
587static const struct soc_enum drc_decay =
588 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
589
590static const char *drc_ff_delay_text[] = {
591 "5 samples", "9 samples"
592};
593
594static const struct soc_enum drc_ff_delay =
595 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
596
597static const char *drc_qr_decay_text[] = {
598 "0.725ms", "1.45ms", "5.8ms"
599};
600
601static const struct soc_enum drc_qr_decay =
602 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
603
604static const char *drc_smoothing_text[] = {
605 "Low", "Medium", "High"
606};
607
608static const struct soc_enum drc_smoothing =
609 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
610
611static const char *soft_mute_text[] = {
612 "Fast (fs/2)", "Slow (fs/32)"
613};
614
615static const struct soc_enum soft_mute =
616 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
617
618static const char *mute_mode_text[] = {
619 "Hard", "Soft"
620};
621
622static const struct soc_enum mute_mode =
623 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
624
f1c0a02f
MB		 625static const char *companding_text[] = {
626 "ulaw", "alaw"
627};
628
629static const struct soc_enum dac_companding =
630 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
631
632static const struct soc_enum adc_companding =
633 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
634
635static const char *input_mode_text[] = {
636 "Single-Ended", "Differential Line", "Differential Mic"
637};
638
639static const struct soc_enum linput_mode_enum =
640 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
641
642static const struct soc_enum rinput_mode_enum =
643 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
644
645static const char *linput_mux_text[] = {
646 "IN1L", "IN2L", "IN3L"
647};
648
649static const struct soc_enum linput_enum =
650 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
651
652static const struct soc_enum linput_inv_enum =
653 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
654
655static const char *rinput_mux_text[] = {
656 "IN1R", "IN2R", "IN3R"
657};
658
659static const struct soc_enum rinput_enum =
660 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
661
662static const struct soc_enum rinput_inv_enum =
663 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
664
665
291ce18c
MB		 666static const char *sidetone_text[] = {
667 "None", "Left", "Right"
668};
669
670static const struct soc_enum lsidetone_enum =
671 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
672
673static const struct soc_enum rsidetone_enum =
674 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
675
1e113bf9
MB		 676static const char *aif_text[] = {
677 "Left", "Right"
678};
679
680static const struct soc_enum lcapture_enum =
681 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
682
683static const struct soc_enum rcapture_enum =
684 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
685
686static const struct soc_enum lplay_enum =
687 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
688
689static const struct soc_enum rplay_enum =
690 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
691
f1c0a02f
MB		 692static const struct snd_kcontrol_new wm8903_snd_controls[] = {
693
694/* Input PGAs - No TLV since the scale depends on PGA mode */
695SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 696 7, 1, 1),
f1c0a02f
MB		 697SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
698 0, 31, 0),
699SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
700 6, 1, 0),
701
702SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 703 7, 1, 1),
f1c0a02f
MB		 704SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
705 0, 31, 0),
706SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
707 6, 1, 0),
708
709/* ADCs */
dcf9ada3 710SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 711SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
712SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 713SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
714SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
715SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 716SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 717 drc_tlv_thresh),
718SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
719SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
720SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
721SOC_ENUM("DRC Attack Rate", drc_attack),
722SOC_ENUM("DRC Decay Rate", drc_decay),
723SOC_ENUM("DRC FF Delay", drc_ff_delay),
724SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
725SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 726SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 727SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
728SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
729SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 730SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 731SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
732
733SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
734 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
735SOC_ENUM("ADC Companding Mode", adc_companding),
736SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
737
291ce18c
MB		 738SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
739 12, 0, digital_sidetone_tlv),
740
f1c0a02f 741/* DAC */
dcf9ada3 742SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 743SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
744 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
745SOC_ENUM("DAC Soft Mute Rate", soft_mute),
746SOC_ENUM("DAC Mute Mode", mute_mode),
747SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 748SOC_ENUM("DAC Companding Mode", dac_companding),
749SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 750SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
751 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 752
753/* Headphones */
754SOC_DOUBLE_R("Headphone Switch",
755 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
756 8, 1, 1),
757SOC_DOUBLE_R("Headphone ZC Switch",
758 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
759 6, 1, 0),
760SOC_DOUBLE_R_TLV("Headphone Volume",
761 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
762 0, 63, 0, out_tlv),
763
764/* Line out */
765SOC_DOUBLE_R("Line Out Switch",
766 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
767 8, 1, 1),
768SOC_DOUBLE_R("Line Out ZC Switch",
769 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
770 6, 1, 0),
771SOC_DOUBLE_R_TLV("Line Out Volume",
772 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
773 0, 63, 0, out_tlv),
774
775/* Speaker */
776SOC_DOUBLE_R("Speaker Switch",
777 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
778SOC_DOUBLE_R("Speaker ZC Switch",
779 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
780SOC_DOUBLE_R_TLV("Speaker Volume",
781 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
782 0, 63, 0, out_tlv),
783};
784
f1c0a02f
MB		 785static const struct snd_kcontrol_new linput_mode_mux =
786 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
787
788static const struct snd_kcontrol_new rinput_mode_mux =
789 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
790
791static const struct snd_kcontrol_new linput_mux =
792 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
793
794static const struct snd_kcontrol_new linput_inv_mux =
795 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
796
797static const struct snd_kcontrol_new rinput_mux =
798 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
799
800static const struct snd_kcontrol_new rinput_inv_mux =
801 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
802
291ce18c
MB		 803static const struct snd_kcontrol_new lsidetone_mux =
804 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
805
806static const struct snd_kcontrol_new rsidetone_mux =
807 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
808
1e113bf9
MB		 809static const struct snd_kcontrol_new lcapture_mux =
810 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
811
812static const struct snd_kcontrol_new rcapture_mux =
813 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
814
815static const struct snd_kcontrol_new lplay_mux =
816 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
817
818static const struct snd_kcontrol_new rplay_mux =
819 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
820
f1c0a02f
MB		 821static const struct snd_kcontrol_new left_output_mixer[] = {
822SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
823SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
824SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 825SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 826};
827
828static const struct snd_kcontrol_new right_output_mixer[] = {
829SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
830SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
831SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 832SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 833};
834
835static const struct snd_kcontrol_new left_speaker_mixer[] = {
836SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
837SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
838SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
839SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 840 0, 1, 0),
f1c0a02f
MB		 841};
842
843static const struct snd_kcontrol_new right_speaker_mixer[] = {
844SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
845SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
846SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
847 1, 1, 0),
848SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 849 0, 1, 0),
f1c0a02f
MB		 850};
851
852static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
853SND_SOC_DAPM_INPUT("IN1L"),
854SND_SOC_DAPM_INPUT("IN1R"),
855SND_SOC_DAPM_INPUT("IN2L"),
856SND_SOC_DAPM_INPUT("IN2R"),
857SND_SOC_DAPM_INPUT("IN3L"),
858SND_SOC_DAPM_INPUT("IN3R"),
859
860SND_SOC_DAPM_OUTPUT("HPOUTL"),
861SND_SOC_DAPM_OUTPUT("HPOUTR"),
862SND_SOC_DAPM_OUTPUT("LINEOUTL"),
863SND_SOC_DAPM_OUTPUT("LINEOUTR"),
864SND_SOC_DAPM_OUTPUT("LOP"),
865SND_SOC_DAPM_OUTPUT("LON"),
866SND_SOC_DAPM_OUTPUT("ROP"),
867SND_SOC_DAPM_OUTPUT("RON"),
868
869SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
870
871SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
872SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
873 &linput_inv_mux),
874SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
875
876SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
877SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
878 &rinput_inv_mux),
879SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
880
881SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
882SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
883
1e113bf9
MB		 884SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
885SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
886
887SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
888SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
889
890SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
891SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 892
291ce18c
MB		 893SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
894SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
895
1e113bf9
MB		 896SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
897SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
898
899SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
900SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
901
902SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
903SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 904
905SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
906 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
907SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
908 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
909
910SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
911 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
912SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
913 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
914
13a9983e
MB		 915SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
916 4, 0, NULL, 0),
917SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_ANALOGUE_HP_0,
918 0, 0, NULL, 0),
919
920SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
921 NULL, 0),
922SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
923 NULL, 0),
924
925SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
926SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
927SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
928SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
929SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
930SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 1, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
931
932SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
933 NULL, 0),
934SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
935 NULL, 0),
936SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
937 NULL, 0),
938SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
939 NULL, 0),
940SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
941 NULL, 0),
942SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 1, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
943 NULL, 0),
944
c5b6a9fe
MB		 945SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
946SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
947 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
948SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
949 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
950SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
951 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
952SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
953 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 954
955SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
956 NULL, 0),
957SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
958 NULL, 0),
959
42768a12
MB		 960SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
961 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 962SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 963SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 964};
965
966static const struct snd_soc_dapm_route intercon[] = {
967
2c8be5a2
MB		 968 { "CLK_DSP", NULL, "CLK_SYS" },
969 { "Mic Bias", NULL, "CLK_SYS" },
970 { "HPL_DCS", NULL, "CLK_SYS" },
971 { "HPR_DCS", NULL, "CLK_SYS" },
972 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
973 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
974
f1c0a02f
MB		 975 { "Left Input Mux", "IN1L", "IN1L" },
976 { "Left Input Mux", "IN2L", "IN2L" },
977 { "Left Input Mux", "IN3L", "IN3L" },
978
979 { "Left Input Inverting Mux", "IN1L", "IN1L" },
980 { "Left Input Inverting Mux", "IN2L", "IN2L" },
981 { "Left Input Inverting Mux", "IN3L", "IN3L" },
982
983 { "Right Input Mux", "IN1R", "IN1R" },
984 { "Right Input Mux", "IN2R", "IN2R" },
985 { "Right Input Mux", "IN3R", "IN3R" },
986
987 { "Right Input Inverting Mux", "IN1R", "IN1R" },
988 { "Right Input Inverting Mux", "IN2R", "IN2R" },
989 { "Right Input Inverting Mux", "IN3R", "IN3R" },
990
991 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
992 { "Left Input Mode Mux", "Differential Line",
993 "Left Input Mux" },
994 { "Left Input Mode Mux", "Differential Line",
995 "Left Input Inverting Mux" },
996 { "Left Input Mode Mux", "Differential Mic",
997 "Left Input Mux" },
998 { "Left Input Mode Mux", "Differential Mic",
999 "Left Input Inverting Mux" },
1000
1001 { "Right Input Mode Mux", "Single-Ended",
1002 "Right Input Inverting Mux" },
1003 { "Right Input Mode Mux", "Differential Line",
1004 "Right Input Mux" },
1005 { "Right Input Mode Mux", "Differential Line",
1006 "Right Input Inverting Mux" },
1007 { "Right Input Mode Mux", "Differential Mic",
1008 "Right Input Mux" },
1009 { "Right Input Mode Mux", "Differential Mic",
1010 "Right Input Inverting Mux" },
1011
1012 { "Left Input PGA", NULL, "Left Input Mode Mux" },
1013 { "Right Input PGA", NULL, "Right Input Mode Mux" },
1014
1e113bf9
MB		 1015 { "Left Capture Mux", "Left", "ADCL" },
1016 { "Left Capture Mux", "Right", "ADCR" },
1017
1018 { "Right Capture Mux", "Left", "ADCL" },
1019 { "Right Capture Mux", "Right", "ADCR" },
1020
1021 { "AIFTXL", NULL, "Left Capture Mux" },
1022 { "AIFTXR", NULL, "Right Capture Mux" },
1023
f1c0a02f 1024 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 1025 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 1026 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 1027 { "ADCR", NULL, "CLK_DSP" },
1028
1e113bf9
MB		 1029 { "Left Playback Mux", "Left", "AIFRXL" },
1030 { "Left Playback Mux", "Right", "AIFRXR" },
1031
1032 { "Right Playback Mux", "Left", "AIFRXL" },
1033 { "Right Playback Mux", "Right", "AIFRXR" },
1034
291ce18c
MB		 1035 { "DACL Sidetone", "Left", "ADCL" },
1036 { "DACL Sidetone", "Right", "ADCR" },
1037 { "DACR Sidetone", "Left", "ADCL" },
1038 { "DACR Sidetone", "Right", "ADCR" },
1039
1e113bf9 1040 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1041 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1042 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1043
1044 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1045 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1046 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1047
1048 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1049 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1050 { "Left Output Mixer", "DACL Switch", "DACL" },
1051 { "Left Output Mixer", "DACR Switch", "DACR" },
1052
1053 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1054 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1055 { "Right Output Mixer", "DACL Switch", "DACL" },
1056 { "Right Output Mixer", "DACR Switch", "DACR" },
1057
1058 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1059 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1060 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1061 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1062
1063 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1064 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1065 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1066 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1067
1068 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1069 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1070
1071 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1072 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1073
1074 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1075 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1076
13a9983e
MB		 1077 { "HPL_ENA_DLY", NULL, "Left Headphone Output PGA" },
1078 { "HPR_ENA_DLY", NULL, "Right Headphone Output PGA" },
1079 { "LINEOUTL_ENA_DLY", NULL, "Left Line Output PGA" },
1080 { "LINEOUTR_ENA_DLY", NULL, "Right Line Output PGA" },
1081
c5b6a9fe
MB		 1082 { "HPL_DCS", NULL, "DCS Master" },
1083 { "HPR_DCS", NULL, "DCS Master" },
1084 { "LINEOUTL_DCS", NULL, "DCS Master" },
1085 { "LINEOUTR_DCS", NULL, "DCS Master" },
1086
13a9983e
MB		 1087 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1088 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1089 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1090 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1091
1092 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1093 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1094 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1095 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1096
1097 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1098 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1099 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1100 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1101
1102 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1103 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1104 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1105 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1106
1107 { "LOP", NULL, "Left Speaker PGA" },
1108 { "LON", NULL, "Left Speaker PGA" },
1109
1110 { "ROP", NULL, "Right Speaker PGA" },
1111 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1112
1113 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1114 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1115 { "Left Line Output PGA", NULL, "Charge Pump" },
1116 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1117};
1118
1119static int wm8903_add_widgets(struct snd_soc_codec *codec)
1120{
ce6120cc 1121 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 1122
ce6120cc
LG		 1123 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1124 ARRAY_SIZE(wm8903_dapm_widgets));
1125 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 1126
f1c0a02f
MB		 1127 return 0;
1128}
1129
1130static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1131 enum snd_soc_bias_level level)
1132{
f1c0a02f
MB		 1133 switch (level) {
1134 case SND_SOC_BIAS_ON:
66daaa59 1135 break;
22f226dd 1136
f1c0a02f 1137 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1138 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1139 WM8903_VMID_RES_MASK,
1140 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1141 break;
1142
1143 case SND_SOC_BIAS_STANDBY:
ce6120cc 1144 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1145 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1146 WM8903_POBCTRL | WM8903_ISEL_MASK |
1147 WM8903_STARTUP_BIAS_ENA |
1148 WM8903_BIAS_ENA,
1149 WM8903_POBCTRL |
1150 (2 << WM8903_ISEL_SHIFT) |
1151 WM8903_STARTUP_BIAS_ENA);
1152
1153 snd_soc_update_bits(codec,
1154 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1155 WM8903_SPK_DISCHARGE,
1156 WM8903_SPK_DISCHARGE);
1157
1158 msleep(33);
1159
1160 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1161 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1162 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1163
1164 snd_soc_update_bits(codec,
1165 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1166 WM8903_SPK_DISCHARGE, 0);
1167
1168 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1169 WM8903_VMID_TIE_ENA |
1170 WM8903_BUFIO_ENA |
1171 WM8903_VMID_IO_ENA |
1172 WM8903_VMID_SOFT_MASK |
1173 WM8903_VMID_RES_MASK |
1174 WM8903_VMID_BUF_ENA,
1175 WM8903_VMID_TIE_ENA |
1176 WM8903_BUFIO_ENA |
1177 WM8903_VMID_IO_ENA |
1178 (2 << WM8903_VMID_SOFT_SHIFT) |
1179 WM8903_VMID_RES_250K |
1180 WM8903_VMID_BUF_ENA);
1181
1182 msleep(129);
1183
1184 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1185 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1186 0);
1187
1188 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1189 WM8903_VMID_SOFT_MASK, 0);
1190
1191 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1192 WM8903_VMID_RES_MASK,
1193 WM8903_VMID_RES_50K);
1194
1195 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1196 WM8903_BIAS_ENA | WM8903_POBCTRL,
1197 WM8903_BIAS_ENA);
f1c0a02f 1198
f1c0a02f
MB		 1199 /* By default no bypass paths are enabled so
1200 * enable Class W support.
1201 */
f0fba2ad 1202 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1203 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1204 WM8903_CP_DYN_FREQ |
1205 WM8903_CP_DYN_V,
1206 WM8903_CP_DYN_FREQ |
1207 WM8903_CP_DYN_V);
f1c0a02f
MB		 1208 }
1209
66daaa59
MB		 1210 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1211 WM8903_VMID_RES_MASK,
1212 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1213 break;
1214
1215 case SND_SOC_BIAS_OFF:
2c8be5a2
MB		 1216 snd_soc_update_bits(codec, WM8903_CLOCK_RATES_2,
1217 WM8903_CLK_SYS_ENA, WM8903_CLK_SYS_ENA);
f1c0a02f 1218 wm8903_run_sequence(codec, 32);
2c8be5a2
MB		 1219 snd_soc_update_bits(codec, WM8903_CLOCK_RATES_2,
1220 WM8903_CLK_SYS_ENA, 0);
f1c0a02f
MB		 1221 break;
1222 }
1223
ce6120cc 1224 codec->dapm.bias_level = level;
f1c0a02f
MB		 1225
1226 return 0;
1227}
1228
1229static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1230 int clk_id, unsigned int freq, int dir)
1231{
1232 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1233 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1234
1235 wm8903->sysclk = freq;
1236
1237 return 0;
1238}
1239
1240static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1241 unsigned int fmt)
1242{
1243 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1244 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1245
1246 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1247 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1248
1249 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1250 case SND_SOC_DAIFMT_CBS_CFS:
1251 break;
1252 case SND_SOC_DAIFMT_CBS_CFM:
1253 aif1 |= WM8903_LRCLK_DIR;
1254 break;
1255 case SND_SOC_DAIFMT_CBM_CFM:
1256 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1257 break;
1258 case SND_SOC_DAIFMT_CBM_CFS:
1259 aif1 |= WM8903_BCLK_DIR;
1260 break;
1261 default:
1262 return -EINVAL;
1263 }
1264
1265 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1266 case SND_SOC_DAIFMT_DSP_A:
1267 aif1 |= 0x3;
1268 break;
1269 case SND_SOC_DAIFMT_DSP_B:
1270 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1271 break;
1272 case SND_SOC_DAIFMT_I2S:
1273 aif1 |= 0x2;
1274 break;
1275 case SND_SOC_DAIFMT_RIGHT_J:
1276 aif1 |= 0x1;
1277 break;
1278 case SND_SOC_DAIFMT_LEFT_J:
1279 break;
1280 default:
1281 return -EINVAL;
1282 }
1283
1284 /* Clock inversion */
1285 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1286 case SND_SOC_DAIFMT_DSP_A:
1287 case SND_SOC_DAIFMT_DSP_B:
1288 /* frame inversion not valid for DSP modes */
1289 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1290 case SND_SOC_DAIFMT_NB_NF:
1291 break;
1292 case SND_SOC_DAIFMT_IB_NF:
1293 aif1 |= WM8903_AIF_BCLK_INV;
1294 break;
1295 default:
1296 return -EINVAL;
1297 }
1298 break;
1299 case SND_SOC_DAIFMT_I2S:
1300 case SND_SOC_DAIFMT_RIGHT_J:
1301 case SND_SOC_DAIFMT_LEFT_J:
1302 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1303 case SND_SOC_DAIFMT_NB_NF:
1304 break;
1305 case SND_SOC_DAIFMT_IB_IF:
1306 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1307 break;
1308 case SND_SOC_DAIFMT_IB_NF:
1309 aif1 |= WM8903_AIF_BCLK_INV;
1310 break;
1311 case SND_SOC_DAIFMT_NB_IF:
1312 aif1 |= WM8903_AIF_LRCLK_INV;
1313 break;
1314 default:
1315 return -EINVAL;
1316 }
1317 break;
1318 default:
1319 return -EINVAL;
1320 }
1321
8d50e447 1322 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1323
1324 return 0;
1325}
1326
1327static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1328{
1329 struct snd_soc_codec *codec = codec_dai->codec;
1330 u16 reg;
1331
8d50e447 1332 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1333
1334 if (mute)
1335 reg |= WM8903_DAC_MUTE;
1336 else
1337 reg &= ~WM8903_DAC_MUTE;
1338
8d50e447 1339 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1340
1341 return 0;
1342}
1343
1344/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1345 * for optimal performance so we list the lower rates first and match
1346 * on the last match we find. */
1347static struct {
1348 int div;
1349 int rate;
1350 int mode;
1351 int mclk_div;
1352} clk_sys_ratios[] = {
1353 { 64, 0x0, 0x0, 1 },
1354 { 68, 0x0, 0x1, 1 },
1355 { 125, 0x0, 0x2, 1 },
1356 { 128, 0x1, 0x0, 1 },
1357 { 136, 0x1, 0x1, 1 },
1358 { 192, 0x2, 0x0, 1 },
1359 { 204, 0x2, 0x1, 1 },
1360
1361 { 64, 0x0, 0x0, 2 },
1362 { 68, 0x0, 0x1, 2 },
1363 { 125, 0x0, 0x2, 2 },
1364 { 128, 0x1, 0x0, 2 },
1365 { 136, 0x1, 0x1, 2 },
1366 { 192, 0x2, 0x0, 2 },
1367 { 204, 0x2, 0x1, 2 },
1368
1369 { 250, 0x2, 0x2, 1 },
1370 { 256, 0x3, 0x0, 1 },
1371 { 272, 0x3, 0x1, 1 },
1372 { 384, 0x4, 0x0, 1 },
1373 { 408, 0x4, 0x1, 1 },
1374 { 375, 0x4, 0x2, 1 },
1375 { 512, 0x5, 0x0, 1 },
1376 { 544, 0x5, 0x1, 1 },
1377 { 500, 0x5, 0x2, 1 },
1378 { 768, 0x6, 0x0, 1 },
1379 { 816, 0x6, 0x1, 1 },
1380 { 750, 0x6, 0x2, 1 },
1381 { 1024, 0x7, 0x0, 1 },
1382 { 1088, 0x7, 0x1, 1 },
1383 { 1000, 0x7, 0x2, 1 },
1384 { 1408, 0x8, 0x0, 1 },
1385 { 1496, 0x8, 0x1, 1 },
1386 { 1536, 0x9, 0x0, 1 },
1387 { 1632, 0x9, 0x1, 1 },
1388 { 1500, 0x9, 0x2, 1 },
1389
1390 { 250, 0x2, 0x2, 2 },
1391 { 256, 0x3, 0x0, 2 },
1392 { 272, 0x3, 0x1, 2 },
1393 { 384, 0x4, 0x0, 2 },
1394 { 408, 0x4, 0x1, 2 },
1395 { 375, 0x4, 0x2, 2 },
1396 { 512, 0x5, 0x0, 2 },
1397 { 544, 0x5, 0x1, 2 },
1398 { 500, 0x5, 0x2, 2 },
1399 { 768, 0x6, 0x0, 2 },
1400 { 816, 0x6, 0x1, 2 },
1401 { 750, 0x6, 0x2, 2 },
1402 { 1024, 0x7, 0x0, 2 },
1403 { 1088, 0x7, 0x1, 2 },
1404 { 1000, 0x7, 0x2, 2 },
1405 { 1408, 0x8, 0x0, 2 },
1406 { 1496, 0x8, 0x1, 2 },
1407 { 1536, 0x9, 0x0, 2 },
1408 { 1632, 0x9, 0x1, 2 },
1409 { 1500, 0x9, 0x2, 2 },
1410};
1411
1412/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1413static struct {
1414 int ratio;
1415 int div;
1416} bclk_divs[] = {
1417 { 10, 0 },
f1c0a02f
MB		 1418 { 20, 2 },
1419 { 30, 3 },
1420 { 40, 4 },
1421 { 50, 5 },
f1c0a02f
MB		 1422 { 60, 7 },
1423 { 80, 8 },
1424 { 100, 9 },
f1c0a02f
MB		 1425 { 120, 11 },
1426 { 160, 12 },
1427 { 200, 13 },
1428 { 220, 14 },
1429 { 240, 15 },
f1c0a02f
MB		 1430 { 300, 17 },
1431 { 320, 18 },
1432 { 440, 19 },
1433 { 480, 20 },
1434};
1435
1436/* Sample rates for DSP */
1437static struct {
1438 int rate;
1439 int value;
1440} sample_rates[] = {
1441 { 8000, 0 },
1442 { 11025, 1 },
1443 { 12000, 2 },
1444 { 16000, 3 },
1445 { 22050, 4 },
1446 { 24000, 5 },
1447 { 32000, 6 },
1448 { 44100, 7 },
1449 { 48000, 8 },
1450 { 88200, 9 },
1451 { 96000, 10 },
1452 { 0, 0 },
1453};
1454
f1c0a02f 1455static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1456 struct snd_pcm_hw_params *params,
1457 struct snd_soc_dai *dai)
f1c0a02f
MB		 1458{
1459 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1460 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1461 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1462 int fs = params_rate(params);
1463 int bclk;
1464 int bclk_div;
1465 int i;
1466 int dsp_config;
1467 int clk_config;
1468 int best_val;
1469 int cur_val;
1470 int clk_sys;
1471
8d50e447
MB		 1472 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1473 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1474 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1475 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1476 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1477 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1478
9e79261f
MB		 1479 /* Enable sloping stopband filter for low sample rates */
1480 if (fs <= 24000)
1481 dac_digital1 |= WM8903_DAC_SB_FILT;
1482 else
1483 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1484
f1c0a02f
MB		 1485 /* Configure sample rate logic for DSP - choose nearest rate */
1486 dsp_config = 0;
1487 best_val = abs(sample_rates[dsp_config].rate - fs);
1488 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1489 cur_val = abs(sample_rates[i].rate - fs);
1490 if (cur_val <= best_val) {
1491 dsp_config = i;
1492 best_val = cur_val;
1493 }
1494 }
1495
f0fba2ad 1496 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1497 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1498 clock1 |= sample_rates[dsp_config].value;
1499
1500 aif1 &= ~WM8903_AIF_WL_MASK;
1501 bclk = 2 * fs;
1502 switch (params_format(params)) {
1503 case SNDRV_PCM_FORMAT_S16_LE:
1504 bclk *= 16;
1505 break;
1506 case SNDRV_PCM_FORMAT_S20_3LE:
1507 bclk *= 20;
1508 aif1 |= 0x4;
1509 break;
1510 case SNDRV_PCM_FORMAT_S24_LE:
1511 bclk *= 24;
1512 aif1 |= 0x8;
1513 break;
1514 case SNDRV_PCM_FORMAT_S32_LE:
1515 bclk *= 32;
1516 aif1 |= 0xc;
1517 break;
1518 default:
1519 return -EINVAL;
1520 }
1521
f0fba2ad 1522 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1523 wm8903->sysclk, fs);
1524
1525 /* We may not have an MCLK which allows us to generate exactly
1526 * the clock we want, particularly with USB derived inputs, so
1527 * approximate.
1528 */
1529 clk_config = 0;
1530 best_val = abs((wm8903->sysclk /
1531 (clk_sys_ratios[0].mclk_div *
1532 clk_sys_ratios[0].div)) - fs);
1533 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1534 cur_val = abs((wm8903->sysclk /
1535 (clk_sys_ratios[i].mclk_div *
1536 clk_sys_ratios[i].div)) - fs);
1537
1538 if (cur_val <= best_val) {
1539 clk_config = i;
1540 best_val = cur_val;
1541 }
1542 }
1543
1544 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1545 clock0 |= WM8903_MCLKDIV2;
1546 clk_sys = wm8903->sysclk / 2;
1547 } else {
1548 clock0 &= ~WM8903_MCLKDIV2;
1549 clk_sys = wm8903->sysclk;
1550 }
1551
1552 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1553 WM8903_CLK_SYS_MODE_MASK);
1554 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1555 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1556
f0fba2ad 1557 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1558 clk_sys_ratios[clk_config].rate,
1559 clk_sys_ratios[clk_config].mode,
1560 clk_sys_ratios[clk_config].div);
1561
f0fba2ad 1562 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1563
1564 /* We may not get quite the right frequency if using
1565 * approximate clocks so look for the closest match that is
1566 * higher than the target (we need to ensure that there enough
1567 * BCLKs to clock out the samples).
1568 */
1569 bclk_div = 0;
1570 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1571 i = 1;
1572 while (i < ARRAY_SIZE(bclk_divs)) {
1573 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1574 if (cur_val < 0) /* BCLK table is sorted */
1575 break;
1576 bclk_div = i;
1577 best_val = cur_val;
1578 i++;
1579 }
1580
1581 aif2 &= ~WM8903_BCLK_DIV_MASK;
1582 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1583
f0fba2ad 1584 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1585 bclk_divs[bclk_div].ratio / 10, bclk,
1586 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1587
1588 aif2 |= bclk_divs[bclk_div].div;
1589 aif3 |= bclk / fs;
1590
69fff9bb
MB		 1591 wm8903->fs = params_rate(params);
1592 wm8903_set_deemph(codec);
1593
8d50e447
MB		 1594 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1595 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1596 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1597 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1598 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1599 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1600
1601 return 0;
1602}
1603
7245387e
MB		 1604/**
1605 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1606 *
1607 * @codec: WM8903 codec
1608 * @jack: jack to report detection events on
1609 * @det: value to report for presence detection
1610 * @shrt: value to report for short detection
1611 *
1612 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1613 * being used to bring out signals to the processor then only platform
1614 * data configuration is needed for WM8903 and processor GPIOs should
1615 * be configured using snd_soc_jack_add_gpios() instead.
1616 *
1617 * The current threasholds for detection should be configured using
1618 * micdet_cfg in the platform data. Using this function will force on
1619 * the microphone bias for the device.
1620 */
1621int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1622 int det, int shrt)
1623{
b2c812e2 1624 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1625 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1626
1627 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1628 det, shrt);
1629
1630 /* Store the configuration */
1631 wm8903->mic_jack = jack;
1632 wm8903->mic_det = det;
1633 wm8903->mic_short = shrt;
1634
1635 /* Enable interrupts we've got a report configured for */
1636 if (det)
1637 irq_mask &= ~WM8903_MICDET_EINT;
1638 if (shrt)
1639 irq_mask &= ~WM8903_MICSHRT_EINT;
1640
1641 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1642 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1643 irq_mask);
1644
69266866
MB		 1645 if (det && shrt) {
1646 /* Enable mic detection, this may not have been set through
1647 * platform data (eg, if the defaults are OK). */
1648 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1649 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1650 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1651 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1652 } else {
1653 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1654 WM8903_MICDET_ENA, 0);
1655 }
7245387e
MB		 1656
1657 return 0;
1658}
1659EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1660
8abd16a6
MB		 1661static irqreturn_t wm8903_irq(int irq, void *data)
1662{
f0fba2ad
LG		 1663 struct snd_soc_codec *codec = data;
1664 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1665 int mic_report;
1666 int int_pol;
1667 int int_val = 0;
1668 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1669
7245387e 1670 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1671
7245387e 1672 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1673 dev_dbg(codec->dev, "Write sequencer done\n");
1674 complete(&wm8903->wseq);
1675 }
1676
7245387e
MB		 1677 /*
1678 * The rest is microphone jack detection. We need to manually
1679 * invert the polarity of the interrupt after each event - to
1680 * simplify the code keep track of the last state we reported
1681 * and just invert the relevant bits in both the report and
1682 * the polarity register.
1683 */
1684 mic_report = wm8903->mic_last_report;
1685 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1686
1435b940 1687#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1688 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1689 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1690#endif
2bbb5d66 1691
7245387e
MB		 1692 if (int_val & WM8903_MICSHRT_EINT) {
1693 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1694
1695 mic_report ^= wm8903->mic_short;
1696 int_pol ^= WM8903_MICSHRT_INV;
1697 }
1698
1699 if (int_val & WM8903_MICDET_EINT) {
1700 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1701
1702 mic_report ^= wm8903->mic_det;
1703 int_pol ^= WM8903_MICDET_INV;
1704
1705 msleep(wm8903->mic_delay);
1706 }
1707
1708 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1709 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1710
1711 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1712 wm8903->mic_short | wm8903->mic_det);
1713
1714 wm8903->mic_last_report = mic_report;
1715
8abd16a6
MB		 1716 return IRQ_HANDLED;
1717}
1718
f1c0a02f
MB		 1719#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1720 SNDRV_PCM_RATE_11025 | \
1721 SNDRV_PCM_RATE_16000 | \
1722 SNDRV_PCM_RATE_22050 | \
1723 SNDRV_PCM_RATE_32000 | \
1724 SNDRV_PCM_RATE_44100 | \
1725 SNDRV_PCM_RATE_48000 | \
1726 SNDRV_PCM_RATE_88200 | \
1727 SNDRV_PCM_RATE_96000)
1728
1729#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1730 SNDRV_PCM_RATE_11025 | \
1731 SNDRV_PCM_RATE_16000 | \
1732 SNDRV_PCM_RATE_22050 | \
1733 SNDRV_PCM_RATE_32000 | \
1734 SNDRV_PCM_RATE_44100 | \
1735 SNDRV_PCM_RATE_48000)
1736
1737#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1738 SNDRV_PCM_FMTBIT_S20_3LE |\
1739 SNDRV_PCM_FMTBIT_S24_LE)
1740
6335d055 1741static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1742 .hw_params = wm8903_hw_params,
1743 .digital_mute = wm8903_digital_mute,
1744 .set_fmt = wm8903_set_dai_fmt,
1745 .set_sysclk = wm8903_set_dai_sysclk,
1746};
1747
f0fba2ad
LG		 1748static struct snd_soc_dai_driver wm8903_dai = {
1749 .name = "wm8903-hifi",
f1c0a02f
MB		 1750 .playback = {
1751 .stream_name = "Playback",
1752 .channels_min = 2,
1753 .channels_max = 2,
1754 .rates = WM8903_PLAYBACK_RATES,
1755 .formats = WM8903_FORMATS,
1756 },
1757 .capture = {
1758 .stream_name = "Capture",
1759 .channels_min = 2,
1760 .channels_max = 2,
1761 .rates = WM8903_CAPTURE_RATES,
1762 .formats = WM8903_FORMATS,
1763 },
6335d055 1764 .ops = &wm8903_dai_ops,
0d960e88 1765 .symmetric_rates = 1,
f1c0a02f 1766};
f1c0a02f 1767
f0fba2ad 1768static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1769{
f1c0a02f
MB		 1770 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1771
1772 return 0;
1773}
1774
f0fba2ad 1775static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1776{
f1c0a02f
MB		 1777 int i;
1778 u16 *reg_cache = codec->reg_cache;
40aa7030 1779 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1780 GFP_KERNEL);
1781
1782 /* Bring the codec back up to standby first to minimise pop/clicks */
1783 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1784
1785 /* Sync back everything else */
1786 if (tmp_cache) {
1787 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1788 if (tmp_cache[i] != reg_cache[i])
8d50e447 1789 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1790 kfree(tmp_cache);
f1c0a02f 1791 } else {
f0fba2ad 1792 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1793 }
1794
1795 return 0;
1796}
1797
7cfe5617
SW		 1798#ifdef CONFIG_GPIOLIB
1799static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1800{
1801 return container_of(chip, struct wm8903_priv, gpio_chip);
1802}
1803
1804static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1805{
1806 if (offset >= WM8903_NUM_GPIO)
1807 return -EINVAL;
1808
1809 return 0;
1810}
1811
1812static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1813{
1814 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1815 struct snd_soc_codec *codec = wm8903->codec;
1816 unsigned int mask, val;
1817
1818 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1819 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1820 WM8903_GP1_DIR;
1821
1822 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1823 mask, val);
1824}
1825
1826static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1827{
1828 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1829 struct snd_soc_codec *codec = wm8903->codec;
1830 int reg;
1831
1832 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1833
1834 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1835}
1836
1837static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1838 unsigned offset, int value)
1839{
1840 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1841 struct snd_soc_codec *codec = wm8903->codec;
1842 unsigned int mask, val;
1843
1844 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1845 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1846 (value << WM8903_GP2_LVL_SHIFT);
1847
1848 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1849 mask, val);
1850}
1851
1852static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1853{
1854 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1855 struct snd_soc_codec *codec = wm8903->codec;
1856
1857 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1858 WM8903_GP1_LVL_MASK,
1859 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1860}
1861
1862static struct gpio_chip wm8903_template_chip = {
1863 .label = "wm8903",
1864 .owner = THIS_MODULE,
1865 .request = wm8903_gpio_request,
1866 .direction_input = wm8903_gpio_direction_in,
1867 .get = wm8903_gpio_get,
1868 .direction_output = wm8903_gpio_direction_out,
1869 .set = wm8903_gpio_set,
1870 .can_sleep = 1,
1871};
1872
1873static void wm8903_init_gpio(struct snd_soc_codec *codec)
1874{
1875 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1876 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1877 int ret;
1878
1879 wm8903->gpio_chip = wm8903_template_chip;
1880 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1881 wm8903->gpio_chip.dev = codec->dev;
1882
1883 if (pdata && pdata->gpio_base)
1884 wm8903->gpio_chip.base = pdata->gpio_base;
1885 else
1886 wm8903->gpio_chip.base = -1;
1887
1888 ret = gpiochip_add(&wm8903->gpio_chip);
1889 if (ret != 0)
1890 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1891}
1892
1893static void wm8903_free_gpio(struct snd_soc_codec *codec)
1894{
1895 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1896 int ret;
1897
1898 ret = gpiochip_remove(&wm8903->gpio_chip);
1899 if (ret != 0)
1900 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1901}
1902#else
1903static void wm8903_init_gpio(struct snd_soc_codec *codec)
1904{
1905}
1906
1907static void wm8903_free_gpio(struct snd_soc_codec *codec)
1908{
1909}
1910#endif
1911
f0fba2ad 1912static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1913{
f0fba2ad
LG		 1914 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1915 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1916 int ret, i;
8abd16a6 1917 int trigger, irq_pol;
f1c0a02f
MB		 1918 u16 val;
1919
7cfe5617 1920 wm8903->codec = codec;
8abd16a6 1921 init_completion(&wm8903->wseq);
d58d5d55 1922
8d50e447
MB		 1923 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1924 if (ret != 0) {
f0fba2ad
LG		 1925 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1926 return ret;
8d50e447
MB		 1927 }
1928
1929 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1930 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1931 dev_err(codec->dev,
d58d5d55
MB		 1932 "Device with ID register %x is not a WM8903\n", val);
1933 return -ENODEV;
f1c0a02f
MB		 1934 }
1935
8d50e447 1936 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1937 dev_info(codec->dev, "WM8903 revision %c\n",
1938 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1939
1940 wm8903_reset(codec);
1941
37f88e84 1942 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1943 if (pdata) {
1944 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
7cfe5617 1945 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
73b34ead
MB		 1946 continue;
1947
1948 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1949 pdata->gpio_cfg[i] & 0xffff);
1950 }
37f88e84
MB		 1951
1952 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1953 pdata->micdet_cfg);
1954
1955 /* Microphone detection needs the WSEQ clock */
1956 if (pdata->micdet_cfg)
1957 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1958 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1959
1960 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1961 }
8abd16a6 1962
f0fba2ad 1963 if (wm8903->irq) {
8abd16a6
MB		 1964 if (pdata && pdata->irq_active_low) {
1965 trigger = IRQF_TRIGGER_LOW;
1966 irq_pol = WM8903_IRQ_POL;
1967 } else {
1968 trigger = IRQF_TRIGGER_HIGH;
1969 irq_pol = 0;
1970 }
1971
1972 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1973 WM8903_IRQ_POL, irq_pol);
1974
f0fba2ad 1975 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1976 trigger | IRQF_ONESHOT,
f0fba2ad 1977 "wm8903", codec);
8abd16a6 1978 if (ret != 0) {
f0fba2ad 1979 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1980 ret);
f0fba2ad 1981 return ret;
8abd16a6
MB		 1982 }
1983
1984 /* Enable write sequencer interrupts */
1985 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1986 WM8903_IM_WSEQ_BUSY_EINT, 0);
1987 }
73b34ead 1988
f1c0a02f
MB		 1989 /* power on device */
1990 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1991
1992 /* Latch volume update bits */
8d50e447 1993 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1994 val |= WM8903_ADCVU;
8d50e447
MB		 1995 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1996 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1997
8d50e447 1998 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1999 val |= WM8903_DACVU;
8d50e447
MB		 2000 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
2001 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 2002
8d50e447 2003 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 2004 val |= WM8903_HPOUTVU;
8d50e447
MB		 2005 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
2006 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 2007
8d50e447 2008 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 2009 val |= WM8903_LINEOUTVU;
8d50e447
MB		 2010 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
2011 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 2012
8d50e447 2013 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 2014 val |= WM8903_SPKVU;
8d50e447
MB		 2015 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
2016 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 2017
2018 /* Enable DAC soft mute by default */
e12adab0
MB		 2019 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
2020 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2021 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 2022
f0fba2ad
LG		 2023 snd_soc_add_controls(codec, wm8903_snd_controls,
2024 ARRAY_SIZE(wm8903_snd_controls));
2025 wm8903_add_widgets(codec);
f1c0a02f 2026
7cfe5617
SW		 2027 wm8903_init_gpio(codec);
2028
f1c0a02f
MB		 2029 return ret;
2030}
2031
f0fba2ad
LG		 2032/* power down chip */
2033static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2034{
7cfe5617 2035 wm8903_free_gpio(codec);
f0fba2ad
LG		 2036 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
2037 return 0;
2038}
f1c0a02f 2039
f0fba2ad
LG		 2040static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2041 .probe = wm8903_probe,
2042 .remove = wm8903_remove,
2043 .suspend = wm8903_suspend,
2044 .resume = wm8903_resume,
2045 .set_bias_level = wm8903_set_bias_level,
2046 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
2047 .reg_word_size = sizeof(u16),
2048 .reg_cache_default = wm8903_reg_defaults,
2049 .volatile_register = wm8903_volatile_register,
c5b6a9fe 2050 .seq_notifier = wm8903_seq_notifier,
f0fba2ad 2051};
f1c0a02f 2052
f0fba2ad
LG		 2053#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2054static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2055 const struct i2c_device_id *id)
2056{
2057 struct wm8903_priv *wm8903;
2058 int ret;
f1c0a02f 2059
f0fba2ad
LG		 2060 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
2061 if (wm8903 == NULL)
2062 return -ENOMEM;
8abd16a6 2063
f0fba2ad 2064 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2065 wm8903->irq = i2c->irq;
d58d5d55 2066
f0fba2ad
LG		 2067 ret = snd_soc_register_codec(&i2c->dev,
2068 &soc_codec_dev_wm8903, &wm8903_dai, 1);
2069 if (ret < 0)
2070 kfree(wm8903);
2071 return ret;
2072}
f1c0a02f 2073
f0fba2ad
LG		 2074static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2075{
2076 snd_soc_unregister_codec(&client->dev);
2077 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 2078 return 0;
2079}
2080
f1c0a02f 2081static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2082 { "wm8903", 0 },
2083 { }
f1c0a02f
MB		 2084};
2085MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2086
2087static struct i2c_driver wm8903_i2c_driver = {
2088 .driver = {
4b592c91 2089 .name = "wm8903",
f1c0a02f
MB		 2090 .owner = THIS_MODULE,
2091 },
f0fba2ad
LG		 2092 .probe = wm8903_i2c_probe,
2093 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2094 .id_table = wm8903_i2c_id,
2095};
f0fba2ad 2096#endif
f1c0a02f 2097
f0fba2ad 2098static int __init wm8903_modinit(void)
f1c0a02f 2099{
f1c0a02f 2100 int ret = 0;
f0fba2ad
LG		 2101#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2102 ret = i2c_add_driver(&wm8903_i2c_driver);
2103 if (ret != 0) {
2104 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2105 ret);
f1c0a02f 2106 }
f0fba2ad 2107#endif
f1c0a02f 2108 return ret;
64089b84
MB		 2109}
2110module_init(wm8903_modinit);
2111
2112static void __exit wm8903_exit(void)
2113{
f0fba2ad 2114#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 2115 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 2116#endif
64089b84
MB		 2117}
2118module_exit(wm8903_exit);
2119
f1c0a02f
MB		 2120MODULE_DESCRIPTION("ASoC WM8903 driver");
2121MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2122MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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