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ASoC: Use DAPM supply widget for WM8903 charge pump
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
14 * - Mic detect.
15 * - Digital microphone support.
16 * - Interrupt support (mic detect and sequencer).
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/pm.h>
24#include <linux/i2c.h>
25#include <linux/platform_device.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/tlv.h>
30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/initval.h>
33
34#include "wm8903.h"
35
f1c0a02f
MB		 36/* Register defaults at reset */
37static u16 wm8903_reg_defaults[] = {
38 0x8903, /* R0 - SW Reset and ID */
39 0x0000, /* R1 - Revision Number */
40 0x0000, /* R2 */
41 0x0000, /* R3 */
42 0x0018, /* R4 - Bias Control 0 */
43 0x0000, /* R5 - VMID Control 0 */
44 0x0000, /* R6 - Mic Bias Control 0 */
45 0x0000, /* R7 */
46 0x0001, /* R8 - Analogue DAC 0 */
47 0x0000, /* R9 */
48 0x0001, /* R10 - Analogue ADC 0 */
49 0x0000, /* R11 */
50 0x0000, /* R12 - Power Management 0 */
51 0x0000, /* R13 - Power Management 1 */
52 0x0000, /* R14 - Power Management 2 */
53 0x0000, /* R15 - Power Management 3 */
54 0x0000, /* R16 - Power Management 4 */
55 0x0000, /* R17 - Power Management 5 */
56 0x0000, /* R18 - Power Management 6 */
57 0x0000, /* R19 */
58 0x0400, /* R20 - Clock Rates 0 */
59 0x0D07, /* R21 - Clock Rates 1 */
60 0x0000, /* R22 - Clock Rates 2 */
61 0x0000, /* R23 */
62 0x0050, /* R24 - Audio Interface 0 */
63 0x0242, /* R25 - Audio Interface 1 */
64 0x0008, /* R26 - Audio Interface 2 */
65 0x0022, /* R27 - Audio Interface 3 */
66 0x0000, /* R28 */
67 0x0000, /* R29 */
68 0x00C0, /* R30 - DAC Digital Volume Left */
69 0x00C0, /* R31 - DAC Digital Volume Right */
70 0x0000, /* R32 - DAC Digital 0 */
71 0x0000, /* R33 - DAC Digital 1 */
72 0x0000, /* R34 */
73 0x0000, /* R35 */
74 0x00C0, /* R36 - ADC Digital Volume Left */
75 0x00C0, /* R37 - ADC Digital Volume Right */
76 0x0000, /* R38 - ADC Digital 0 */
77 0x0073, /* R39 - Digital Microphone 0 */
78 0x09BF, /* R40 - DRC 0 */
79 0x3241, /* R41 - DRC 1 */
80 0x0020, /* R42 - DRC 2 */
81 0x0000, /* R43 - DRC 3 */
82 0x0085, /* R44 - Analogue Left Input 0 */
83 0x0085, /* R45 - Analogue Right Input 0 */
84 0x0044, /* R46 - Analogue Left Input 1 */
85 0x0044, /* R47 - Analogue Right Input 1 */
86 0x0000, /* R48 */
87 0x0000, /* R49 */
88 0x0008, /* R50 - Analogue Left Mix 0 */
89 0x0004, /* R51 - Analogue Right Mix 0 */
90 0x0000, /* R52 - Analogue Spk Mix Left 0 */
91 0x0000, /* R53 - Analogue Spk Mix Left 1 */
92 0x0000, /* R54 - Analogue Spk Mix Right 0 */
93 0x0000, /* R55 - Analogue Spk Mix Right 1 */
94 0x0000, /* R56 */
95 0x002D, /* R57 - Analogue OUT1 Left */
96 0x002D, /* R58 - Analogue OUT1 Right */
97 0x0039, /* R59 - Analogue OUT2 Left */
98 0x0039, /* R60 - Analogue OUT2 Right */
99 0x0100, /* R61 */
100 0x0139, /* R62 - Analogue OUT3 Left */
101 0x0139, /* R63 - Analogue OUT3 Right */
102 0x0000, /* R64 */
103 0x0000, /* R65 - Analogue SPK Output Control 0 */
104 0x0000, /* R66 */
105 0x0010, /* R67 - DC Servo 0 */
106 0x0100, /* R68 */
107 0x00A4, /* R69 - DC Servo 2 */
108 0x0807, /* R70 */
109 0x0000, /* R71 */
110 0x0000, /* R72 */
111 0x0000, /* R73 */
112 0x0000, /* R74 */
113 0x0000, /* R75 */
114 0x0000, /* R76 */
115 0x0000, /* R77 */
116 0x0000, /* R78 */
117 0x000E, /* R79 */
118 0x0000, /* R80 */
119 0x0000, /* R81 */
120 0x0000, /* R82 */
121 0x0000, /* R83 */
122 0x0000, /* R84 */
123 0x0000, /* R85 */
124 0x0000, /* R86 */
125 0x0006, /* R87 */
126 0x0000, /* R88 */
127 0x0000, /* R89 */
128 0x0000, /* R90 - Analogue HP 0 */
129 0x0060, /* R91 */
130 0x0000, /* R92 */
131 0x0000, /* R93 */
132 0x0000, /* R94 - Analogue Lineout 0 */
133 0x0060, /* R95 */
134 0x0000, /* R96 */
135 0x0000, /* R97 */
136 0x0000, /* R98 - Charge Pump 0 */
137 0x1F25, /* R99 */
138 0x2B19, /* R100 */
139 0x01C0, /* R101 */
140 0x01EF, /* R102 */
141 0x2B00, /* R103 */
142 0x0000, /* R104 - Class W 0 */
143 0x01C0, /* R105 */
144 0x1C10, /* R106 */
145 0x0000, /* R107 */
146 0x0000, /* R108 - Write Sequencer 0 */
147 0x0000, /* R109 - Write Sequencer 1 */
148 0x0000, /* R110 - Write Sequencer 2 */
149 0x0000, /* R111 - Write Sequencer 3 */
150 0x0000, /* R112 - Write Sequencer 4 */
151 0x0000, /* R113 */
152 0x0000, /* R114 - Control Interface */
153 0x0000, /* R115 */
154 0x00A8, /* R116 - GPIO Control 1 */
155 0x00A8, /* R117 - GPIO Control 2 */
156 0x00A8, /* R118 - GPIO Control 3 */
157 0x0220, /* R119 - GPIO Control 4 */
158 0x01A0, /* R120 - GPIO Control 5 */
159 0x0000, /* R121 - Interrupt Status 1 */
160 0xFFFF, /* R122 - Interrupt Status 1 Mask */
161 0x0000, /* R123 - Interrupt Polarity 1 */
162 0x0000, /* R124 */
163 0x0003, /* R125 */
164 0x0000, /* R126 - Interrupt Control */
165 0x0000, /* R127 */
166 0x0005, /* R128 */
167 0x0000, /* R129 - Control Interface Test 1 */
168 0x0000, /* R130 */
169 0x0000, /* R131 */
170 0x0000, /* R132 */
171 0x0000, /* R133 */
172 0x0000, /* R134 */
173 0x03FF, /* R135 */
174 0x0007, /* R136 */
175 0x0040, /* R137 */
176 0x0000, /* R138 */
177 0x0000, /* R139 */
178 0x0000, /* R140 */
179 0x0000, /* R141 */
180 0x0000, /* R142 */
181 0x0000, /* R143 */
182 0x0000, /* R144 */
183 0x0000, /* R145 */
184 0x0000, /* R146 */
185 0x0000, /* R147 */
186 0x4000, /* R148 */
187 0x6810, /* R149 - Charge Pump Test 1 */
188 0x0004, /* R150 */
189 0x0000, /* R151 */
190 0x0000, /* R152 */
191 0x0000, /* R153 */
192 0x0000, /* R154 */
193 0x0000, /* R155 */
194 0x0000, /* R156 */
195 0x0000, /* R157 */
196 0x0000, /* R158 */
197 0x0000, /* R159 */
198 0x0000, /* R160 */
199 0x0000, /* R161 */
200 0x0000, /* R162 */
201 0x0000, /* R163 */
202 0x0028, /* R164 - Clock Rate Test 4 */
203 0x0004, /* R165 */
204 0x0000, /* R166 */
205 0x0060, /* R167 */
206 0x0000, /* R168 */
207 0x0000, /* R169 */
208 0x0000, /* R170 */
209 0x0000, /* R171 */
210 0x0000, /* R172 - Analogue Output Bias 0 */
211};
212
d58d5d55
MB		 213struct wm8903_priv {
214 struct snd_soc_codec codec;
215 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
216
217 int sysclk;
218
219 /* Reference counts */
d58d5d55
MB		 220 int class_w_users;
221 int playback_active;
222 int capture_active;
223
224 struct snd_pcm_substream *master_substream;
225 struct snd_pcm_substream *slave_substream;
226};
227
228
f1c0a02f
MB		 229static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
230 unsigned int reg)
231{
232 u16 *cache = codec->reg_cache;
233
234 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
235
236 return cache[reg];
237}
238
239static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
240{
241 struct i2c_msg xfer[2];
242 u16 data;
243 int ret;
244 struct i2c_client *client = codec->control_data;
245
246 /* Write register */
247 xfer[0].addr = client->addr;
248 xfer[0].flags = 0;
249 xfer[0].len = 1;
250 xfer[0].buf = &reg;
251
252 /* Read data */
253 xfer[1].addr = client->addr;
254 xfer[1].flags = I2C_M_RD;
255 xfer[1].len = 2;
256 xfer[1].buf = (u8 *)&data;
257
258 ret = i2c_transfer(client->adapter, xfer, 2);
259 if (ret != 2) {
260 pr_err("i2c_transfer returned %d\n", ret);
261 return 0;
262 }
263
264 return (data >> 8) | ((data & 0xff) << 8);
265}
266
267static unsigned int wm8903_read(struct snd_soc_codec *codec,
268 unsigned int reg)
269{
270 switch (reg) {
271 case WM8903_SW_RESET_AND_ID:
272 case WM8903_REVISION_NUMBER:
273 case WM8903_INTERRUPT_STATUS_1:
274 case WM8903_WRITE_SEQUENCER_4:
275 return wm8903_hw_read(codec, reg);
276
277 default:
278 return wm8903_read_reg_cache(codec, reg);
279 }
280}
281
282static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
283 u16 reg, unsigned int value)
284{
285 u16 *cache = codec->reg_cache;
286
287 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
288
289 switch (reg) {
290 case WM8903_SW_RESET_AND_ID:
291 case WM8903_REVISION_NUMBER:
292 break;
293
294 default:
295 cache[reg] = value;
296 break;
297 }
298}
299
300static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
301 unsigned int value)
302{
303 u8 data[3];
304
305 wm8903_write_reg_cache(codec, reg, value);
306
307 /* Data format is 1 byte of address followed by 2 bytes of data */
308 data[0] = reg;
309 data[1] = (value >> 8) & 0xff;
310 data[2] = value & 0xff;
311
312 if (codec->hw_write(codec->control_data, data, 3) == 2)
313 return 0;
314 else
315 return -EIO;
316}
317
318static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
319{
320 u16 reg[5];
321 struct i2c_client *i2c = codec->control_data;
322
323 BUG_ON(start > 48);
324
325 /* Enable the sequencer */
326 reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0);
327 reg[0] |= WM8903_WSEQ_ENA;
328 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
329
330 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
331
332 wm8903_write(codec, WM8903_WRITE_SEQUENCER_3,
333 start | WM8903_WSEQ_START);
334
335 /* Wait for it to complete. If we have the interrupt wired up then
336 * we could block waiting for an interrupt, though polling may still
337 * be desirable for diagnostic purposes.
338 */
339 do {
340 msleep(10);
341
342 reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4);
343 } while (reg[4] & WM8903_WSEQ_BUSY);
344
345 dev_dbg(&i2c->dev, "Sequence complete\n");
346
347 /* Disable the sequencer again */
348 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0,
349 reg[0] & ~WM8903_WSEQ_ENA);
350
351 return 0;
352}
353
354static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
355{
356 int i;
357
358 /* There really ought to be something better we can do here :/ */
359 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
360 cache[i] = wm8903_hw_read(codec, i);
361}
362
363static void wm8903_reset(struct snd_soc_codec *codec)
364{
365 wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 366 memcpy(codec->reg_cache, wm8903_reg_defaults,
367 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 368}
369
370#define WM8903_OUTPUT_SHORT 0x8
371#define WM8903_OUTPUT_OUT 0x4
372#define WM8903_OUTPUT_INT 0x2
373#define WM8903_OUTPUT_IN 0x1
374
42768a12
MB		 375static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
376 struct snd_kcontrol *kcontrol, int event)
377{
378 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
379 mdelay(4);
380
381 return 0;
382}
383
f1c0a02f
MB		 384/*
385 * Event for headphone and line out amplifier power changes. Special
386 * power up/down sequences are required in order to maximise pop/click
387 * performance.
388 */
389static int wm8903_output_event(struct snd_soc_dapm_widget *w,
390 struct snd_kcontrol *kcontrol, int event)
391{
392 struct snd_soc_codec *codec = w->codec;
f1c0a02f 393 u16 val;
0bc286e2
TI		 394 u16 reg;
395 int shift;
f1c0a02f
MB		 396
397 switch (w->reg) {
398 case WM8903_POWER_MANAGEMENT_2:
399 reg = WM8903_ANALOGUE_HP_0;
400 break;
401 case WM8903_POWER_MANAGEMENT_3:
402 reg = WM8903_ANALOGUE_LINEOUT_0;
403 break;
404 default:
405 BUG();
1e297a19 406 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 407 }
408
409 switch (w->shift) {
410 case 0:
411 shift = 0;
412 break;
413 case 1:
414 shift = 4;
415 break;
416 default:
417 BUG();
1e297a19 418 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 419 }
420
421 if (event & SND_SOC_DAPM_PRE_PMU) {
422 val = wm8903_read(codec, reg);
423
424 /* Short the output */
425 val &= ~(WM8903_OUTPUT_SHORT << shift);
426 wm8903_write(codec, reg, val);
f1c0a02f
MB		 427 }
428
429 if (event & SND_SOC_DAPM_POST_PMU) {
430 val = wm8903_read(codec, reg);
431
432 val |= (WM8903_OUTPUT_IN << shift);
433 wm8903_write(codec, reg, val);
434
435 val |= (WM8903_OUTPUT_INT << shift);
436 wm8903_write(codec, reg, val);
437
438 /* Turn on the output ENA_OUTP */
439 val |= (WM8903_OUTPUT_OUT << shift);
440 wm8903_write(codec, reg, val);
441
442 /* Remove the short */
443 val |= (WM8903_OUTPUT_SHORT << shift);
444 wm8903_write(codec, reg, val);
445 }
446
447 if (event & SND_SOC_DAPM_PRE_PMD) {
448 val = wm8903_read(codec, reg);
449
450 /* Short the output */
451 val &= ~(WM8903_OUTPUT_SHORT << shift);
452 wm8903_write(codec, reg, val);
453
454 /* Then disable the intermediate and output stages */
455 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
456 WM8903_OUTPUT_IN) << shift);
457 wm8903_write(codec, reg, val);
458 }
459
f1c0a02f
MB		 460 return 0;
461}
462
463/*
464 * When used with DAC outputs only the WM8903 charge pump supports
465 * operation in class W mode, providing very low power consumption
466 * when used with digital sources. Enable and disable this mode
467 * automatically depending on the mixer configuration.
468 *
469 * All the relevant controls are simple switches.
470 */
471static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
472 struct snd_ctl_elem_value *ucontrol)
473{
474 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
475 struct snd_soc_codec *codec = widget->codec;
476 struct wm8903_priv *wm8903 = codec->private_data;
477 struct i2c_client *i2c = codec->control_data;
478 u16 reg;
479 int ret;
480
481 reg = wm8903_read(codec, WM8903_CLASS_W_0);
482
483 /* Turn it off if we're about to enable bypass */
484 if (ucontrol->value.integer.value[0]) {
485 if (wm8903->class_w_users == 0) {
486 dev_dbg(&i2c->dev, "Disabling Class W\n");
487 wm8903_write(codec, WM8903_CLASS_W_0, reg &
488 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
489 }
490 wm8903->class_w_users++;
491 }
492
493 /* Implement the change */
494 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
495
496 /* If we've just disabled the last bypass path turn Class W on */
497 if (!ucontrol->value.integer.value[0]) {
498 if (wm8903->class_w_users == 1) {
499 dev_dbg(&i2c->dev, "Enabling Class W\n");
500 wm8903_write(codec, WM8903_CLASS_W_0, reg |
501 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
502 }
503 wm8903->class_w_users--;
504 }
505
506 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
507 wm8903->class_w_users);
508
509 return ret;
510}
511
512#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
513{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
514 .info = snd_soc_info_volsw, \
515 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
516 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
517
518
519/* ALSA can only do steps of .01dB */
520static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
521
522static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
523
524static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
525static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
526static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
527static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
528static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
529
530static const char *drc_slope_text[] = {
531 "1", "1/2", "1/4", "1/8", "1/16", "0"
532};
533
534static const struct soc_enum drc_slope_r0 =
535 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
536
537static const struct soc_enum drc_slope_r1 =
538 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
539
540static const char *drc_attack_text[] = {
541 "instantaneous",
542 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
543 "46.4ms", "92.8ms", "185.6ms"
544};
545
546static const struct soc_enum drc_attack =
547 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
548
549static const char *drc_decay_text[] = {
550 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
551 "23.87s", "47.56s"
552};
553
554static const struct soc_enum drc_decay =
555 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
556
557static const char *drc_ff_delay_text[] = {
558 "5 samples", "9 samples"
559};
560
561static const struct soc_enum drc_ff_delay =
562 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
563
564static const char *drc_qr_decay_text[] = {
565 "0.725ms", "1.45ms", "5.8ms"
566};
567
568static const struct soc_enum drc_qr_decay =
569 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
570
571static const char *drc_smoothing_text[] = {
572 "Low", "Medium", "High"
573};
574
575static const struct soc_enum drc_smoothing =
576 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
577
578static const char *soft_mute_text[] = {
579 "Fast (fs/2)", "Slow (fs/32)"
580};
581
582static const struct soc_enum soft_mute =
583 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
584
585static const char *mute_mode_text[] = {
586 "Hard", "Soft"
587};
588
589static const struct soc_enum mute_mode =
590 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
591
592static const char *dac_deemphasis_text[] = {
593 "Disabled", "32kHz", "44.1kHz", "48kHz"
594};
595
596static const struct soc_enum dac_deemphasis =
597 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
598
599static const char *companding_text[] = {
600 "ulaw", "alaw"
601};
602
603static const struct soc_enum dac_companding =
604 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
605
606static const struct soc_enum adc_companding =
607 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
608
609static const char *input_mode_text[] = {
610 "Single-Ended", "Differential Line", "Differential Mic"
611};
612
613static const struct soc_enum linput_mode_enum =
614 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
615
616static const struct soc_enum rinput_mode_enum =
617 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
618
619static const char *linput_mux_text[] = {
620 "IN1L", "IN2L", "IN3L"
621};
622
623static const struct soc_enum linput_enum =
624 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
625
626static const struct soc_enum linput_inv_enum =
627 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
628
629static const char *rinput_mux_text[] = {
630 "IN1R", "IN2R", "IN3R"
631};
632
633static const struct soc_enum rinput_enum =
634 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
635
636static const struct soc_enum rinput_inv_enum =
637 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
638
639
640static const struct snd_kcontrol_new wm8903_snd_controls[] = {
641
642/* Input PGAs - No TLV since the scale depends on PGA mode */
643SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 644 7, 1, 1),
f1c0a02f
MB		 645SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
646 0, 31, 0),
647SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
648 6, 1, 0),
649
650SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 651 7, 1, 1),
f1c0a02f
MB		 652SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
653 0, 31, 0),
654SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
655 6, 1, 0),
656
657/* ADCs */
658SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
659SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
660SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
661SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1,
662 drc_tlv_thresh),
663SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
664SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
665SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
666SOC_ENUM("DRC Attack Rate", drc_attack),
667SOC_ENUM("DRC Decay Rate", drc_decay),
668SOC_ENUM("DRC FF Delay", drc_ff_delay),
669SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
670SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
671SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
672SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
673SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
674SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
675SOC_ENUM("DRC Smoothing Threashold", drc_smoothing),
676SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
677
678SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
679 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
680SOC_ENUM("ADC Companding Mode", adc_companding),
681SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
682
683/* DAC */
684SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
685 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
686SOC_ENUM("DAC Soft Mute Rate", soft_mute),
687SOC_ENUM("DAC Mute Mode", mute_mode),
688SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
689SOC_ENUM("DAC De-emphasis", dac_deemphasis),
690SOC_SINGLE("DAC Sloping Stopband Filter Switch",
691 WM8903_DAC_DIGITAL_1, 11, 1, 0),
692SOC_ENUM("DAC Companding Mode", dac_companding),
693SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
694
695/* Headphones */
696SOC_DOUBLE_R("Headphone Switch",
697 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
698 8, 1, 1),
699SOC_DOUBLE_R("Headphone ZC Switch",
700 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
701 6, 1, 0),
702SOC_DOUBLE_R_TLV("Headphone Volume",
703 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
704 0, 63, 0, out_tlv),
705
706/* Line out */
707SOC_DOUBLE_R("Line Out Switch",
708 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
709 8, 1, 1),
710SOC_DOUBLE_R("Line Out ZC Switch",
711 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
712 6, 1, 0),
713SOC_DOUBLE_R_TLV("Line Out Volume",
714 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
715 0, 63, 0, out_tlv),
716
717/* Speaker */
718SOC_DOUBLE_R("Speaker Switch",
719 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
720SOC_DOUBLE_R("Speaker ZC Switch",
721 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
722SOC_DOUBLE_R_TLV("Speaker Volume",
723 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
724 0, 63, 0, out_tlv),
725};
726
f1c0a02f
MB		 727static const struct snd_kcontrol_new linput_mode_mux =
728 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
729
730static const struct snd_kcontrol_new rinput_mode_mux =
731 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
732
733static const struct snd_kcontrol_new linput_mux =
734 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
735
736static const struct snd_kcontrol_new linput_inv_mux =
737 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
738
739static const struct snd_kcontrol_new rinput_mux =
740 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
741
742static const struct snd_kcontrol_new rinput_inv_mux =
743 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
744
745static const struct snd_kcontrol_new left_output_mixer[] = {
746SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
747SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
748SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 749SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 750};
751
752static const struct snd_kcontrol_new right_output_mixer[] = {
753SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
754SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
755SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 756SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 757};
758
759static const struct snd_kcontrol_new left_speaker_mixer[] = {
760SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
761SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
762SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
763SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 764 0, 1, 0),
f1c0a02f
MB		 765};
766
767static const struct snd_kcontrol_new right_speaker_mixer[] = {
768SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
769SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
770SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
771 1, 1, 0),
772SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 773 0, 1, 0),
f1c0a02f
MB		 774};
775
776static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
777SND_SOC_DAPM_INPUT("IN1L"),
778SND_SOC_DAPM_INPUT("IN1R"),
779SND_SOC_DAPM_INPUT("IN2L"),
780SND_SOC_DAPM_INPUT("IN2R"),
781SND_SOC_DAPM_INPUT("IN3L"),
782SND_SOC_DAPM_INPUT("IN3R"),
783
784SND_SOC_DAPM_OUTPUT("HPOUTL"),
785SND_SOC_DAPM_OUTPUT("HPOUTR"),
786SND_SOC_DAPM_OUTPUT("LINEOUTL"),
787SND_SOC_DAPM_OUTPUT("LINEOUTR"),
788SND_SOC_DAPM_OUTPUT("LOP"),
789SND_SOC_DAPM_OUTPUT("LON"),
790SND_SOC_DAPM_OUTPUT("ROP"),
791SND_SOC_DAPM_OUTPUT("RON"),
792
793SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
794
795SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
796SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
797 &linput_inv_mux),
798SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
799
800SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
801SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
802 &rinput_inv_mux),
803SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
804
805SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
806SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
807
808SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
809SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
810
811SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
812SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
813
814SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
815 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
816SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
817 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
818
819SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
820 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
821SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
822 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
823
824SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
825 1, 0, NULL, 0, wm8903_output_event,
826 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 827 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 828SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
829 0, 0, NULL, 0, wm8903_output_event,
830 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 831 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 832
833SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
834 NULL, 0, wm8903_output_event,
835 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 836 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 837SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
838 NULL, 0, wm8903_output_event,
839 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 840 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 841
842SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
843 NULL, 0),
844SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
845 NULL, 0),
846
42768a12
MB		 847SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
848 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
f1c0a02f
MB		 849};
850
851static const struct snd_soc_dapm_route intercon[] = {
852
853 { "Left Input Mux", "IN1L", "IN1L" },
854 { "Left Input Mux", "IN2L", "IN2L" },
855 { "Left Input Mux", "IN3L", "IN3L" },
856
857 { "Left Input Inverting Mux", "IN1L", "IN1L" },
858 { "Left Input Inverting Mux", "IN2L", "IN2L" },
859 { "Left Input Inverting Mux", "IN3L", "IN3L" },
860
861 { "Right Input Mux", "IN1R", "IN1R" },
862 { "Right Input Mux", "IN2R", "IN2R" },
863 { "Right Input Mux", "IN3R", "IN3R" },
864
865 { "Right Input Inverting Mux", "IN1R", "IN1R" },
866 { "Right Input Inverting Mux", "IN2R", "IN2R" },
867 { "Right Input Inverting Mux", "IN3R", "IN3R" },
868
869 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
870 { "Left Input Mode Mux", "Differential Line",
871 "Left Input Mux" },
872 { "Left Input Mode Mux", "Differential Line",
873 "Left Input Inverting Mux" },
874 { "Left Input Mode Mux", "Differential Mic",
875 "Left Input Mux" },
876 { "Left Input Mode Mux", "Differential Mic",
877 "Left Input Inverting Mux" },
878
879 { "Right Input Mode Mux", "Single-Ended",
880 "Right Input Inverting Mux" },
881 { "Right Input Mode Mux", "Differential Line",
882 "Right Input Mux" },
883 { "Right Input Mode Mux", "Differential Line",
884 "Right Input Inverting Mux" },
885 { "Right Input Mode Mux", "Differential Mic",
886 "Right Input Mux" },
887 { "Right Input Mode Mux", "Differential Mic",
888 "Right Input Inverting Mux" },
889
890 { "Left Input PGA", NULL, "Left Input Mode Mux" },
891 { "Right Input PGA", NULL, "Right Input Mode Mux" },
892
893 { "ADCL", NULL, "Left Input PGA" },
894 { "ADCR", NULL, "Right Input PGA" },
895
896 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
897 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
898 { "Left Output Mixer", "DACL Switch", "DACL" },
899 { "Left Output Mixer", "DACR Switch", "DACR" },
900
901 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
902 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
903 { "Right Output Mixer", "DACL Switch", "DACL" },
904 { "Right Output Mixer", "DACR Switch", "DACR" },
905
906 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
907 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
908 { "Left Speaker Mixer", "DACL Switch", "DACL" },
909 { "Left Speaker Mixer", "DACR Switch", "DACR" },
910
911 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
912 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
913 { "Right Speaker Mixer", "DACL Switch", "DACL" },
914 { "Right Speaker Mixer", "DACR Switch", "DACR" },
915
916 { "Left Line Output PGA", NULL, "Left Output Mixer" },
917 { "Right Line Output PGA", NULL, "Right Output Mixer" },
918
919 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
920 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
921
922 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
923 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
924
925 { "HPOUTL", NULL, "Left Headphone Output PGA" },
926 { "HPOUTR", NULL, "Right Headphone Output PGA" },
927
928 { "LINEOUTL", NULL, "Left Line Output PGA" },
929 { "LINEOUTR", NULL, "Right Line Output PGA" },
930
931 { "LOP", NULL, "Left Speaker PGA" },
932 { "LON", NULL, "Left Speaker PGA" },
933
934 { "ROP", NULL, "Right Speaker PGA" },
935 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 936
937 { "Left Headphone Output PGA", NULL, "Charge Pump" },
938 { "Right Headphone Output PGA", NULL, "Charge Pump" },
939 { "Left Line Output PGA", NULL, "Charge Pump" },
940 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 941};
942
943static int wm8903_add_widgets(struct snd_soc_codec *codec)
944{
945 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
946 ARRAY_SIZE(wm8903_dapm_widgets));
947
948 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
949
950 snd_soc_dapm_new_widgets(codec);
951
952 return 0;
953}
954
955static int wm8903_set_bias_level(struct snd_soc_codec *codec,
956 enum snd_soc_bias_level level)
957{
958 struct i2c_client *i2c = codec->control_data;
959 u16 reg, reg2;
960
961 switch (level) {
962 case SND_SOC_BIAS_ON:
963 case SND_SOC_BIAS_PREPARE:
964 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
965 reg &= ~(WM8903_VMID_RES_MASK);
966 reg |= WM8903_VMID_RES_50K;
967 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
968 break;
969
970 case SND_SOC_BIAS_STANDBY:
971 if (codec->bias_level == SND_SOC_BIAS_OFF) {
3b1228ab
MB		 972 wm8903_write(codec, WM8903_CLOCK_RATES_2,
973 WM8903_CLK_SYS_ENA);
974
f1c0a02f
MB		 975 wm8903_run_sequence(codec, 0);
976 wm8903_sync_reg_cache(codec, codec->reg_cache);
977
978 /* Enable low impedence charge pump output */
979 reg = wm8903_read(codec,
980 WM8903_CONTROL_INTERFACE_TEST_1);
981 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
982 reg | WM8903_TEST_KEY);
983 reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1);
984 wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1,
985 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
986 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
987 reg);
988
989 /* By default no bypass paths are enabled so
990 * enable Class W support.
991 */
992 dev_dbg(&i2c->dev, "Enabling Class W\n");
993 wm8903_write(codec, WM8903_CLASS_W_0, reg |
994 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
995 }
996
997 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
998 reg &= ~(WM8903_VMID_RES_MASK);
999 reg |= WM8903_VMID_RES_250K;
1000 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
1001 break;
1002
1003 case SND_SOC_BIAS_OFF:
1004 wm8903_run_sequence(codec, 32);
3b1228ab
MB		 1005 reg = wm8903_read(codec, WM8903_CLOCK_RATES_2);
1006 reg &= ~WM8903_CLK_SYS_ENA;
1007 wm8903_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1008 break;
1009 }
1010
1011 codec->bias_level = level;
1012
1013 return 0;
1014}
1015
1016static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1017 int clk_id, unsigned int freq, int dir)
1018{
1019 struct snd_soc_codec *codec = codec_dai->codec;
1020 struct wm8903_priv *wm8903 = codec->private_data;
1021
1022 wm8903->sysclk = freq;
1023
1024 return 0;
1025}
1026
1027static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1028 unsigned int fmt)
1029{
1030 struct snd_soc_codec *codec = codec_dai->codec;
1031 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1032
1033 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1034 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1035
1036 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1037 case SND_SOC_DAIFMT_CBS_CFS:
1038 break;
1039 case SND_SOC_DAIFMT_CBS_CFM:
1040 aif1 |= WM8903_LRCLK_DIR;
1041 break;
1042 case SND_SOC_DAIFMT_CBM_CFM:
1043 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1044 break;
1045 case SND_SOC_DAIFMT_CBM_CFS:
1046 aif1 |= WM8903_BCLK_DIR;
1047 break;
1048 default:
1049 return -EINVAL;
1050 }
1051
1052 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1053 case SND_SOC_DAIFMT_DSP_A:
1054 aif1 |= 0x3;
1055 break;
1056 case SND_SOC_DAIFMT_DSP_B:
1057 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1058 break;
1059 case SND_SOC_DAIFMT_I2S:
1060 aif1 |= 0x2;
1061 break;
1062 case SND_SOC_DAIFMT_RIGHT_J:
1063 aif1 |= 0x1;
1064 break;
1065 case SND_SOC_DAIFMT_LEFT_J:
1066 break;
1067 default:
1068 return -EINVAL;
1069 }
1070
1071 /* Clock inversion */
1072 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1073 case SND_SOC_DAIFMT_DSP_A:
1074 case SND_SOC_DAIFMT_DSP_B:
1075 /* frame inversion not valid for DSP modes */
1076 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1077 case SND_SOC_DAIFMT_NB_NF:
1078 break;
1079 case SND_SOC_DAIFMT_IB_NF:
1080 aif1 |= WM8903_AIF_BCLK_INV;
1081 break;
1082 default:
1083 return -EINVAL;
1084 }
1085 break;
1086 case SND_SOC_DAIFMT_I2S:
1087 case SND_SOC_DAIFMT_RIGHT_J:
1088 case SND_SOC_DAIFMT_LEFT_J:
1089 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1090 case SND_SOC_DAIFMT_NB_NF:
1091 break;
1092 case SND_SOC_DAIFMT_IB_IF:
1093 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1094 break;
1095 case SND_SOC_DAIFMT_IB_NF:
1096 aif1 |= WM8903_AIF_BCLK_INV;
1097 break;
1098 case SND_SOC_DAIFMT_NB_IF:
1099 aif1 |= WM8903_AIF_LRCLK_INV;
1100 break;
1101 default:
1102 return -EINVAL;
1103 }
1104 break;
1105 default:
1106 return -EINVAL;
1107 }
1108
1109 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1110
1111 return 0;
1112}
1113
1114static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1115{
1116 struct snd_soc_codec *codec = codec_dai->codec;
1117 u16 reg;
1118
1119 reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1120
1121 if (mute)
1122 reg |= WM8903_DAC_MUTE;
1123 else
1124 reg &= ~WM8903_DAC_MUTE;
1125
1126 wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg);
1127
1128 return 0;
1129}
1130
1131/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1132 * for optimal performance so we list the lower rates first and match
1133 * on the last match we find. */
1134static struct {
1135 int div;
1136 int rate;
1137 int mode;
1138 int mclk_div;
1139} clk_sys_ratios[] = {
1140 { 64, 0x0, 0x0, 1 },
1141 { 68, 0x0, 0x1, 1 },
1142 { 125, 0x0, 0x2, 1 },
1143 { 128, 0x1, 0x0, 1 },
1144 { 136, 0x1, 0x1, 1 },
1145 { 192, 0x2, 0x0, 1 },
1146 { 204, 0x2, 0x1, 1 },
1147
1148 { 64, 0x0, 0x0, 2 },
1149 { 68, 0x0, 0x1, 2 },
1150 { 125, 0x0, 0x2, 2 },
1151 { 128, 0x1, 0x0, 2 },
1152 { 136, 0x1, 0x1, 2 },
1153 { 192, 0x2, 0x0, 2 },
1154 { 204, 0x2, 0x1, 2 },
1155
1156 { 250, 0x2, 0x2, 1 },
1157 { 256, 0x3, 0x0, 1 },
1158 { 272, 0x3, 0x1, 1 },
1159 { 384, 0x4, 0x0, 1 },
1160 { 408, 0x4, 0x1, 1 },
1161 { 375, 0x4, 0x2, 1 },
1162 { 512, 0x5, 0x0, 1 },
1163 { 544, 0x5, 0x1, 1 },
1164 { 500, 0x5, 0x2, 1 },
1165 { 768, 0x6, 0x0, 1 },
1166 { 816, 0x6, 0x1, 1 },
1167 { 750, 0x6, 0x2, 1 },
1168 { 1024, 0x7, 0x0, 1 },
1169 { 1088, 0x7, 0x1, 1 },
1170 { 1000, 0x7, 0x2, 1 },
1171 { 1408, 0x8, 0x0, 1 },
1172 { 1496, 0x8, 0x1, 1 },
1173 { 1536, 0x9, 0x0, 1 },
1174 { 1632, 0x9, 0x1, 1 },
1175 { 1500, 0x9, 0x2, 1 },
1176
1177 { 250, 0x2, 0x2, 2 },
1178 { 256, 0x3, 0x0, 2 },
1179 { 272, 0x3, 0x1, 2 },
1180 { 384, 0x4, 0x0, 2 },
1181 { 408, 0x4, 0x1, 2 },
1182 { 375, 0x4, 0x2, 2 },
1183 { 512, 0x5, 0x0, 2 },
1184 { 544, 0x5, 0x1, 2 },
1185 { 500, 0x5, 0x2, 2 },
1186 { 768, 0x6, 0x0, 2 },
1187 { 816, 0x6, 0x1, 2 },
1188 { 750, 0x6, 0x2, 2 },
1189 { 1024, 0x7, 0x0, 2 },
1190 { 1088, 0x7, 0x1, 2 },
1191 { 1000, 0x7, 0x2, 2 },
1192 { 1408, 0x8, 0x0, 2 },
1193 { 1496, 0x8, 0x1, 2 },
1194 { 1536, 0x9, 0x0, 2 },
1195 { 1632, 0x9, 0x1, 2 },
1196 { 1500, 0x9, 0x2, 2 },
1197};
1198
1199/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1200static struct {
1201 int ratio;
1202 int div;
1203} bclk_divs[] = {
1204 { 10, 0 },
1205 { 15, 1 },
1206 { 20, 2 },
1207 { 30, 3 },
1208 { 40, 4 },
1209 { 50, 5 },
1210 { 55, 6 },
1211 { 60, 7 },
1212 { 80, 8 },
1213 { 100, 9 },
1214 { 110, 10 },
1215 { 120, 11 },
1216 { 160, 12 },
1217 { 200, 13 },
1218 { 220, 14 },
1219 { 240, 15 },
1220 { 250, 16 },
1221 { 300, 17 },
1222 { 320, 18 },
1223 { 440, 19 },
1224 { 480, 20 },
1225};
1226
1227/* Sample rates for DSP */
1228static struct {
1229 int rate;
1230 int value;
1231} sample_rates[] = {
1232 { 8000, 0 },
1233 { 11025, 1 },
1234 { 12000, 2 },
1235 { 16000, 3 },
1236 { 22050, 4 },
1237 { 24000, 5 },
1238 { 32000, 6 },
1239 { 44100, 7 },
1240 { 48000, 8 },
1241 { 88200, 9 },
1242 { 96000, 10 },
1243 { 0, 0 },
1244};
1245
dee89c4d
MB		 1246static int wm8903_startup(struct snd_pcm_substream *substream,
1247 struct snd_soc_dai *dai)
f1c0a02f
MB		 1248{
1249 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1250 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1251 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1252 struct wm8903_priv *wm8903 = codec->private_data;
1253 struct i2c_client *i2c = codec->control_data;
1254 struct snd_pcm_runtime *master_runtime;
1255
1256 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1257 wm8903->playback_active++;
1258 else
1259 wm8903->capture_active++;
1260
1261 /* The DAI has shared clocks so if we already have a playback or
1262 * capture going then constrain this substream to match it.
1263 */
1264 if (wm8903->master_substream) {
1265 master_runtime = wm8903->master_substream->runtime;
1266
1267 dev_dbg(&i2c->dev, "Constraining to %d bits at %dHz\n",
1268 master_runtime->sample_bits,
1269 master_runtime->rate);
1270
1271 snd_pcm_hw_constraint_minmax(substream->runtime,
1272 SNDRV_PCM_HW_PARAM_RATE,
1273 master_runtime->rate,
1274 master_runtime->rate);
1275
1276 snd_pcm_hw_constraint_minmax(substream->runtime,
1277 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1278 master_runtime->sample_bits,
1279 master_runtime->sample_bits);
1280
1281 wm8903->slave_substream = substream;
1282 } else
1283 wm8903->master_substream = substream;
1284
1285 return 0;
1286}
1287
dee89c4d
MB		 1288static void wm8903_shutdown(struct snd_pcm_substream *substream,
1289 struct snd_soc_dai *dai)
f1c0a02f
MB		 1290{
1291 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1292 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1293 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1294 struct wm8903_priv *wm8903 = codec->private_data;
1295
1296 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1297 wm8903->playback_active--;
1298 else
1299 wm8903->capture_active--;
1300
1301 if (wm8903->master_substream == substream)
1302 wm8903->master_substream = wm8903->slave_substream;
1303
1304 wm8903->slave_substream = NULL;
1305}
1306
1307static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1308 struct snd_pcm_hw_params *params,
1309 struct snd_soc_dai *dai)
f1c0a02f
MB		 1310{
1311 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1312 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1313 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1314 struct wm8903_priv *wm8903 = codec->private_data;
1315 struct i2c_client *i2c = codec->control_data;
1316 int fs = params_rate(params);
1317 int bclk;
1318 int bclk_div;
1319 int i;
1320 int dsp_config;
1321 int clk_config;
1322 int best_val;
1323 int cur_val;
1324 int clk_sys;
1325
1326 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1327 u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2);
1328 u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3);
1329 u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0);
1330 u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1);
1331
1332 if (substream == wm8903->slave_substream) {
1333 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1334 return 0;
1335 }
1336
1337 /* Configure sample rate logic for DSP - choose nearest rate */
1338 dsp_config = 0;
1339 best_val = abs(sample_rates[dsp_config].rate - fs);
1340 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1341 cur_val = abs(sample_rates[i].rate - fs);
1342 if (cur_val <= best_val) {
1343 dsp_config = i;
1344 best_val = cur_val;
1345 }
1346 }
1347
1348 /* Constraints should stop us hitting this but let's make sure */
1349 if (wm8903->capture_active)
1350 switch (sample_rates[dsp_config].rate) {
1351 case 88200:
1352 case 96000:
1353 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1354 fs);
1355 return -EINVAL;
1356
1357 default:
1358 break;
1359 }
1360
1361 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1362 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1363 clock1 |= sample_rates[dsp_config].value;
1364
1365 aif1 &= ~WM8903_AIF_WL_MASK;
1366 bclk = 2 * fs;
1367 switch (params_format(params)) {
1368 case SNDRV_PCM_FORMAT_S16_LE:
1369 bclk *= 16;
1370 break;
1371 case SNDRV_PCM_FORMAT_S20_3LE:
1372 bclk *= 20;
1373 aif1 |= 0x4;
1374 break;
1375 case SNDRV_PCM_FORMAT_S24_LE:
1376 bclk *= 24;
1377 aif1 |= 0x8;
1378 break;
1379 case SNDRV_PCM_FORMAT_S32_LE:
1380 bclk *= 32;
1381 aif1 |= 0xc;
1382 break;
1383 default:
1384 return -EINVAL;
1385 }
1386
1387 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1388 wm8903->sysclk, fs);
1389
1390 /* We may not have an MCLK which allows us to generate exactly
1391 * the clock we want, particularly with USB derived inputs, so
1392 * approximate.
1393 */
1394 clk_config = 0;
1395 best_val = abs((wm8903->sysclk /
1396 (clk_sys_ratios[0].mclk_div *
1397 clk_sys_ratios[0].div)) - fs);
1398 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1399 cur_val = abs((wm8903->sysclk /
1400 (clk_sys_ratios[i].mclk_div *
1401 clk_sys_ratios[i].div)) - fs);
1402
1403 if (cur_val <= best_val) {
1404 clk_config = i;
1405 best_val = cur_val;
1406 }
1407 }
1408
1409 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1410 clock0 |= WM8903_MCLKDIV2;
1411 clk_sys = wm8903->sysclk / 2;
1412 } else {
1413 clock0 &= ~WM8903_MCLKDIV2;
1414 clk_sys = wm8903->sysclk;
1415 }
1416
1417 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1418 WM8903_CLK_SYS_MODE_MASK);
1419 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1420 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1421
1422 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1423 clk_sys_ratios[clk_config].rate,
1424 clk_sys_ratios[clk_config].mode,
1425 clk_sys_ratios[clk_config].div);
1426
1427 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1428
1429 /* We may not get quite the right frequency if using
1430 * approximate clocks so look for the closest match that is
1431 * higher than the target (we need to ensure that there enough
1432 * BCLKs to clock out the samples).
1433 */
1434 bclk_div = 0;
1435 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1436 i = 1;
1437 while (i < ARRAY_SIZE(bclk_divs)) {
1438 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1439 if (cur_val < 0) /* BCLK table is sorted */
1440 break;
1441 bclk_div = i;
1442 best_val = cur_val;
1443 i++;
1444 }
1445
1446 aif2 &= ~WM8903_BCLK_DIV_MASK;
1447 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1448
1449 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1450 bclk_divs[bclk_div].ratio / 10, bclk,
1451 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1452
1453 aif2 |= bclk_divs[bclk_div].div;
1454 aif3 |= bclk / fs;
1455
1456 wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0);
1457 wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1);
1458 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1459 wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1460 wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1461
1462 return 0;
1463}
1464
1465#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1466 SNDRV_PCM_RATE_11025 | \
1467 SNDRV_PCM_RATE_16000 | \
1468 SNDRV_PCM_RATE_22050 | \
1469 SNDRV_PCM_RATE_32000 | \
1470 SNDRV_PCM_RATE_44100 | \
1471 SNDRV_PCM_RATE_48000 | \
1472 SNDRV_PCM_RATE_88200 | \
1473 SNDRV_PCM_RATE_96000)
1474
1475#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1476 SNDRV_PCM_RATE_11025 | \
1477 SNDRV_PCM_RATE_16000 | \
1478 SNDRV_PCM_RATE_22050 | \
1479 SNDRV_PCM_RATE_32000 | \
1480 SNDRV_PCM_RATE_44100 | \
1481 SNDRV_PCM_RATE_48000)
1482
1483#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1484 SNDRV_PCM_FMTBIT_S20_3LE |\
1485 SNDRV_PCM_FMTBIT_S24_LE)
1486
6335d055
EM		 1487static struct snd_soc_dai_ops wm8903_dai_ops = {
1488 .startup = wm8903_startup,
1489 .shutdown = wm8903_shutdown,
1490 .hw_params = wm8903_hw_params,
1491 .digital_mute = wm8903_digital_mute,
1492 .set_fmt = wm8903_set_dai_fmt,
1493 .set_sysclk = wm8903_set_dai_sysclk,
1494};
1495
f1c0a02f
MB		 1496struct snd_soc_dai wm8903_dai = {
1497 .name = "WM8903",
1498 .playback = {
1499 .stream_name = "Playback",
1500 .channels_min = 2,
1501 .channels_max = 2,
1502 .rates = WM8903_PLAYBACK_RATES,
1503 .formats = WM8903_FORMATS,
1504 },
1505 .capture = {
1506 .stream_name = "Capture",
1507 .channels_min = 2,
1508 .channels_max = 2,
1509 .rates = WM8903_CAPTURE_RATES,
1510 .formats = WM8903_FORMATS,
1511 },
6335d055 1512 .ops = &wm8903_dai_ops,
0d960e88 1513 .symmetric_rates = 1,
f1c0a02f
MB		 1514};
1515EXPORT_SYMBOL_GPL(wm8903_dai);
1516
1517static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1518{
1519 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1520 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1521
1522 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1523
1524 return 0;
1525}
1526
1527static int wm8903_resume(struct platform_device *pdev)
1528{
1529 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1530 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1531 struct i2c_client *i2c = codec->control_data;
1532 int i;
1533 u16 *reg_cache = codec->reg_cache;
1534 u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults),
1535 GFP_KERNEL);
1536
1537 /* Bring the codec back up to standby first to minimise pop/clicks */
1538 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1539 wm8903_set_bias_level(codec, codec->suspend_bias_level);
1540
1541 /* Sync back everything else */
1542 if (tmp_cache) {
1543 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1544 if (tmp_cache[i] != reg_cache[i])
1545 wm8903_write(codec, i, tmp_cache[i]);
1546 } else {
1547 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1548 }
1549
1550 return 0;
1551}
1552
d58d5d55
MB		 1553static struct snd_soc_codec *wm8903_codec;
1554
c6f29811
MB		 1555static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1556 const struct i2c_device_id *id)
f1c0a02f 1557{
d58d5d55
MB		 1558 struct wm8903_priv *wm8903;
1559 struct snd_soc_codec *codec;
1560 int ret;
f1c0a02f
MB		 1561 u16 val;
1562
d58d5d55
MB		 1563 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1564 if (wm8903 == NULL)
1565 return -ENOMEM;
f1c0a02f 1566
d58d5d55
MB		 1567 codec = &wm8903->codec;
1568
1569 mutex_init(&codec->mutex);
1570 INIT_LIST_HEAD(&codec->dapm_widgets);
1571 INIT_LIST_HEAD(&codec->dapm_paths);
1572
1573 codec->dev = &i2c->dev;
f1c0a02f
MB		 1574 codec->name = "WM8903";
1575 codec->owner = THIS_MODULE;
1576 codec->read = wm8903_read;
1577 codec->write = wm8903_write;
d58d5d55 1578 codec->hw_write = (hw_write_t)i2c_master_send;
f1c0a02f
MB		 1579 codec->bias_level = SND_SOC_BIAS_OFF;
1580 codec->set_bias_level = wm8903_set_bias_level;
1581 codec->dai = &wm8903_dai;
1582 codec->num_dai = 1;
d58d5d55
MB		 1583 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1584 codec->reg_cache = &wm8903->reg_cache[0];
1585 codec->private_data = wm8903;
1586
1587 i2c_set_clientdata(i2c, codec);
1588 codec->control_data = i2c;
1589
1590 val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID);
1591 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1592 dev_err(&i2c->dev,
1593 "Device with ID register %x is not a WM8903\n", val);
1594 return -ENODEV;
f1c0a02f
MB		 1595 }
1596
1597 val = wm8903_read(codec, WM8903_REVISION_NUMBER);
1598 dev_info(&i2c->dev, "WM8903 revision %d\n",
1599 val & WM8903_CHIP_REV_MASK);
1600
1601 wm8903_reset(codec);
1602
f1c0a02f
MB		 1603 /* power on device */
1604 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1605
1606 /* Latch volume update bits */
1607 val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1608 val |= WM8903_ADCVU;
1609 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1610 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1611
1612 val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1613 val |= WM8903_DACVU;
1614 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1615 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1616
1617 val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1618 val |= WM8903_HPOUTVU;
1619 wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1620 wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1621
1622 val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1623 val |= WM8903_LINEOUTVU;
1624 wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1625 wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1626
1627 val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1628 val |= WM8903_SPKVU;
1629 wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1630 wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1631
1632 /* Enable DAC soft mute by default */
1633 val = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1634 val |= WM8903_DAC_MUTEMODE;
1635 wm8903_write(codec, WM8903_DAC_DIGITAL_1, val);
1636
d58d5d55
MB		 1637 wm8903_dai.dev = &i2c->dev;
1638 wm8903_codec = codec;
1639
1640 ret = snd_soc_register_codec(codec);
1641 if (ret != 0) {
1642 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1643 goto err;
1644 }
1645
1646 ret = snd_soc_register_dai(&wm8903_dai);
1647 if (ret != 0) {
1648 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1649 goto err_codec;
f1c0a02f
MB		 1650 }
1651
1652 return ret;
1653
d58d5d55
MB		 1654err_codec:
1655 snd_soc_unregister_codec(codec);
1656err:
1657 wm8903_codec = NULL;
1658 kfree(wm8903);
f1c0a02f
MB		 1659 return ret;
1660}
1661
c6f29811 1662static __devexit int wm8903_i2c_remove(struct i2c_client *client)
f1c0a02f 1663{
d58d5d55 1664 struct snd_soc_codec *codec = i2c_get_clientdata(client);
f1c0a02f 1665
d58d5d55
MB		 1666 snd_soc_unregister_dai(&wm8903_dai);
1667 snd_soc_unregister_codec(codec);
f1c0a02f 1668
d58d5d55 1669 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f1c0a02f 1670
d58d5d55
MB		 1671 kfree(codec->private_data);
1672
1673 wm8903_codec = NULL;
1674 wm8903_dai.dev = NULL;
f1c0a02f 1675
f1c0a02f
MB		 1676 return 0;
1677}
1678
1679/* i2c codec control layer */
1680static const struct i2c_device_id wm8903_i2c_id[] = {
1681 { "wm8903", 0 },
1682 { }
1683};
1684MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1685
1686static struct i2c_driver wm8903_i2c_driver = {
1687 .driver = {
1688 .name = "WM8903",
1689 .owner = THIS_MODULE,
1690 },
1691 .probe = wm8903_i2c_probe,
c6f29811 1692 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1693 .id_table = wm8903_i2c_id,
1694};
1695
f1c0a02f
MB		 1696static int wm8903_probe(struct platform_device *pdev)
1697{
1698 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
f1c0a02f
MB		 1699 int ret = 0;
1700
d58d5d55
MB		 1701 if (!wm8903_codec) {
1702 dev_err(&pdev->dev, "I2C device not yet probed\n");
1703 goto err;
f1c0a02f
MB		 1704 }
1705
6627a653 1706 socdev->card->codec = wm8903_codec;
f1c0a02f 1707
d58d5d55
MB		 1708 /* register pcms */
1709 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1710 if (ret < 0) {
1711 dev_err(&pdev->dev, "failed to create pcms\n");
1712 goto err;
f1c0a02f
MB		 1713 }
1714
6627a653 1715 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
3e8e1952 1716 ARRAY_SIZE(wm8903_snd_controls));
6627a653 1717 wm8903_add_widgets(socdev->card->codec);
f1c0a02f 1718
d58d5d55
MB		 1719 ret = snd_soc_init_card(socdev);
1720 if (ret < 0) {
1721 dev_err(&pdev->dev, "wm8903: failed to register card\n");
1722 goto card_err;
f1c0a02f
MB		 1723 }
1724
1725 return ret;
1726
d58d5d55
MB		 1727card_err:
1728 snd_soc_free_pcms(socdev);
1729 snd_soc_dapm_free(socdev);
1730err:
f1c0a02f
MB		 1731 return ret;
1732}
1733
1734/* power down chip */
1735static int wm8903_remove(struct platform_device *pdev)
1736{
1737 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1738 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1739
1740 if (codec->control_data)
1741 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1742
1743 snd_soc_free_pcms(socdev);
1744 snd_soc_dapm_free(socdev);
f1c0a02f
MB		 1745
1746 return 0;
1747}
1748
1749struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1750 .probe = wm8903_probe,
1751 .remove = wm8903_remove,
1752 .suspend = wm8903_suspend,
1753 .resume = wm8903_resume,
1754};
1755EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1756
c9b3a40f 1757static int __init wm8903_modinit(void)
64089b84 1758{
d58d5d55 1759 return i2c_add_driver(&wm8903_i2c_driver);
64089b84
MB		 1760}
1761module_init(wm8903_modinit);
1762
1763static void __exit wm8903_exit(void)
1764{
d58d5d55 1765 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 1766}
1767module_exit(wm8903_exit);
1768
f1c0a02f
MB		 1769MODULE_DESCRIPTION("ASoC WM8903 driver");
1770MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1771MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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