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ASoC: Implement WM8903 high pass filter support
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
f1c0a02f 14 * - Digital microphone support.
f1c0a02f
MB		 15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
8abd16a6 20#include <linux/completion.h>
f1c0a02f
MB		 21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
5a0e3ad6 25#include <linux/slab.h>
f1c0a02f 26#include <sound/core.h>
7245387e 27#include <sound/jack.h>
f1c0a02f
MB		 28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/tlv.h>
31#include <sound/soc.h>
f1c0a02f 32#include <sound/initval.h>
8abd16a6 33#include <sound/wm8903.h>
f1c0a02f
MB		 34
35#include "wm8903.h"
36
f1c0a02f
MB		 37/* Register defaults at reset */
38static u16 wm8903_reg_defaults[] = {
39 0x8903, /* R0 - SW Reset and ID */
40 0x0000, /* R1 - Revision Number */
41 0x0000, /* R2 */
42 0x0000, /* R3 */
43 0x0018, /* R4 - Bias Control 0 */
44 0x0000, /* R5 - VMID Control 0 */
45 0x0000, /* R6 - Mic Bias Control 0 */
46 0x0000, /* R7 */
47 0x0001, /* R8 - Analogue DAC 0 */
48 0x0000, /* R9 */
49 0x0001, /* R10 - Analogue ADC 0 */
50 0x0000, /* R11 */
51 0x0000, /* R12 - Power Management 0 */
52 0x0000, /* R13 - Power Management 1 */
53 0x0000, /* R14 - Power Management 2 */
54 0x0000, /* R15 - Power Management 3 */
55 0x0000, /* R16 - Power Management 4 */
56 0x0000, /* R17 - Power Management 5 */
57 0x0000, /* R18 - Power Management 6 */
58 0x0000, /* R19 */
59 0x0400, /* R20 - Clock Rates 0 */
60 0x0D07, /* R21 - Clock Rates 1 */
61 0x0000, /* R22 - Clock Rates 2 */
62 0x0000, /* R23 */
63 0x0050, /* R24 - Audio Interface 0 */
64 0x0242, /* R25 - Audio Interface 1 */
65 0x0008, /* R26 - Audio Interface 2 */
66 0x0022, /* R27 - Audio Interface 3 */
67 0x0000, /* R28 */
68 0x0000, /* R29 */
69 0x00C0, /* R30 - DAC Digital Volume Left */
70 0x00C0, /* R31 - DAC Digital Volume Right */
71 0x0000, /* R32 - DAC Digital 0 */
72 0x0000, /* R33 - DAC Digital 1 */
73 0x0000, /* R34 */
74 0x0000, /* R35 */
75 0x00C0, /* R36 - ADC Digital Volume Left */
76 0x00C0, /* R37 - ADC Digital Volume Right */
77 0x0000, /* R38 - ADC Digital 0 */
78 0x0073, /* R39 - Digital Microphone 0 */
79 0x09BF, /* R40 - DRC 0 */
80 0x3241, /* R41 - DRC 1 */
81 0x0020, /* R42 - DRC 2 */
82 0x0000, /* R43 - DRC 3 */
83 0x0085, /* R44 - Analogue Left Input 0 */
84 0x0085, /* R45 - Analogue Right Input 0 */
85 0x0044, /* R46 - Analogue Left Input 1 */
86 0x0044, /* R47 - Analogue Right Input 1 */
87 0x0000, /* R48 */
88 0x0000, /* R49 */
89 0x0008, /* R50 - Analogue Left Mix 0 */
90 0x0004, /* R51 - Analogue Right Mix 0 */
91 0x0000, /* R52 - Analogue Spk Mix Left 0 */
92 0x0000, /* R53 - Analogue Spk Mix Left 1 */
93 0x0000, /* R54 - Analogue Spk Mix Right 0 */
94 0x0000, /* R55 - Analogue Spk Mix Right 1 */
95 0x0000, /* R56 */
96 0x002D, /* R57 - Analogue OUT1 Left */
97 0x002D, /* R58 - Analogue OUT1 Right */
98 0x0039, /* R59 - Analogue OUT2 Left */
99 0x0039, /* R60 - Analogue OUT2 Right */
100 0x0100, /* R61 */
101 0x0139, /* R62 - Analogue OUT3 Left */
102 0x0139, /* R63 - Analogue OUT3 Right */
103 0x0000, /* R64 */
104 0x0000, /* R65 - Analogue SPK Output Control 0 */
105 0x0000, /* R66 */
106 0x0010, /* R67 - DC Servo 0 */
107 0x0100, /* R68 */
108 0x00A4, /* R69 - DC Servo 2 */
109 0x0807, /* R70 */
110 0x0000, /* R71 */
111 0x0000, /* R72 */
112 0x0000, /* R73 */
113 0x0000, /* R74 */
114 0x0000, /* R75 */
115 0x0000, /* R76 */
116 0x0000, /* R77 */
117 0x0000, /* R78 */
118 0x000E, /* R79 */
119 0x0000, /* R80 */
120 0x0000, /* R81 */
121 0x0000, /* R82 */
122 0x0000, /* R83 */
123 0x0000, /* R84 */
124 0x0000, /* R85 */
125 0x0000, /* R86 */
126 0x0006, /* R87 */
127 0x0000, /* R88 */
128 0x0000, /* R89 */
129 0x0000, /* R90 - Analogue HP 0 */
130 0x0060, /* R91 */
131 0x0000, /* R92 */
132 0x0000, /* R93 */
133 0x0000, /* R94 - Analogue Lineout 0 */
134 0x0060, /* R95 */
135 0x0000, /* R96 */
136 0x0000, /* R97 */
137 0x0000, /* R98 - Charge Pump 0 */
138 0x1F25, /* R99 */
139 0x2B19, /* R100 */
140 0x01C0, /* R101 */
141 0x01EF, /* R102 */
142 0x2B00, /* R103 */
143 0x0000, /* R104 - Class W 0 */
144 0x01C0, /* R105 */
145 0x1C10, /* R106 */
146 0x0000, /* R107 */
147 0x0000, /* R108 - Write Sequencer 0 */
148 0x0000, /* R109 - Write Sequencer 1 */
149 0x0000, /* R110 - Write Sequencer 2 */
150 0x0000, /* R111 - Write Sequencer 3 */
151 0x0000, /* R112 - Write Sequencer 4 */
152 0x0000, /* R113 */
153 0x0000, /* R114 - Control Interface */
154 0x0000, /* R115 */
155 0x00A8, /* R116 - GPIO Control 1 */
156 0x00A8, /* R117 - GPIO Control 2 */
157 0x00A8, /* R118 - GPIO Control 3 */
158 0x0220, /* R119 - GPIO Control 4 */
159 0x01A0, /* R120 - GPIO Control 5 */
160 0x0000, /* R121 - Interrupt Status 1 */
161 0xFFFF, /* R122 - Interrupt Status 1 Mask */
162 0x0000, /* R123 - Interrupt Polarity 1 */
163 0x0000, /* R124 */
164 0x0003, /* R125 */
165 0x0000, /* R126 - Interrupt Control */
166 0x0000, /* R127 */
167 0x0005, /* R128 */
168 0x0000, /* R129 - Control Interface Test 1 */
169 0x0000, /* R130 */
170 0x0000, /* R131 */
171 0x0000, /* R132 */
172 0x0000, /* R133 */
173 0x0000, /* R134 */
174 0x03FF, /* R135 */
175 0x0007, /* R136 */
176 0x0040, /* R137 */
177 0x0000, /* R138 */
178 0x0000, /* R139 */
179 0x0000, /* R140 */
180 0x0000, /* R141 */
181 0x0000, /* R142 */
182 0x0000, /* R143 */
183 0x0000, /* R144 */
184 0x0000, /* R145 */
185 0x0000, /* R146 */
186 0x0000, /* R147 */
187 0x4000, /* R148 */
188 0x6810, /* R149 - Charge Pump Test 1 */
189 0x0004, /* R150 */
190 0x0000, /* R151 */
191 0x0000, /* R152 */
192 0x0000, /* R153 */
193 0x0000, /* R154 */
194 0x0000, /* R155 */
195 0x0000, /* R156 */
196 0x0000, /* R157 */
197 0x0000, /* R158 */
198 0x0000, /* R159 */
199 0x0000, /* R160 */
200 0x0000, /* R161 */
201 0x0000, /* R162 */
202 0x0000, /* R163 */
203 0x0028, /* R164 - Clock Rate Test 4 */
204 0x0004, /* R165 */
205 0x0000, /* R166 */
206 0x0060, /* R167 */
207 0x0000, /* R168 */
208 0x0000, /* R169 */
209 0x0000, /* R170 */
210 0x0000, /* R171 */
211 0x0000, /* R172 - Analogue Output Bias 0 */
212};
213
d58d5d55 214struct wm8903_priv {
f0fba2ad 215
d58d5d55
MB		 216 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
217
218 int sysclk;
f0fba2ad 219 int irq;
d58d5d55
MB		 220
221 /* Reference counts */
d58d5d55
MB		 222 int class_w_users;
223 int playback_active;
224 int capture_active;
225
8abd16a6
MB		 226 struct completion wseq;
227
7245387e
MB		 228 struct snd_soc_jack *mic_jack;
229 int mic_det;
230 int mic_short;
231 int mic_last_report;
232 int mic_delay;
233
d58d5d55
MB		 234 struct snd_pcm_substream *master_substream;
235 struct snd_pcm_substream *slave_substream;
236};
237
8d50e447 238static int wm8903_volatile_register(unsigned int reg)
f1c0a02f
MB		 239{
240 switch (reg) {
241 case WM8903_SW_RESET_AND_ID:
242 case WM8903_REVISION_NUMBER:
243 case WM8903_INTERRUPT_STATUS_1:
244 case WM8903_WRITE_SEQUENCER_4:
8d50e447 245 return 1;
f1c0a02f
MB		 246
247 default:
f1c0a02f 248 return 0;
8d50e447 249 }
f1c0a02f
MB		 250}
251
252static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
253{
254 u16 reg[5];
b2c812e2 255 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 256
257 BUG_ON(start > 48);
258
37f88e84 259 /* Enable the sequencer if it's not already on */
8d50e447 260 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 261 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
262 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 263
f0fba2ad 264 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 265
8d50e447 266 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 267 start | WM8903_WSEQ_START);
268
269 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 270 * that will break us out of the poll early.
f1c0a02f
MB		 271 */
272 do {
8abd16a6
MB		 273 wait_for_completion_timeout(&wm8903->wseq,
274 msecs_to_jiffies(10));
f1c0a02f 275
8d50e447 276 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 277 } while (reg[4] & WM8903_WSEQ_BUSY);
278
f0fba2ad 279 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 280
37f88e84
MB		 281 /* Disable the sequencer again if we enabled it */
282 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 283
284 return 0;
285}
286
287static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
288{
289 int i;
290
291 /* There really ought to be something better we can do here :/ */
292 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 293 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 294}
295
296static void wm8903_reset(struct snd_soc_codec *codec)
297{
8d50e447 298 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 299 memcpy(codec->reg_cache, wm8903_reg_defaults,
300 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 301}
302
303#define WM8903_OUTPUT_SHORT 0x8
304#define WM8903_OUTPUT_OUT 0x4
305#define WM8903_OUTPUT_INT 0x2
306#define WM8903_OUTPUT_IN 0x1
307
42768a12
MB		 308static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
309 struct snd_kcontrol *kcontrol, int event)
310{
311 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
312 mdelay(4);
313
314 return 0;
315}
316
f1c0a02f
MB		 317/*
318 * Event for headphone and line out amplifier power changes. Special
319 * power up/down sequences are required in order to maximise pop/click
320 * performance.
321 */
322static int wm8903_output_event(struct snd_soc_dapm_widget *w,
323 struct snd_kcontrol *kcontrol, int event)
324{
325 struct snd_soc_codec *codec = w->codec;
f1c0a02f 326 u16 val;
0bc286e2 327 u16 reg;
d7d5c547
MB		 328 u16 dcs_reg;
329 u16 dcs_bit;
0bc286e2 330 int shift;
f1c0a02f
MB		 331
332 switch (w->reg) {
333 case WM8903_POWER_MANAGEMENT_2:
334 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 335 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 336 break;
337 case WM8903_POWER_MANAGEMENT_3:
338 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 339 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 340 break;
341 default:
342 BUG();
1e297a19 343 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 344 }
345
346 switch (w->shift) {
347 case 0:
348 shift = 0;
349 break;
350 case 1:
351 shift = 4;
352 break;
353 default:
354 BUG();
1e297a19 355 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 356 }
357
358 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 359 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 360
361 /* Short the output */
362 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 363 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 364 }
365
366 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 367 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 368
369 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 370 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 371
372 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 373 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 374
375 /* Turn on the output ENA_OUTP */
376 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 377 snd_soc_write(codec, reg, val);
f1c0a02f 378
d7d5c547 379 /* Enable the DC servo */
8d50e447 380 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 381 dcs_reg |= dcs_bit;
8d50e447 382 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 383
f1c0a02f
MB		 384 /* Remove the short */
385 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 386 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 387 }
388
389 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 390 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 391
392 /* Short the output */
393 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 394 snd_soc_write(codec, reg, val);
f1c0a02f 395
d7d5c547 396 /* Disable the DC servo */
8d50e447 397 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 398 dcs_reg &= ~dcs_bit;
8d50e447 399 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 400
f1c0a02f
MB		 401 /* Then disable the intermediate and output stages */
402 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
403 WM8903_OUTPUT_IN) << shift);
8d50e447 404 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 405 }
406
f1c0a02f
MB		 407 return 0;
408}
409
410/*
411 * When used with DAC outputs only the WM8903 charge pump supports
412 * operation in class W mode, providing very low power consumption
413 * when used with digital sources. Enable and disable this mode
414 * automatically depending on the mixer configuration.
415 *
416 * All the relevant controls are simple switches.
417 */
418static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
419 struct snd_ctl_elem_value *ucontrol)
420{
421 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
422 struct snd_soc_codec *codec = widget->codec;
b2c812e2 423 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 424 u16 reg;
425 int ret;
426
8d50e447 427 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 428
429 /* Turn it off if we're about to enable bypass */
430 if (ucontrol->value.integer.value[0]) {
431 if (wm8903->class_w_users == 0) {
f0fba2ad 432 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 433 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 434 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
435 }
436 wm8903->class_w_users++;
437 }
438
439 /* Implement the change */
440 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
441
442 /* If we've just disabled the last bypass path turn Class W on */
443 if (!ucontrol->value.integer.value[0]) {
444 if (wm8903->class_w_users == 1) {
f0fba2ad 445 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 446 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 447 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
448 }
449 wm8903->class_w_users--;
450 }
451
f0fba2ad 452 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 453 wm8903->class_w_users);
454
455 return ret;
456}
457
458#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
459{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
460 .info = snd_soc_info_volsw, \
461 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
462 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
463
464
465/* ALSA can only do steps of .01dB */
466static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
467
291ce18c 468static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 469static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
470
471static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
472static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
473static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
474static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
475static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
476
460f4aae
MB		 477static const char *hpf_mode_text[] = {
478 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
479};
480
481static const struct soc_enum hpf_mode =
482 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
483
f1c0a02f
MB		 484static const char *drc_slope_text[] = {
485 "1", "1/2", "1/4", "1/8", "1/16", "0"
486};
487
488static const struct soc_enum drc_slope_r0 =
489 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
490
491static const struct soc_enum drc_slope_r1 =
492 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
493
494static const char *drc_attack_text[] = {
495 "instantaneous",
496 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
497 "46.4ms", "92.8ms", "185.6ms"
498};
499
500static const struct soc_enum drc_attack =
501 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
502
503static const char *drc_decay_text[] = {
504 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
505 "23.87s", "47.56s"
506};
507
508static const struct soc_enum drc_decay =
509 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
510
511static const char *drc_ff_delay_text[] = {
512 "5 samples", "9 samples"
513};
514
515static const struct soc_enum drc_ff_delay =
516 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
517
518static const char *drc_qr_decay_text[] = {
519 "0.725ms", "1.45ms", "5.8ms"
520};
521
522static const struct soc_enum drc_qr_decay =
523 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
524
525static const char *drc_smoothing_text[] = {
526 "Low", "Medium", "High"
527};
528
529static const struct soc_enum drc_smoothing =
530 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
531
532static const char *soft_mute_text[] = {
533 "Fast (fs/2)", "Slow (fs/32)"
534};
535
536static const struct soc_enum soft_mute =
537 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
538
539static const char *mute_mode_text[] = {
540 "Hard", "Soft"
541};
542
543static const struct soc_enum mute_mode =
544 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
545
546static const char *dac_deemphasis_text[] = {
547 "Disabled", "32kHz", "44.1kHz", "48kHz"
548};
549
550static const struct soc_enum dac_deemphasis =
551 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
552
553static const char *companding_text[] = {
554 "ulaw", "alaw"
555};
556
557static const struct soc_enum dac_companding =
558 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
559
560static const struct soc_enum adc_companding =
561 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
562
563static const char *input_mode_text[] = {
564 "Single-Ended", "Differential Line", "Differential Mic"
565};
566
567static const struct soc_enum linput_mode_enum =
568 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
569
570static const struct soc_enum rinput_mode_enum =
571 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
572
573static const char *linput_mux_text[] = {
574 "IN1L", "IN2L", "IN3L"
575};
576
577static const struct soc_enum linput_enum =
578 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
579
580static const struct soc_enum linput_inv_enum =
581 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
582
583static const char *rinput_mux_text[] = {
584 "IN1R", "IN2R", "IN3R"
585};
586
587static const struct soc_enum rinput_enum =
588 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
589
590static const struct soc_enum rinput_inv_enum =
591 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
592
593
291ce18c
MB		 594static const char *sidetone_text[] = {
595 "None", "Left", "Right"
596};
597
598static const struct soc_enum lsidetone_enum =
599 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
600
601static const struct soc_enum rsidetone_enum =
602 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
603
f1c0a02f
MB		 604static const struct snd_kcontrol_new wm8903_snd_controls[] = {
605
606/* Input PGAs - No TLV since the scale depends on PGA mode */
607SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 608 7, 1, 1),
f1c0a02f
MB		 609SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
610 0, 31, 0),
611SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
612 6, 1, 0),
613
614SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 615 7, 1, 1),
f1c0a02f
MB		 616SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
617 0, 31, 0),
618SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
619 6, 1, 0),
620
621/* ADCs */
460f4aae
MB		 622SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
623SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 624SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
625SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
626SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 627SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 628 drc_tlv_thresh),
629SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
630SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
631SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
632SOC_ENUM("DRC Attack Rate", drc_attack),
633SOC_ENUM("DRC Decay Rate", drc_decay),
634SOC_ENUM("DRC FF Delay", drc_ff_delay),
635SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
636SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 637SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 638SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
639SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
640SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 641SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 642SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
643
644SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
645 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
646SOC_ENUM("ADC Companding Mode", adc_companding),
647SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
648
291ce18c
MB		 649SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
650 12, 0, digital_sidetone_tlv),
651
f1c0a02f
MB		 652/* DAC */
653SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
654 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
655SOC_ENUM("DAC Soft Mute Rate", soft_mute),
656SOC_ENUM("DAC Mute Mode", mute_mode),
657SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
658SOC_ENUM("DAC De-emphasis", dac_deemphasis),
f1c0a02f
MB		 659SOC_ENUM("DAC Companding Mode", dac_companding),
660SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
661
662/* Headphones */
663SOC_DOUBLE_R("Headphone Switch",
664 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
665 8, 1, 1),
666SOC_DOUBLE_R("Headphone ZC Switch",
667 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
668 6, 1, 0),
669SOC_DOUBLE_R_TLV("Headphone Volume",
670 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
671 0, 63, 0, out_tlv),
672
673/* Line out */
674SOC_DOUBLE_R("Line Out Switch",
675 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
676 8, 1, 1),
677SOC_DOUBLE_R("Line Out ZC Switch",
678 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
679 6, 1, 0),
680SOC_DOUBLE_R_TLV("Line Out Volume",
681 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
682 0, 63, 0, out_tlv),
683
684/* Speaker */
685SOC_DOUBLE_R("Speaker Switch",
686 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
687SOC_DOUBLE_R("Speaker ZC Switch",
688 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
689SOC_DOUBLE_R_TLV("Speaker Volume",
690 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
691 0, 63, 0, out_tlv),
692};
693
f1c0a02f
MB		 694static const struct snd_kcontrol_new linput_mode_mux =
695 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
696
697static const struct snd_kcontrol_new rinput_mode_mux =
698 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
699
700static const struct snd_kcontrol_new linput_mux =
701 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
702
703static const struct snd_kcontrol_new linput_inv_mux =
704 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
705
706static const struct snd_kcontrol_new rinput_mux =
707 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
708
709static const struct snd_kcontrol_new rinput_inv_mux =
710 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
711
291ce18c
MB		 712static const struct snd_kcontrol_new lsidetone_mux =
713 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
714
715static const struct snd_kcontrol_new rsidetone_mux =
716 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
717
f1c0a02f
MB		 718static const struct snd_kcontrol_new left_output_mixer[] = {
719SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
720SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
721SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 722SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 723};
724
725static const struct snd_kcontrol_new right_output_mixer[] = {
726SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
727SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
728SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 729SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 730};
731
732static const struct snd_kcontrol_new left_speaker_mixer[] = {
733SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
734SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
735SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
736SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 737 0, 1, 0),
f1c0a02f
MB		 738};
739
740static const struct snd_kcontrol_new right_speaker_mixer[] = {
741SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
742SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
743SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
744 1, 1, 0),
745SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 746 0, 1, 0),
f1c0a02f
MB		 747};
748
749static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
750SND_SOC_DAPM_INPUT("IN1L"),
751SND_SOC_DAPM_INPUT("IN1R"),
752SND_SOC_DAPM_INPUT("IN2L"),
753SND_SOC_DAPM_INPUT("IN2R"),
754SND_SOC_DAPM_INPUT("IN3L"),
755SND_SOC_DAPM_INPUT("IN3R"),
756
757SND_SOC_DAPM_OUTPUT("HPOUTL"),
758SND_SOC_DAPM_OUTPUT("HPOUTR"),
759SND_SOC_DAPM_OUTPUT("LINEOUTL"),
760SND_SOC_DAPM_OUTPUT("LINEOUTR"),
761SND_SOC_DAPM_OUTPUT("LOP"),
762SND_SOC_DAPM_OUTPUT("LON"),
763SND_SOC_DAPM_OUTPUT("ROP"),
764SND_SOC_DAPM_OUTPUT("RON"),
765
766SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
767
768SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
769SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
770 &linput_inv_mux),
771SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
772
773SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
774SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
775 &rinput_inv_mux),
776SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
777
778SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
779SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
780
781SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
782SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
783
291ce18c
MB		 784SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
785SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
786
f1c0a02f
MB		 787SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
788SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
789
790SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
791 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
792SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
793 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
794
795SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
796 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
797SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
798 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
799
800SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
801 1, 0, NULL, 0, wm8903_output_event,
802 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 803 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 804SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
805 0, 0, NULL, 0, wm8903_output_event,
806 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 807 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 808
809SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
810 NULL, 0, wm8903_output_event,
811 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 812 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 813SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
814 NULL, 0, wm8903_output_event,
815 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 816 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 817
818SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
819 NULL, 0),
820SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
821 NULL, 0),
822
42768a12
MB		 823SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
824 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 825SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 826};
827
828static const struct snd_soc_dapm_route intercon[] = {
829
830 { "Left Input Mux", "IN1L", "IN1L" },
831 { "Left Input Mux", "IN2L", "IN2L" },
832 { "Left Input Mux", "IN3L", "IN3L" },
833
834 { "Left Input Inverting Mux", "IN1L", "IN1L" },
835 { "Left Input Inverting Mux", "IN2L", "IN2L" },
836 { "Left Input Inverting Mux", "IN3L", "IN3L" },
837
838 { "Right Input Mux", "IN1R", "IN1R" },
839 { "Right Input Mux", "IN2R", "IN2R" },
840 { "Right Input Mux", "IN3R", "IN3R" },
841
842 { "Right Input Inverting Mux", "IN1R", "IN1R" },
843 { "Right Input Inverting Mux", "IN2R", "IN2R" },
844 { "Right Input Inverting Mux", "IN3R", "IN3R" },
845
846 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
847 { "Left Input Mode Mux", "Differential Line",
848 "Left Input Mux" },
849 { "Left Input Mode Mux", "Differential Line",
850 "Left Input Inverting Mux" },
851 { "Left Input Mode Mux", "Differential Mic",
852 "Left Input Mux" },
853 { "Left Input Mode Mux", "Differential Mic",
854 "Left Input Inverting Mux" },
855
856 { "Right Input Mode Mux", "Single-Ended",
857 "Right Input Inverting Mux" },
858 { "Right Input Mode Mux", "Differential Line",
859 "Right Input Mux" },
860 { "Right Input Mode Mux", "Differential Line",
861 "Right Input Inverting Mux" },
862 { "Right Input Mode Mux", "Differential Mic",
863 "Right Input Mux" },
864 { "Right Input Mode Mux", "Differential Mic",
865 "Right Input Inverting Mux" },
866
867 { "Left Input PGA", NULL, "Left Input Mode Mux" },
868 { "Right Input PGA", NULL, "Right Input Mode Mux" },
869
870 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 871 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 872 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 873 { "ADCR", NULL, "CLK_DSP" },
874
291ce18c
MB		 875 { "DACL Sidetone", "Left", "ADCL" },
876 { "DACL Sidetone", "Right", "ADCR" },
877 { "DACR Sidetone", "Left", "ADCL" },
878 { "DACR Sidetone", "Right", "ADCR" },
879
880 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 881 { "DACL", NULL, "CLK_DSP" },
291ce18c 882 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 883 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 884
885 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
886 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
887 { "Left Output Mixer", "DACL Switch", "DACL" },
888 { "Left Output Mixer", "DACR Switch", "DACR" },
889
890 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
891 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
892 { "Right Output Mixer", "DACL Switch", "DACL" },
893 { "Right Output Mixer", "DACR Switch", "DACR" },
894
895 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
896 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
897 { "Left Speaker Mixer", "DACL Switch", "DACL" },
898 { "Left Speaker Mixer", "DACR Switch", "DACR" },
899
900 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
901 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
902 { "Right Speaker Mixer", "DACL Switch", "DACL" },
903 { "Right Speaker Mixer", "DACR Switch", "DACR" },
904
905 { "Left Line Output PGA", NULL, "Left Output Mixer" },
906 { "Right Line Output PGA", NULL, "Right Output Mixer" },
907
908 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
909 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
910
911 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
912 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
913
914 { "HPOUTL", NULL, "Left Headphone Output PGA" },
915 { "HPOUTR", NULL, "Right Headphone Output PGA" },
916
917 { "LINEOUTL", NULL, "Left Line Output PGA" },
918 { "LINEOUTR", NULL, "Right Line Output PGA" },
919
920 { "LOP", NULL, "Left Speaker PGA" },
921 { "LON", NULL, "Left Speaker PGA" },
922
923 { "ROP", NULL, "Right Speaker PGA" },
924 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 925
926 { "Left Headphone Output PGA", NULL, "Charge Pump" },
927 { "Right Headphone Output PGA", NULL, "Charge Pump" },
928 { "Left Line Output PGA", NULL, "Charge Pump" },
929 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 930};
931
932static int wm8903_add_widgets(struct snd_soc_codec *codec)
933{
ce6120cc 934 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 935
ce6120cc
LG		 936 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
937 ARRAY_SIZE(wm8903_dapm_widgets));
938 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 939
f1c0a02f
MB		 940 return 0;
941}
942
943static int wm8903_set_bias_level(struct snd_soc_codec *codec,
944 enum snd_soc_bias_level level)
945{
f1c0a02f
MB		 946 u16 reg, reg2;
947
948 switch (level) {
949 case SND_SOC_BIAS_ON:
950 case SND_SOC_BIAS_PREPARE:
8d50e447 951 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 952 reg &= ~(WM8903_VMID_RES_MASK);
953 reg |= WM8903_VMID_RES_50K;
8d50e447 954 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 955 break;
956
957 case SND_SOC_BIAS_STANDBY:
ce6120cc 958 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 959 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 960 WM8903_CLK_SYS_ENA);
961
4dbfe809 962 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 963 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
964 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
965 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 966
f1c0a02f
MB		 967 wm8903_run_sequence(codec, 0);
968 wm8903_sync_reg_cache(codec, codec->reg_cache);
969
970 /* Enable low impedence charge pump output */
8d50e447 971 reg = snd_soc_read(codec,
f1c0a02f 972 WM8903_CONTROL_INTERFACE_TEST_1);
8d50e447 973 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f 974 reg | WM8903_TEST_KEY);
8d50e447
MB		 975 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
976 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
f1c0a02f 977 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
8d50e447 978 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f
MB		 979 reg);
980
981 /* By default no bypass paths are enabled so
982 * enable Class W support.
983 */
f0fba2ad 984 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 985 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 986 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
987 }
988
8d50e447 989 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 990 reg &= ~(WM8903_VMID_RES_MASK);
991 reg |= WM8903_VMID_RES_250K;
8d50e447 992 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 993 break;
994
995 case SND_SOC_BIAS_OFF:
996 wm8903_run_sequence(codec, 32);
8d50e447 997 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 998 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 999 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1000 break;
1001 }
1002
ce6120cc 1003 codec->dapm.bias_level = level;
f1c0a02f
MB		 1004
1005 return 0;
1006}
1007
1008static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1009 int clk_id, unsigned int freq, int dir)
1010{
1011 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1012 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1013
1014 wm8903->sysclk = freq;
1015
1016 return 0;
1017}
1018
1019static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1020 unsigned int fmt)
1021{
1022 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1023 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1024
1025 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1026 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1027
1028 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1029 case SND_SOC_DAIFMT_CBS_CFS:
1030 break;
1031 case SND_SOC_DAIFMT_CBS_CFM:
1032 aif1 |= WM8903_LRCLK_DIR;
1033 break;
1034 case SND_SOC_DAIFMT_CBM_CFM:
1035 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1036 break;
1037 case SND_SOC_DAIFMT_CBM_CFS:
1038 aif1 |= WM8903_BCLK_DIR;
1039 break;
1040 default:
1041 return -EINVAL;
1042 }
1043
1044 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1045 case SND_SOC_DAIFMT_DSP_A:
1046 aif1 |= 0x3;
1047 break;
1048 case SND_SOC_DAIFMT_DSP_B:
1049 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1050 break;
1051 case SND_SOC_DAIFMT_I2S:
1052 aif1 |= 0x2;
1053 break;
1054 case SND_SOC_DAIFMT_RIGHT_J:
1055 aif1 |= 0x1;
1056 break;
1057 case SND_SOC_DAIFMT_LEFT_J:
1058 break;
1059 default:
1060 return -EINVAL;
1061 }
1062
1063 /* Clock inversion */
1064 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1065 case SND_SOC_DAIFMT_DSP_A:
1066 case SND_SOC_DAIFMT_DSP_B:
1067 /* frame inversion not valid for DSP modes */
1068 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1069 case SND_SOC_DAIFMT_NB_NF:
1070 break;
1071 case SND_SOC_DAIFMT_IB_NF:
1072 aif1 |= WM8903_AIF_BCLK_INV;
1073 break;
1074 default:
1075 return -EINVAL;
1076 }
1077 break;
1078 case SND_SOC_DAIFMT_I2S:
1079 case SND_SOC_DAIFMT_RIGHT_J:
1080 case SND_SOC_DAIFMT_LEFT_J:
1081 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1082 case SND_SOC_DAIFMT_NB_NF:
1083 break;
1084 case SND_SOC_DAIFMT_IB_IF:
1085 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1086 break;
1087 case SND_SOC_DAIFMT_IB_NF:
1088 aif1 |= WM8903_AIF_BCLK_INV;
1089 break;
1090 case SND_SOC_DAIFMT_NB_IF:
1091 aif1 |= WM8903_AIF_LRCLK_INV;
1092 break;
1093 default:
1094 return -EINVAL;
1095 }
1096 break;
1097 default:
1098 return -EINVAL;
1099 }
1100
8d50e447 1101 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1102
1103 return 0;
1104}
1105
1106static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1107{
1108 struct snd_soc_codec *codec = codec_dai->codec;
1109 u16 reg;
1110
8d50e447 1111 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1112
1113 if (mute)
1114 reg |= WM8903_DAC_MUTE;
1115 else
1116 reg &= ~WM8903_DAC_MUTE;
1117
8d50e447 1118 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1119
1120 return 0;
1121}
1122
1123/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1124 * for optimal performance so we list the lower rates first and match
1125 * on the last match we find. */
1126static struct {
1127 int div;
1128 int rate;
1129 int mode;
1130 int mclk_div;
1131} clk_sys_ratios[] = {
1132 { 64, 0x0, 0x0, 1 },
1133 { 68, 0x0, 0x1, 1 },
1134 { 125, 0x0, 0x2, 1 },
1135 { 128, 0x1, 0x0, 1 },
1136 { 136, 0x1, 0x1, 1 },
1137 { 192, 0x2, 0x0, 1 },
1138 { 204, 0x2, 0x1, 1 },
1139
1140 { 64, 0x0, 0x0, 2 },
1141 { 68, 0x0, 0x1, 2 },
1142 { 125, 0x0, 0x2, 2 },
1143 { 128, 0x1, 0x0, 2 },
1144 { 136, 0x1, 0x1, 2 },
1145 { 192, 0x2, 0x0, 2 },
1146 { 204, 0x2, 0x1, 2 },
1147
1148 { 250, 0x2, 0x2, 1 },
1149 { 256, 0x3, 0x0, 1 },
1150 { 272, 0x3, 0x1, 1 },
1151 { 384, 0x4, 0x0, 1 },
1152 { 408, 0x4, 0x1, 1 },
1153 { 375, 0x4, 0x2, 1 },
1154 { 512, 0x5, 0x0, 1 },
1155 { 544, 0x5, 0x1, 1 },
1156 { 500, 0x5, 0x2, 1 },
1157 { 768, 0x6, 0x0, 1 },
1158 { 816, 0x6, 0x1, 1 },
1159 { 750, 0x6, 0x2, 1 },
1160 { 1024, 0x7, 0x0, 1 },
1161 { 1088, 0x7, 0x1, 1 },
1162 { 1000, 0x7, 0x2, 1 },
1163 { 1408, 0x8, 0x0, 1 },
1164 { 1496, 0x8, 0x1, 1 },
1165 { 1536, 0x9, 0x0, 1 },
1166 { 1632, 0x9, 0x1, 1 },
1167 { 1500, 0x9, 0x2, 1 },
1168
1169 { 250, 0x2, 0x2, 2 },
1170 { 256, 0x3, 0x0, 2 },
1171 { 272, 0x3, 0x1, 2 },
1172 { 384, 0x4, 0x0, 2 },
1173 { 408, 0x4, 0x1, 2 },
1174 { 375, 0x4, 0x2, 2 },
1175 { 512, 0x5, 0x0, 2 },
1176 { 544, 0x5, 0x1, 2 },
1177 { 500, 0x5, 0x2, 2 },
1178 { 768, 0x6, 0x0, 2 },
1179 { 816, 0x6, 0x1, 2 },
1180 { 750, 0x6, 0x2, 2 },
1181 { 1024, 0x7, 0x0, 2 },
1182 { 1088, 0x7, 0x1, 2 },
1183 { 1000, 0x7, 0x2, 2 },
1184 { 1408, 0x8, 0x0, 2 },
1185 { 1496, 0x8, 0x1, 2 },
1186 { 1536, 0x9, 0x0, 2 },
1187 { 1632, 0x9, 0x1, 2 },
1188 { 1500, 0x9, 0x2, 2 },
1189};
1190
1191/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1192static struct {
1193 int ratio;
1194 int div;
1195} bclk_divs[] = {
1196 { 10, 0 },
f1c0a02f
MB		 1197 { 20, 2 },
1198 { 30, 3 },
1199 { 40, 4 },
1200 { 50, 5 },
f1c0a02f
MB		 1201 { 60, 7 },
1202 { 80, 8 },
1203 { 100, 9 },
f1c0a02f
MB		 1204 { 120, 11 },
1205 { 160, 12 },
1206 { 200, 13 },
1207 { 220, 14 },
1208 { 240, 15 },
f1c0a02f
MB		 1209 { 300, 17 },
1210 { 320, 18 },
1211 { 440, 19 },
1212 { 480, 20 },
1213};
1214
1215/* Sample rates for DSP */
1216static struct {
1217 int rate;
1218 int value;
1219} sample_rates[] = {
1220 { 8000, 0 },
1221 { 11025, 1 },
1222 { 12000, 2 },
1223 { 16000, 3 },
1224 { 22050, 4 },
1225 { 24000, 5 },
1226 { 32000, 6 },
1227 { 44100, 7 },
1228 { 48000, 8 },
1229 { 88200, 9 },
1230 { 96000, 10 },
1231 { 0, 0 },
1232};
1233
dee89c4d
MB		 1234static int wm8903_startup(struct snd_pcm_substream *substream,
1235 struct snd_soc_dai *dai)
f1c0a02f
MB		 1236{
1237 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1238 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1239 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1240 struct snd_pcm_runtime *master_runtime;
1241
1242 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1243 wm8903->playback_active++;
1244 else
1245 wm8903->capture_active++;
1246
1247 /* The DAI has shared clocks so if we already have a playback or
1248 * capture going then constrain this substream to match it.
1249 */
1250 if (wm8903->master_substream) {
1251 master_runtime = wm8903->master_substream->runtime;
1252
f0fba2ad 1253 dev_dbg(codec->dev, "Constraining to %d bits\n",
727fb909 1254 master_runtime->sample_bits);
f1c0a02f
MB		 1255
1256 snd_pcm_hw_constraint_minmax(substream->runtime,
1257 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1258 master_runtime->sample_bits,
1259 master_runtime->sample_bits);
1260
1261 wm8903->slave_substream = substream;
1262 } else
1263 wm8903->master_substream = substream;
1264
1265 return 0;
1266}
1267
dee89c4d
MB		 1268static void wm8903_shutdown(struct snd_pcm_substream *substream,
1269 struct snd_soc_dai *dai)
f1c0a02f
MB		 1270{
1271 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1272 struct snd_soc_codec *codec = rtd->codec;
b2c812e2 1273 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1274
1275 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1276 wm8903->playback_active--;
1277 else
1278 wm8903->capture_active--;
1279
1280 if (wm8903->master_substream == substream)
1281 wm8903->master_substream = wm8903->slave_substream;
1282
1283 wm8903->slave_substream = NULL;
1284}
1285
1286static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1287 struct snd_pcm_hw_params *params,
1288 struct snd_soc_dai *dai)
f1c0a02f
MB		 1289{
1290 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1291 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1292 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1293 int fs = params_rate(params);
1294 int bclk;
1295 int bclk_div;
1296 int i;
1297 int dsp_config;
1298 int clk_config;
1299 int best_val;
1300 int cur_val;
1301 int clk_sys;
1302
8d50e447
MB		 1303 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1304 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1305 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1306 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1307 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1308 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1309
1310 if (substream == wm8903->slave_substream) {
f0fba2ad 1311 dev_dbg(codec->dev, "Ignoring hw_params for slave substream\n");
f1c0a02f
MB		 1312 return 0;
1313 }
1314
9e79261f
MB		 1315 /* Enable sloping stopband filter for low sample rates */
1316 if (fs <= 24000)
1317 dac_digital1 |= WM8903_DAC_SB_FILT;
1318 else
1319 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1320
f1c0a02f
MB		 1321 /* Configure sample rate logic for DSP - choose nearest rate */
1322 dsp_config = 0;
1323 best_val = abs(sample_rates[dsp_config].rate - fs);
1324 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1325 cur_val = abs(sample_rates[i].rate - fs);
1326 if (cur_val <= best_val) {
1327 dsp_config = i;
1328 best_val = cur_val;
1329 }
1330 }
1331
1332 /* Constraints should stop us hitting this but let's make sure */
1333 if (wm8903->capture_active)
1334 switch (sample_rates[dsp_config].rate) {
1335 case 88200:
1336 case 96000:
f0fba2ad 1337 dev_err(codec->dev, "%dHz unsupported by ADC\n",
f1c0a02f
MB		 1338 fs);
1339 return -EINVAL;
1340
1341 default:
1342 break;
1343 }
1344
f0fba2ad 1345 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1346 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1347 clock1 |= sample_rates[dsp_config].value;
1348
1349 aif1 &= ~WM8903_AIF_WL_MASK;
1350 bclk = 2 * fs;
1351 switch (params_format(params)) {
1352 case SNDRV_PCM_FORMAT_S16_LE:
1353 bclk *= 16;
1354 break;
1355 case SNDRV_PCM_FORMAT_S20_3LE:
1356 bclk *= 20;
1357 aif1 |= 0x4;
1358 break;
1359 case SNDRV_PCM_FORMAT_S24_LE:
1360 bclk *= 24;
1361 aif1 |= 0x8;
1362 break;
1363 case SNDRV_PCM_FORMAT_S32_LE:
1364 bclk *= 32;
1365 aif1 |= 0xc;
1366 break;
1367 default:
1368 return -EINVAL;
1369 }
1370
f0fba2ad 1371 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1372 wm8903->sysclk, fs);
1373
1374 /* We may not have an MCLK which allows us to generate exactly
1375 * the clock we want, particularly with USB derived inputs, so
1376 * approximate.
1377 */
1378 clk_config = 0;
1379 best_val = abs((wm8903->sysclk /
1380 (clk_sys_ratios[0].mclk_div *
1381 clk_sys_ratios[0].div)) - fs);
1382 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1383 cur_val = abs((wm8903->sysclk /
1384 (clk_sys_ratios[i].mclk_div *
1385 clk_sys_ratios[i].div)) - fs);
1386
1387 if (cur_val <= best_val) {
1388 clk_config = i;
1389 best_val = cur_val;
1390 }
1391 }
1392
1393 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1394 clock0 |= WM8903_MCLKDIV2;
1395 clk_sys = wm8903->sysclk / 2;
1396 } else {
1397 clock0 &= ~WM8903_MCLKDIV2;
1398 clk_sys = wm8903->sysclk;
1399 }
1400
1401 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1402 WM8903_CLK_SYS_MODE_MASK);
1403 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1404 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1405
f0fba2ad 1406 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1407 clk_sys_ratios[clk_config].rate,
1408 clk_sys_ratios[clk_config].mode,
1409 clk_sys_ratios[clk_config].div);
1410
f0fba2ad 1411 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1412
1413 /* We may not get quite the right frequency if using
1414 * approximate clocks so look for the closest match that is
1415 * higher than the target (we need to ensure that there enough
1416 * BCLKs to clock out the samples).
1417 */
1418 bclk_div = 0;
1419 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1420 i = 1;
1421 while (i < ARRAY_SIZE(bclk_divs)) {
1422 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1423 if (cur_val < 0) /* BCLK table is sorted */
1424 break;
1425 bclk_div = i;
1426 best_val = cur_val;
1427 i++;
1428 }
1429
1430 aif2 &= ~WM8903_BCLK_DIV_MASK;
1431 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1432
f0fba2ad 1433 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1434 bclk_divs[bclk_div].ratio / 10, bclk,
1435 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1436
1437 aif2 |= bclk_divs[bclk_div].div;
1438 aif3 |= bclk / fs;
1439
8d50e447
MB		 1440 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1441 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1442 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1443 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1444 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1445 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1446
1447 return 0;
1448}
1449
7245387e
MB		 1450/**
1451 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1452 *
1453 * @codec: WM8903 codec
1454 * @jack: jack to report detection events on
1455 * @det: value to report for presence detection
1456 * @shrt: value to report for short detection
1457 *
1458 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1459 * being used to bring out signals to the processor then only platform
1460 * data configuration is needed for WM8903 and processor GPIOs should
1461 * be configured using snd_soc_jack_add_gpios() instead.
1462 *
1463 * The current threasholds for detection should be configured using
1464 * micdet_cfg in the platform data. Using this function will force on
1465 * the microphone bias for the device.
1466 */
1467int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1468 int det, int shrt)
1469{
b2c812e2 1470 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1471 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1472
1473 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1474 det, shrt);
1475
1476 /* Store the configuration */
1477 wm8903->mic_jack = jack;
1478 wm8903->mic_det = det;
1479 wm8903->mic_short = shrt;
1480
1481 /* Enable interrupts we've got a report configured for */
1482 if (det)
1483 irq_mask &= ~WM8903_MICDET_EINT;
1484 if (shrt)
1485 irq_mask &= ~WM8903_MICSHRT_EINT;
1486
1487 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1488 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1489 irq_mask);
1490
69266866
MB		 1491 if (det && shrt) {
1492 /* Enable mic detection, this may not have been set through
1493 * platform data (eg, if the defaults are OK). */
1494 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1495 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1496 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1497 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1498 } else {
1499 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1500 WM8903_MICDET_ENA, 0);
1501 }
7245387e
MB		 1502
1503 return 0;
1504}
1505EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1506
8abd16a6
MB		 1507static irqreturn_t wm8903_irq(int irq, void *data)
1508{
f0fba2ad
LG		 1509 struct snd_soc_codec *codec = data;
1510 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1511 int mic_report;
1512 int int_pol;
1513 int int_val = 0;
1514 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1515
7245387e 1516 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1517
7245387e 1518 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1519 dev_dbg(codec->dev, "Write sequencer done\n");
1520 complete(&wm8903->wseq);
1521 }
1522
7245387e
MB		 1523 /*
1524 * The rest is microphone jack detection. We need to manually
1525 * invert the polarity of the interrupt after each event - to
1526 * simplify the code keep track of the last state we reported
1527 * and just invert the relevant bits in both the report and
1528 * the polarity register.
1529 */
1530 mic_report = wm8903->mic_last_report;
1531 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1532
1533 if (int_val & WM8903_MICSHRT_EINT) {
1534 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1535
1536 mic_report ^= wm8903->mic_short;
1537 int_pol ^= WM8903_MICSHRT_INV;
1538 }
1539
1540 if (int_val & WM8903_MICDET_EINT) {
1541 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1542
1543 mic_report ^= wm8903->mic_det;
1544 int_pol ^= WM8903_MICDET_INV;
1545
1546 msleep(wm8903->mic_delay);
1547 }
1548
1549 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1550 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1551
1552 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1553 wm8903->mic_short | wm8903->mic_det);
1554
1555 wm8903->mic_last_report = mic_report;
1556
8abd16a6
MB		 1557 return IRQ_HANDLED;
1558}
1559
f1c0a02f
MB		 1560#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1561 SNDRV_PCM_RATE_11025 | \
1562 SNDRV_PCM_RATE_16000 | \
1563 SNDRV_PCM_RATE_22050 | \
1564 SNDRV_PCM_RATE_32000 | \
1565 SNDRV_PCM_RATE_44100 | \
1566 SNDRV_PCM_RATE_48000 | \
1567 SNDRV_PCM_RATE_88200 | \
1568 SNDRV_PCM_RATE_96000)
1569
1570#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1571 SNDRV_PCM_RATE_11025 | \
1572 SNDRV_PCM_RATE_16000 | \
1573 SNDRV_PCM_RATE_22050 | \
1574 SNDRV_PCM_RATE_32000 | \
1575 SNDRV_PCM_RATE_44100 | \
1576 SNDRV_PCM_RATE_48000)
1577
1578#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1579 SNDRV_PCM_FMTBIT_S20_3LE |\
1580 SNDRV_PCM_FMTBIT_S24_LE)
1581
6335d055
EM		 1582static struct snd_soc_dai_ops wm8903_dai_ops = {
1583 .startup = wm8903_startup,
1584 .shutdown = wm8903_shutdown,
1585 .hw_params = wm8903_hw_params,
1586 .digital_mute = wm8903_digital_mute,
1587 .set_fmt = wm8903_set_dai_fmt,
1588 .set_sysclk = wm8903_set_dai_sysclk,
1589};
1590
f0fba2ad
LG		 1591static struct snd_soc_dai_driver wm8903_dai = {
1592 .name = "wm8903-hifi",
f1c0a02f
MB		 1593 .playback = {
1594 .stream_name = "Playback",
1595 .channels_min = 2,
1596 .channels_max = 2,
1597 .rates = WM8903_PLAYBACK_RATES,
1598 .formats = WM8903_FORMATS,
1599 },
1600 .capture = {
1601 .stream_name = "Capture",
1602 .channels_min = 2,
1603 .channels_max = 2,
1604 .rates = WM8903_CAPTURE_RATES,
1605 .formats = WM8903_FORMATS,
1606 },
6335d055 1607 .ops = &wm8903_dai_ops,
0d960e88 1608 .symmetric_rates = 1,
f1c0a02f 1609};
f1c0a02f 1610
f0fba2ad 1611static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1612{
f1c0a02f
MB		 1613 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1614
1615 return 0;
1616}
1617
f0fba2ad 1618static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1619{
f1c0a02f
MB		 1620 int i;
1621 u16 *reg_cache = codec->reg_cache;
40aa7030 1622 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1623 GFP_KERNEL);
1624
1625 /* Bring the codec back up to standby first to minimise pop/clicks */
1626 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1627
1628 /* Sync back everything else */
1629 if (tmp_cache) {
1630 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1631 if (tmp_cache[i] != reg_cache[i])
8d50e447 1632 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1633 kfree(tmp_cache);
f1c0a02f 1634 } else {
f0fba2ad 1635 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1636 }
1637
1638 return 0;
1639}
1640
f0fba2ad 1641static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1642{
f0fba2ad
LG		 1643 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1644 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1645 int ret, i;
8abd16a6 1646 int trigger, irq_pol;
f1c0a02f
MB		 1647 u16 val;
1648
8abd16a6 1649 init_completion(&wm8903->wseq);
d58d5d55 1650
8d50e447
MB		 1651 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1652 if (ret != 0) {
f0fba2ad
LG		 1653 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1654 return ret;
8d50e447
MB		 1655 }
1656
1657 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1658 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1659 dev_err(codec->dev,
d58d5d55
MB		 1660 "Device with ID register %x is not a WM8903\n", val);
1661 return -ENODEV;
f1c0a02f
MB		 1662 }
1663
8d50e447 1664 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
f0fba2ad 1665 dev_info(codec->dev, "WM8903 revision %d\n",
f1c0a02f
MB		 1666 val & WM8903_CHIP_REV_MASK);
1667
1668 wm8903_reset(codec);
1669
37f88e84 1670 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1671 if (pdata) {
1672 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1673 if (!pdata->gpio_cfg[i])
1674 continue;
1675
1676 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1677 pdata->gpio_cfg[i] & 0xffff);
1678 }
37f88e84
MB		 1679
1680 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1681 pdata->micdet_cfg);
1682
1683 /* Microphone detection needs the WSEQ clock */
1684 if (pdata->micdet_cfg)
1685 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1686 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1687
1688 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1689 }
8abd16a6 1690
f0fba2ad 1691 if (wm8903->irq) {
8abd16a6
MB		 1692 if (pdata && pdata->irq_active_low) {
1693 trigger = IRQF_TRIGGER_LOW;
1694 irq_pol = WM8903_IRQ_POL;
1695 } else {
1696 trigger = IRQF_TRIGGER_HIGH;
1697 irq_pol = 0;
1698 }
1699
1700 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1701 WM8903_IRQ_POL, irq_pol);
1702
f0fba2ad 1703 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1704 trigger | IRQF_ONESHOT,
f0fba2ad 1705 "wm8903", codec);
8abd16a6 1706 if (ret != 0) {
f0fba2ad 1707 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1708 ret);
f0fba2ad 1709 return ret;
8abd16a6
MB		 1710 }
1711
1712 /* Enable write sequencer interrupts */
1713 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1714 WM8903_IM_WSEQ_BUSY_EINT, 0);
1715 }
73b34ead 1716
f1c0a02f
MB		 1717 /* power on device */
1718 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1719
1720 /* Latch volume update bits */
8d50e447 1721 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1722 val |= WM8903_ADCVU;
8d50e447
MB		 1723 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1724 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1725
8d50e447 1726 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1727 val |= WM8903_DACVU;
8d50e447
MB		 1728 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1729 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1730
8d50e447 1731 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1732 val |= WM8903_HPOUTVU;
8d50e447
MB		 1733 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1734 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1735
8d50e447 1736 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1737 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1738 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1739 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1740
8d50e447 1741 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1742 val |= WM8903_SPKVU;
8d50e447
MB		 1743 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1744 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1745
1746 /* Enable DAC soft mute by default */
8d50e447 1747 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1748 val |= WM8903_DAC_MUTEMODE;
8d50e447 1749 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1750
f0fba2ad
LG		 1751 snd_soc_add_controls(codec, wm8903_snd_controls,
1752 ARRAY_SIZE(wm8903_snd_controls));
1753 wm8903_add_widgets(codec);
f1c0a02f 1754
f1c0a02f
MB		 1755 return ret;
1756}
1757
f0fba2ad
LG		 1758/* power down chip */
1759static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1760{
f0fba2ad
LG		 1761 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1762 return 0;
1763}
f1c0a02f 1764
f0fba2ad
LG		 1765static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1766 .probe = wm8903_probe,
1767 .remove = wm8903_remove,
1768 .suspend = wm8903_suspend,
1769 .resume = wm8903_resume,
1770 .set_bias_level = wm8903_set_bias_level,
1771 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1772 .reg_word_size = sizeof(u16),
1773 .reg_cache_default = wm8903_reg_defaults,
1774 .volatile_register = wm8903_volatile_register,
1775};
f1c0a02f 1776
f0fba2ad
LG		 1777#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1778static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1779 const struct i2c_device_id *id)
1780{
1781 struct wm8903_priv *wm8903;
1782 int ret;
f1c0a02f 1783
f0fba2ad
LG		 1784 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1785 if (wm8903 == NULL)
1786 return -ENOMEM;
8abd16a6 1787
f0fba2ad 1788 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 1789 wm8903->irq = i2c->irq;
d58d5d55 1790
f0fba2ad
LG		 1791 ret = snd_soc_register_codec(&i2c->dev,
1792 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1793 if (ret < 0)
1794 kfree(wm8903);
1795 return ret;
1796}
f1c0a02f 1797
f0fba2ad
LG		 1798static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1799{
1800 snd_soc_unregister_codec(&client->dev);
1801 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 1802 return 0;
1803}
1804
f1c0a02f 1805static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 1806 { "wm8903", 0 },
1807 { }
f1c0a02f
MB		 1808};
1809MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1810
1811static struct i2c_driver wm8903_i2c_driver = {
1812 .driver = {
f0fba2ad 1813 .name = "wm8903-codec",
f1c0a02f
MB		 1814 .owner = THIS_MODULE,
1815 },
f0fba2ad
LG		 1816 .probe = wm8903_i2c_probe,
1817 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1818 .id_table = wm8903_i2c_id,
1819};
f0fba2ad 1820#endif
f1c0a02f 1821
f0fba2ad 1822static int __init wm8903_modinit(void)
f1c0a02f 1823{
f1c0a02f 1824 int ret = 0;
f0fba2ad
LG		 1825#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1826 ret = i2c_add_driver(&wm8903_i2c_driver);
1827 if (ret != 0) {
1828 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1829 ret);
f1c0a02f 1830 }
f0fba2ad 1831#endif
f1c0a02f 1832 return ret;
64089b84
MB		 1833}
1834module_init(wm8903_modinit);
1835
1836static void __exit wm8903_exit(void)
1837{
f0fba2ad 1838#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 1839 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 1840#endif
64089b84
MB		 1841}
1842module_exit(wm8903_exit);
1843
f1c0a02f
MB		 1844MODULE_DESCRIPTION("ASoC WM8903 driver");
1845MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1846MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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