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ASoC: Convert CODEC drivers to module_platform_driver
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
5a0e3ad6 26#include <linux/slab.h>
f1c0a02f 27#include <sound/core.h>
7245387e 28#include <sound/jack.h>
f1c0a02f
MB		 29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/tlv.h>
32#include <sound/soc.h>
f1c0a02f 33#include <sound/initval.h>
8abd16a6 34#include <sound/wm8903.h>
2bbb5d66 35#include <trace/events/asoc.h>
f1c0a02f
MB		 36
37#include "wm8903.h"
38
f1c0a02f
MB		 39/* Register defaults at reset */
40static u16 wm8903_reg_defaults[] = {
41 0x8903, /* R0 - SW Reset and ID */
42 0x0000, /* R1 - Revision Number */
43 0x0000, /* R2 */
44 0x0000, /* R3 */
45 0x0018, /* R4 - Bias Control 0 */
46 0x0000, /* R5 - VMID Control 0 */
47 0x0000, /* R6 - Mic Bias Control 0 */
48 0x0000, /* R7 */
49 0x0001, /* R8 - Analogue DAC 0 */
50 0x0000, /* R9 */
51 0x0001, /* R10 - Analogue ADC 0 */
52 0x0000, /* R11 */
53 0x0000, /* R12 - Power Management 0 */
54 0x0000, /* R13 - Power Management 1 */
55 0x0000, /* R14 - Power Management 2 */
56 0x0000, /* R15 - Power Management 3 */
57 0x0000, /* R16 - Power Management 4 */
58 0x0000, /* R17 - Power Management 5 */
59 0x0000, /* R18 - Power Management 6 */
60 0x0000, /* R19 */
61 0x0400, /* R20 - Clock Rates 0 */
62 0x0D07, /* R21 - Clock Rates 1 */
63 0x0000, /* R22 - Clock Rates 2 */
64 0x0000, /* R23 */
65 0x0050, /* R24 - Audio Interface 0 */
66 0x0242, /* R25 - Audio Interface 1 */
67 0x0008, /* R26 - Audio Interface 2 */
68 0x0022, /* R27 - Audio Interface 3 */
69 0x0000, /* R28 */
70 0x0000, /* R29 */
71 0x00C0, /* R30 - DAC Digital Volume Left */
72 0x00C0, /* R31 - DAC Digital Volume Right */
73 0x0000, /* R32 - DAC Digital 0 */
74 0x0000, /* R33 - DAC Digital 1 */
75 0x0000, /* R34 */
76 0x0000, /* R35 */
77 0x00C0, /* R36 - ADC Digital Volume Left */
78 0x00C0, /* R37 - ADC Digital Volume Right */
79 0x0000, /* R38 - ADC Digital 0 */
80 0x0073, /* R39 - Digital Microphone 0 */
81 0x09BF, /* R40 - DRC 0 */
82 0x3241, /* R41 - DRC 1 */
83 0x0020, /* R42 - DRC 2 */
84 0x0000, /* R43 - DRC 3 */
85 0x0085, /* R44 - Analogue Left Input 0 */
86 0x0085, /* R45 - Analogue Right Input 0 */
87 0x0044, /* R46 - Analogue Left Input 1 */
88 0x0044, /* R47 - Analogue Right Input 1 */
89 0x0000, /* R48 */
90 0x0000, /* R49 */
91 0x0008, /* R50 - Analogue Left Mix 0 */
92 0x0004, /* R51 - Analogue Right Mix 0 */
93 0x0000, /* R52 - Analogue Spk Mix Left 0 */
94 0x0000, /* R53 - Analogue Spk Mix Left 1 */
95 0x0000, /* R54 - Analogue Spk Mix Right 0 */
96 0x0000, /* R55 - Analogue Spk Mix Right 1 */
97 0x0000, /* R56 */
98 0x002D, /* R57 - Analogue OUT1 Left */
99 0x002D, /* R58 - Analogue OUT1 Right */
100 0x0039, /* R59 - Analogue OUT2 Left */
101 0x0039, /* R60 - Analogue OUT2 Right */
102 0x0100, /* R61 */
103 0x0139, /* R62 - Analogue OUT3 Left */
104 0x0139, /* R63 - Analogue OUT3 Right */
105 0x0000, /* R64 */
106 0x0000, /* R65 - Analogue SPK Output Control 0 */
107 0x0000, /* R66 */
108 0x0010, /* R67 - DC Servo 0 */
109 0x0100, /* R68 */
110 0x00A4, /* R69 - DC Servo 2 */
111 0x0807, /* R70 */
112 0x0000, /* R71 */
113 0x0000, /* R72 */
114 0x0000, /* R73 */
115 0x0000, /* R74 */
116 0x0000, /* R75 */
117 0x0000, /* R76 */
118 0x0000, /* R77 */
119 0x0000, /* R78 */
120 0x000E, /* R79 */
121 0x0000, /* R80 */
122 0x0000, /* R81 */
123 0x0000, /* R82 */
124 0x0000, /* R83 */
125 0x0000, /* R84 */
126 0x0000, /* R85 */
127 0x0000, /* R86 */
128 0x0006, /* R87 */
129 0x0000, /* R88 */
130 0x0000, /* R89 */
131 0x0000, /* R90 - Analogue HP 0 */
132 0x0060, /* R91 */
133 0x0000, /* R92 */
134 0x0000, /* R93 */
135 0x0000, /* R94 - Analogue Lineout 0 */
136 0x0060, /* R95 */
137 0x0000, /* R96 */
138 0x0000, /* R97 */
139 0x0000, /* R98 - Charge Pump 0 */
140 0x1F25, /* R99 */
141 0x2B19, /* R100 */
142 0x01C0, /* R101 */
143 0x01EF, /* R102 */
144 0x2B00, /* R103 */
145 0x0000, /* R104 - Class W 0 */
146 0x01C0, /* R105 */
147 0x1C10, /* R106 */
148 0x0000, /* R107 */
149 0x0000, /* R108 - Write Sequencer 0 */
150 0x0000, /* R109 - Write Sequencer 1 */
151 0x0000, /* R110 - Write Sequencer 2 */
152 0x0000, /* R111 - Write Sequencer 3 */
153 0x0000, /* R112 - Write Sequencer 4 */
154 0x0000, /* R113 */
155 0x0000, /* R114 - Control Interface */
156 0x0000, /* R115 */
157 0x00A8, /* R116 - GPIO Control 1 */
158 0x00A8, /* R117 - GPIO Control 2 */
159 0x00A8, /* R118 - GPIO Control 3 */
160 0x0220, /* R119 - GPIO Control 4 */
161 0x01A0, /* R120 - GPIO Control 5 */
162 0x0000, /* R121 - Interrupt Status 1 */
163 0xFFFF, /* R122 - Interrupt Status 1 Mask */
164 0x0000, /* R123 - Interrupt Polarity 1 */
165 0x0000, /* R124 */
166 0x0003, /* R125 */
167 0x0000, /* R126 - Interrupt Control */
168 0x0000, /* R127 */
169 0x0005, /* R128 */
170 0x0000, /* R129 - Control Interface Test 1 */
171 0x0000, /* R130 */
172 0x0000, /* R131 */
173 0x0000, /* R132 */
174 0x0000, /* R133 */
175 0x0000, /* R134 */
176 0x03FF, /* R135 */
177 0x0007, /* R136 */
178 0x0040, /* R137 */
179 0x0000, /* R138 */
180 0x0000, /* R139 */
181 0x0000, /* R140 */
182 0x0000, /* R141 */
183 0x0000, /* R142 */
184 0x0000, /* R143 */
185 0x0000, /* R144 */
186 0x0000, /* R145 */
187 0x0000, /* R146 */
188 0x0000, /* R147 */
189 0x4000, /* R148 */
190 0x6810, /* R149 - Charge Pump Test 1 */
191 0x0004, /* R150 */
192 0x0000, /* R151 */
193 0x0000, /* R152 */
194 0x0000, /* R153 */
195 0x0000, /* R154 */
196 0x0000, /* R155 */
197 0x0000, /* R156 */
198 0x0000, /* R157 */
199 0x0000, /* R158 */
200 0x0000, /* R159 */
201 0x0000, /* R160 */
202 0x0000, /* R161 */
203 0x0000, /* R162 */
204 0x0000, /* R163 */
205 0x0028, /* R164 - Clock Rate Test 4 */
206 0x0004, /* R165 */
207 0x0000, /* R166 */
208 0x0060, /* R167 */
209 0x0000, /* R168 */
210 0x0000, /* R169 */
211 0x0000, /* R170 */
212 0x0000, /* R171 */
213 0x0000, /* R172 - Analogue Output Bias 0 */
214};
215
d58d5d55 216struct wm8903_priv {
7cfe5617 217 struct snd_soc_codec *codec;
f0fba2ad 218
d58d5d55 219 int sysclk;
f0fba2ad 220 int irq;
d58d5d55 221
69fff9bb
MB		 222 int fs;
223 int deemph;
224
c5b6a9fe
MB		 225 int dcs_pending;
226 int dcs_cache[4];
227
f2c1fe09 228 /* Reference count */
d58d5d55 229 int class_w_users;
d58d5d55 230
7245387e
MB		 231 struct snd_soc_jack *mic_jack;
232 int mic_det;
233 int mic_short;
234 int mic_last_report;
235 int mic_delay;
7cfe5617
SW		 236
237#ifdef CONFIG_GPIOLIB
238 struct gpio_chip gpio_chip;
239#endif
d58d5d55
MB		 240};
241
d4754ec9 242static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 243{
244 switch (reg) {
245 case WM8903_SW_RESET_AND_ID:
246 case WM8903_REVISION_NUMBER:
247 case WM8903_INTERRUPT_STATUS_1:
248 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 249 case WM8903_DC_SERVO_READBACK_1:
250 case WM8903_DC_SERVO_READBACK_2:
251 case WM8903_DC_SERVO_READBACK_3:
252 case WM8903_DC_SERVO_READBACK_4:
8d50e447 253 return 1;
f1c0a02f
MB		 254
255 default:
f1c0a02f 256 return 0;
8d50e447 257 }
f1c0a02f
MB		 258}
259
f1c0a02f
MB		 260static void wm8903_reset(struct snd_soc_codec *codec)
261{
8d50e447 262 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 263 memcpy(codec->reg_cache, wm8903_reg_defaults,
264 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 265}
266
42768a12
MB		 267static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
268 struct snd_kcontrol *kcontrol, int event)
269{
270 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
271 mdelay(4);
272
273 return 0;
274}
275
c5b6a9fe
MB		 276static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
277 struct snd_kcontrol *kcontrol, int event)
278{
279 struct snd_soc_codec *codec = w->codec;
280 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
281
282 switch (event) {
283 case SND_SOC_DAPM_POST_PMU:
284 wm8903->dcs_pending |= 1 << w->shift;
285 break;
286 case SND_SOC_DAPM_PRE_PMD:
287 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
288 1 << w->shift, 0);
289 break;
290 }
291
292 return 0;
293}
294
295#define WM8903_DCS_MODE_WRITE_STOP 0
296#define WM8903_DCS_MODE_START_STOP 2
297
298static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
299 enum snd_soc_dapm_type event, int subseq)
300{
301 struct snd_soc_codec *codec = container_of(dapm,
302 struct snd_soc_codec, dapm);
303 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
304 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
305 int i, val;
306
307 /* Complete any pending DC servo starts */
308 if (wm8903->dcs_pending) {
309 dev_dbg(codec->dev, "Starting DC servo for %x\n",
310 wm8903->dcs_pending);
311
312 /* If we've no cached values then we need to do startup */
313 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
314 if (!(wm8903->dcs_pending & (1 << i)))
315 continue;
316
317 if (wm8903->dcs_cache[i]) {
318 dev_dbg(codec->dev,
319 "Restore DC servo %d value %x\n",
320 3 - i, wm8903->dcs_cache[i]);
321
322 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
323 wm8903->dcs_cache[i] & 0xff);
324 } else {
325 dev_dbg(codec->dev,
326 "Calibrate DC servo %d\n", 3 - i);
327 dcs_mode = WM8903_DCS_MODE_START_STOP;
328 }
329 }
330
331 /* Don't trust the cache for analogue */
332 if (wm8903->class_w_users)
333 dcs_mode = WM8903_DCS_MODE_START_STOP;
334
335 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
336 WM8903_DCS_MODE_MASK, dcs_mode);
337
338 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
339 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
340
341 switch (dcs_mode) {
342 case WM8903_DCS_MODE_WRITE_STOP:
343 break;
344
345 case WM8903_DCS_MODE_START_STOP:
346 msleep(270);
347
348 /* Cache the measured offsets for digital */
349 if (wm8903->class_w_users)
350 break;
351
352 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
353 if (!(wm8903->dcs_pending & (1 << i)))
354 continue;
355
356 val = snd_soc_read(codec,
357 WM8903_DC_SERVO_READBACK_1 + i);
358 dev_dbg(codec->dev, "DC servo %d: %x\n",
359 3 - i, val);
360 wm8903->dcs_cache[i] = val;
361 }
362 break;
363
364 default:
365 pr_warn("DCS mode %d delay not set\n", dcs_mode);
366 break;
367 }
368
369 wm8903->dcs_pending = 0;
370 }
371}
372
f1c0a02f
MB		 373/*
374 * When used with DAC outputs only the WM8903 charge pump supports
375 * operation in class W mode, providing very low power consumption
376 * when used with digital sources. Enable and disable this mode
377 * automatically depending on the mixer configuration.
378 *
379 * All the relevant controls are simple switches.
380 */
381static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
382 struct snd_ctl_elem_value *ucontrol)
383{
9d03545d
JN		 384 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
385 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
f1c0a02f 386 struct snd_soc_codec *codec = widget->codec;
b2c812e2 387 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 388 u16 reg;
389 int ret;
390
8d50e447 391 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 392
393 /* Turn it off if we're about to enable bypass */
394 if (ucontrol->value.integer.value[0]) {
395 if (wm8903->class_w_users == 0) {
f0fba2ad 396 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 397 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 398 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
399 }
400 wm8903->class_w_users++;
401 }
402
403 /* Implement the change */
404 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
405
406 /* If we've just disabled the last bypass path turn Class W on */
407 if (!ucontrol->value.integer.value[0]) {
408 if (wm8903->class_w_users == 1) {
f0fba2ad 409 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 410 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 411 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
412 }
413 wm8903->class_w_users--;
414 }
415
f0fba2ad 416 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 417 wm8903->class_w_users);
418
419 return ret;
420}
421
422#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
423{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
424 .info = snd_soc_info_volsw, \
425 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
426 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
427
428
69fff9bb
MB		 429static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
430
431static int wm8903_set_deemph(struct snd_soc_codec *codec)
432{
433 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
434 int val, i, best;
435
436 /* If we're using deemphasis select the nearest available sample
437 * rate.
438 */
439 if (wm8903->deemph) {
440 best = 1;
441 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
442 if (abs(wm8903_deemph[i] - wm8903->fs) <
443 abs(wm8903_deemph[best] - wm8903->fs))
444 best = i;
445 }
446
447 val = best << WM8903_DEEMPH_SHIFT;
448 } else {
449 best = 0;
450 val = 0;
451 }
452
453 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
454 best, wm8903_deemph[best]);
455
456 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
457 WM8903_DEEMPH_MASK, val);
458}
459
460static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
461 struct snd_ctl_elem_value *ucontrol)
462{
463 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
464 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
465
466 ucontrol->value.enumerated.item[0] = wm8903->deemph;
467
468 return 0;
469}
470
471static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
472 struct snd_ctl_elem_value *ucontrol)
473{
474 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
475 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
476 int deemph = ucontrol->value.enumerated.item[0];
477 int ret = 0;
478
479 if (deemph > 1)
480 return -EINVAL;
481
482 mutex_lock(&codec->mutex);
483 if (wm8903->deemph != deemph) {
484 wm8903->deemph = deemph;
485
486 wm8903_set_deemph(codec);
487
488 ret = 1;
489 }
490 mutex_unlock(&codec->mutex);
491
492 return ret;
493}
494
f1c0a02f
MB		 495/* ALSA can only do steps of .01dB */
496static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
497
291ce18c 498static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 499static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
500
501static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
502static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
503static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
504static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
505static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
506
460f4aae
MB		 507static const char *hpf_mode_text[] = {
508 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
509};
510
511static const struct soc_enum hpf_mode =
512 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
513
dcf9ada3
MB		 514static const char *osr_text[] = {
515 "Low power", "High performance"
516};
517
518static const struct soc_enum adc_osr =
519 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
520
521static const struct soc_enum dac_osr =
522 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
523
f1c0a02f
MB		 524static const char *drc_slope_text[] = {
525 "1", "1/2", "1/4", "1/8", "1/16", "0"
526};
527
528static const struct soc_enum drc_slope_r0 =
529 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
530
531static const struct soc_enum drc_slope_r1 =
532 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
533
534static const char *drc_attack_text[] = {
535 "instantaneous",
536 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
537 "46.4ms", "92.8ms", "185.6ms"
538};
539
540static const struct soc_enum drc_attack =
541 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
542
543static const char *drc_decay_text[] = {
544 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
545 "23.87s", "47.56s"
546};
547
548static const struct soc_enum drc_decay =
549 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
550
551static const char *drc_ff_delay_text[] = {
552 "5 samples", "9 samples"
553};
554
555static const struct soc_enum drc_ff_delay =
556 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
557
558static const char *drc_qr_decay_text[] = {
559 "0.725ms", "1.45ms", "5.8ms"
560};
561
562static const struct soc_enum drc_qr_decay =
563 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
564
565static const char *drc_smoothing_text[] = {
566 "Low", "Medium", "High"
567};
568
569static const struct soc_enum drc_smoothing =
570 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
571
572static const char *soft_mute_text[] = {
573 "Fast (fs/2)", "Slow (fs/32)"
574};
575
576static const struct soc_enum soft_mute =
577 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
578
579static const char *mute_mode_text[] = {
580 "Hard", "Soft"
581};
582
583static const struct soc_enum mute_mode =
584 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
585
f1c0a02f
MB		 586static const char *companding_text[] = {
587 "ulaw", "alaw"
588};
589
590static const struct soc_enum dac_companding =
591 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
592
593static const struct soc_enum adc_companding =
594 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
595
596static const char *input_mode_text[] = {
597 "Single-Ended", "Differential Line", "Differential Mic"
598};
599
600static const struct soc_enum linput_mode_enum =
601 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
602
603static const struct soc_enum rinput_mode_enum =
604 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
605
606static const char *linput_mux_text[] = {
607 "IN1L", "IN2L", "IN3L"
608};
609
610static const struct soc_enum linput_enum =
611 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
612
613static const struct soc_enum linput_inv_enum =
614 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
615
616static const char *rinput_mux_text[] = {
617 "IN1R", "IN2R", "IN3R"
618};
619
620static const struct soc_enum rinput_enum =
621 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
622
623static const struct soc_enum rinput_inv_enum =
624 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
625
626
291ce18c
MB		 627static const char *sidetone_text[] = {
628 "None", "Left", "Right"
629};
630
631static const struct soc_enum lsidetone_enum =
632 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
633
634static const struct soc_enum rsidetone_enum =
635 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
636
97945c46
SW		 637static const char *adcinput_text[] = {
638 "ADC", "DMIC"
639};
640
641static const struct soc_enum adcinput_enum =
642 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text);
643
1e113bf9
MB		 644static const char *aif_text[] = {
645 "Left", "Right"
646};
647
648static const struct soc_enum lcapture_enum =
649 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
650
651static const struct soc_enum rcapture_enum =
652 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
653
654static const struct soc_enum lplay_enum =
655 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
656
657static const struct soc_enum rplay_enum =
658 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
659
f1c0a02f
MB		 660static const struct snd_kcontrol_new wm8903_snd_controls[] = {
661
662/* Input PGAs - No TLV since the scale depends on PGA mode */
663SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 664 7, 1, 1),
f1c0a02f
MB		 665SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
666 0, 31, 0),
667SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
668 6, 1, 0),
669
670SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 671 7, 1, 1),
f1c0a02f
MB		 672SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
673 0, 31, 0),
674SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
675 6, 1, 0),
676
677/* ADCs */
dcf9ada3 678SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 679SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
680SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 681SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
682SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
683SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 684SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 685 drc_tlv_thresh),
686SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
687SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
688SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
689SOC_ENUM("DRC Attack Rate", drc_attack),
690SOC_ENUM("DRC Decay Rate", drc_decay),
691SOC_ENUM("DRC FF Delay", drc_ff_delay),
692SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
693SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 694SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 695SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
696SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
697SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 698SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 699SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
700
701SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
61bf35b9 702 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
f1c0a02f
MB		 703SOC_ENUM("ADC Companding Mode", adc_companding),
704SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
705
291ce18c
MB		 706SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
707 12, 0, digital_sidetone_tlv),
708
f1c0a02f 709/* DAC */
dcf9ada3 710SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 711SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
712 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
713SOC_ENUM("DAC Soft Mute Rate", soft_mute),
714SOC_ENUM("DAC Mute Mode", mute_mode),
715SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 716SOC_ENUM("DAC Companding Mode", dac_companding),
717SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 718SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
719 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 720
721/* Headphones */
722SOC_DOUBLE_R("Headphone Switch",
723 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
724 8, 1, 1),
725SOC_DOUBLE_R("Headphone ZC Switch",
726 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
727 6, 1, 0),
728SOC_DOUBLE_R_TLV("Headphone Volume",
729 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
730 0, 63, 0, out_tlv),
731
732/* Line out */
733SOC_DOUBLE_R("Line Out Switch",
734 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
735 8, 1, 1),
736SOC_DOUBLE_R("Line Out ZC Switch",
737 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
738 6, 1, 0),
739SOC_DOUBLE_R_TLV("Line Out Volume",
740 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
741 0, 63, 0, out_tlv),
742
743/* Speaker */
744SOC_DOUBLE_R("Speaker Switch",
745 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
746SOC_DOUBLE_R("Speaker ZC Switch",
747 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
748SOC_DOUBLE_R_TLV("Speaker Volume",
749 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
750 0, 63, 0, out_tlv),
751};
752
f1c0a02f
MB		 753static const struct snd_kcontrol_new linput_mode_mux =
754 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
755
756static const struct snd_kcontrol_new rinput_mode_mux =
757 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
758
759static const struct snd_kcontrol_new linput_mux =
760 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
761
762static const struct snd_kcontrol_new linput_inv_mux =
763 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
764
765static const struct snd_kcontrol_new rinput_mux =
766 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
767
768static const struct snd_kcontrol_new rinput_inv_mux =
769 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
770
291ce18c
MB		 771static const struct snd_kcontrol_new lsidetone_mux =
772 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
773
774static const struct snd_kcontrol_new rsidetone_mux =
775 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
776
97945c46
SW		 777static const struct snd_kcontrol_new adcinput_mux =
778 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
779
1e113bf9
MB		 780static const struct snd_kcontrol_new lcapture_mux =
781 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
782
783static const struct snd_kcontrol_new rcapture_mux =
784 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
785
786static const struct snd_kcontrol_new lplay_mux =
787 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
788
789static const struct snd_kcontrol_new rplay_mux =
790 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
791
f1c0a02f
MB		 792static const struct snd_kcontrol_new left_output_mixer[] = {
793SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
794SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
795SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 796SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 797};
798
799static const struct snd_kcontrol_new right_output_mixer[] = {
800SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
801SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
802SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 803SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 804};
805
806static const struct snd_kcontrol_new left_speaker_mixer[] = {
807SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
808SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
809SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
810SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 811 0, 1, 0),
f1c0a02f
MB		 812};
813
814static const struct snd_kcontrol_new right_speaker_mixer[] = {
815SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
816SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
817SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
818 1, 1, 0),
819SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 820 0, 1, 0),
f1c0a02f
MB		 821};
822
823static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
824SND_SOC_DAPM_INPUT("IN1L"),
825SND_SOC_DAPM_INPUT("IN1R"),
826SND_SOC_DAPM_INPUT("IN2L"),
827SND_SOC_DAPM_INPUT("IN2R"),
828SND_SOC_DAPM_INPUT("IN3L"),
829SND_SOC_DAPM_INPUT("IN3R"),
97945c46 830SND_SOC_DAPM_INPUT("DMICDAT"),
f1c0a02f
MB		 831
832SND_SOC_DAPM_OUTPUT("HPOUTL"),
833SND_SOC_DAPM_OUTPUT("HPOUTR"),
834SND_SOC_DAPM_OUTPUT("LINEOUTL"),
835SND_SOC_DAPM_OUTPUT("LINEOUTR"),
836SND_SOC_DAPM_OUTPUT("LOP"),
837SND_SOC_DAPM_OUTPUT("LON"),
838SND_SOC_DAPM_OUTPUT("ROP"),
839SND_SOC_DAPM_OUTPUT("RON"),
840
841SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
842
843SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
844SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
845 &linput_inv_mux),
846SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
847
848SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
849SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
850 &rinput_inv_mux),
851SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
852
853SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
854SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
855
97945c46
SW		 856SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
857SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
858
1e113bf9
MB		 859SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
860SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
861
862SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
863SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
864
865SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
866SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 867
291ce18c
MB		 868SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
869SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
870
1e113bf9
MB		 871SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
872SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
873
874SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
875SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
876
877SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
878SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 879
880SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
881 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
882SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
883 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
884
885SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
886 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
887SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
888 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
889
1b877cb5
DL		 890SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
891 1, 0, NULL, 0),
892SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 893 0, 0, NULL, 0),
894
1b877cb5 895SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 896 NULL, 0),
1b877cb5 897SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 898 NULL, 0),
899
900SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
901SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 902SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
903SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 904SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
905SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 906SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
907SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 908
909SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
910 NULL, 0),
911SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
912 NULL, 0),
1b877cb5
DL		 913SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
914 NULL, 0),
915SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 916 NULL, 0),
917SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
918 NULL, 0),
919SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
920 NULL, 0),
1b877cb5
DL		 921SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
922 NULL, 0),
923SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 924 NULL, 0),
925
c5b6a9fe
MB		 926SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
927SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
928 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
929SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
930 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
931SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
932 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
933SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
934 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 935
936SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
937 NULL, 0),
938SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
939 NULL, 0),
940
42768a12
MB		 941SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
942 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 943SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 944SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 945};
946
ecd01512 947static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 948
2c8be5a2
MB		 949 { "CLK_DSP", NULL, "CLK_SYS" },
950 { "Mic Bias", NULL, "CLK_SYS" },
951 { "HPL_DCS", NULL, "CLK_SYS" },
952 { "HPR_DCS", NULL, "CLK_SYS" },
953 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
954 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
955
f1c0a02f
MB		 956 { "Left Input Mux", "IN1L", "IN1L" },
957 { "Left Input Mux", "IN2L", "IN2L" },
958 { "Left Input Mux", "IN3L", "IN3L" },
959
960 { "Left Input Inverting Mux", "IN1L", "IN1L" },
961 { "Left Input Inverting Mux", "IN2L", "IN2L" },
962 { "Left Input Inverting Mux", "IN3L", "IN3L" },
963
964 { "Right Input Mux", "IN1R", "IN1R" },
965 { "Right Input Mux", "IN2R", "IN2R" },
966 { "Right Input Mux", "IN3R", "IN3R" },
967
968 { "Right Input Inverting Mux", "IN1R", "IN1R" },
969 { "Right Input Inverting Mux", "IN2R", "IN2R" },
970 { "Right Input Inverting Mux", "IN3R", "IN3R" },
971
972 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
973 { "Left Input Mode Mux", "Differential Line",
974 "Left Input Mux" },
975 { "Left Input Mode Mux", "Differential Line",
976 "Left Input Inverting Mux" },
977 { "Left Input Mode Mux", "Differential Mic",
978 "Left Input Mux" },
979 { "Left Input Mode Mux", "Differential Mic",
980 "Left Input Inverting Mux" },
981
982 { "Right Input Mode Mux", "Single-Ended",
983 "Right Input Inverting Mux" },
984 { "Right Input Mode Mux", "Differential Line",
985 "Right Input Mux" },
986 { "Right Input Mode Mux", "Differential Line",
987 "Right Input Inverting Mux" },
988 { "Right Input Mode Mux", "Differential Mic",
989 "Right Input Mux" },
990 { "Right Input Mode Mux", "Differential Mic",
991 "Right Input Inverting Mux" },
992
993 { "Left Input PGA", NULL, "Left Input Mode Mux" },
994 { "Right Input PGA", NULL, "Right Input Mode Mux" },
995
97945c46
SW		 996 { "Left ADC Input", "ADC", "Left Input PGA" },
997 { "Left ADC Input", "DMIC", "DMICDAT" },
998 { "Right ADC Input", "ADC", "Right Input PGA" },
999 { "Right ADC Input", "DMIC", "DMICDAT" },
1000
1e113bf9
MB		 1001 { "Left Capture Mux", "Left", "ADCL" },
1002 { "Left Capture Mux", "Right", "ADCR" },
1003
1004 { "Right Capture Mux", "Left", "ADCL" },
1005 { "Right Capture Mux", "Right", "ADCR" },
1006
1007 { "AIFTXL", NULL, "Left Capture Mux" },
1008 { "AIFTXR", NULL, "Right Capture Mux" },
1009
97945c46 1010 { "ADCL", NULL, "Left ADC Input" },
c2aef4ff 1011 { "ADCL", NULL, "CLK_DSP" },
97945c46 1012 { "ADCR", NULL, "Right ADC Input" },
c2aef4ff
MB		 1013 { "ADCR", NULL, "CLK_DSP" },
1014
1e113bf9
MB		 1015 { "Left Playback Mux", "Left", "AIFRXL" },
1016 { "Left Playback Mux", "Right", "AIFRXR" },
1017
1018 { "Right Playback Mux", "Left", "AIFRXL" },
1019 { "Right Playback Mux", "Right", "AIFRXR" },
1020
291ce18c
MB		 1021 { "DACL Sidetone", "Left", "ADCL" },
1022 { "DACL Sidetone", "Right", "ADCR" },
1023 { "DACR Sidetone", "Left", "ADCL" },
1024 { "DACR Sidetone", "Right", "ADCR" },
1025
1e113bf9 1026 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1027 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1028 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1029
1030 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1031 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1032 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1033
1034 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1035 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1036 { "Left Output Mixer", "DACL Switch", "DACL" },
1037 { "Left Output Mixer", "DACR Switch", "DACR" },
1038
1039 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1040 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1041 { "Right Output Mixer", "DACL Switch", "DACL" },
1042 { "Right Output Mixer", "DACR Switch", "DACR" },
1043
1044 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1045 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1046 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1047 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1048
1049 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1050 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1051 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1052 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1053
1054 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1055 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1056
1057 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1058 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1059
1060 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1061 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1062
1b877cb5
DL		 1063 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1064 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1065 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1066 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1067 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1068 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1069 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1070 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1071
c5b6a9fe
MB		 1072 { "HPL_DCS", NULL, "DCS Master" },
1073 { "HPR_DCS", NULL, "DCS Master" },
1074 { "LINEOUTL_DCS", NULL, "DCS Master" },
1075 { "LINEOUTR_DCS", NULL, "DCS Master" },
1076
13a9983e
MB		 1077 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1078 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1079 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1080 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1081
1082 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1083 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1084 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1085 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1086
1087 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1088 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1089 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1090 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1091
1092 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1093 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1094 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1095 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1096
1097 { "LOP", NULL, "Left Speaker PGA" },
1098 { "LON", NULL, "Left Speaker PGA" },
1099
1100 { "ROP", NULL, "Right Speaker PGA" },
1101 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1102
1103 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1104 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1105 { "Left Line Output PGA", NULL, "Charge Pump" },
1106 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1107};
1108
f1c0a02f
MB		 1109static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1110 enum snd_soc_bias_level level)
1111{
f1c0a02f
MB		 1112 switch (level) {
1113 case SND_SOC_BIAS_ON:
66daaa59 1114 break;
22f226dd 1115
f1c0a02f 1116 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1117 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1118 WM8903_VMID_RES_MASK,
1119 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1120 break;
1121
1122 case SND_SOC_BIAS_STANDBY:
ce6120cc 1123 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1124 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1125 WM8903_POBCTRL | WM8903_ISEL_MASK |
1126 WM8903_STARTUP_BIAS_ENA |
1127 WM8903_BIAS_ENA,
1128 WM8903_POBCTRL |
1129 (2 << WM8903_ISEL_SHIFT) |
1130 WM8903_STARTUP_BIAS_ENA);
1131
1132 snd_soc_update_bits(codec,
1133 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1134 WM8903_SPK_DISCHARGE,
1135 WM8903_SPK_DISCHARGE);
1136
1137 msleep(33);
1138
1139 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1140 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1141 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1142
1143 snd_soc_update_bits(codec,
1144 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1145 WM8903_SPK_DISCHARGE, 0);
1146
1147 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1148 WM8903_VMID_TIE_ENA |
1149 WM8903_BUFIO_ENA |
1150 WM8903_VMID_IO_ENA |
1151 WM8903_VMID_SOFT_MASK |
1152 WM8903_VMID_RES_MASK |
1153 WM8903_VMID_BUF_ENA,
1154 WM8903_VMID_TIE_ENA |
1155 WM8903_BUFIO_ENA |
1156 WM8903_VMID_IO_ENA |
1157 (2 << WM8903_VMID_SOFT_SHIFT) |
1158 WM8903_VMID_RES_250K |
1159 WM8903_VMID_BUF_ENA);
1160
1161 msleep(129);
1162
1163 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1164 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1165 0);
1166
1167 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1168 WM8903_VMID_SOFT_MASK, 0);
1169
1170 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1171 WM8903_VMID_RES_MASK,
1172 WM8903_VMID_RES_50K);
1173
1174 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1175 WM8903_BIAS_ENA | WM8903_POBCTRL,
1176 WM8903_BIAS_ENA);
f1c0a02f 1177
f1c0a02f
MB		 1178 /* By default no bypass paths are enabled so
1179 * enable Class W support.
1180 */
f0fba2ad 1181 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1182 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1183 WM8903_CP_DYN_FREQ |
1184 WM8903_CP_DYN_V,
1185 WM8903_CP_DYN_FREQ |
1186 WM8903_CP_DYN_V);
f1c0a02f
MB		 1187 }
1188
66daaa59
MB		 1189 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1190 WM8903_VMID_RES_MASK,
1191 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1192 break;
1193
1194 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1195 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1196 WM8903_BIAS_ENA, 0);
1197
1198 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1199 WM8903_VMID_SOFT_MASK,
1200 2 << WM8903_VMID_SOFT_SHIFT);
1201
1202 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1203 WM8903_VMID_BUF_ENA, 0);
1204
1205 msleep(290);
1206
1207 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1208 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1209 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1210 WM8903_VMID_SOFT_MASK |
1211 WM8903_VMID_BUF_ENA, 0);
1212
1213 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1214 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1215 break;
1216 }
1217
ce6120cc 1218 codec->dapm.bias_level = level;
f1c0a02f
MB		 1219
1220 return 0;
1221}
1222
1223static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1224 int clk_id, unsigned int freq, int dir)
1225{
1226 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1227 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1228
1229 wm8903->sysclk = freq;
1230
1231 return 0;
1232}
1233
1234static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1235 unsigned int fmt)
1236{
1237 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1238 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1239
1240 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1241 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1242
1243 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1244 case SND_SOC_DAIFMT_CBS_CFS:
1245 break;
1246 case SND_SOC_DAIFMT_CBS_CFM:
1247 aif1 |= WM8903_LRCLK_DIR;
1248 break;
1249 case SND_SOC_DAIFMT_CBM_CFM:
1250 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1251 break;
1252 case SND_SOC_DAIFMT_CBM_CFS:
1253 aif1 |= WM8903_BCLK_DIR;
1254 break;
1255 default:
1256 return -EINVAL;
1257 }
1258
1259 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1260 case SND_SOC_DAIFMT_DSP_A:
1261 aif1 |= 0x3;
1262 break;
1263 case SND_SOC_DAIFMT_DSP_B:
1264 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1265 break;
1266 case SND_SOC_DAIFMT_I2S:
1267 aif1 |= 0x2;
1268 break;
1269 case SND_SOC_DAIFMT_RIGHT_J:
1270 aif1 |= 0x1;
1271 break;
1272 case SND_SOC_DAIFMT_LEFT_J:
1273 break;
1274 default:
1275 return -EINVAL;
1276 }
1277
1278 /* Clock inversion */
1279 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1280 case SND_SOC_DAIFMT_DSP_A:
1281 case SND_SOC_DAIFMT_DSP_B:
1282 /* frame inversion not valid for DSP modes */
1283 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1284 case SND_SOC_DAIFMT_NB_NF:
1285 break;
1286 case SND_SOC_DAIFMT_IB_NF:
1287 aif1 |= WM8903_AIF_BCLK_INV;
1288 break;
1289 default:
1290 return -EINVAL;
1291 }
1292 break;
1293 case SND_SOC_DAIFMT_I2S:
1294 case SND_SOC_DAIFMT_RIGHT_J:
1295 case SND_SOC_DAIFMT_LEFT_J:
1296 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1297 case SND_SOC_DAIFMT_NB_NF:
1298 break;
1299 case SND_SOC_DAIFMT_IB_IF:
1300 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1301 break;
1302 case SND_SOC_DAIFMT_IB_NF:
1303 aif1 |= WM8903_AIF_BCLK_INV;
1304 break;
1305 case SND_SOC_DAIFMT_NB_IF:
1306 aif1 |= WM8903_AIF_LRCLK_INV;
1307 break;
1308 default:
1309 return -EINVAL;
1310 }
1311 break;
1312 default:
1313 return -EINVAL;
1314 }
1315
8d50e447 1316 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1317
1318 return 0;
1319}
1320
1321static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1322{
1323 struct snd_soc_codec *codec = codec_dai->codec;
1324 u16 reg;
1325
8d50e447 1326 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1327
1328 if (mute)
1329 reg |= WM8903_DAC_MUTE;
1330 else
1331 reg &= ~WM8903_DAC_MUTE;
1332
8d50e447 1333 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1334
1335 return 0;
1336}
1337
1338/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1339 * for optimal performance so we list the lower rates first and match
1340 * on the last match we find. */
1341static struct {
1342 int div;
1343 int rate;
1344 int mode;
1345 int mclk_div;
1346} clk_sys_ratios[] = {
1347 { 64, 0x0, 0x0, 1 },
1348 { 68, 0x0, 0x1, 1 },
1349 { 125, 0x0, 0x2, 1 },
1350 { 128, 0x1, 0x0, 1 },
1351 { 136, 0x1, 0x1, 1 },
1352 { 192, 0x2, 0x0, 1 },
1353 { 204, 0x2, 0x1, 1 },
1354
1355 { 64, 0x0, 0x0, 2 },
1356 { 68, 0x0, 0x1, 2 },
1357 { 125, 0x0, 0x2, 2 },
1358 { 128, 0x1, 0x0, 2 },
1359 { 136, 0x1, 0x1, 2 },
1360 { 192, 0x2, 0x0, 2 },
1361 { 204, 0x2, 0x1, 2 },
1362
1363 { 250, 0x2, 0x2, 1 },
1364 { 256, 0x3, 0x0, 1 },
1365 { 272, 0x3, 0x1, 1 },
1366 { 384, 0x4, 0x0, 1 },
1367 { 408, 0x4, 0x1, 1 },
1368 { 375, 0x4, 0x2, 1 },
1369 { 512, 0x5, 0x0, 1 },
1370 { 544, 0x5, 0x1, 1 },
1371 { 500, 0x5, 0x2, 1 },
1372 { 768, 0x6, 0x0, 1 },
1373 { 816, 0x6, 0x1, 1 },
1374 { 750, 0x6, 0x2, 1 },
1375 { 1024, 0x7, 0x0, 1 },
1376 { 1088, 0x7, 0x1, 1 },
1377 { 1000, 0x7, 0x2, 1 },
1378 { 1408, 0x8, 0x0, 1 },
1379 { 1496, 0x8, 0x1, 1 },
1380 { 1536, 0x9, 0x0, 1 },
1381 { 1632, 0x9, 0x1, 1 },
1382 { 1500, 0x9, 0x2, 1 },
1383
1384 { 250, 0x2, 0x2, 2 },
1385 { 256, 0x3, 0x0, 2 },
1386 { 272, 0x3, 0x1, 2 },
1387 { 384, 0x4, 0x0, 2 },
1388 { 408, 0x4, 0x1, 2 },
1389 { 375, 0x4, 0x2, 2 },
1390 { 512, 0x5, 0x0, 2 },
1391 { 544, 0x5, 0x1, 2 },
1392 { 500, 0x5, 0x2, 2 },
1393 { 768, 0x6, 0x0, 2 },
1394 { 816, 0x6, 0x1, 2 },
1395 { 750, 0x6, 0x2, 2 },
1396 { 1024, 0x7, 0x0, 2 },
1397 { 1088, 0x7, 0x1, 2 },
1398 { 1000, 0x7, 0x2, 2 },
1399 { 1408, 0x8, 0x0, 2 },
1400 { 1496, 0x8, 0x1, 2 },
1401 { 1536, 0x9, 0x0, 2 },
1402 { 1632, 0x9, 0x1, 2 },
1403 { 1500, 0x9, 0x2, 2 },
1404};
1405
1406/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1407static struct {
1408 int ratio;
1409 int div;
1410} bclk_divs[] = {
1411 { 10, 0 },
f1c0a02f
MB		 1412 { 20, 2 },
1413 { 30, 3 },
1414 { 40, 4 },
1415 { 50, 5 },
f1c0a02f
MB		 1416 { 60, 7 },
1417 { 80, 8 },
1418 { 100, 9 },
f1c0a02f
MB		 1419 { 120, 11 },
1420 { 160, 12 },
1421 { 200, 13 },
1422 { 220, 14 },
1423 { 240, 15 },
f1c0a02f
MB		 1424 { 300, 17 },
1425 { 320, 18 },
1426 { 440, 19 },
1427 { 480, 20 },
1428};
1429
1430/* Sample rates for DSP */
1431static struct {
1432 int rate;
1433 int value;
1434} sample_rates[] = {
1435 { 8000, 0 },
1436 { 11025, 1 },
1437 { 12000, 2 },
1438 { 16000, 3 },
1439 { 22050, 4 },
1440 { 24000, 5 },
1441 { 32000, 6 },
1442 { 44100, 7 },
1443 { 48000, 8 },
1444 { 88200, 9 },
1445 { 96000, 10 },
1446 { 0, 0 },
1447};
1448
f1c0a02f 1449static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1450 struct snd_pcm_hw_params *params,
1451 struct snd_soc_dai *dai)
f1c0a02f
MB		 1452{
1453 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1454 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1455 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1456 int fs = params_rate(params);
1457 int bclk;
1458 int bclk_div;
1459 int i;
1460 int dsp_config;
1461 int clk_config;
1462 int best_val;
1463 int cur_val;
1464 int clk_sys;
1465
8d50e447
MB		 1466 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1467 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1468 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1469 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1470 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1471 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1472
9e79261f
MB		 1473 /* Enable sloping stopband filter for low sample rates */
1474 if (fs <= 24000)
1475 dac_digital1 |= WM8903_DAC_SB_FILT;
1476 else
1477 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1478
f1c0a02f
MB		 1479 /* Configure sample rate logic for DSP - choose nearest rate */
1480 dsp_config = 0;
1481 best_val = abs(sample_rates[dsp_config].rate - fs);
1482 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1483 cur_val = abs(sample_rates[i].rate - fs);
1484 if (cur_val <= best_val) {
1485 dsp_config = i;
1486 best_val = cur_val;
1487 }
1488 }
1489
f0fba2ad 1490 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1491 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1492 clock1 |= sample_rates[dsp_config].value;
1493
1494 aif1 &= ~WM8903_AIF_WL_MASK;
1495 bclk = 2 * fs;
1496 switch (params_format(params)) {
1497 case SNDRV_PCM_FORMAT_S16_LE:
1498 bclk *= 16;
1499 break;
1500 case SNDRV_PCM_FORMAT_S20_3LE:
1501 bclk *= 20;
1502 aif1 |= 0x4;
1503 break;
1504 case SNDRV_PCM_FORMAT_S24_LE:
1505 bclk *= 24;
1506 aif1 |= 0x8;
1507 break;
1508 case SNDRV_PCM_FORMAT_S32_LE:
1509 bclk *= 32;
1510 aif1 |= 0xc;
1511 break;
1512 default:
1513 return -EINVAL;
1514 }
1515
f0fba2ad 1516 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1517 wm8903->sysclk, fs);
1518
1519 /* We may not have an MCLK which allows us to generate exactly
1520 * the clock we want, particularly with USB derived inputs, so
1521 * approximate.
1522 */
1523 clk_config = 0;
1524 best_val = abs((wm8903->sysclk /
1525 (clk_sys_ratios[0].mclk_div *
1526 clk_sys_ratios[0].div)) - fs);
1527 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1528 cur_val = abs((wm8903->sysclk /
1529 (clk_sys_ratios[i].mclk_div *
1530 clk_sys_ratios[i].div)) - fs);
1531
1532 if (cur_val <= best_val) {
1533 clk_config = i;
1534 best_val = cur_val;
1535 }
1536 }
1537
1538 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1539 clock0 |= WM8903_MCLKDIV2;
1540 clk_sys = wm8903->sysclk / 2;
1541 } else {
1542 clock0 &= ~WM8903_MCLKDIV2;
1543 clk_sys = wm8903->sysclk;
1544 }
1545
1546 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1547 WM8903_CLK_SYS_MODE_MASK);
1548 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1549 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1550
f0fba2ad 1551 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1552 clk_sys_ratios[clk_config].rate,
1553 clk_sys_ratios[clk_config].mode,
1554 clk_sys_ratios[clk_config].div);
1555
f0fba2ad 1556 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1557
1558 /* We may not get quite the right frequency if using
1559 * approximate clocks so look for the closest match that is
1560 * higher than the target (we need to ensure that there enough
1561 * BCLKs to clock out the samples).
1562 */
1563 bclk_div = 0;
1564 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1565 i = 1;
1566 while (i < ARRAY_SIZE(bclk_divs)) {
1567 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1568 if (cur_val < 0) /* BCLK table is sorted */
1569 break;
1570 bclk_div = i;
1571 best_val = cur_val;
1572 i++;
1573 }
1574
1575 aif2 &= ~WM8903_BCLK_DIV_MASK;
1576 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1577
f0fba2ad 1578 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1579 bclk_divs[bclk_div].ratio / 10, bclk,
1580 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1581
1582 aif2 |= bclk_divs[bclk_div].div;
1583 aif3 |= bclk / fs;
1584
69fff9bb
MB		 1585 wm8903->fs = params_rate(params);
1586 wm8903_set_deemph(codec);
1587
8d50e447
MB		 1588 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1589 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1590 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1591 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1592 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1593 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1594
1595 return 0;
1596}
1597
7245387e
MB		 1598/**
1599 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1600 *
1601 * @codec: WM8903 codec
1602 * @jack: jack to report detection events on
1603 * @det: value to report for presence detection
1604 * @shrt: value to report for short detection
1605 *
1606 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1607 * being used to bring out signals to the processor then only platform
1608 * data configuration is needed for WM8903 and processor GPIOs should
1609 * be configured using snd_soc_jack_add_gpios() instead.
1610 *
1611 * The current threasholds for detection should be configured using
1612 * micdet_cfg in the platform data. Using this function will force on
1613 * the microphone bias for the device.
1614 */
1615int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1616 int det, int shrt)
1617{
b2c812e2 1618 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1619 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1620
1621 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1622 det, shrt);
1623
1624 /* Store the configuration */
1625 wm8903->mic_jack = jack;
1626 wm8903->mic_det = det;
1627 wm8903->mic_short = shrt;
1628
1629 /* Enable interrupts we've got a report configured for */
1630 if (det)
1631 irq_mask &= ~WM8903_MICDET_EINT;
1632 if (shrt)
1633 irq_mask &= ~WM8903_MICSHRT_EINT;
1634
1635 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1636 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1637 irq_mask);
1638
3088e3b4 1639 if (det || shrt) {
69266866
MB		 1640 /* Enable mic detection, this may not have been set through
1641 * platform data (eg, if the defaults are OK). */
1642 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1643 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1644 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1645 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1646 } else {
1647 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1648 WM8903_MICDET_ENA, 0);
1649 }
7245387e
MB		 1650
1651 return 0;
1652}
1653EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1654
8abd16a6
MB		 1655static irqreturn_t wm8903_irq(int irq, void *data)
1656{
f0fba2ad
LG		 1657 struct snd_soc_codec *codec = data;
1658 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1659 int mic_report;
1660 int int_pol;
1661 int int_val = 0;
1662 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1663
7245387e 1664 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1665
7245387e 1666 if (int_val & WM8903_WSEQ_BUSY_EINT) {
b4d06f45 1667 dev_warn(codec->dev, "Write sequencer done\n");
8abd16a6
MB		 1668 }
1669
7245387e
MB		 1670 /*
1671 * The rest is microphone jack detection. We need to manually
1672 * invert the polarity of the interrupt after each event - to
1673 * simplify the code keep track of the last state we reported
1674 * and just invert the relevant bits in both the report and
1675 * the polarity register.
1676 */
1677 mic_report = wm8903->mic_last_report;
1678 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1679
1435b940 1680#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1681 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1682 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1683#endif
2bbb5d66 1684
7245387e
MB		 1685 if (int_val & WM8903_MICSHRT_EINT) {
1686 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1687
1688 mic_report ^= wm8903->mic_short;
1689 int_pol ^= WM8903_MICSHRT_INV;
1690 }
1691
1692 if (int_val & WM8903_MICDET_EINT) {
1693 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1694
1695 mic_report ^= wm8903->mic_det;
1696 int_pol ^= WM8903_MICDET_INV;
1697
1698 msleep(wm8903->mic_delay);
1699 }
1700
1701 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1702 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1703
1704 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1705 wm8903->mic_short | wm8903->mic_det);
1706
1707 wm8903->mic_last_report = mic_report;
1708
8abd16a6
MB		 1709 return IRQ_HANDLED;
1710}
1711
f1c0a02f
MB		 1712#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1713 SNDRV_PCM_RATE_11025 | \
1714 SNDRV_PCM_RATE_16000 | \
1715 SNDRV_PCM_RATE_22050 | \
1716 SNDRV_PCM_RATE_32000 | \
1717 SNDRV_PCM_RATE_44100 | \
1718 SNDRV_PCM_RATE_48000 | \
1719 SNDRV_PCM_RATE_88200 | \
1720 SNDRV_PCM_RATE_96000)
1721
1722#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1723 SNDRV_PCM_RATE_11025 | \
1724 SNDRV_PCM_RATE_16000 | \
1725 SNDRV_PCM_RATE_22050 | \
1726 SNDRV_PCM_RATE_32000 | \
1727 SNDRV_PCM_RATE_44100 | \
1728 SNDRV_PCM_RATE_48000)
1729
1730#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1731 SNDRV_PCM_FMTBIT_S20_3LE |\
1732 SNDRV_PCM_FMTBIT_S24_LE)
1733
85e7652d 1734static const struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1735 .hw_params = wm8903_hw_params,
1736 .digital_mute = wm8903_digital_mute,
1737 .set_fmt = wm8903_set_dai_fmt,
1738 .set_sysclk = wm8903_set_dai_sysclk,
1739};
1740
f0fba2ad
LG		 1741static struct snd_soc_dai_driver wm8903_dai = {
1742 .name = "wm8903-hifi",
f1c0a02f
MB		 1743 .playback = {
1744 .stream_name = "Playback",
1745 .channels_min = 2,
1746 .channels_max = 2,
1747 .rates = WM8903_PLAYBACK_RATES,
1748 .formats = WM8903_FORMATS,
1749 },
1750 .capture = {
1751 .stream_name = "Capture",
1752 .channels_min = 2,
1753 .channels_max = 2,
1754 .rates = WM8903_CAPTURE_RATES,
1755 .formats = WM8903_FORMATS,
1756 },
6335d055 1757 .ops = &wm8903_dai_ops,
0d960e88 1758 .symmetric_rates = 1,
f1c0a02f 1759};
f1c0a02f 1760
f0fba2ad 1761static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1762{
f1c0a02f
MB		 1763 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1764
1765 return 0;
1766}
1767
f0fba2ad 1768static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1769{
f1c0a02f
MB		 1770 int i;
1771 u16 *reg_cache = codec->reg_cache;
40aa7030 1772 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1773 GFP_KERNEL);
1774
1775 /* Bring the codec back up to standby first to minimise pop/clicks */
1776 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1777
1778 /* Sync back everything else */
1779 if (tmp_cache) {
1780 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1781 if (tmp_cache[i] != reg_cache[i])
8d50e447 1782 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1783 kfree(tmp_cache);
f1c0a02f 1784 } else {
f0fba2ad 1785 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1786 }
1787
1788 return 0;
1789}
1790
7cfe5617
SW		 1791#ifdef CONFIG_GPIOLIB
1792static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1793{
1794 return container_of(chip, struct wm8903_priv, gpio_chip);
1795}
1796
1797static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1798{
1799 if (offset >= WM8903_NUM_GPIO)
1800 return -EINVAL;
1801
1802 return 0;
1803}
1804
1805static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1806{
1807 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1808 struct snd_soc_codec *codec = wm8903->codec;
1809 unsigned int mask, val;
1810
1811 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1812 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1813 WM8903_GP1_DIR;
1814
1815 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1816 mask, val);
1817}
1818
1819static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1820{
1821 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1822 struct snd_soc_codec *codec = wm8903->codec;
1823 int reg;
1824
1825 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1826
1827 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1828}
1829
1830static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1831 unsigned offset, int value)
1832{
1833 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1834 struct snd_soc_codec *codec = wm8903->codec;
1835 unsigned int mask, val;
1836
1837 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1838 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1839 (value << WM8903_GP2_LVL_SHIFT);
1840
1841 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1842 mask, val);
1843}
1844
1845static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1846{
1847 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1848 struct snd_soc_codec *codec = wm8903->codec;
1849
1850 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1851 WM8903_GP1_LVL_MASK,
1852 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1853}
1854
1855static struct gpio_chip wm8903_template_chip = {
1856 .label = "wm8903",
1857 .owner = THIS_MODULE,
1858 .request = wm8903_gpio_request,
1859 .direction_input = wm8903_gpio_direction_in,
1860 .get = wm8903_gpio_get,
1861 .direction_output = wm8903_gpio_direction_out,
1862 .set = wm8903_gpio_set,
1863 .can_sleep = 1,
1864};
1865
1866static void wm8903_init_gpio(struct snd_soc_codec *codec)
1867{
1868 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1869 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1870 int ret;
1871
1872 wm8903->gpio_chip = wm8903_template_chip;
1873 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1874 wm8903->gpio_chip.dev = codec->dev;
1875
1876 if (pdata && pdata->gpio_base)
1877 wm8903->gpio_chip.base = pdata->gpio_base;
1878 else
1879 wm8903->gpio_chip.base = -1;
1880
1881 ret = gpiochip_add(&wm8903->gpio_chip);
1882 if (ret != 0)
1883 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1884}
1885
1886static void wm8903_free_gpio(struct snd_soc_codec *codec)
1887{
1888 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1889 int ret;
1890
1891 ret = gpiochip_remove(&wm8903->gpio_chip);
1892 if (ret != 0)
1893 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1894}
1895#else
1896static void wm8903_init_gpio(struct snd_soc_codec *codec)
1897{
1898}
1899
1900static void wm8903_free_gpio(struct snd_soc_codec *codec)
1901{
1902}
1903#endif
1904
f0fba2ad 1905static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1906{
f0fba2ad
LG		 1907 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1908 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1909 int ret, i;
8abd16a6 1910 int trigger, irq_pol;
f1c0a02f
MB		 1911 u16 val;
1912
7cfe5617 1913 wm8903->codec = codec;
d58d5d55 1914
8d50e447
MB		 1915 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1916 if (ret != 0) {
f0fba2ad
LG		 1917 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1918 return ret;
8d50e447
MB		 1919 }
1920
1921 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1922 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1923 dev_err(codec->dev,
d58d5d55
MB		 1924 "Device with ID register %x is not a WM8903\n", val);
1925 return -ENODEV;
f1c0a02f
MB		 1926 }
1927
8d50e447 1928 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1929 dev_info(codec->dev, "WM8903 revision %c\n",
1930 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1931
1932 wm8903_reset(codec);
1933
37f88e84 1934 /* Set up GPIOs and microphone detection */
73b34ead 1935 if (pdata) {
905f6952
MB		 1936 bool mic_gpio = false;
1937
73b34ead 1938 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
7cfe5617 1939 if (pdata->gpio_cfg[i] == WM8903_GPIO_NO_CONFIG)
73b34ead
MB		 1940 continue;
1941
1942 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1943 pdata->gpio_cfg[i] & 0xffff);
905f6952
MB		 1944
1945 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
1946 >> WM8903_GP1_FN_SHIFT;
1947
1948 switch (val) {
1949 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
1950 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
1951 mic_gpio = true;
1952 break;
1953 default:
1954 break;
1955 }
73b34ead 1956 }
37f88e84
MB		 1957
1958 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1959 pdata->micdet_cfg);
1960
1961 /* Microphone detection needs the WSEQ clock */
1962 if (pdata->micdet_cfg)
1963 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1964 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1965
905f6952
MB		 1966 /* If microphone detection is enabled by pdata but
1967 * detected via IRQ then interrupts can be lost before
1968 * the machine driver has set up microphone detection
1969 * IRQs as the IRQs are clear on read. The detection
1970 * will be enabled when the machine driver configures.
1971 */
1972 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
1973
37f88e84 1974 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1975 }
8abd16a6 1976
f0fba2ad 1977 if (wm8903->irq) {
8abd16a6
MB		 1978 if (pdata && pdata->irq_active_low) {
1979 trigger = IRQF_TRIGGER_LOW;
1980 irq_pol = WM8903_IRQ_POL;
1981 } else {
1982 trigger = IRQF_TRIGGER_HIGH;
1983 irq_pol = 0;
1984 }
1985
1986 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1987 WM8903_IRQ_POL, irq_pol);
1988
f0fba2ad 1989 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1990 trigger | IRQF_ONESHOT,
f0fba2ad 1991 "wm8903", codec);
8abd16a6 1992 if (ret != 0) {
f0fba2ad 1993 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1994 ret);
f0fba2ad 1995 return ret;
8abd16a6
MB		 1996 }
1997
1998 /* Enable write sequencer interrupts */
1999 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
2000 WM8903_IM_WSEQ_BUSY_EINT, 0);
2001 }
73b34ead 2002
f1c0a02f
MB		 2003 /* power on device */
2004 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2005
2006 /* Latch volume update bits */
8d50e447 2007 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 2008 val |= WM8903_ADCVU;
8d50e447
MB		 2009 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
2010 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 2011
8d50e447 2012 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 2013 val |= WM8903_DACVU;
8d50e447
MB		 2014 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
2015 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 2016
8d50e447 2017 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 2018 val |= WM8903_HPOUTVU;
8d50e447
MB		 2019 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
2020 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 2021
8d50e447 2022 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 2023 val |= WM8903_LINEOUTVU;
8d50e447
MB		 2024 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
2025 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 2026
8d50e447 2027 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 2028 val |= WM8903_SPKVU;
8d50e447
MB		 2029 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
2030 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 2031
2032 /* Enable DAC soft mute by default */
e12adab0
MB		 2033 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
2034 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2035 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 2036
f0fba2ad
LG		 2037 snd_soc_add_controls(codec, wm8903_snd_controls,
2038 ARRAY_SIZE(wm8903_snd_controls));
f1c0a02f 2039
7cfe5617
SW		 2040 wm8903_init_gpio(codec);
2041
f1c0a02f
MB		 2042 return ret;
2043}
2044
f0fba2ad
LG		 2045/* power down chip */
2046static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2047{
f99847a6
SW		 2048 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
2049
7cfe5617 2050 wm8903_free_gpio(codec);
f0fba2ad 2051 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f99847a6
SW		 2052 if (wm8903->irq)
2053 free_irq(wm8903->irq, codec);
2054
f0fba2ad
LG		 2055 return 0;
2056}
f1c0a02f 2057
f0fba2ad
LG		 2058static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2059 .probe = wm8903_probe,
2060 .remove = wm8903_remove,
2061 .suspend = wm8903_suspend,
2062 .resume = wm8903_resume,
2063 .set_bias_level = wm8903_set_bias_level,
2064 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
2065 .reg_word_size = sizeof(u16),
2066 .reg_cache_default = wm8903_reg_defaults,
2067 .volatile_register = wm8903_volatile_register,
c5b6a9fe 2068 .seq_notifier = wm8903_seq_notifier,
ecd01512
MB		 2069 .dapm_widgets = wm8903_dapm_widgets,
2070 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
2071 .dapm_routes = wm8903_intercon,
2072 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 2073};
f1c0a02f 2074
f0fba2ad
LG		 2075#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2076static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2077 const struct i2c_device_id *id)
2078{
2079 struct wm8903_priv *wm8903;
2080 int ret;
f1c0a02f 2081
f0fba2ad
LG		 2082 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
2083 if (wm8903 == NULL)
2084 return -ENOMEM;
8abd16a6 2085
f0fba2ad 2086 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2087 wm8903->irq = i2c->irq;
d58d5d55 2088
f0fba2ad
LG		 2089 ret = snd_soc_register_codec(&i2c->dev,
2090 &soc_codec_dev_wm8903, &wm8903_dai, 1);
2091 if (ret < 0)
2092 kfree(wm8903);
2093 return ret;
2094}
f1c0a02f 2095
f0fba2ad
LG		 2096static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2097{
2098 snd_soc_unregister_codec(&client->dev);
2099 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 2100 return 0;
2101}
2102
f1c0a02f 2103static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2104 { "wm8903", 0 },
2105 { }
f1c0a02f
MB		 2106};
2107MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2108
2109static struct i2c_driver wm8903_i2c_driver = {
2110 .driver = {
4b592c91 2111 .name = "wm8903",
f1c0a02f
MB		 2112 .owner = THIS_MODULE,
2113 },
f0fba2ad
LG		 2114 .probe = wm8903_i2c_probe,
2115 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2116 .id_table = wm8903_i2c_id,
2117};
f0fba2ad 2118#endif
f1c0a02f 2119
f0fba2ad 2120static int __init wm8903_modinit(void)
f1c0a02f 2121{
f1c0a02f 2122 int ret = 0;
f0fba2ad
LG		 2123#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
2124 ret = i2c_add_driver(&wm8903_i2c_driver);
2125 if (ret != 0) {
2126 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2127 ret);
f1c0a02f 2128 }
f0fba2ad 2129#endif
f1c0a02f 2130 return ret;
64089b84
MB		 2131}
2132module_init(wm8903_modinit);
2133
2134static void __exit wm8903_exit(void)
2135{
f0fba2ad 2136#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 2137 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 2138#endif
64089b84
MB		 2139}
2140module_exit(wm8903_exit);
2141
f1c0a02f
MB		 2142MODULE_DESCRIPTION("ASoC WM8903 driver");
2143MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2144MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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