projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ASoC: WM8903: Add device tree binding
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
ee244ce4 26#include <linux/regmap.h>
5a0e3ad6 27#include <linux/slab.h>
9d35f3e1 28#include <linux/irq.h>
f1c0a02f 29#include <sound/core.h>
7245387e 30#include <sound/jack.h>
f1c0a02f
MB		 31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/tlv.h>
34#include <sound/soc.h>
f1c0a02f 35#include <sound/initval.h>
8abd16a6 36#include <sound/wm8903.h>
2bbb5d66 37#include <trace/events/asoc.h>
f1c0a02f
MB		 38
39#include "wm8903.h"
40
f1c0a02f 41/* Register defaults at reset */
ee244ce4
MB		 42static const struct reg_default wm8903_reg_defaults[] = {
43 { 4, 0x0018 }, /* R4 - Bias Control 0 */
44 { 5, 0x0000 }, /* R5 - VMID Control 0 */
45 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
46 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
47 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
48 { 12, 0x0000 }, /* R12 - Power Management 0 */
49 { 13, 0x0000 }, /* R13 - Power Management 1 */
50 { 14, 0x0000 }, /* R14 - Power Management 2 */
51 { 15, 0x0000 }, /* R15 - Power Management 3 */
52 { 16, 0x0000 }, /* R16 - Power Management 4 */
53 { 17, 0x0000 }, /* R17 - Power Management 5 */
54 { 18, 0x0000 }, /* R18 - Power Management 6 */
55 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
56 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
57 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
58 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
59 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
60 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
61 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
62 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
63 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
64 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
65 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
66 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
67 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
68 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
69 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
70 { 40, 0x09BF }, /* R40 - DRC 0 */
71 { 41, 0x3241 }, /* R41 - DRC 1 */
72 { 42, 0x0020 }, /* R42 - DRC 2 */
73 { 43, 0x0000 }, /* R43 - DRC 3 */
74 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
75 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
76 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
77 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
78 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
79 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
80 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
81 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
82 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
83 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
84 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
85 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
86 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
87 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
88 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
89 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
90 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
91 { 67, 0x0010 }, /* R67 - DC Servo 0 */
92 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
93 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
94 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
95 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
96 { 104, 0x0000 }, /* R104 - Class W 0 */
97 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
98 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
99 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
100 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
101 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
102 { 114, 0x0000 }, /* R114 - Control Interface */
103 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
104 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
105 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
106 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
107 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
108 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
109 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
110 { 126, 0x0000 }, /* R126 - Interrupt Control */
111 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
112 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
113 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
114 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
f1c0a02f
MB		 115};
116
d58d5d55 117struct wm8903_priv {
c0eb27cf 118 struct wm8903_platform_data *pdata;
7cfe5617 119 struct snd_soc_codec *codec;
ee244ce4 120 struct regmap *regmap;
f0fba2ad 121
d58d5d55 122 int sysclk;
f0fba2ad 123 int irq;
d58d5d55 124
69fff9bb
MB		 125 int fs;
126 int deemph;
127
c5b6a9fe
MB		 128 int dcs_pending;
129 int dcs_cache[4];
130
f2c1fe09 131 /* Reference count */
d58d5d55 132 int class_w_users;
d58d5d55 133
7245387e
MB		 134 struct snd_soc_jack *mic_jack;
135 int mic_det;
136 int mic_short;
137 int mic_last_report;
138 int mic_delay;
7cfe5617
SW		 139
140#ifdef CONFIG_GPIOLIB
141 struct gpio_chip gpio_chip;
142#endif
d58d5d55
MB		 143};
144
ee244ce4
MB		 145static bool wm8903_readable_register(struct device *dev, unsigned int reg)
146{
147 switch (reg) {
148 case WM8903_SW_RESET_AND_ID:
149 case WM8903_REVISION_NUMBER:
150 case WM8903_BIAS_CONTROL_0:
151 case WM8903_VMID_CONTROL_0:
152 case WM8903_MIC_BIAS_CONTROL_0:
153 case WM8903_ANALOGUE_DAC_0:
154 case WM8903_ANALOGUE_ADC_0:
155 case WM8903_POWER_MANAGEMENT_0:
156 case WM8903_POWER_MANAGEMENT_1:
157 case WM8903_POWER_MANAGEMENT_2:
158 case WM8903_POWER_MANAGEMENT_3:
159 case WM8903_POWER_MANAGEMENT_4:
160 case WM8903_POWER_MANAGEMENT_5:
161 case WM8903_POWER_MANAGEMENT_6:
162 case WM8903_CLOCK_RATES_0:
163 case WM8903_CLOCK_RATES_1:
164 case WM8903_CLOCK_RATES_2:
165 case WM8903_AUDIO_INTERFACE_0:
166 case WM8903_AUDIO_INTERFACE_1:
167 case WM8903_AUDIO_INTERFACE_2:
168 case WM8903_AUDIO_INTERFACE_3:
169 case WM8903_DAC_DIGITAL_VOLUME_LEFT:
170 case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
171 case WM8903_DAC_DIGITAL_0:
172 case WM8903_DAC_DIGITAL_1:
173 case WM8903_ADC_DIGITAL_VOLUME_LEFT:
174 case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
175 case WM8903_ADC_DIGITAL_0:
176 case WM8903_DIGITAL_MICROPHONE_0:
177 case WM8903_DRC_0:
178 case WM8903_DRC_1:
179 case WM8903_DRC_2:
180 case WM8903_DRC_3:
181 case WM8903_ANALOGUE_LEFT_INPUT_0:
182 case WM8903_ANALOGUE_RIGHT_INPUT_0:
183 case WM8903_ANALOGUE_LEFT_INPUT_1:
184 case WM8903_ANALOGUE_RIGHT_INPUT_1:
185 case WM8903_ANALOGUE_LEFT_MIX_0:
186 case WM8903_ANALOGUE_RIGHT_MIX_0:
187 case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
188 case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
189 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
190 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
191 case WM8903_ANALOGUE_OUT1_LEFT:
192 case WM8903_ANALOGUE_OUT1_RIGHT:
193 case WM8903_ANALOGUE_OUT2_LEFT:
194 case WM8903_ANALOGUE_OUT2_RIGHT:
195 case WM8903_ANALOGUE_OUT3_LEFT:
196 case WM8903_ANALOGUE_OUT3_RIGHT:
197 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
198 case WM8903_DC_SERVO_0:
199 case WM8903_DC_SERVO_2:
200 case WM8903_DC_SERVO_READBACK_1:
201 case WM8903_DC_SERVO_READBACK_2:
202 case WM8903_DC_SERVO_READBACK_3:
203 case WM8903_DC_SERVO_READBACK_4:
204 case WM8903_ANALOGUE_HP_0:
205 case WM8903_ANALOGUE_LINEOUT_0:
206 case WM8903_CHARGE_PUMP_0:
207 case WM8903_CLASS_W_0:
208 case WM8903_WRITE_SEQUENCER_0:
209 case WM8903_WRITE_SEQUENCER_1:
210 case WM8903_WRITE_SEQUENCER_2:
211 case WM8903_WRITE_SEQUENCER_3:
212 case WM8903_WRITE_SEQUENCER_4:
213 case WM8903_CONTROL_INTERFACE:
214 case WM8903_GPIO_CONTROL_1:
215 case WM8903_GPIO_CONTROL_2:
216 case WM8903_GPIO_CONTROL_3:
217 case WM8903_GPIO_CONTROL_4:
218 case WM8903_GPIO_CONTROL_5:
219 case WM8903_INTERRUPT_STATUS_1:
220 case WM8903_INTERRUPT_STATUS_1_MASK:
221 case WM8903_INTERRUPT_POLARITY_1:
222 case WM8903_INTERRUPT_CONTROL:
223 case WM8903_CLOCK_RATE_TEST_4:
224 case WM8903_ANALOGUE_OUTPUT_BIAS_0:
225 return true;
226 default:
227 return false;
228 }
229}
230
231static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
f1c0a02f
MB		 232{
233 switch (reg) {
234 case WM8903_SW_RESET_AND_ID:
235 case WM8903_REVISION_NUMBER:
236 case WM8903_INTERRUPT_STATUS_1:
237 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 238 case WM8903_DC_SERVO_READBACK_1:
239 case WM8903_DC_SERVO_READBACK_2:
240 case WM8903_DC_SERVO_READBACK_3:
241 case WM8903_DC_SERVO_READBACK_4:
8d50e447 242 return 1;
f1c0a02f
MB		 243
244 default:
f1c0a02f 245 return 0;
8d50e447 246 }
f1c0a02f
MB		 247}
248
42768a12
MB		 249static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
250 struct snd_kcontrol *kcontrol, int event)
251{
252 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
253 mdelay(4);
254
255 return 0;
256}
257
c5b6a9fe
MB		 258static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
259 struct snd_kcontrol *kcontrol, int event)
260{
261 struct snd_soc_codec *codec = w->codec;
262 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
263
264 switch (event) {
265 case SND_SOC_DAPM_POST_PMU:
266 wm8903->dcs_pending |= 1 << w->shift;
267 break;
268 case SND_SOC_DAPM_PRE_PMD:
269 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
270 1 << w->shift, 0);
271 break;
272 }
273
274 return 0;
275}
276
277#define WM8903_DCS_MODE_WRITE_STOP 0
278#define WM8903_DCS_MODE_START_STOP 2
279
280static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
281 enum snd_soc_dapm_type event, int subseq)
282{
283 struct snd_soc_codec *codec = container_of(dapm,
284 struct snd_soc_codec, dapm);
285 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
286 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
287 int i, val;
288
289 /* Complete any pending DC servo starts */
290 if (wm8903->dcs_pending) {
291 dev_dbg(codec->dev, "Starting DC servo for %x\n",
292 wm8903->dcs_pending);
293
294 /* If we've no cached values then we need to do startup */
295 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
296 if (!(wm8903->dcs_pending & (1 << i)))
297 continue;
298
299 if (wm8903->dcs_cache[i]) {
300 dev_dbg(codec->dev,
301 "Restore DC servo %d value %x\n",
302 3 - i, wm8903->dcs_cache[i]);
303
304 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
305 wm8903->dcs_cache[i] & 0xff);
306 } else {
307 dev_dbg(codec->dev,
308 "Calibrate DC servo %d\n", 3 - i);
309 dcs_mode = WM8903_DCS_MODE_START_STOP;
310 }
311 }
312
313 /* Don't trust the cache for analogue */
314 if (wm8903->class_w_users)
315 dcs_mode = WM8903_DCS_MODE_START_STOP;
316
317 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
318 WM8903_DCS_MODE_MASK, dcs_mode);
319
320 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
321 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
322
323 switch (dcs_mode) {
324 case WM8903_DCS_MODE_WRITE_STOP:
325 break;
326
327 case WM8903_DCS_MODE_START_STOP:
328 msleep(270);
329
330 /* Cache the measured offsets for digital */
331 if (wm8903->class_w_users)
332 break;
333
334 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
335 if (!(wm8903->dcs_pending & (1 << i)))
336 continue;
337
338 val = snd_soc_read(codec,
339 WM8903_DC_SERVO_READBACK_1 + i);
340 dev_dbg(codec->dev, "DC servo %d: %x\n",
341 3 - i, val);
342 wm8903->dcs_cache[i] = val;
343 }
344 break;
345
346 default:
347 pr_warn("DCS mode %d delay not set\n", dcs_mode);
348 break;
349 }
350
351 wm8903->dcs_pending = 0;
352 }
353}
354
f1c0a02f
MB		 355/*
356 * When used with DAC outputs only the WM8903 charge pump supports
357 * operation in class W mode, providing very low power consumption
358 * when used with digital sources. Enable and disable this mode
359 * automatically depending on the mixer configuration.
360 *
361 * All the relevant controls are simple switches.
362 */
363static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_value *ucontrol)
365{
9d03545d
JN		 366 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
367 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
f1c0a02f 368 struct snd_soc_codec *codec = widget->codec;
b2c812e2 369 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 370 u16 reg;
371 int ret;
372
8d50e447 373 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 374
375 /* Turn it off if we're about to enable bypass */
376 if (ucontrol->value.integer.value[0]) {
377 if (wm8903->class_w_users == 0) {
f0fba2ad 378 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 379 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 380 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
381 }
382 wm8903->class_w_users++;
383 }
384
385 /* Implement the change */
386 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
387
388 /* If we've just disabled the last bypass path turn Class W on */
389 if (!ucontrol->value.integer.value[0]) {
390 if (wm8903->class_w_users == 1) {
f0fba2ad 391 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 392 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 393 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
394 }
395 wm8903->class_w_users--;
396 }
397
f0fba2ad 398 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 399 wm8903->class_w_users);
400
401 return ret;
402}
403
404#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
405{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
406 .info = snd_soc_info_volsw, \
407 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
408 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
409
410
69fff9bb
MB		 411static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
412
413static int wm8903_set_deemph(struct snd_soc_codec *codec)
414{
415 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
416 int val, i, best;
417
418 /* If we're using deemphasis select the nearest available sample
419 * rate.
420 */
421 if (wm8903->deemph) {
422 best = 1;
423 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
424 if (abs(wm8903_deemph[i] - wm8903->fs) <
425 abs(wm8903_deemph[best] - wm8903->fs))
426 best = i;
427 }
428
429 val = best << WM8903_DEEMPH_SHIFT;
430 } else {
431 best = 0;
432 val = 0;
433 }
434
435 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
436 best, wm8903_deemph[best]);
437
438 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
439 WM8903_DEEMPH_MASK, val);
440}
441
442static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
443 struct snd_ctl_elem_value *ucontrol)
444{
445 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
446 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
447
448 ucontrol->value.enumerated.item[0] = wm8903->deemph;
449
450 return 0;
451}
452
453static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
454 struct snd_ctl_elem_value *ucontrol)
455{
456 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
457 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
458 int deemph = ucontrol->value.enumerated.item[0];
459 int ret = 0;
460
461 if (deemph > 1)
462 return -EINVAL;
463
464 mutex_lock(&codec->mutex);
465 if (wm8903->deemph != deemph) {
466 wm8903->deemph = deemph;
467
468 wm8903_set_deemph(codec);
469
470 ret = 1;
471 }
472 mutex_unlock(&codec->mutex);
473
474 return ret;
475}
476
f1c0a02f
MB		 477/* ALSA can only do steps of .01dB */
478static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
479
291ce18c 480static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 481static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
482
483static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
484static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
485static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
486static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
487static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
488
460f4aae
MB		 489static const char *hpf_mode_text[] = {
490 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
491};
492
493static const struct soc_enum hpf_mode =
494 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
495
dcf9ada3
MB		 496static const char *osr_text[] = {
497 "Low power", "High performance"
498};
499
500static const struct soc_enum adc_osr =
501 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
502
503static const struct soc_enum dac_osr =
504 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
505
f1c0a02f
MB		 506static const char *drc_slope_text[] = {
507 "1", "1/2", "1/4", "1/8", "1/16", "0"
508};
509
510static const struct soc_enum drc_slope_r0 =
511 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
512
513static const struct soc_enum drc_slope_r1 =
514 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
515
516static const char *drc_attack_text[] = {
517 "instantaneous",
518 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
519 "46.4ms", "92.8ms", "185.6ms"
520};
521
522static const struct soc_enum drc_attack =
523 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
524
525static const char *drc_decay_text[] = {
526 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
527 "23.87s", "47.56s"
528};
529
530static const struct soc_enum drc_decay =
531 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
532
533static const char *drc_ff_delay_text[] = {
534 "5 samples", "9 samples"
535};
536
537static const struct soc_enum drc_ff_delay =
538 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
539
540static const char *drc_qr_decay_text[] = {
541 "0.725ms", "1.45ms", "5.8ms"
542};
543
544static const struct soc_enum drc_qr_decay =
545 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
546
547static const char *drc_smoothing_text[] = {
548 "Low", "Medium", "High"
549};
550
551static const struct soc_enum drc_smoothing =
552 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
553
554static const char *soft_mute_text[] = {
555 "Fast (fs/2)", "Slow (fs/32)"
556};
557
558static const struct soc_enum soft_mute =
559 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
560
561static const char *mute_mode_text[] = {
562 "Hard", "Soft"
563};
564
565static const struct soc_enum mute_mode =
566 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
567
f1c0a02f
MB		 568static const char *companding_text[] = {
569 "ulaw", "alaw"
570};
571
572static const struct soc_enum dac_companding =
573 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
574
575static const struct soc_enum adc_companding =
576 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
577
578static const char *input_mode_text[] = {
579 "Single-Ended", "Differential Line", "Differential Mic"
580};
581
582static const struct soc_enum linput_mode_enum =
583 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
584
585static const struct soc_enum rinput_mode_enum =
586 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
587
588static const char *linput_mux_text[] = {
589 "IN1L", "IN2L", "IN3L"
590};
591
592static const struct soc_enum linput_enum =
593 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
594
595static const struct soc_enum linput_inv_enum =
596 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
597
598static const char *rinput_mux_text[] = {
599 "IN1R", "IN2R", "IN3R"
600};
601
602static const struct soc_enum rinput_enum =
603 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
604
605static const struct soc_enum rinput_inv_enum =
606 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
607
608
291ce18c
MB		 609static const char *sidetone_text[] = {
610 "None", "Left", "Right"
611};
612
613static const struct soc_enum lsidetone_enum =
614 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
615
616static const struct soc_enum rsidetone_enum =
617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
618
97945c46
SW		 619static const char *adcinput_text[] = {
620 "ADC", "DMIC"
621};
622
623static const struct soc_enum adcinput_enum =
624 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text);
625
1e113bf9
MB		 626static const char *aif_text[] = {
627 "Left", "Right"
628};
629
630static const struct soc_enum lcapture_enum =
631 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
632
633static const struct soc_enum rcapture_enum =
634 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
635
636static const struct soc_enum lplay_enum =
637 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
638
639static const struct soc_enum rplay_enum =
640 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
641
f1c0a02f
MB		 642static const struct snd_kcontrol_new wm8903_snd_controls[] = {
643
644/* Input PGAs - No TLV since the scale depends on PGA mode */
645SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 646 7, 1, 1),
f1c0a02f
MB		 647SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
648 0, 31, 0),
649SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
650 6, 1, 0),
651
652SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 653 7, 1, 1),
f1c0a02f
MB		 654SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
655 0, 31, 0),
656SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
657 6, 1, 0),
658
659/* ADCs */
dcf9ada3 660SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 661SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
662SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 663SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
664SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
665SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 666SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 667 drc_tlv_thresh),
668SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
669SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
670SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
671SOC_ENUM("DRC Attack Rate", drc_attack),
672SOC_ENUM("DRC Decay Rate", drc_decay),
673SOC_ENUM("DRC FF Delay", drc_ff_delay),
674SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
675SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 676SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 677SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
678SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
679SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 680SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 681SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
682
683SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
61bf35b9 684 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
f1c0a02f
MB		 685SOC_ENUM("ADC Companding Mode", adc_companding),
686SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
687
291ce18c
MB		 688SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
689 12, 0, digital_sidetone_tlv),
690
f1c0a02f 691/* DAC */
dcf9ada3 692SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 693SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
694 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
695SOC_ENUM("DAC Soft Mute Rate", soft_mute),
696SOC_ENUM("DAC Mute Mode", mute_mode),
697SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 698SOC_ENUM("DAC Companding Mode", dac_companding),
699SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 700SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
701 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 702
703/* Headphones */
704SOC_DOUBLE_R("Headphone Switch",
705 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
706 8, 1, 1),
707SOC_DOUBLE_R("Headphone ZC Switch",
708 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
709 6, 1, 0),
710SOC_DOUBLE_R_TLV("Headphone Volume",
711 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
712 0, 63, 0, out_tlv),
713
714/* Line out */
715SOC_DOUBLE_R("Line Out Switch",
716 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
717 8, 1, 1),
718SOC_DOUBLE_R("Line Out ZC Switch",
719 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
720 6, 1, 0),
721SOC_DOUBLE_R_TLV("Line Out Volume",
722 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
723 0, 63, 0, out_tlv),
724
725/* Speaker */
726SOC_DOUBLE_R("Speaker Switch",
727 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
728SOC_DOUBLE_R("Speaker ZC Switch",
729 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
730SOC_DOUBLE_R_TLV("Speaker Volume",
731 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
732 0, 63, 0, out_tlv),
733};
734
f1c0a02f
MB		 735static const struct snd_kcontrol_new linput_mode_mux =
736 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
737
738static const struct snd_kcontrol_new rinput_mode_mux =
739 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
740
741static const struct snd_kcontrol_new linput_mux =
742 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
743
744static const struct snd_kcontrol_new linput_inv_mux =
745 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
746
747static const struct snd_kcontrol_new rinput_mux =
748 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
749
750static const struct snd_kcontrol_new rinput_inv_mux =
751 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
752
291ce18c
MB		 753static const struct snd_kcontrol_new lsidetone_mux =
754 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
755
756static const struct snd_kcontrol_new rsidetone_mux =
757 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
758
97945c46
SW		 759static const struct snd_kcontrol_new adcinput_mux =
760 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
761
1e113bf9
MB		 762static const struct snd_kcontrol_new lcapture_mux =
763 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
764
765static const struct snd_kcontrol_new rcapture_mux =
766 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
767
768static const struct snd_kcontrol_new lplay_mux =
769 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
770
771static const struct snd_kcontrol_new rplay_mux =
772 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
773
f1c0a02f
MB		 774static const struct snd_kcontrol_new left_output_mixer[] = {
775SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
776SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
777SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 778SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 779};
780
781static const struct snd_kcontrol_new right_output_mixer[] = {
782SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
783SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
784SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 785SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 786};
787
788static const struct snd_kcontrol_new left_speaker_mixer[] = {
789SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
790SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
791SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
792SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 793 0, 1, 0),
f1c0a02f
MB		 794};
795
796static const struct snd_kcontrol_new right_speaker_mixer[] = {
797SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
798SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
799SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
800 1, 1, 0),
801SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 802 0, 1, 0),
f1c0a02f
MB		 803};
804
805static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
806SND_SOC_DAPM_INPUT("IN1L"),
807SND_SOC_DAPM_INPUT("IN1R"),
808SND_SOC_DAPM_INPUT("IN2L"),
809SND_SOC_DAPM_INPUT("IN2R"),
810SND_SOC_DAPM_INPUT("IN3L"),
811SND_SOC_DAPM_INPUT("IN3R"),
97945c46 812SND_SOC_DAPM_INPUT("DMICDAT"),
f1c0a02f
MB		 813
814SND_SOC_DAPM_OUTPUT("HPOUTL"),
815SND_SOC_DAPM_OUTPUT("HPOUTR"),
816SND_SOC_DAPM_OUTPUT("LINEOUTL"),
817SND_SOC_DAPM_OUTPUT("LINEOUTR"),
818SND_SOC_DAPM_OUTPUT("LOP"),
819SND_SOC_DAPM_OUTPUT("LON"),
820SND_SOC_DAPM_OUTPUT("ROP"),
821SND_SOC_DAPM_OUTPUT("RON"),
822
5032dc34 823SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
f1c0a02f
MB		 824
825SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
826SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
827 &linput_inv_mux),
828SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
829
830SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
831SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
832 &rinput_inv_mux),
833SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
834
835SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
836SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
837
97945c46
SW		 838SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
839SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
840
1e113bf9
MB		 841SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
842SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
843
844SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
845SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
846
847SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
848SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 849
291ce18c
MB		 850SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
851SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
852
1e113bf9
MB		 853SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
854SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
855
856SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
857SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
858
859SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
860SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 861
862SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
863 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
864SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
865 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
866
867SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
868 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
869SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
870 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
871
1b877cb5
DL		 872SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
873 1, 0, NULL, 0),
874SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 875 0, 0, NULL, 0),
876
1b877cb5 877SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 878 NULL, 0),
1b877cb5 879SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 880 NULL, 0),
881
882SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
883SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 884SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
885SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 886SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
887SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 888SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
889SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 890
891SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
892 NULL, 0),
893SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
894 NULL, 0),
1b877cb5
DL		 895SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
896 NULL, 0),
897SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 898 NULL, 0),
899SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
900 NULL, 0),
901SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
902 NULL, 0),
1b877cb5
DL		 903SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
904 NULL, 0),
905SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 906 NULL, 0),
907
c5b6a9fe
MB		 908SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
909SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
910 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
911SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
912 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
913SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
914 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
915SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
916 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 917
918SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
919 NULL, 0),
920SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
921 NULL, 0),
922
42768a12
MB		 923SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
924 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 925SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 926SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 927};
928
ecd01512 929static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 930
2c8be5a2 931 { "CLK_DSP", NULL, "CLK_SYS" },
5032dc34 932 { "MICBIAS", NULL, "CLK_SYS" },
2c8be5a2
MB		 933 { "HPL_DCS", NULL, "CLK_SYS" },
934 { "HPR_DCS", NULL, "CLK_SYS" },
935 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
936 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
937
f1c0a02f
MB		 938 { "Left Input Mux", "IN1L", "IN1L" },
939 { "Left Input Mux", "IN2L", "IN2L" },
940 { "Left Input Mux", "IN3L", "IN3L" },
941
942 { "Left Input Inverting Mux", "IN1L", "IN1L" },
943 { "Left Input Inverting Mux", "IN2L", "IN2L" },
944 { "Left Input Inverting Mux", "IN3L", "IN3L" },
945
946 { "Right Input Mux", "IN1R", "IN1R" },
947 { "Right Input Mux", "IN2R", "IN2R" },
948 { "Right Input Mux", "IN3R", "IN3R" },
949
950 { "Right Input Inverting Mux", "IN1R", "IN1R" },
951 { "Right Input Inverting Mux", "IN2R", "IN2R" },
952 { "Right Input Inverting Mux", "IN3R", "IN3R" },
953
954 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
955 { "Left Input Mode Mux", "Differential Line",
956 "Left Input Mux" },
957 { "Left Input Mode Mux", "Differential Line",
958 "Left Input Inverting Mux" },
959 { "Left Input Mode Mux", "Differential Mic",
960 "Left Input Mux" },
961 { "Left Input Mode Mux", "Differential Mic",
962 "Left Input Inverting Mux" },
963
964 { "Right Input Mode Mux", "Single-Ended",
965 "Right Input Inverting Mux" },
966 { "Right Input Mode Mux", "Differential Line",
967 "Right Input Mux" },
968 { "Right Input Mode Mux", "Differential Line",
969 "Right Input Inverting Mux" },
970 { "Right Input Mode Mux", "Differential Mic",
971 "Right Input Mux" },
972 { "Right Input Mode Mux", "Differential Mic",
973 "Right Input Inverting Mux" },
974
975 { "Left Input PGA", NULL, "Left Input Mode Mux" },
976 { "Right Input PGA", NULL, "Right Input Mode Mux" },
977
97945c46
SW		 978 { "Left ADC Input", "ADC", "Left Input PGA" },
979 { "Left ADC Input", "DMIC", "DMICDAT" },
980 { "Right ADC Input", "ADC", "Right Input PGA" },
981 { "Right ADC Input", "DMIC", "DMICDAT" },
982
1e113bf9
MB		 983 { "Left Capture Mux", "Left", "ADCL" },
984 { "Left Capture Mux", "Right", "ADCR" },
985
986 { "Right Capture Mux", "Left", "ADCL" },
987 { "Right Capture Mux", "Right", "ADCR" },
988
989 { "AIFTXL", NULL, "Left Capture Mux" },
990 { "AIFTXR", NULL, "Right Capture Mux" },
991
97945c46 992 { "ADCL", NULL, "Left ADC Input" },
c2aef4ff 993 { "ADCL", NULL, "CLK_DSP" },
97945c46 994 { "ADCR", NULL, "Right ADC Input" },
c2aef4ff
MB		 995 { "ADCR", NULL, "CLK_DSP" },
996
1e113bf9
MB		 997 { "Left Playback Mux", "Left", "AIFRXL" },
998 { "Left Playback Mux", "Right", "AIFRXR" },
999
1000 { "Right Playback Mux", "Left", "AIFRXL" },
1001 { "Right Playback Mux", "Right", "AIFRXR" },
1002
291ce18c
MB		 1003 { "DACL Sidetone", "Left", "ADCL" },
1004 { "DACL Sidetone", "Right", "ADCR" },
1005 { "DACR Sidetone", "Left", "ADCL" },
1006 { "DACR Sidetone", "Right", "ADCR" },
1007
1e113bf9 1008 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1009 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1010 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1011
1012 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1013 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1014 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1015
1016 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1017 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1018 { "Left Output Mixer", "DACL Switch", "DACL" },
1019 { "Left Output Mixer", "DACR Switch", "DACR" },
1020
1021 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1022 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1023 { "Right Output Mixer", "DACL Switch", "DACL" },
1024 { "Right Output Mixer", "DACR Switch", "DACR" },
1025
1026 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1027 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1028 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1029 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1030
1031 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1032 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1033 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1034 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1035
1036 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1037 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1038
1039 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1040 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1041
1042 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1043 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1044
1b877cb5
DL		 1045 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1046 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1047 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1048 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1049 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1050 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1051 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1052 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1053
c5b6a9fe
MB		 1054 { "HPL_DCS", NULL, "DCS Master" },
1055 { "HPR_DCS", NULL, "DCS Master" },
1056 { "LINEOUTL_DCS", NULL, "DCS Master" },
1057 { "LINEOUTR_DCS", NULL, "DCS Master" },
1058
13a9983e
MB		 1059 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1060 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1061 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1062 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1063
1064 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1065 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1066 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1067 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1068
1069 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1070 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1071 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1072 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1073
1074 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1075 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1076 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1077 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1078
1079 { "LOP", NULL, "Left Speaker PGA" },
1080 { "LON", NULL, "Left Speaker PGA" },
1081
1082 { "ROP", NULL, "Right Speaker PGA" },
1083 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1084
1085 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1086 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1087 { "Left Line Output PGA", NULL, "Charge Pump" },
1088 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1089};
1090
f1c0a02f
MB		 1091static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1092 enum snd_soc_bias_level level)
1093{
f1c0a02f
MB		 1094 switch (level) {
1095 case SND_SOC_BIAS_ON:
66daaa59 1096 break;
22f226dd 1097
f1c0a02f 1098 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1099 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1100 WM8903_VMID_RES_MASK,
1101 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1102 break;
1103
1104 case SND_SOC_BIAS_STANDBY:
ce6120cc 1105 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1106 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1107 WM8903_POBCTRL | WM8903_ISEL_MASK |
1108 WM8903_STARTUP_BIAS_ENA |
1109 WM8903_BIAS_ENA,
1110 WM8903_POBCTRL |
1111 (2 << WM8903_ISEL_SHIFT) |
1112 WM8903_STARTUP_BIAS_ENA);
1113
1114 snd_soc_update_bits(codec,
1115 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1116 WM8903_SPK_DISCHARGE,
1117 WM8903_SPK_DISCHARGE);
1118
1119 msleep(33);
1120
1121 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1122 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1123 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1124
1125 snd_soc_update_bits(codec,
1126 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1127 WM8903_SPK_DISCHARGE, 0);
1128
1129 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1130 WM8903_VMID_TIE_ENA |
1131 WM8903_BUFIO_ENA |
1132 WM8903_VMID_IO_ENA |
1133 WM8903_VMID_SOFT_MASK |
1134 WM8903_VMID_RES_MASK |
1135 WM8903_VMID_BUF_ENA,
1136 WM8903_VMID_TIE_ENA |
1137 WM8903_BUFIO_ENA |
1138 WM8903_VMID_IO_ENA |
1139 (2 << WM8903_VMID_SOFT_SHIFT) |
1140 WM8903_VMID_RES_250K |
1141 WM8903_VMID_BUF_ENA);
1142
1143 msleep(129);
1144
1145 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1146 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1147 0);
1148
1149 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1150 WM8903_VMID_SOFT_MASK, 0);
1151
1152 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1153 WM8903_VMID_RES_MASK,
1154 WM8903_VMID_RES_50K);
1155
1156 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1157 WM8903_BIAS_ENA | WM8903_POBCTRL,
1158 WM8903_BIAS_ENA);
f1c0a02f 1159
f1c0a02f
MB		 1160 /* By default no bypass paths are enabled so
1161 * enable Class W support.
1162 */
f0fba2ad 1163 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1164 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1165 WM8903_CP_DYN_FREQ |
1166 WM8903_CP_DYN_V,
1167 WM8903_CP_DYN_FREQ |
1168 WM8903_CP_DYN_V);
f1c0a02f
MB		 1169 }
1170
66daaa59
MB		 1171 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1172 WM8903_VMID_RES_MASK,
1173 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1174 break;
1175
1176 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1177 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1178 WM8903_BIAS_ENA, 0);
1179
1180 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1181 WM8903_VMID_SOFT_MASK,
1182 2 << WM8903_VMID_SOFT_SHIFT);
1183
1184 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1185 WM8903_VMID_BUF_ENA, 0);
1186
1187 msleep(290);
1188
1189 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1190 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1191 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1192 WM8903_VMID_SOFT_MASK |
1193 WM8903_VMID_BUF_ENA, 0);
1194
1195 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1196 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1197 break;
1198 }
1199
ce6120cc 1200 codec->dapm.bias_level = level;
f1c0a02f
MB		 1201
1202 return 0;
1203}
1204
1205static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1206 int clk_id, unsigned int freq, int dir)
1207{
1208 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1209 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1210
1211 wm8903->sysclk = freq;
1212
1213 return 0;
1214}
1215
1216static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1217 unsigned int fmt)
1218{
1219 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1220 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1221
1222 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1223 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1224
1225 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1226 case SND_SOC_DAIFMT_CBS_CFS:
1227 break;
1228 case SND_SOC_DAIFMT_CBS_CFM:
1229 aif1 |= WM8903_LRCLK_DIR;
1230 break;
1231 case SND_SOC_DAIFMT_CBM_CFM:
1232 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1233 break;
1234 case SND_SOC_DAIFMT_CBM_CFS:
1235 aif1 |= WM8903_BCLK_DIR;
1236 break;
1237 default:
1238 return -EINVAL;
1239 }
1240
1241 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1242 case SND_SOC_DAIFMT_DSP_A:
1243 aif1 |= 0x3;
1244 break;
1245 case SND_SOC_DAIFMT_DSP_B:
1246 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1247 break;
1248 case SND_SOC_DAIFMT_I2S:
1249 aif1 |= 0x2;
1250 break;
1251 case SND_SOC_DAIFMT_RIGHT_J:
1252 aif1 |= 0x1;
1253 break;
1254 case SND_SOC_DAIFMT_LEFT_J:
1255 break;
1256 default:
1257 return -EINVAL;
1258 }
1259
1260 /* Clock inversion */
1261 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1262 case SND_SOC_DAIFMT_DSP_A:
1263 case SND_SOC_DAIFMT_DSP_B:
1264 /* frame inversion not valid for DSP modes */
1265 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1266 case SND_SOC_DAIFMT_NB_NF:
1267 break;
1268 case SND_SOC_DAIFMT_IB_NF:
1269 aif1 |= WM8903_AIF_BCLK_INV;
1270 break;
1271 default:
1272 return -EINVAL;
1273 }
1274 break;
1275 case SND_SOC_DAIFMT_I2S:
1276 case SND_SOC_DAIFMT_RIGHT_J:
1277 case SND_SOC_DAIFMT_LEFT_J:
1278 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1279 case SND_SOC_DAIFMT_NB_NF:
1280 break;
1281 case SND_SOC_DAIFMT_IB_IF:
1282 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1283 break;
1284 case SND_SOC_DAIFMT_IB_NF:
1285 aif1 |= WM8903_AIF_BCLK_INV;
1286 break;
1287 case SND_SOC_DAIFMT_NB_IF:
1288 aif1 |= WM8903_AIF_LRCLK_INV;
1289 break;
1290 default:
1291 return -EINVAL;
1292 }
1293 break;
1294 default:
1295 return -EINVAL;
1296 }
1297
8d50e447 1298 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1299
1300 return 0;
1301}
1302
1303static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1304{
1305 struct snd_soc_codec *codec = codec_dai->codec;
1306 u16 reg;
1307
8d50e447 1308 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1309
1310 if (mute)
1311 reg |= WM8903_DAC_MUTE;
1312 else
1313 reg &= ~WM8903_DAC_MUTE;
1314
8d50e447 1315 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1316
1317 return 0;
1318}
1319
1320/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1321 * for optimal performance so we list the lower rates first and match
1322 * on the last match we find. */
1323static struct {
1324 int div;
1325 int rate;
1326 int mode;
1327 int mclk_div;
1328} clk_sys_ratios[] = {
1329 { 64, 0x0, 0x0, 1 },
1330 { 68, 0x0, 0x1, 1 },
1331 { 125, 0x0, 0x2, 1 },
1332 { 128, 0x1, 0x0, 1 },
1333 { 136, 0x1, 0x1, 1 },
1334 { 192, 0x2, 0x0, 1 },
1335 { 204, 0x2, 0x1, 1 },
1336
1337 { 64, 0x0, 0x0, 2 },
1338 { 68, 0x0, 0x1, 2 },
1339 { 125, 0x0, 0x2, 2 },
1340 { 128, 0x1, 0x0, 2 },
1341 { 136, 0x1, 0x1, 2 },
1342 { 192, 0x2, 0x0, 2 },
1343 { 204, 0x2, 0x1, 2 },
1344
1345 { 250, 0x2, 0x2, 1 },
1346 { 256, 0x3, 0x0, 1 },
1347 { 272, 0x3, 0x1, 1 },
1348 { 384, 0x4, 0x0, 1 },
1349 { 408, 0x4, 0x1, 1 },
1350 { 375, 0x4, 0x2, 1 },
1351 { 512, 0x5, 0x0, 1 },
1352 { 544, 0x5, 0x1, 1 },
1353 { 500, 0x5, 0x2, 1 },
1354 { 768, 0x6, 0x0, 1 },
1355 { 816, 0x6, 0x1, 1 },
1356 { 750, 0x6, 0x2, 1 },
1357 { 1024, 0x7, 0x0, 1 },
1358 { 1088, 0x7, 0x1, 1 },
1359 { 1000, 0x7, 0x2, 1 },
1360 { 1408, 0x8, 0x0, 1 },
1361 { 1496, 0x8, 0x1, 1 },
1362 { 1536, 0x9, 0x0, 1 },
1363 { 1632, 0x9, 0x1, 1 },
1364 { 1500, 0x9, 0x2, 1 },
1365
1366 { 250, 0x2, 0x2, 2 },
1367 { 256, 0x3, 0x0, 2 },
1368 { 272, 0x3, 0x1, 2 },
1369 { 384, 0x4, 0x0, 2 },
1370 { 408, 0x4, 0x1, 2 },
1371 { 375, 0x4, 0x2, 2 },
1372 { 512, 0x5, 0x0, 2 },
1373 { 544, 0x5, 0x1, 2 },
1374 { 500, 0x5, 0x2, 2 },
1375 { 768, 0x6, 0x0, 2 },
1376 { 816, 0x6, 0x1, 2 },
1377 { 750, 0x6, 0x2, 2 },
1378 { 1024, 0x7, 0x0, 2 },
1379 { 1088, 0x7, 0x1, 2 },
1380 { 1000, 0x7, 0x2, 2 },
1381 { 1408, 0x8, 0x0, 2 },
1382 { 1496, 0x8, 0x1, 2 },
1383 { 1536, 0x9, 0x0, 2 },
1384 { 1632, 0x9, 0x1, 2 },
1385 { 1500, 0x9, 0x2, 2 },
1386};
1387
1388/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1389static struct {
1390 int ratio;
1391 int div;
1392} bclk_divs[] = {
1393 { 10, 0 },
f1c0a02f
MB		 1394 { 20, 2 },
1395 { 30, 3 },
1396 { 40, 4 },
1397 { 50, 5 },
f1c0a02f
MB		 1398 { 60, 7 },
1399 { 80, 8 },
1400 { 100, 9 },
f1c0a02f
MB		 1401 { 120, 11 },
1402 { 160, 12 },
1403 { 200, 13 },
1404 { 220, 14 },
1405 { 240, 15 },
f1c0a02f
MB		 1406 { 300, 17 },
1407 { 320, 18 },
1408 { 440, 19 },
1409 { 480, 20 },
1410};
1411
1412/* Sample rates for DSP */
1413static struct {
1414 int rate;
1415 int value;
1416} sample_rates[] = {
1417 { 8000, 0 },
1418 { 11025, 1 },
1419 { 12000, 2 },
1420 { 16000, 3 },
1421 { 22050, 4 },
1422 { 24000, 5 },
1423 { 32000, 6 },
1424 { 44100, 7 },
1425 { 48000, 8 },
1426 { 88200, 9 },
1427 { 96000, 10 },
1428 { 0, 0 },
1429};
1430
f1c0a02f 1431static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1432 struct snd_pcm_hw_params *params,
1433 struct snd_soc_dai *dai)
f1c0a02f
MB		 1434{
1435 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1436 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1437 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1438 int fs = params_rate(params);
1439 int bclk;
1440 int bclk_div;
1441 int i;
1442 int dsp_config;
1443 int clk_config;
1444 int best_val;
1445 int cur_val;
1446 int clk_sys;
1447
8d50e447
MB		 1448 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1449 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1450 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1451 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1452 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1453 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1454
9e79261f
MB		 1455 /* Enable sloping stopband filter for low sample rates */
1456 if (fs <= 24000)
1457 dac_digital1 |= WM8903_DAC_SB_FILT;
1458 else
1459 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1460
f1c0a02f
MB		 1461 /* Configure sample rate logic for DSP - choose nearest rate */
1462 dsp_config = 0;
1463 best_val = abs(sample_rates[dsp_config].rate - fs);
1464 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1465 cur_val = abs(sample_rates[i].rate - fs);
1466 if (cur_val <= best_val) {
1467 dsp_config = i;
1468 best_val = cur_val;
1469 }
1470 }
1471
f0fba2ad 1472 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1473 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1474 clock1 |= sample_rates[dsp_config].value;
1475
1476 aif1 &= ~WM8903_AIF_WL_MASK;
1477 bclk = 2 * fs;
1478 switch (params_format(params)) {
1479 case SNDRV_PCM_FORMAT_S16_LE:
1480 bclk *= 16;
1481 break;
1482 case SNDRV_PCM_FORMAT_S20_3LE:
1483 bclk *= 20;
1484 aif1 |= 0x4;
1485 break;
1486 case SNDRV_PCM_FORMAT_S24_LE:
1487 bclk *= 24;
1488 aif1 |= 0x8;
1489 break;
1490 case SNDRV_PCM_FORMAT_S32_LE:
1491 bclk *= 32;
1492 aif1 |= 0xc;
1493 break;
1494 default:
1495 return -EINVAL;
1496 }
1497
f0fba2ad 1498 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1499 wm8903->sysclk, fs);
1500
1501 /* We may not have an MCLK which allows us to generate exactly
1502 * the clock we want, particularly with USB derived inputs, so
1503 * approximate.
1504 */
1505 clk_config = 0;
1506 best_val = abs((wm8903->sysclk /
1507 (clk_sys_ratios[0].mclk_div *
1508 clk_sys_ratios[0].div)) - fs);
1509 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1510 cur_val = abs((wm8903->sysclk /
1511 (clk_sys_ratios[i].mclk_div *
1512 clk_sys_ratios[i].div)) - fs);
1513
1514 if (cur_val <= best_val) {
1515 clk_config = i;
1516 best_val = cur_val;
1517 }
1518 }
1519
1520 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1521 clock0 |= WM8903_MCLKDIV2;
1522 clk_sys = wm8903->sysclk / 2;
1523 } else {
1524 clock0 &= ~WM8903_MCLKDIV2;
1525 clk_sys = wm8903->sysclk;
1526 }
1527
1528 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1529 WM8903_CLK_SYS_MODE_MASK);
1530 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1531 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1532
f0fba2ad 1533 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1534 clk_sys_ratios[clk_config].rate,
1535 clk_sys_ratios[clk_config].mode,
1536 clk_sys_ratios[clk_config].div);
1537
f0fba2ad 1538 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1539
1540 /* We may not get quite the right frequency if using
1541 * approximate clocks so look for the closest match that is
1542 * higher than the target (we need to ensure that there enough
1543 * BCLKs to clock out the samples).
1544 */
1545 bclk_div = 0;
1546 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1547 i = 1;
1548 while (i < ARRAY_SIZE(bclk_divs)) {
1549 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1550 if (cur_val < 0) /* BCLK table is sorted */
1551 break;
1552 bclk_div = i;
1553 best_val = cur_val;
1554 i++;
1555 }
1556
1557 aif2 &= ~WM8903_BCLK_DIV_MASK;
1558 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1559
f0fba2ad 1560 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1561 bclk_divs[bclk_div].ratio / 10, bclk,
1562 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1563
1564 aif2 |= bclk_divs[bclk_div].div;
1565 aif3 |= bclk / fs;
1566
69fff9bb
MB		 1567 wm8903->fs = params_rate(params);
1568 wm8903_set_deemph(codec);
1569
8d50e447
MB		 1570 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1571 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1572 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1573 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1574 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1575 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1576
1577 return 0;
1578}
1579
7245387e
MB		 1580/**
1581 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1582 *
1583 * @codec: WM8903 codec
1584 * @jack: jack to report detection events on
1585 * @det: value to report for presence detection
1586 * @shrt: value to report for short detection
1587 *
1588 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1589 * being used to bring out signals to the processor then only platform
1590 * data configuration is needed for WM8903 and processor GPIOs should
1591 * be configured using snd_soc_jack_add_gpios() instead.
1592 *
1593 * The current threasholds for detection should be configured using
1594 * micdet_cfg in the platform data. Using this function will force on
1595 * the microphone bias for the device.
1596 */
1597int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1598 int det, int shrt)
1599{
b2c812e2 1600 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1601 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1602
1603 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1604 det, shrt);
1605
1606 /* Store the configuration */
1607 wm8903->mic_jack = jack;
1608 wm8903->mic_det = det;
1609 wm8903->mic_short = shrt;
1610
1611 /* Enable interrupts we've got a report configured for */
1612 if (det)
1613 irq_mask &= ~WM8903_MICDET_EINT;
1614 if (shrt)
1615 irq_mask &= ~WM8903_MICSHRT_EINT;
1616
1617 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1618 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1619 irq_mask);
1620
3088e3b4 1621 if (det || shrt) {
69266866
MB		 1622 /* Enable mic detection, this may not have been set through
1623 * platform data (eg, if the defaults are OK). */
1624 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1625 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1626 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1627 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1628 } else {
1629 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1630 WM8903_MICDET_ENA, 0);
1631 }
7245387e
MB		 1632
1633 return 0;
1634}
1635EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1636
8abd16a6
MB		 1637static irqreturn_t wm8903_irq(int irq, void *data)
1638{
f0fba2ad
LG		 1639 struct snd_soc_codec *codec = data;
1640 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1641 int mic_report;
1642 int int_pol;
1643 int int_val = 0;
1644 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1645
7245387e 1646 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1647
7245387e 1648 if (int_val & WM8903_WSEQ_BUSY_EINT) {
b4d06f45 1649 dev_warn(codec->dev, "Write sequencer done\n");
8abd16a6
MB		 1650 }
1651
7245387e
MB		 1652 /*
1653 * The rest is microphone jack detection. We need to manually
1654 * invert the polarity of the interrupt after each event - to
1655 * simplify the code keep track of the last state we reported
1656 * and just invert the relevant bits in both the report and
1657 * the polarity register.
1658 */
1659 mic_report = wm8903->mic_last_report;
1660 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1661
1435b940 1662#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1663 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1664 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1665#endif
2bbb5d66 1666
7245387e
MB		 1667 if (int_val & WM8903_MICSHRT_EINT) {
1668 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1669
1670 mic_report ^= wm8903->mic_short;
1671 int_pol ^= WM8903_MICSHRT_INV;
1672 }
1673
1674 if (int_val & WM8903_MICDET_EINT) {
1675 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1676
1677 mic_report ^= wm8903->mic_det;
1678 int_pol ^= WM8903_MICDET_INV;
1679
1680 msleep(wm8903->mic_delay);
1681 }
1682
1683 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1684 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1685
1686 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1687 wm8903->mic_short | wm8903->mic_det);
1688
1689 wm8903->mic_last_report = mic_report;
1690
8abd16a6
MB		 1691 return IRQ_HANDLED;
1692}
1693
f1c0a02f
MB		 1694#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1695 SNDRV_PCM_RATE_11025 | \
1696 SNDRV_PCM_RATE_16000 | \
1697 SNDRV_PCM_RATE_22050 | \
1698 SNDRV_PCM_RATE_32000 | \
1699 SNDRV_PCM_RATE_44100 | \
1700 SNDRV_PCM_RATE_48000 | \
1701 SNDRV_PCM_RATE_88200 | \
1702 SNDRV_PCM_RATE_96000)
1703
1704#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1705 SNDRV_PCM_RATE_11025 | \
1706 SNDRV_PCM_RATE_16000 | \
1707 SNDRV_PCM_RATE_22050 | \
1708 SNDRV_PCM_RATE_32000 | \
1709 SNDRV_PCM_RATE_44100 | \
1710 SNDRV_PCM_RATE_48000)
1711
1712#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1713 SNDRV_PCM_FMTBIT_S20_3LE |\
1714 SNDRV_PCM_FMTBIT_S24_LE)
1715
85e7652d 1716static const struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1717 .hw_params = wm8903_hw_params,
1718 .digital_mute = wm8903_digital_mute,
1719 .set_fmt = wm8903_set_dai_fmt,
1720 .set_sysclk = wm8903_set_dai_sysclk,
1721};
1722
f0fba2ad
LG		 1723static struct snd_soc_dai_driver wm8903_dai = {
1724 .name = "wm8903-hifi",
f1c0a02f
MB		 1725 .playback = {
1726 .stream_name = "Playback",
1727 .channels_min = 2,
1728 .channels_max = 2,
1729 .rates = WM8903_PLAYBACK_RATES,
1730 .formats = WM8903_FORMATS,
1731 },
1732 .capture = {
1733 .stream_name = "Capture",
1734 .channels_min = 2,
1735 .channels_max = 2,
1736 .rates = WM8903_CAPTURE_RATES,
1737 .formats = WM8903_FORMATS,
1738 },
6335d055 1739 .ops = &wm8903_dai_ops,
0d960e88 1740 .symmetric_rates = 1,
f1c0a02f 1741};
f1c0a02f 1742
84b315ee 1743static int wm8903_suspend(struct snd_soc_codec *codec)
f1c0a02f 1744{
f1c0a02f
MB		 1745 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1746
1747 return 0;
1748}
1749
f0fba2ad 1750static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1751{
45e96755 1752 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f 1753
ee244ce4 1754 regcache_sync(wm8903->regmap);
f1c0a02f 1755
45e96755 1756 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1757
1758 return 0;
1759}
1760
7cfe5617
SW		 1761#ifdef CONFIG_GPIOLIB
1762static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1763{
1764 return container_of(chip, struct wm8903_priv, gpio_chip);
1765}
1766
1767static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1768{
1769 if (offset >= WM8903_NUM_GPIO)
1770 return -EINVAL;
1771
1772 return 0;
1773}
1774
1775static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1776{
1777 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1778 struct snd_soc_codec *codec = wm8903->codec;
1779 unsigned int mask, val;
1780
1781 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1782 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1783 WM8903_GP1_DIR;
1784
1785 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1786 mask, val);
1787}
1788
1789static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1790{
1791 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1792 struct snd_soc_codec *codec = wm8903->codec;
1793 int reg;
1794
1795 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1796
1797 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1798}
1799
1800static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1801 unsigned offset, int value)
1802{
1803 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1804 struct snd_soc_codec *codec = wm8903->codec;
1805 unsigned int mask, val;
1806
1807 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1808 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1809 (value << WM8903_GP2_LVL_SHIFT);
1810
1811 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1812 mask, val);
1813}
1814
1815static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1816{
1817 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1818 struct snd_soc_codec *codec = wm8903->codec;
1819
1820 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1821 WM8903_GP1_LVL_MASK,
1822 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1823}
1824
1825static struct gpio_chip wm8903_template_chip = {
1826 .label = "wm8903",
1827 .owner = THIS_MODULE,
1828 .request = wm8903_gpio_request,
1829 .direction_input = wm8903_gpio_direction_in,
1830 .get = wm8903_gpio_get,
1831 .direction_output = wm8903_gpio_direction_out,
1832 .set = wm8903_gpio_set,
1833 .can_sleep = 1,
1834};
1835
1836static void wm8903_init_gpio(struct snd_soc_codec *codec)
1837{
1838 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
c0eb27cf 1839 struct wm8903_platform_data *pdata = wm8903->pdata;
7cfe5617
SW		 1840 int ret;
1841
1842 wm8903->gpio_chip = wm8903_template_chip;
1843 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1844 wm8903->gpio_chip.dev = codec->dev;
1845
db817784 1846 if (pdata->gpio_base)
7cfe5617
SW		 1847 wm8903->gpio_chip.base = pdata->gpio_base;
1848 else
1849 wm8903->gpio_chip.base = -1;
1850
1851 ret = gpiochip_add(&wm8903->gpio_chip);
1852 if (ret != 0)
1853 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1854}
1855
1856static void wm8903_free_gpio(struct snd_soc_codec *codec)
1857{
1858 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1859 int ret;
1860
1861 ret = gpiochip_remove(&wm8903->gpio_chip);
1862 if (ret != 0)
1863 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1864}
1865#else
1866static void wm8903_init_gpio(struct snd_soc_codec *codec)
1867{
1868}
1869
1870static void wm8903_free_gpio(struct snd_soc_codec *codec)
1871{
1872}
1873#endif
1874
f0fba2ad 1875static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1876{
f0fba2ad 1877 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
c0eb27cf 1878 struct wm8903_platform_data *pdata = wm8903->pdata;
73b34ead 1879 int ret, i;
8abd16a6 1880 int trigger, irq_pol;
f1c0a02f 1881 u16 val;
db817784 1882 bool mic_gpio = false;
f1c0a02f 1883
7cfe5617 1884 wm8903->codec = codec;
ee244ce4 1885 codec->control_data = wm8903->regmap;
d58d5d55 1886
ee244ce4 1887 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
8d50e447 1888 if (ret != 0) {
f0fba2ad
LG		 1889 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1890 return ret;
8d50e447
MB		 1891 }
1892
db817784
SW		 1893 /* Set up GPIOs, detect if any are MIC detect outputs */
1894 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1895 if ((!pdata->gpio_cfg[i]) ||
1896 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))
1897 continue;
905f6952 1898
db817784
SW		 1899 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1900 pdata->gpio_cfg[i] & 0x7fff);
905f6952 1901
db817784
SW		 1902 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
1903 >> WM8903_GP1_FN_SHIFT;
905f6952 1904
db817784
SW		 1905 switch (val) {
1906 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
1907 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
1908 mic_gpio = true;
1909 break;
1910 default:
1911 break;
73b34ead 1912 }
db817784
SW		 1913 }
1914
1915 /* Set up microphone detection */
1916 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1917 pdata->micdet_cfg);
37f88e84 1918
db817784
SW		 1919 /* Microphone detection needs the WSEQ clock */
1920 if (pdata->micdet_cfg)
1921 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1922 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
37f88e84 1923
db817784
SW		 1924 /* If microphone detection is enabled by pdata but
1925 * detected via IRQ then interrupts can be lost before
1926 * the machine driver has set up microphone detection
1927 * IRQs as the IRQs are clear on read. The detection
1928 * will be enabled when the machine driver configures.
1929 */
1930 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
37f88e84 1931
db817784 1932 wm8903->mic_delay = pdata->micdet_delay;
905f6952 1933
f0fba2ad 1934 if (wm8903->irq) {
db817784 1935 if (pdata->irq_active_low) {
8abd16a6
MB		 1936 trigger = IRQF_TRIGGER_LOW;
1937 irq_pol = WM8903_IRQ_POL;
1938 } else {
1939 trigger = IRQF_TRIGGER_HIGH;
1940 irq_pol = 0;
1941 }
1942
1943 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1944 WM8903_IRQ_POL, irq_pol);
1945
f0fba2ad 1946 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1947 trigger | IRQF_ONESHOT,
f0fba2ad 1948 "wm8903", codec);
8abd16a6 1949 if (ret != 0) {
f0fba2ad 1950 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1951 ret);
f0fba2ad 1952 return ret;
8abd16a6
MB		 1953 }
1954
1955 /* Enable write sequencer interrupts */
1956 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1957 WM8903_IM_WSEQ_BUSY_EINT, 0);
1958 }
73b34ead 1959
f1c0a02f
MB		 1960 /* power on device */
1961 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1962
1963 /* Latch volume update bits */
8d50e447 1964 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1965 val |= WM8903_ADCVU;
8d50e447
MB		 1966 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1967 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1968
8d50e447 1969 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1970 val |= WM8903_DACVU;
8d50e447
MB		 1971 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1972 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1973
8d50e447 1974 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1975 val |= WM8903_HPOUTVU;
8d50e447
MB		 1976 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1977 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1978
8d50e447 1979 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1980 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1981 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1982 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1983
8d50e447 1984 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1985 val |= WM8903_SPKVU;
8d50e447
MB		 1986 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1987 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1988
1989 /* Enable DAC soft mute by default */
e12adab0
MB		 1990 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
1991 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
1992 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 1993
7cfe5617
SW		 1994 wm8903_init_gpio(codec);
1995
f1c0a02f
MB		 1996 return ret;
1997}
1998
f0fba2ad
LG		 1999/* power down chip */
2000static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2001{
f99847a6
SW		 2002 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
2003
7cfe5617 2004 wm8903_free_gpio(codec);
f0fba2ad 2005 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f99847a6
SW		 2006 if (wm8903->irq)
2007 free_irq(wm8903->irq, codec);
2008
f0fba2ad
LG		 2009 return 0;
2010}
f1c0a02f 2011
f0fba2ad
LG		 2012static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2013 .probe = wm8903_probe,
2014 .remove = wm8903_remove,
2015 .suspend = wm8903_suspend,
2016 .resume = wm8903_resume,
2017 .set_bias_level = wm8903_set_bias_level,
c5b6a9fe 2018 .seq_notifier = wm8903_seq_notifier,
f4a10837
MB		 2019 .controls = wm8903_snd_controls,
2020 .num_controls = ARRAY_SIZE(wm8903_snd_controls),
ecd01512
MB		 2021 .dapm_widgets = wm8903_dapm_widgets,
2022 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
2023 .dapm_routes = wm8903_intercon,
2024 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 2025};
f1c0a02f 2026
ee244ce4
MB		 2027static const struct regmap_config wm8903_regmap = {
2028 .reg_bits = 8,
2029 .val_bits = 16,
2030
2031 .max_register = WM8903_MAX_REGISTER,
2032 .volatile_reg = wm8903_volatile_register,
2033 .readable_reg = wm8903_readable_register,
2034
2035 .cache_type = REGCACHE_RBTREE,
2036 .reg_defaults = wm8903_reg_defaults,
2037 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
2038};
2039
9d35f3e1
SW		 2040static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c,
2041 struct wm8903_platform_data *pdata)
2042{
2043 struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
2044 if (!irq_data) {
2045 dev_err(&i2c->dev, "Invalid IRQ: %d\n",
2046 i2c->irq);
2047 return -EINVAL;
2048 }
2049
2050 switch (irqd_get_trigger_type(irq_data)) {
2051 case IRQ_TYPE_NONE:
2052 /*
2053 * We assume the controller imposes no restrictions,
2054 * so we are able to select active-high
2055 */
2056 /* Fall-through */
2057 case IRQ_TYPE_LEVEL_HIGH:
2058 pdata->irq_active_low = false;
2059 break;
2060 case IRQ_TYPE_LEVEL_LOW:
2061 pdata->irq_active_low = true;
2062 break;
2063 default:
2064 dev_err(&i2c->dev,
2065 "Unsupported IRQ_TYPE %x\n",
2066 irqd_get_trigger_type(irq_data));
2067 return -EINVAL;
2068 }
2069
2070 return 0;
2071}
2072
5d680b3a
SW		 2073static int wm8903_set_pdata_from_of(struct i2c_client *i2c,
2074 struct wm8903_platform_data *pdata)
2075{
2076 const struct device_node *np = i2c->dev.of_node;
2077 u32 val32;
2078 int i;
2079
2080 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0)
2081 pdata->micdet_cfg = val32;
2082
2083 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0)
2084 pdata->micdet_delay = val32;
2085
2086 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg,
2087 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) {
2088 /*
2089 * In device tree: 0 means "write 0",
2090 * 0xffffffff means "don't touch".
2091 *
2092 * In platform data: 0 means "don't touch",
2093 * 0x8000 means "write 0".
2094 *
2095 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
2096 *
2097 * Convert from DT to pdata representation here,
2098 * so no other code needs to change.
2099 */
2100 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
2101 if (pdata->gpio_cfg[i] == 0) {
2102 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO;
2103 } else if (pdata->gpio_cfg[i] == 0xffffffff) {
2104 pdata->gpio_cfg[i] = 0;
2105 } else if (pdata->gpio_cfg[i] > 0x7fff) {
2106 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n",
2107 i, pdata->gpio_cfg[i]);
2108 return -EINVAL;
2109 }
2110 }
2111 }
2112
2113 return 0;
2114}
2115
f0fba2ad
LG		 2116static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2117 const struct i2c_device_id *id)
2118{
c0eb27cf 2119 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
f0fba2ad 2120 struct wm8903_priv *wm8903;
7d46a528 2121 unsigned int val;
f0fba2ad 2122 int ret;
f1c0a02f 2123
2950cd22
MB		 2124 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv),
2125 GFP_KERNEL);
f0fba2ad
LG		 2126 if (wm8903 == NULL)
2127 return -ENOMEM;
8abd16a6 2128
ee244ce4
MB		 2129 wm8903->regmap = regmap_init_i2c(i2c, &wm8903_regmap);
2130 if (IS_ERR(wm8903->regmap)) {
2131 ret = PTR_ERR(wm8903->regmap);
2132 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2133 ret);
2134 return ret;
2135 }
2136
f0fba2ad 2137 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2138 wm8903->irq = i2c->irq;
d58d5d55 2139
c0eb27cf
SW		 2140 /* If no platform data was supplied, create storage for defaults */
2141 if (pdata) {
2142 wm8903->pdata = pdata;
2143 } else {
2144 wm8903->pdata = devm_kzalloc(&i2c->dev,
2145 sizeof(struct wm8903_platform_data),
2146 GFP_KERNEL);
2147 if (wm8903->pdata == NULL) {
2148 dev_err(&i2c->dev, "Failed to allocate pdata\n");
2149 return -ENOMEM;
2150 }
9d35f3e1
SW		 2151
2152 if (i2c->irq) {
2153 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata);
2154 if (ret != 0)
2155 return ret;
2156 }
5d680b3a
SW		 2157
2158 if (i2c->dev.of_node) {
2159 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata);
2160 if (ret != 0)
2161 return ret;
2162 }
c0eb27cf
SW		 2163 }
2164
7d46a528
MB		 2165 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
2166 if (ret != 0) {
2167 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
2168 goto err;
2169 }
2170 if (val != 0x8903) {
2171 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
2172 ret = -ENODEV;
2173 goto err;
2174 }
2175
2176 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
2177 if (ret != 0) {
2178 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
2179 goto err;
2180 }
2181 dev_info(&i2c->dev, "WM8903 revision %c\n",
2182 (val & WM8903_CHIP_REV_MASK) + 'A');
2183
2184 /* Reset the device */
2185 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
2186
f0fba2ad
LG		 2187 ret = snd_soc_register_codec(&i2c->dev,
2188 &soc_codec_dev_wm8903, &wm8903_dai, 1);
ee244ce4
MB		 2189 if (ret != 0)
2190 goto err;
2950cd22 2191
ee244ce4
MB		 2192 return 0;
2193err:
2194 regmap_exit(wm8903->regmap);
f0fba2ad
LG		 2195 return ret;
2196}
f1c0a02f 2197
f0fba2ad
LG		 2198static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2199{
ee244ce4
MB		 2200 struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
2201
2202 regmap_exit(wm8903->regmap);
f0fba2ad 2203 snd_soc_unregister_codec(&client->dev);
ee244ce4 2204
f1c0a02f
MB		 2205 return 0;
2206}
2207
f1c0a02f 2208static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2209 { "wm8903", 0 },
2210 { }
f1c0a02f
MB		 2211};
2212MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2213
2214static struct i2c_driver wm8903_i2c_driver = {
2215 .driver = {
4b592c91 2216 .name = "wm8903",
f1c0a02f
MB		 2217 .owner = THIS_MODULE,
2218 },
f0fba2ad
LG		 2219 .probe = wm8903_i2c_probe,
2220 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2221 .id_table = wm8903_i2c_id,
2222};
2223
f0fba2ad 2224static int __init wm8903_modinit(void)
f1c0a02f 2225{
f1c0a02f 2226 int ret = 0;
f0fba2ad
LG		 2227 ret = i2c_add_driver(&wm8903_i2c_driver);
2228 if (ret != 0) {
2229 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2230 ret);
f1c0a02f 2231 }
f1c0a02f 2232 return ret;
64089b84
MB		 2233}
2234module_init(wm8903_modinit);
2235
2236static void __exit wm8903_exit(void)
2237{
d58d5d55 2238 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 2239}
2240module_exit(wm8903_exit);
2241
f1c0a02f
MB		 2242MODULE_DESCRIPTION("ASoC WM8903 driver");
2243MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2244MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.249772 seconds and 5 git commands to generate.