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Merge branch 'for-3.2' into for-3.3
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
ee244ce4 26#include <linux/regmap.h>
5a0e3ad6 27#include <linux/slab.h>
f1c0a02f 28#include <sound/core.h>
7245387e 29#include <sound/jack.h>
f1c0a02f
MB		 30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/tlv.h>
33#include <sound/soc.h>
f1c0a02f 34#include <sound/initval.h>
8abd16a6 35#include <sound/wm8903.h>
2bbb5d66 36#include <trace/events/asoc.h>
f1c0a02f
MB		 37
38#include "wm8903.h"
39
f1c0a02f 40/* Register defaults at reset */
ee244ce4
MB		 41static const struct reg_default wm8903_reg_defaults[] = {
42 { 4, 0x0018 }, /* R4 - Bias Control 0 */
43 { 5, 0x0000 }, /* R5 - VMID Control 0 */
44 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
45 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
46 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
47 { 12, 0x0000 }, /* R12 - Power Management 0 */
48 { 13, 0x0000 }, /* R13 - Power Management 1 */
49 { 14, 0x0000 }, /* R14 - Power Management 2 */
50 { 15, 0x0000 }, /* R15 - Power Management 3 */
51 { 16, 0x0000 }, /* R16 - Power Management 4 */
52 { 17, 0x0000 }, /* R17 - Power Management 5 */
53 { 18, 0x0000 }, /* R18 - Power Management 6 */
54 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
55 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
56 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
57 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
58 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
59 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
60 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
61 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
62 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
63 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
64 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
65 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
66 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
67 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
68 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
69 { 40, 0x09BF }, /* R40 - DRC 0 */
70 { 41, 0x3241 }, /* R41 - DRC 1 */
71 { 42, 0x0020 }, /* R42 - DRC 2 */
72 { 43, 0x0000 }, /* R43 - DRC 3 */
73 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
74 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
75 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
76 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
77 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
78 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
79 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
80 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
81 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
82 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
83 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
84 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
85 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
86 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
87 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
88 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
89 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
90 { 67, 0x0010 }, /* R67 - DC Servo 0 */
91 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
92 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
93 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
94 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
95 { 104, 0x0000 }, /* R104 - Class W 0 */
96 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
97 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
98 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
99 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
100 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
101 { 114, 0x0000 }, /* R114 - Control Interface */
102 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
103 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
104 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
105 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
106 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
107 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
108 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
109 { 126, 0x0000 }, /* R126 - Interrupt Control */
110 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
111 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
112 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
113 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
f1c0a02f
MB		 114};
115
d58d5d55 116struct wm8903_priv {
7cfe5617 117 struct snd_soc_codec *codec;
ee244ce4 118 struct regmap *regmap;
f0fba2ad 119
d58d5d55 120 int sysclk;
f0fba2ad 121 int irq;
d58d5d55 122
69fff9bb
MB		 123 int fs;
124 int deemph;
125
c5b6a9fe
MB		 126 int dcs_pending;
127 int dcs_cache[4];
128
f2c1fe09 129 /* Reference count */
d58d5d55 130 int class_w_users;
d58d5d55 131
7245387e
MB		 132 struct snd_soc_jack *mic_jack;
133 int mic_det;
134 int mic_short;
135 int mic_last_report;
136 int mic_delay;
7cfe5617
SW		 137
138#ifdef CONFIG_GPIOLIB
139 struct gpio_chip gpio_chip;
140#endif
d58d5d55
MB		 141};
142
ee244ce4
MB		 143static bool wm8903_readable_register(struct device *dev, unsigned int reg)
144{
145 switch (reg) {
146 case WM8903_SW_RESET_AND_ID:
147 case WM8903_REVISION_NUMBER:
148 case WM8903_BIAS_CONTROL_0:
149 case WM8903_VMID_CONTROL_0:
150 case WM8903_MIC_BIAS_CONTROL_0:
151 case WM8903_ANALOGUE_DAC_0:
152 case WM8903_ANALOGUE_ADC_0:
153 case WM8903_POWER_MANAGEMENT_0:
154 case WM8903_POWER_MANAGEMENT_1:
155 case WM8903_POWER_MANAGEMENT_2:
156 case WM8903_POWER_MANAGEMENT_3:
157 case WM8903_POWER_MANAGEMENT_4:
158 case WM8903_POWER_MANAGEMENT_5:
159 case WM8903_POWER_MANAGEMENT_6:
160 case WM8903_CLOCK_RATES_0:
161 case WM8903_CLOCK_RATES_1:
162 case WM8903_CLOCK_RATES_2:
163 case WM8903_AUDIO_INTERFACE_0:
164 case WM8903_AUDIO_INTERFACE_1:
165 case WM8903_AUDIO_INTERFACE_2:
166 case WM8903_AUDIO_INTERFACE_3:
167 case WM8903_DAC_DIGITAL_VOLUME_LEFT:
168 case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
169 case WM8903_DAC_DIGITAL_0:
170 case WM8903_DAC_DIGITAL_1:
171 case WM8903_ADC_DIGITAL_VOLUME_LEFT:
172 case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
173 case WM8903_ADC_DIGITAL_0:
174 case WM8903_DIGITAL_MICROPHONE_0:
175 case WM8903_DRC_0:
176 case WM8903_DRC_1:
177 case WM8903_DRC_2:
178 case WM8903_DRC_3:
179 case WM8903_ANALOGUE_LEFT_INPUT_0:
180 case WM8903_ANALOGUE_RIGHT_INPUT_0:
181 case WM8903_ANALOGUE_LEFT_INPUT_1:
182 case WM8903_ANALOGUE_RIGHT_INPUT_1:
183 case WM8903_ANALOGUE_LEFT_MIX_0:
184 case WM8903_ANALOGUE_RIGHT_MIX_0:
185 case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
186 case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
187 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
188 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
189 case WM8903_ANALOGUE_OUT1_LEFT:
190 case WM8903_ANALOGUE_OUT1_RIGHT:
191 case WM8903_ANALOGUE_OUT2_LEFT:
192 case WM8903_ANALOGUE_OUT2_RIGHT:
193 case WM8903_ANALOGUE_OUT3_LEFT:
194 case WM8903_ANALOGUE_OUT3_RIGHT:
195 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
196 case WM8903_DC_SERVO_0:
197 case WM8903_DC_SERVO_2:
198 case WM8903_DC_SERVO_READBACK_1:
199 case WM8903_DC_SERVO_READBACK_2:
200 case WM8903_DC_SERVO_READBACK_3:
201 case WM8903_DC_SERVO_READBACK_4:
202 case WM8903_ANALOGUE_HP_0:
203 case WM8903_ANALOGUE_LINEOUT_0:
204 case WM8903_CHARGE_PUMP_0:
205 case WM8903_CLASS_W_0:
206 case WM8903_WRITE_SEQUENCER_0:
207 case WM8903_WRITE_SEQUENCER_1:
208 case WM8903_WRITE_SEQUENCER_2:
209 case WM8903_WRITE_SEQUENCER_3:
210 case WM8903_WRITE_SEQUENCER_4:
211 case WM8903_CONTROL_INTERFACE:
212 case WM8903_GPIO_CONTROL_1:
213 case WM8903_GPIO_CONTROL_2:
214 case WM8903_GPIO_CONTROL_3:
215 case WM8903_GPIO_CONTROL_4:
216 case WM8903_GPIO_CONTROL_5:
217 case WM8903_INTERRUPT_STATUS_1:
218 case WM8903_INTERRUPT_STATUS_1_MASK:
219 case WM8903_INTERRUPT_POLARITY_1:
220 case WM8903_INTERRUPT_CONTROL:
221 case WM8903_CLOCK_RATE_TEST_4:
222 case WM8903_ANALOGUE_OUTPUT_BIAS_0:
223 return true;
224 default:
225 return false;
226 }
227}
228
229static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
f1c0a02f
MB		 230{
231 switch (reg) {
232 case WM8903_SW_RESET_AND_ID:
233 case WM8903_REVISION_NUMBER:
234 case WM8903_INTERRUPT_STATUS_1:
235 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 236 case WM8903_DC_SERVO_READBACK_1:
237 case WM8903_DC_SERVO_READBACK_2:
238 case WM8903_DC_SERVO_READBACK_3:
239 case WM8903_DC_SERVO_READBACK_4:
8d50e447 240 return 1;
f1c0a02f
MB		 241
242 default:
f1c0a02f 243 return 0;
8d50e447 244 }
f1c0a02f
MB		 245}
246
42768a12
MB		 247static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
248 struct snd_kcontrol *kcontrol, int event)
249{
250 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
251 mdelay(4);
252
253 return 0;
254}
255
c5b6a9fe
MB		 256static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
257 struct snd_kcontrol *kcontrol, int event)
258{
259 struct snd_soc_codec *codec = w->codec;
260 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
261
262 switch (event) {
263 case SND_SOC_DAPM_POST_PMU:
264 wm8903->dcs_pending |= 1 << w->shift;
265 break;
266 case SND_SOC_DAPM_PRE_PMD:
267 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
268 1 << w->shift, 0);
269 break;
270 }
271
272 return 0;
273}
274
275#define WM8903_DCS_MODE_WRITE_STOP 0
276#define WM8903_DCS_MODE_START_STOP 2
277
278static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
279 enum snd_soc_dapm_type event, int subseq)
280{
281 struct snd_soc_codec *codec = container_of(dapm,
282 struct snd_soc_codec, dapm);
283 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
284 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
285 int i, val;
286
287 /* Complete any pending DC servo starts */
288 if (wm8903->dcs_pending) {
289 dev_dbg(codec->dev, "Starting DC servo for %x\n",
290 wm8903->dcs_pending);
291
292 /* If we've no cached values then we need to do startup */
293 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
294 if (!(wm8903->dcs_pending & (1 << i)))
295 continue;
296
297 if (wm8903->dcs_cache[i]) {
298 dev_dbg(codec->dev,
299 "Restore DC servo %d value %x\n",
300 3 - i, wm8903->dcs_cache[i]);
301
302 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
303 wm8903->dcs_cache[i] & 0xff);
304 } else {
305 dev_dbg(codec->dev,
306 "Calibrate DC servo %d\n", 3 - i);
307 dcs_mode = WM8903_DCS_MODE_START_STOP;
308 }
309 }
310
311 /* Don't trust the cache for analogue */
312 if (wm8903->class_w_users)
313 dcs_mode = WM8903_DCS_MODE_START_STOP;
314
315 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
316 WM8903_DCS_MODE_MASK, dcs_mode);
317
318 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
319 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
320
321 switch (dcs_mode) {
322 case WM8903_DCS_MODE_WRITE_STOP:
323 break;
324
325 case WM8903_DCS_MODE_START_STOP:
326 msleep(270);
327
328 /* Cache the measured offsets for digital */
329 if (wm8903->class_w_users)
330 break;
331
332 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
333 if (!(wm8903->dcs_pending & (1 << i)))
334 continue;
335
336 val = snd_soc_read(codec,
337 WM8903_DC_SERVO_READBACK_1 + i);
338 dev_dbg(codec->dev, "DC servo %d: %x\n",
339 3 - i, val);
340 wm8903->dcs_cache[i] = val;
341 }
342 break;
343
344 default:
345 pr_warn("DCS mode %d delay not set\n", dcs_mode);
346 break;
347 }
348
349 wm8903->dcs_pending = 0;
350 }
351}
352
f1c0a02f
MB		 353/*
354 * When used with DAC outputs only the WM8903 charge pump supports
355 * operation in class W mode, providing very low power consumption
356 * when used with digital sources. Enable and disable this mode
357 * automatically depending on the mixer configuration.
358 *
359 * All the relevant controls are simple switches.
360 */
361static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
362 struct snd_ctl_elem_value *ucontrol)
363{
9d03545d
JN		 364 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
365 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
f1c0a02f 366 struct snd_soc_codec *codec = widget->codec;
b2c812e2 367 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 368 u16 reg;
369 int ret;
370
8d50e447 371 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 372
373 /* Turn it off if we're about to enable bypass */
374 if (ucontrol->value.integer.value[0]) {
375 if (wm8903->class_w_users == 0) {
f0fba2ad 376 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 377 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 378 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
379 }
380 wm8903->class_w_users++;
381 }
382
383 /* Implement the change */
384 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
385
386 /* If we've just disabled the last bypass path turn Class W on */
387 if (!ucontrol->value.integer.value[0]) {
388 if (wm8903->class_w_users == 1) {
f0fba2ad 389 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 390 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 391 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
392 }
393 wm8903->class_w_users--;
394 }
395
f0fba2ad 396 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 397 wm8903->class_w_users);
398
399 return ret;
400}
401
402#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
403{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
404 .info = snd_soc_info_volsw, \
405 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
406 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
407
408
69fff9bb
MB		 409static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
410
411static int wm8903_set_deemph(struct snd_soc_codec *codec)
412{
413 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
414 int val, i, best;
415
416 /* If we're using deemphasis select the nearest available sample
417 * rate.
418 */
419 if (wm8903->deemph) {
420 best = 1;
421 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
422 if (abs(wm8903_deemph[i] - wm8903->fs) <
423 abs(wm8903_deemph[best] - wm8903->fs))
424 best = i;
425 }
426
427 val = best << WM8903_DEEMPH_SHIFT;
428 } else {
429 best = 0;
430 val = 0;
431 }
432
433 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
434 best, wm8903_deemph[best]);
435
436 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
437 WM8903_DEEMPH_MASK, val);
438}
439
440static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
441 struct snd_ctl_elem_value *ucontrol)
442{
443 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
444 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
445
446 ucontrol->value.enumerated.item[0] = wm8903->deemph;
447
448 return 0;
449}
450
451static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
452 struct snd_ctl_elem_value *ucontrol)
453{
454 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
455 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
456 int deemph = ucontrol->value.enumerated.item[0];
457 int ret = 0;
458
459 if (deemph > 1)
460 return -EINVAL;
461
462 mutex_lock(&codec->mutex);
463 if (wm8903->deemph != deemph) {
464 wm8903->deemph = deemph;
465
466 wm8903_set_deemph(codec);
467
468 ret = 1;
469 }
470 mutex_unlock(&codec->mutex);
471
472 return ret;
473}
474
f1c0a02f
MB		 475/* ALSA can only do steps of .01dB */
476static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
477
291ce18c 478static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 479static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
480
481static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
482static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
483static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
484static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
485static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
486
460f4aae
MB		 487static const char *hpf_mode_text[] = {
488 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
489};
490
491static const struct soc_enum hpf_mode =
492 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
493
dcf9ada3
MB		 494static const char *osr_text[] = {
495 "Low power", "High performance"
496};
497
498static const struct soc_enum adc_osr =
499 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
500
501static const struct soc_enum dac_osr =
502 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
503
f1c0a02f
MB		 504static const char *drc_slope_text[] = {
505 "1", "1/2", "1/4", "1/8", "1/16", "0"
506};
507
508static const struct soc_enum drc_slope_r0 =
509 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
510
511static const struct soc_enum drc_slope_r1 =
512 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
513
514static const char *drc_attack_text[] = {
515 "instantaneous",
516 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
517 "46.4ms", "92.8ms", "185.6ms"
518};
519
520static const struct soc_enum drc_attack =
521 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
522
523static const char *drc_decay_text[] = {
524 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
525 "23.87s", "47.56s"
526};
527
528static const struct soc_enum drc_decay =
529 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
530
531static const char *drc_ff_delay_text[] = {
532 "5 samples", "9 samples"
533};
534
535static const struct soc_enum drc_ff_delay =
536 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
537
538static const char *drc_qr_decay_text[] = {
539 "0.725ms", "1.45ms", "5.8ms"
540};
541
542static const struct soc_enum drc_qr_decay =
543 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
544
545static const char *drc_smoothing_text[] = {
546 "Low", "Medium", "High"
547};
548
549static const struct soc_enum drc_smoothing =
550 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
551
552static const char *soft_mute_text[] = {
553 "Fast (fs/2)", "Slow (fs/32)"
554};
555
556static const struct soc_enum soft_mute =
557 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
558
559static const char *mute_mode_text[] = {
560 "Hard", "Soft"
561};
562
563static const struct soc_enum mute_mode =
564 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
565
f1c0a02f
MB		 566static const char *companding_text[] = {
567 "ulaw", "alaw"
568};
569
570static const struct soc_enum dac_companding =
571 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
572
573static const struct soc_enum adc_companding =
574 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
575
576static const char *input_mode_text[] = {
577 "Single-Ended", "Differential Line", "Differential Mic"
578};
579
580static const struct soc_enum linput_mode_enum =
581 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
582
583static const struct soc_enum rinput_mode_enum =
584 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
585
586static const char *linput_mux_text[] = {
587 "IN1L", "IN2L", "IN3L"
588};
589
590static const struct soc_enum linput_enum =
591 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
592
593static const struct soc_enum linput_inv_enum =
594 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
595
596static const char *rinput_mux_text[] = {
597 "IN1R", "IN2R", "IN3R"
598};
599
600static const struct soc_enum rinput_enum =
601 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
602
603static const struct soc_enum rinput_inv_enum =
604 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
605
606
291ce18c
MB		 607static const char *sidetone_text[] = {
608 "None", "Left", "Right"
609};
610
611static const struct soc_enum lsidetone_enum =
612 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
613
614static const struct soc_enum rsidetone_enum =
615 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
616
97945c46
SW		 617static const char *adcinput_text[] = {
618 "ADC", "DMIC"
619};
620
621static const struct soc_enum adcinput_enum =
622 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text);
623
1e113bf9
MB		 624static const char *aif_text[] = {
625 "Left", "Right"
626};
627
628static const struct soc_enum lcapture_enum =
629 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
630
631static const struct soc_enum rcapture_enum =
632 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
633
634static const struct soc_enum lplay_enum =
635 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
636
637static const struct soc_enum rplay_enum =
638 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
639
f1c0a02f
MB		 640static const struct snd_kcontrol_new wm8903_snd_controls[] = {
641
642/* Input PGAs - No TLV since the scale depends on PGA mode */
643SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 644 7, 1, 1),
f1c0a02f
MB		 645SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
646 0, 31, 0),
647SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
648 6, 1, 0),
649
650SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 651 7, 1, 1),
f1c0a02f
MB		 652SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
653 0, 31, 0),
654SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
655 6, 1, 0),
656
657/* ADCs */
dcf9ada3 658SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 659SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
660SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 661SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
662SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
663SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 664SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 665 drc_tlv_thresh),
666SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
667SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
668SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
669SOC_ENUM("DRC Attack Rate", drc_attack),
670SOC_ENUM("DRC Decay Rate", drc_decay),
671SOC_ENUM("DRC FF Delay", drc_ff_delay),
672SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
673SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 674SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 675SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
676SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
677SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 678SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 679SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
680
681SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
61bf35b9 682 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
f1c0a02f
MB		 683SOC_ENUM("ADC Companding Mode", adc_companding),
684SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
685
291ce18c
MB		 686SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
687 12, 0, digital_sidetone_tlv),
688
f1c0a02f 689/* DAC */
dcf9ada3 690SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 691SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
692 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
693SOC_ENUM("DAC Soft Mute Rate", soft_mute),
694SOC_ENUM("DAC Mute Mode", mute_mode),
695SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 696SOC_ENUM("DAC Companding Mode", dac_companding),
697SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 698SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
699 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 700
701/* Headphones */
702SOC_DOUBLE_R("Headphone Switch",
703 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
704 8, 1, 1),
705SOC_DOUBLE_R("Headphone ZC Switch",
706 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
707 6, 1, 0),
708SOC_DOUBLE_R_TLV("Headphone Volume",
709 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
710 0, 63, 0, out_tlv),
711
712/* Line out */
713SOC_DOUBLE_R("Line Out Switch",
714 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
715 8, 1, 1),
716SOC_DOUBLE_R("Line Out ZC Switch",
717 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
718 6, 1, 0),
719SOC_DOUBLE_R_TLV("Line Out Volume",
720 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
721 0, 63, 0, out_tlv),
722
723/* Speaker */
724SOC_DOUBLE_R("Speaker Switch",
725 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
726SOC_DOUBLE_R("Speaker ZC Switch",
727 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
728SOC_DOUBLE_R_TLV("Speaker Volume",
729 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
730 0, 63, 0, out_tlv),
731};
732
f1c0a02f
MB		 733static const struct snd_kcontrol_new linput_mode_mux =
734 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
735
736static const struct snd_kcontrol_new rinput_mode_mux =
737 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
738
739static const struct snd_kcontrol_new linput_mux =
740 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
741
742static const struct snd_kcontrol_new linput_inv_mux =
743 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
744
745static const struct snd_kcontrol_new rinput_mux =
746 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
747
748static const struct snd_kcontrol_new rinput_inv_mux =
749 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
750
291ce18c
MB		 751static const struct snd_kcontrol_new lsidetone_mux =
752 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
753
754static const struct snd_kcontrol_new rsidetone_mux =
755 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
756
97945c46
SW		 757static const struct snd_kcontrol_new adcinput_mux =
758 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
759
1e113bf9
MB		 760static const struct snd_kcontrol_new lcapture_mux =
761 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
762
763static const struct snd_kcontrol_new rcapture_mux =
764 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
765
766static const struct snd_kcontrol_new lplay_mux =
767 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
768
769static const struct snd_kcontrol_new rplay_mux =
770 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
771
f1c0a02f
MB		 772static const struct snd_kcontrol_new left_output_mixer[] = {
773SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
774SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
775SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 776SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 777};
778
779static const struct snd_kcontrol_new right_output_mixer[] = {
780SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
781SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
782SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 783SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 784};
785
786static const struct snd_kcontrol_new left_speaker_mixer[] = {
787SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
788SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
789SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
790SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 791 0, 1, 0),
f1c0a02f
MB		 792};
793
794static const struct snd_kcontrol_new right_speaker_mixer[] = {
795SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
796SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
797SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
798 1, 1, 0),
799SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 800 0, 1, 0),
f1c0a02f
MB		 801};
802
803static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
804SND_SOC_DAPM_INPUT("IN1L"),
805SND_SOC_DAPM_INPUT("IN1R"),
806SND_SOC_DAPM_INPUT("IN2L"),
807SND_SOC_DAPM_INPUT("IN2R"),
808SND_SOC_DAPM_INPUT("IN3L"),
809SND_SOC_DAPM_INPUT("IN3R"),
97945c46 810SND_SOC_DAPM_INPUT("DMICDAT"),
f1c0a02f
MB		 811
812SND_SOC_DAPM_OUTPUT("HPOUTL"),
813SND_SOC_DAPM_OUTPUT("HPOUTR"),
814SND_SOC_DAPM_OUTPUT("LINEOUTL"),
815SND_SOC_DAPM_OUTPUT("LINEOUTR"),
816SND_SOC_DAPM_OUTPUT("LOP"),
817SND_SOC_DAPM_OUTPUT("LON"),
818SND_SOC_DAPM_OUTPUT("ROP"),
819SND_SOC_DAPM_OUTPUT("RON"),
820
5032dc34 821SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
f1c0a02f
MB		 822
823SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
824SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
825 &linput_inv_mux),
826SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
827
828SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
829SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
830 &rinput_inv_mux),
831SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
832
833SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
834SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
835
97945c46
SW		 836SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
837SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
838
1e113bf9
MB		 839SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
840SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
841
842SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
843SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
844
845SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
846SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 847
291ce18c
MB		 848SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
849SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
850
1e113bf9
MB		 851SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
852SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
853
854SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
855SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
856
857SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
858SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 859
860SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
861 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
862SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
863 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
864
865SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
866 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
867SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
868 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
869
1b877cb5
DL		 870SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
871 1, 0, NULL, 0),
872SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 873 0, 0, NULL, 0),
874
1b877cb5 875SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 876 NULL, 0),
1b877cb5 877SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 878 NULL, 0),
879
880SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
881SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 882SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
883SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 884SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
885SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 886SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
887SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 888
889SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
890 NULL, 0),
891SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
892 NULL, 0),
1b877cb5
DL		 893SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
894 NULL, 0),
895SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 896 NULL, 0),
897SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
898 NULL, 0),
899SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
900 NULL, 0),
1b877cb5
DL		 901SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
902 NULL, 0),
903SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 904 NULL, 0),
905
c5b6a9fe
MB		 906SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
907SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
908 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
909SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
910 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
911SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
912 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
913SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
914 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 915
916SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
917 NULL, 0),
918SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
919 NULL, 0),
920
42768a12
MB		 921SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
922 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 923SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 924SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 925};
926
ecd01512 927static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 928
2c8be5a2 929 { "CLK_DSP", NULL, "CLK_SYS" },
5032dc34 930 { "MICBIAS", NULL, "CLK_SYS" },
2c8be5a2
MB		 931 { "HPL_DCS", NULL, "CLK_SYS" },
932 { "HPR_DCS", NULL, "CLK_SYS" },
933 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
934 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
935
f1c0a02f
MB		 936 { "Left Input Mux", "IN1L", "IN1L" },
937 { "Left Input Mux", "IN2L", "IN2L" },
938 { "Left Input Mux", "IN3L", "IN3L" },
939
940 { "Left Input Inverting Mux", "IN1L", "IN1L" },
941 { "Left Input Inverting Mux", "IN2L", "IN2L" },
942 { "Left Input Inverting Mux", "IN3L", "IN3L" },
943
944 { "Right Input Mux", "IN1R", "IN1R" },
945 { "Right Input Mux", "IN2R", "IN2R" },
946 { "Right Input Mux", "IN3R", "IN3R" },
947
948 { "Right Input Inverting Mux", "IN1R", "IN1R" },
949 { "Right Input Inverting Mux", "IN2R", "IN2R" },
950 { "Right Input Inverting Mux", "IN3R", "IN3R" },
951
952 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
953 { "Left Input Mode Mux", "Differential Line",
954 "Left Input Mux" },
955 { "Left Input Mode Mux", "Differential Line",
956 "Left Input Inverting Mux" },
957 { "Left Input Mode Mux", "Differential Mic",
958 "Left Input Mux" },
959 { "Left Input Mode Mux", "Differential Mic",
960 "Left Input Inverting Mux" },
961
962 { "Right Input Mode Mux", "Single-Ended",
963 "Right Input Inverting Mux" },
964 { "Right Input Mode Mux", "Differential Line",
965 "Right Input Mux" },
966 { "Right Input Mode Mux", "Differential Line",
967 "Right Input Inverting Mux" },
968 { "Right Input Mode Mux", "Differential Mic",
969 "Right Input Mux" },
970 { "Right Input Mode Mux", "Differential Mic",
971 "Right Input Inverting Mux" },
972
973 { "Left Input PGA", NULL, "Left Input Mode Mux" },
974 { "Right Input PGA", NULL, "Right Input Mode Mux" },
975
97945c46
SW		 976 { "Left ADC Input", "ADC", "Left Input PGA" },
977 { "Left ADC Input", "DMIC", "DMICDAT" },
978 { "Right ADC Input", "ADC", "Right Input PGA" },
979 { "Right ADC Input", "DMIC", "DMICDAT" },
980
1e113bf9
MB		 981 { "Left Capture Mux", "Left", "ADCL" },
982 { "Left Capture Mux", "Right", "ADCR" },
983
984 { "Right Capture Mux", "Left", "ADCL" },
985 { "Right Capture Mux", "Right", "ADCR" },
986
987 { "AIFTXL", NULL, "Left Capture Mux" },
988 { "AIFTXR", NULL, "Right Capture Mux" },
989
97945c46 990 { "ADCL", NULL, "Left ADC Input" },
c2aef4ff 991 { "ADCL", NULL, "CLK_DSP" },
97945c46 992 { "ADCR", NULL, "Right ADC Input" },
c2aef4ff
MB		 993 { "ADCR", NULL, "CLK_DSP" },
994
1e113bf9
MB		 995 { "Left Playback Mux", "Left", "AIFRXL" },
996 { "Left Playback Mux", "Right", "AIFRXR" },
997
998 { "Right Playback Mux", "Left", "AIFRXL" },
999 { "Right Playback Mux", "Right", "AIFRXR" },
1000
291ce18c
MB		 1001 { "DACL Sidetone", "Left", "ADCL" },
1002 { "DACL Sidetone", "Right", "ADCR" },
1003 { "DACR Sidetone", "Left", "ADCL" },
1004 { "DACR Sidetone", "Right", "ADCR" },
1005
1e113bf9 1006 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1007 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1008 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1009
1010 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1011 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1012 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1013
1014 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1015 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1016 { "Left Output Mixer", "DACL Switch", "DACL" },
1017 { "Left Output Mixer", "DACR Switch", "DACR" },
1018
1019 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1020 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1021 { "Right Output Mixer", "DACL Switch", "DACL" },
1022 { "Right Output Mixer", "DACR Switch", "DACR" },
1023
1024 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1025 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1026 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1027 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1028
1029 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1030 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1031 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1032 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1033
1034 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1035 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1036
1037 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1038 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1039
1040 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1041 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1042
1b877cb5
DL		 1043 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1044 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1045 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1046 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1047 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1048 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1049 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1050 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1051
c5b6a9fe
MB		 1052 { "HPL_DCS", NULL, "DCS Master" },
1053 { "HPR_DCS", NULL, "DCS Master" },
1054 { "LINEOUTL_DCS", NULL, "DCS Master" },
1055 { "LINEOUTR_DCS", NULL, "DCS Master" },
1056
13a9983e
MB		 1057 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1058 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1059 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1060 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1061
1062 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1063 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1064 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1065 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1066
1067 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1068 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1069 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1070 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1071
1072 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1073 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1074 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1075 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1076
1077 { "LOP", NULL, "Left Speaker PGA" },
1078 { "LON", NULL, "Left Speaker PGA" },
1079
1080 { "ROP", NULL, "Right Speaker PGA" },
1081 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1082
1083 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1084 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1085 { "Left Line Output PGA", NULL, "Charge Pump" },
1086 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1087};
1088
f1c0a02f
MB		 1089static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1090 enum snd_soc_bias_level level)
1091{
f1c0a02f
MB		 1092 switch (level) {
1093 case SND_SOC_BIAS_ON:
66daaa59 1094 break;
22f226dd 1095
f1c0a02f 1096 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1097 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1098 WM8903_VMID_RES_MASK,
1099 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1100 break;
1101
1102 case SND_SOC_BIAS_STANDBY:
ce6120cc 1103 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1104 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1105 WM8903_POBCTRL | WM8903_ISEL_MASK |
1106 WM8903_STARTUP_BIAS_ENA |
1107 WM8903_BIAS_ENA,
1108 WM8903_POBCTRL |
1109 (2 << WM8903_ISEL_SHIFT) |
1110 WM8903_STARTUP_BIAS_ENA);
1111
1112 snd_soc_update_bits(codec,
1113 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1114 WM8903_SPK_DISCHARGE,
1115 WM8903_SPK_DISCHARGE);
1116
1117 msleep(33);
1118
1119 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1120 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1121 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1122
1123 snd_soc_update_bits(codec,
1124 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1125 WM8903_SPK_DISCHARGE, 0);
1126
1127 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1128 WM8903_VMID_TIE_ENA |
1129 WM8903_BUFIO_ENA |
1130 WM8903_VMID_IO_ENA |
1131 WM8903_VMID_SOFT_MASK |
1132 WM8903_VMID_RES_MASK |
1133 WM8903_VMID_BUF_ENA,
1134 WM8903_VMID_TIE_ENA |
1135 WM8903_BUFIO_ENA |
1136 WM8903_VMID_IO_ENA |
1137 (2 << WM8903_VMID_SOFT_SHIFT) |
1138 WM8903_VMID_RES_250K |
1139 WM8903_VMID_BUF_ENA);
1140
1141 msleep(129);
1142
1143 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1144 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1145 0);
1146
1147 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1148 WM8903_VMID_SOFT_MASK, 0);
1149
1150 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1151 WM8903_VMID_RES_MASK,
1152 WM8903_VMID_RES_50K);
1153
1154 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1155 WM8903_BIAS_ENA | WM8903_POBCTRL,
1156 WM8903_BIAS_ENA);
f1c0a02f 1157
f1c0a02f
MB		 1158 /* By default no bypass paths are enabled so
1159 * enable Class W support.
1160 */
f0fba2ad 1161 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1162 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1163 WM8903_CP_DYN_FREQ |
1164 WM8903_CP_DYN_V,
1165 WM8903_CP_DYN_FREQ |
1166 WM8903_CP_DYN_V);
f1c0a02f
MB		 1167 }
1168
66daaa59
MB		 1169 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1170 WM8903_VMID_RES_MASK,
1171 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1172 break;
1173
1174 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1175 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1176 WM8903_BIAS_ENA, 0);
1177
1178 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1179 WM8903_VMID_SOFT_MASK,
1180 2 << WM8903_VMID_SOFT_SHIFT);
1181
1182 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1183 WM8903_VMID_BUF_ENA, 0);
1184
1185 msleep(290);
1186
1187 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1188 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1189 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1190 WM8903_VMID_SOFT_MASK |
1191 WM8903_VMID_BUF_ENA, 0);
1192
1193 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1194 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1195 break;
1196 }
1197
ce6120cc 1198 codec->dapm.bias_level = level;
f1c0a02f
MB		 1199
1200 return 0;
1201}
1202
1203static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1204 int clk_id, unsigned int freq, int dir)
1205{
1206 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1207 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1208
1209 wm8903->sysclk = freq;
1210
1211 return 0;
1212}
1213
1214static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1215 unsigned int fmt)
1216{
1217 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1218 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1219
1220 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1221 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1222
1223 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1224 case SND_SOC_DAIFMT_CBS_CFS:
1225 break;
1226 case SND_SOC_DAIFMT_CBS_CFM:
1227 aif1 |= WM8903_LRCLK_DIR;
1228 break;
1229 case SND_SOC_DAIFMT_CBM_CFM:
1230 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1231 break;
1232 case SND_SOC_DAIFMT_CBM_CFS:
1233 aif1 |= WM8903_BCLK_DIR;
1234 break;
1235 default:
1236 return -EINVAL;
1237 }
1238
1239 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1240 case SND_SOC_DAIFMT_DSP_A:
1241 aif1 |= 0x3;
1242 break;
1243 case SND_SOC_DAIFMT_DSP_B:
1244 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1245 break;
1246 case SND_SOC_DAIFMT_I2S:
1247 aif1 |= 0x2;
1248 break;
1249 case SND_SOC_DAIFMT_RIGHT_J:
1250 aif1 |= 0x1;
1251 break;
1252 case SND_SOC_DAIFMT_LEFT_J:
1253 break;
1254 default:
1255 return -EINVAL;
1256 }
1257
1258 /* Clock inversion */
1259 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1260 case SND_SOC_DAIFMT_DSP_A:
1261 case SND_SOC_DAIFMT_DSP_B:
1262 /* frame inversion not valid for DSP modes */
1263 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1264 case SND_SOC_DAIFMT_NB_NF:
1265 break;
1266 case SND_SOC_DAIFMT_IB_NF:
1267 aif1 |= WM8903_AIF_BCLK_INV;
1268 break;
1269 default:
1270 return -EINVAL;
1271 }
1272 break;
1273 case SND_SOC_DAIFMT_I2S:
1274 case SND_SOC_DAIFMT_RIGHT_J:
1275 case SND_SOC_DAIFMT_LEFT_J:
1276 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1277 case SND_SOC_DAIFMT_NB_NF:
1278 break;
1279 case SND_SOC_DAIFMT_IB_IF:
1280 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1281 break;
1282 case SND_SOC_DAIFMT_IB_NF:
1283 aif1 |= WM8903_AIF_BCLK_INV;
1284 break;
1285 case SND_SOC_DAIFMT_NB_IF:
1286 aif1 |= WM8903_AIF_LRCLK_INV;
1287 break;
1288 default:
1289 return -EINVAL;
1290 }
1291 break;
1292 default:
1293 return -EINVAL;
1294 }
1295
8d50e447 1296 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1297
1298 return 0;
1299}
1300
1301static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1302{
1303 struct snd_soc_codec *codec = codec_dai->codec;
1304 u16 reg;
1305
8d50e447 1306 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1307
1308 if (mute)
1309 reg |= WM8903_DAC_MUTE;
1310 else
1311 reg &= ~WM8903_DAC_MUTE;
1312
8d50e447 1313 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1314
1315 return 0;
1316}
1317
1318/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1319 * for optimal performance so we list the lower rates first and match
1320 * on the last match we find. */
1321static struct {
1322 int div;
1323 int rate;
1324 int mode;
1325 int mclk_div;
1326} clk_sys_ratios[] = {
1327 { 64, 0x0, 0x0, 1 },
1328 { 68, 0x0, 0x1, 1 },
1329 { 125, 0x0, 0x2, 1 },
1330 { 128, 0x1, 0x0, 1 },
1331 { 136, 0x1, 0x1, 1 },
1332 { 192, 0x2, 0x0, 1 },
1333 { 204, 0x2, 0x1, 1 },
1334
1335 { 64, 0x0, 0x0, 2 },
1336 { 68, 0x0, 0x1, 2 },
1337 { 125, 0x0, 0x2, 2 },
1338 { 128, 0x1, 0x0, 2 },
1339 { 136, 0x1, 0x1, 2 },
1340 { 192, 0x2, 0x0, 2 },
1341 { 204, 0x2, 0x1, 2 },
1342
1343 { 250, 0x2, 0x2, 1 },
1344 { 256, 0x3, 0x0, 1 },
1345 { 272, 0x3, 0x1, 1 },
1346 { 384, 0x4, 0x0, 1 },
1347 { 408, 0x4, 0x1, 1 },
1348 { 375, 0x4, 0x2, 1 },
1349 { 512, 0x5, 0x0, 1 },
1350 { 544, 0x5, 0x1, 1 },
1351 { 500, 0x5, 0x2, 1 },
1352 { 768, 0x6, 0x0, 1 },
1353 { 816, 0x6, 0x1, 1 },
1354 { 750, 0x6, 0x2, 1 },
1355 { 1024, 0x7, 0x0, 1 },
1356 { 1088, 0x7, 0x1, 1 },
1357 { 1000, 0x7, 0x2, 1 },
1358 { 1408, 0x8, 0x0, 1 },
1359 { 1496, 0x8, 0x1, 1 },
1360 { 1536, 0x9, 0x0, 1 },
1361 { 1632, 0x9, 0x1, 1 },
1362 { 1500, 0x9, 0x2, 1 },
1363
1364 { 250, 0x2, 0x2, 2 },
1365 { 256, 0x3, 0x0, 2 },
1366 { 272, 0x3, 0x1, 2 },
1367 { 384, 0x4, 0x0, 2 },
1368 { 408, 0x4, 0x1, 2 },
1369 { 375, 0x4, 0x2, 2 },
1370 { 512, 0x5, 0x0, 2 },
1371 { 544, 0x5, 0x1, 2 },
1372 { 500, 0x5, 0x2, 2 },
1373 { 768, 0x6, 0x0, 2 },
1374 { 816, 0x6, 0x1, 2 },
1375 { 750, 0x6, 0x2, 2 },
1376 { 1024, 0x7, 0x0, 2 },
1377 { 1088, 0x7, 0x1, 2 },
1378 { 1000, 0x7, 0x2, 2 },
1379 { 1408, 0x8, 0x0, 2 },
1380 { 1496, 0x8, 0x1, 2 },
1381 { 1536, 0x9, 0x0, 2 },
1382 { 1632, 0x9, 0x1, 2 },
1383 { 1500, 0x9, 0x2, 2 },
1384};
1385
1386/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1387static struct {
1388 int ratio;
1389 int div;
1390} bclk_divs[] = {
1391 { 10, 0 },
f1c0a02f
MB		 1392 { 20, 2 },
1393 { 30, 3 },
1394 { 40, 4 },
1395 { 50, 5 },
f1c0a02f
MB		 1396 { 60, 7 },
1397 { 80, 8 },
1398 { 100, 9 },
f1c0a02f
MB		 1399 { 120, 11 },
1400 { 160, 12 },
1401 { 200, 13 },
1402 { 220, 14 },
1403 { 240, 15 },
f1c0a02f
MB		 1404 { 300, 17 },
1405 { 320, 18 },
1406 { 440, 19 },
1407 { 480, 20 },
1408};
1409
1410/* Sample rates for DSP */
1411static struct {
1412 int rate;
1413 int value;
1414} sample_rates[] = {
1415 { 8000, 0 },
1416 { 11025, 1 },
1417 { 12000, 2 },
1418 { 16000, 3 },
1419 { 22050, 4 },
1420 { 24000, 5 },
1421 { 32000, 6 },
1422 { 44100, 7 },
1423 { 48000, 8 },
1424 { 88200, 9 },
1425 { 96000, 10 },
1426 { 0, 0 },
1427};
1428
f1c0a02f 1429static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1430 struct snd_pcm_hw_params *params,
1431 struct snd_soc_dai *dai)
f1c0a02f
MB		 1432{
1433 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1434 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1435 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1436 int fs = params_rate(params);
1437 int bclk;
1438 int bclk_div;
1439 int i;
1440 int dsp_config;
1441 int clk_config;
1442 int best_val;
1443 int cur_val;
1444 int clk_sys;
1445
8d50e447
MB		 1446 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1447 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1448 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1449 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1450 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1451 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1452
9e79261f
MB		 1453 /* Enable sloping stopband filter for low sample rates */
1454 if (fs <= 24000)
1455 dac_digital1 |= WM8903_DAC_SB_FILT;
1456 else
1457 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1458
f1c0a02f
MB		 1459 /* Configure sample rate logic for DSP - choose nearest rate */
1460 dsp_config = 0;
1461 best_val = abs(sample_rates[dsp_config].rate - fs);
1462 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1463 cur_val = abs(sample_rates[i].rate - fs);
1464 if (cur_val <= best_val) {
1465 dsp_config = i;
1466 best_val = cur_val;
1467 }
1468 }
1469
f0fba2ad 1470 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1471 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1472 clock1 |= sample_rates[dsp_config].value;
1473
1474 aif1 &= ~WM8903_AIF_WL_MASK;
1475 bclk = 2 * fs;
1476 switch (params_format(params)) {
1477 case SNDRV_PCM_FORMAT_S16_LE:
1478 bclk *= 16;
1479 break;
1480 case SNDRV_PCM_FORMAT_S20_3LE:
1481 bclk *= 20;
1482 aif1 |= 0x4;
1483 break;
1484 case SNDRV_PCM_FORMAT_S24_LE:
1485 bclk *= 24;
1486 aif1 |= 0x8;
1487 break;
1488 case SNDRV_PCM_FORMAT_S32_LE:
1489 bclk *= 32;
1490 aif1 |= 0xc;
1491 break;
1492 default:
1493 return -EINVAL;
1494 }
1495
f0fba2ad 1496 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1497 wm8903->sysclk, fs);
1498
1499 /* We may not have an MCLK which allows us to generate exactly
1500 * the clock we want, particularly with USB derived inputs, so
1501 * approximate.
1502 */
1503 clk_config = 0;
1504 best_val = abs((wm8903->sysclk /
1505 (clk_sys_ratios[0].mclk_div *
1506 clk_sys_ratios[0].div)) - fs);
1507 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1508 cur_val = abs((wm8903->sysclk /
1509 (clk_sys_ratios[i].mclk_div *
1510 clk_sys_ratios[i].div)) - fs);
1511
1512 if (cur_val <= best_val) {
1513 clk_config = i;
1514 best_val = cur_val;
1515 }
1516 }
1517
1518 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1519 clock0 |= WM8903_MCLKDIV2;
1520 clk_sys = wm8903->sysclk / 2;
1521 } else {
1522 clock0 &= ~WM8903_MCLKDIV2;
1523 clk_sys = wm8903->sysclk;
1524 }
1525
1526 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1527 WM8903_CLK_SYS_MODE_MASK);
1528 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1529 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1530
f0fba2ad 1531 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1532 clk_sys_ratios[clk_config].rate,
1533 clk_sys_ratios[clk_config].mode,
1534 clk_sys_ratios[clk_config].div);
1535
f0fba2ad 1536 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1537
1538 /* We may not get quite the right frequency if using
1539 * approximate clocks so look for the closest match that is
1540 * higher than the target (we need to ensure that there enough
1541 * BCLKs to clock out the samples).
1542 */
1543 bclk_div = 0;
1544 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1545 i = 1;
1546 while (i < ARRAY_SIZE(bclk_divs)) {
1547 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1548 if (cur_val < 0) /* BCLK table is sorted */
1549 break;
1550 bclk_div = i;
1551 best_val = cur_val;
1552 i++;
1553 }
1554
1555 aif2 &= ~WM8903_BCLK_DIV_MASK;
1556 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1557
f0fba2ad 1558 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1559 bclk_divs[bclk_div].ratio / 10, bclk,
1560 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1561
1562 aif2 |= bclk_divs[bclk_div].div;
1563 aif3 |= bclk / fs;
1564
69fff9bb
MB		 1565 wm8903->fs = params_rate(params);
1566 wm8903_set_deemph(codec);
1567
8d50e447
MB		 1568 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1569 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1570 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1571 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1572 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1573 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1574
1575 return 0;
1576}
1577
7245387e
MB		 1578/**
1579 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1580 *
1581 * @codec: WM8903 codec
1582 * @jack: jack to report detection events on
1583 * @det: value to report for presence detection
1584 * @shrt: value to report for short detection
1585 *
1586 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1587 * being used to bring out signals to the processor then only platform
1588 * data configuration is needed for WM8903 and processor GPIOs should
1589 * be configured using snd_soc_jack_add_gpios() instead.
1590 *
1591 * The current threasholds for detection should be configured using
1592 * micdet_cfg in the platform data. Using this function will force on
1593 * the microphone bias for the device.
1594 */
1595int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1596 int det, int shrt)
1597{
b2c812e2 1598 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1599 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1600
1601 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1602 det, shrt);
1603
1604 /* Store the configuration */
1605 wm8903->mic_jack = jack;
1606 wm8903->mic_det = det;
1607 wm8903->mic_short = shrt;
1608
1609 /* Enable interrupts we've got a report configured for */
1610 if (det)
1611 irq_mask &= ~WM8903_MICDET_EINT;
1612 if (shrt)
1613 irq_mask &= ~WM8903_MICSHRT_EINT;
1614
1615 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1616 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1617 irq_mask);
1618
3088e3b4 1619 if (det || shrt) {
69266866
MB		 1620 /* Enable mic detection, this may not have been set through
1621 * platform data (eg, if the defaults are OK). */
1622 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1623 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1624 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1625 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1626 } else {
1627 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1628 WM8903_MICDET_ENA, 0);
1629 }
7245387e
MB		 1630
1631 return 0;
1632}
1633EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1634
8abd16a6
MB		 1635static irqreturn_t wm8903_irq(int irq, void *data)
1636{
f0fba2ad
LG		 1637 struct snd_soc_codec *codec = data;
1638 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1639 int mic_report;
1640 int int_pol;
1641 int int_val = 0;
1642 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1643
7245387e 1644 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1645
7245387e 1646 if (int_val & WM8903_WSEQ_BUSY_EINT) {
b4d06f45 1647 dev_warn(codec->dev, "Write sequencer done\n");
8abd16a6
MB		 1648 }
1649
7245387e
MB		 1650 /*
1651 * The rest is microphone jack detection. We need to manually
1652 * invert the polarity of the interrupt after each event - to
1653 * simplify the code keep track of the last state we reported
1654 * and just invert the relevant bits in both the report and
1655 * the polarity register.
1656 */
1657 mic_report = wm8903->mic_last_report;
1658 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1659
1435b940 1660#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1661 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1662 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1663#endif
2bbb5d66 1664
7245387e
MB		 1665 if (int_val & WM8903_MICSHRT_EINT) {
1666 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1667
1668 mic_report ^= wm8903->mic_short;
1669 int_pol ^= WM8903_MICSHRT_INV;
1670 }
1671
1672 if (int_val & WM8903_MICDET_EINT) {
1673 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1674
1675 mic_report ^= wm8903->mic_det;
1676 int_pol ^= WM8903_MICDET_INV;
1677
1678 msleep(wm8903->mic_delay);
1679 }
1680
1681 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1682 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1683
1684 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1685 wm8903->mic_short | wm8903->mic_det);
1686
1687 wm8903->mic_last_report = mic_report;
1688
8abd16a6
MB		 1689 return IRQ_HANDLED;
1690}
1691
f1c0a02f
MB		 1692#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1693 SNDRV_PCM_RATE_11025 | \
1694 SNDRV_PCM_RATE_16000 | \
1695 SNDRV_PCM_RATE_22050 | \
1696 SNDRV_PCM_RATE_32000 | \
1697 SNDRV_PCM_RATE_44100 | \
1698 SNDRV_PCM_RATE_48000 | \
1699 SNDRV_PCM_RATE_88200 | \
1700 SNDRV_PCM_RATE_96000)
1701
1702#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1703 SNDRV_PCM_RATE_11025 | \
1704 SNDRV_PCM_RATE_16000 | \
1705 SNDRV_PCM_RATE_22050 | \
1706 SNDRV_PCM_RATE_32000 | \
1707 SNDRV_PCM_RATE_44100 | \
1708 SNDRV_PCM_RATE_48000)
1709
1710#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1711 SNDRV_PCM_FMTBIT_S20_3LE |\
1712 SNDRV_PCM_FMTBIT_S24_LE)
1713
85e7652d 1714static const struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1715 .hw_params = wm8903_hw_params,
1716 .digital_mute = wm8903_digital_mute,
1717 .set_fmt = wm8903_set_dai_fmt,
1718 .set_sysclk = wm8903_set_dai_sysclk,
1719};
1720
f0fba2ad
LG		 1721static struct snd_soc_dai_driver wm8903_dai = {
1722 .name = "wm8903-hifi",
f1c0a02f
MB		 1723 .playback = {
1724 .stream_name = "Playback",
1725 .channels_min = 2,
1726 .channels_max = 2,
1727 .rates = WM8903_PLAYBACK_RATES,
1728 .formats = WM8903_FORMATS,
1729 },
1730 .capture = {
1731 .stream_name = "Capture",
1732 .channels_min = 2,
1733 .channels_max = 2,
1734 .rates = WM8903_CAPTURE_RATES,
1735 .formats = WM8903_FORMATS,
1736 },
6335d055 1737 .ops = &wm8903_dai_ops,
0d960e88 1738 .symmetric_rates = 1,
f1c0a02f 1739};
f1c0a02f 1740
84b315ee 1741static int wm8903_suspend(struct snd_soc_codec *codec)
f1c0a02f 1742{
f1c0a02f
MB		 1743 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1744
1745 return 0;
1746}
1747
f0fba2ad 1748static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1749{
45e96755 1750 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f 1751
ee244ce4 1752 regcache_sync(wm8903->regmap);
f1c0a02f 1753
45e96755 1754 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1755
1756 return 0;
1757}
1758
7cfe5617
SW		 1759#ifdef CONFIG_GPIOLIB
1760static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1761{
1762 return container_of(chip, struct wm8903_priv, gpio_chip);
1763}
1764
1765static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1766{
1767 if (offset >= WM8903_NUM_GPIO)
1768 return -EINVAL;
1769
1770 return 0;
1771}
1772
1773static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1774{
1775 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1776 struct snd_soc_codec *codec = wm8903->codec;
1777 unsigned int mask, val;
1778
1779 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1780 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1781 WM8903_GP1_DIR;
1782
1783 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1784 mask, val);
1785}
1786
1787static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1788{
1789 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1790 struct snd_soc_codec *codec = wm8903->codec;
1791 int reg;
1792
1793 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1794
1795 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1796}
1797
1798static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1799 unsigned offset, int value)
1800{
1801 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1802 struct snd_soc_codec *codec = wm8903->codec;
1803 unsigned int mask, val;
1804
1805 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1806 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1807 (value << WM8903_GP2_LVL_SHIFT);
1808
1809 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1810 mask, val);
1811}
1812
1813static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1814{
1815 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1816 struct snd_soc_codec *codec = wm8903->codec;
1817
1818 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1819 WM8903_GP1_LVL_MASK,
1820 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1821}
1822
1823static struct gpio_chip wm8903_template_chip = {
1824 .label = "wm8903",
1825 .owner = THIS_MODULE,
1826 .request = wm8903_gpio_request,
1827 .direction_input = wm8903_gpio_direction_in,
1828 .get = wm8903_gpio_get,
1829 .direction_output = wm8903_gpio_direction_out,
1830 .set = wm8903_gpio_set,
1831 .can_sleep = 1,
1832};
1833
1834static void wm8903_init_gpio(struct snd_soc_codec *codec)
1835{
1836 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1837 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1838 int ret;
1839
1840 wm8903->gpio_chip = wm8903_template_chip;
1841 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1842 wm8903->gpio_chip.dev = codec->dev;
1843
1844 if (pdata && pdata->gpio_base)
1845 wm8903->gpio_chip.base = pdata->gpio_base;
1846 else
1847 wm8903->gpio_chip.base = -1;
1848
1849 ret = gpiochip_add(&wm8903->gpio_chip);
1850 if (ret != 0)
1851 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1852}
1853
1854static void wm8903_free_gpio(struct snd_soc_codec *codec)
1855{
1856 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1857 int ret;
1858
1859 ret = gpiochip_remove(&wm8903->gpio_chip);
1860 if (ret != 0)
1861 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1862}
1863#else
1864static void wm8903_init_gpio(struct snd_soc_codec *codec)
1865{
1866}
1867
1868static void wm8903_free_gpio(struct snd_soc_codec *codec)
1869{
1870}
1871#endif
1872
f0fba2ad 1873static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1874{
f0fba2ad
LG		 1875 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1876 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1877 int ret, i;
8abd16a6 1878 int trigger, irq_pol;
f1c0a02f
MB		 1879 u16 val;
1880
7cfe5617 1881 wm8903->codec = codec;
ee244ce4 1882 codec->control_data = wm8903->regmap;
d58d5d55 1883
ee244ce4 1884 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
8d50e447 1885 if (ret != 0) {
f0fba2ad
LG		 1886 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1887 return ret;
8d50e447
MB		 1888 }
1889
37f88e84 1890 /* Set up GPIOs and microphone detection */
73b34ead 1891 if (pdata) {
905f6952
MB		 1892 bool mic_gpio = false;
1893
73b34ead 1894 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
6f526f0a 1895 if (pdata->gpio_cfg[i] > 0x7fff)
73b34ead
MB		 1896 continue;
1897
1898 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
6f526f0a 1899 pdata->gpio_cfg[i] & 0x7fff);
905f6952
MB		 1900
1901 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
1902 >> WM8903_GP1_FN_SHIFT;
1903
1904 switch (val) {
1905 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
1906 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
1907 mic_gpio = true;
1908 break;
1909 default:
1910 break;
1911 }
73b34ead 1912 }
37f88e84
MB		 1913
1914 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1915 pdata->micdet_cfg);
1916
1917 /* Microphone detection needs the WSEQ clock */
1918 if (pdata->micdet_cfg)
1919 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1920 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1921
905f6952
MB		 1922 /* If microphone detection is enabled by pdata but
1923 * detected via IRQ then interrupts can be lost before
1924 * the machine driver has set up microphone detection
1925 * IRQs as the IRQs are clear on read. The detection
1926 * will be enabled when the machine driver configures.
1927 */
1928 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
1929
37f88e84 1930 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1931 }
8abd16a6 1932
f0fba2ad 1933 if (wm8903->irq) {
8abd16a6
MB		 1934 if (pdata && pdata->irq_active_low) {
1935 trigger = IRQF_TRIGGER_LOW;
1936 irq_pol = WM8903_IRQ_POL;
1937 } else {
1938 trigger = IRQF_TRIGGER_HIGH;
1939 irq_pol = 0;
1940 }
1941
1942 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1943 WM8903_IRQ_POL, irq_pol);
1944
f0fba2ad 1945 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1946 trigger | IRQF_ONESHOT,
f0fba2ad 1947 "wm8903", codec);
8abd16a6 1948 if (ret != 0) {
f0fba2ad 1949 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1950 ret);
f0fba2ad 1951 return ret;
8abd16a6
MB		 1952 }
1953
1954 /* Enable write sequencer interrupts */
1955 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1956 WM8903_IM_WSEQ_BUSY_EINT, 0);
1957 }
73b34ead 1958
f1c0a02f
MB		 1959 /* power on device */
1960 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1961
1962 /* Latch volume update bits */
8d50e447 1963 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1964 val |= WM8903_ADCVU;
8d50e447
MB		 1965 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1966 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1967
8d50e447 1968 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1969 val |= WM8903_DACVU;
8d50e447
MB		 1970 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1971 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1972
8d50e447 1973 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1974 val |= WM8903_HPOUTVU;
8d50e447
MB		 1975 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1976 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1977
8d50e447 1978 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1979 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1980 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1981 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1982
8d50e447 1983 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1984 val |= WM8903_SPKVU;
8d50e447
MB		 1985 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1986 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1987
1988 /* Enable DAC soft mute by default */
e12adab0
MB		 1989 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
1990 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
1991 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 1992
7cfe5617
SW		 1993 wm8903_init_gpio(codec);
1994
f1c0a02f
MB		 1995 return ret;
1996}
1997
f0fba2ad
LG		 1998/* power down chip */
1999static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2000{
f99847a6
SW		 2001 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
2002
7cfe5617 2003 wm8903_free_gpio(codec);
f0fba2ad 2004 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f99847a6
SW		 2005 if (wm8903->irq)
2006 free_irq(wm8903->irq, codec);
2007
f0fba2ad
LG		 2008 return 0;
2009}
f1c0a02f 2010
f0fba2ad
LG		 2011static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2012 .probe = wm8903_probe,
2013 .remove = wm8903_remove,
2014 .suspend = wm8903_suspend,
2015 .resume = wm8903_resume,
2016 .set_bias_level = wm8903_set_bias_level,
c5b6a9fe 2017 .seq_notifier = wm8903_seq_notifier,
f4a10837
MB		 2018 .controls = wm8903_snd_controls,
2019 .num_controls = ARRAY_SIZE(wm8903_snd_controls),
ecd01512
MB		 2020 .dapm_widgets = wm8903_dapm_widgets,
2021 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
2022 .dapm_routes = wm8903_intercon,
2023 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 2024};
f1c0a02f 2025
ee244ce4
MB		 2026static const struct regmap_config wm8903_regmap = {
2027 .reg_bits = 8,
2028 .val_bits = 16,
2029
2030 .max_register = WM8903_MAX_REGISTER,
2031 .volatile_reg = wm8903_volatile_register,
2032 .readable_reg = wm8903_readable_register,
2033
2034 .cache_type = REGCACHE_RBTREE,
2035 .reg_defaults = wm8903_reg_defaults,
2036 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
2037};
2038
f0fba2ad
LG		 2039static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2040 const struct i2c_device_id *id)
2041{
2042 struct wm8903_priv *wm8903;
7d46a528 2043 unsigned int val;
f0fba2ad 2044 int ret;
f1c0a02f 2045
2950cd22
MB		 2046 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv),
2047 GFP_KERNEL);
f0fba2ad
LG		 2048 if (wm8903 == NULL)
2049 return -ENOMEM;
8abd16a6 2050
ee244ce4
MB		 2051 wm8903->regmap = regmap_init_i2c(i2c, &wm8903_regmap);
2052 if (IS_ERR(wm8903->regmap)) {
2053 ret = PTR_ERR(wm8903->regmap);
2054 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2055 ret);
2056 return ret;
2057 }
2058
f0fba2ad 2059 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2060 wm8903->irq = i2c->irq;
d58d5d55 2061
7d46a528
MB		 2062 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
2063 if (ret != 0) {
2064 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
2065 goto err;
2066 }
2067 if (val != 0x8903) {
2068 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
2069 ret = -ENODEV;
2070 goto err;
2071 }
2072
2073 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
2074 if (ret != 0) {
2075 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
2076 goto err;
2077 }
2078 dev_info(&i2c->dev, "WM8903 revision %c\n",
2079 (val & WM8903_CHIP_REV_MASK) + 'A');
2080
2081 /* Reset the device */
2082 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
2083
f0fba2ad
LG		 2084 ret = snd_soc_register_codec(&i2c->dev,
2085 &soc_codec_dev_wm8903, &wm8903_dai, 1);
ee244ce4
MB		 2086 if (ret != 0)
2087 goto err;
2950cd22 2088
ee244ce4
MB		 2089 return 0;
2090err:
2091 regmap_exit(wm8903->regmap);
f0fba2ad
LG		 2092 return ret;
2093}
f1c0a02f 2094
f0fba2ad
LG		 2095static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2096{
ee244ce4
MB		 2097 struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
2098
2099 regmap_exit(wm8903->regmap);
f0fba2ad 2100 snd_soc_unregister_codec(&client->dev);
ee244ce4 2101
f1c0a02f
MB		 2102 return 0;
2103}
2104
f1c0a02f 2105static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2106 { "wm8903", 0 },
2107 { }
f1c0a02f
MB		 2108};
2109MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2110
2111static struct i2c_driver wm8903_i2c_driver = {
2112 .driver = {
4b592c91 2113 .name = "wm8903",
f1c0a02f
MB		 2114 .owner = THIS_MODULE,
2115 },
f0fba2ad
LG		 2116 .probe = wm8903_i2c_probe,
2117 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2118 .id_table = wm8903_i2c_id,
2119};
2120
f0fba2ad 2121static int __init wm8903_modinit(void)
f1c0a02f 2122{
f1c0a02f 2123 int ret = 0;
f0fba2ad
LG		 2124 ret = i2c_add_driver(&wm8903_i2c_driver);
2125 if (ret != 0) {
2126 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2127 ret);
f1c0a02f 2128 }
f1c0a02f 2129 return ret;
64089b84
MB		 2130}
2131module_init(wm8903_modinit);
2132
2133static void __exit wm8903_exit(void)
2134{
d58d5d55 2135 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 2136}
2137module_exit(wm8903_exit);
2138
f1c0a02f
MB		 2139MODULE_DESCRIPTION("ASoC WM8903 driver");
2140MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2141MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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