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ASoC: Add initial WM8995 driver
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
f1c0a02f 14 * - Digital microphone support.
f1c0a02f
MB		 15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
8abd16a6 20#include <linux/completion.h>
f1c0a02f
MB		 21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
5a0e3ad6 25#include <linux/slab.h>
f1c0a02f 26#include <sound/core.h>
7245387e 27#include <sound/jack.h>
f1c0a02f
MB		 28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/tlv.h>
31#include <sound/soc.h>
f1c0a02f 32#include <sound/initval.h>
8abd16a6 33#include <sound/wm8903.h>
2bbb5d66 34#include <trace/events/asoc.h>
f1c0a02f
MB		 35
36#include "wm8903.h"
37
f1c0a02f
MB		 38/* Register defaults at reset */
39static u16 wm8903_reg_defaults[] = {
40 0x8903, /* R0 - SW Reset and ID */
41 0x0000, /* R1 - Revision Number */
42 0x0000, /* R2 */
43 0x0000, /* R3 */
44 0x0018, /* R4 - Bias Control 0 */
45 0x0000, /* R5 - VMID Control 0 */
46 0x0000, /* R6 - Mic Bias Control 0 */
47 0x0000, /* R7 */
48 0x0001, /* R8 - Analogue DAC 0 */
49 0x0000, /* R9 */
50 0x0001, /* R10 - Analogue ADC 0 */
51 0x0000, /* R11 */
52 0x0000, /* R12 - Power Management 0 */
53 0x0000, /* R13 - Power Management 1 */
54 0x0000, /* R14 - Power Management 2 */
55 0x0000, /* R15 - Power Management 3 */
56 0x0000, /* R16 - Power Management 4 */
57 0x0000, /* R17 - Power Management 5 */
58 0x0000, /* R18 - Power Management 6 */
59 0x0000, /* R19 */
60 0x0400, /* R20 - Clock Rates 0 */
61 0x0D07, /* R21 - Clock Rates 1 */
62 0x0000, /* R22 - Clock Rates 2 */
63 0x0000, /* R23 */
64 0x0050, /* R24 - Audio Interface 0 */
65 0x0242, /* R25 - Audio Interface 1 */
66 0x0008, /* R26 - Audio Interface 2 */
67 0x0022, /* R27 - Audio Interface 3 */
68 0x0000, /* R28 */
69 0x0000, /* R29 */
70 0x00C0, /* R30 - DAC Digital Volume Left */
71 0x00C0, /* R31 - DAC Digital Volume Right */
72 0x0000, /* R32 - DAC Digital 0 */
73 0x0000, /* R33 - DAC Digital 1 */
74 0x0000, /* R34 */
75 0x0000, /* R35 */
76 0x00C0, /* R36 - ADC Digital Volume Left */
77 0x00C0, /* R37 - ADC Digital Volume Right */
78 0x0000, /* R38 - ADC Digital 0 */
79 0x0073, /* R39 - Digital Microphone 0 */
80 0x09BF, /* R40 - DRC 0 */
81 0x3241, /* R41 - DRC 1 */
82 0x0020, /* R42 - DRC 2 */
83 0x0000, /* R43 - DRC 3 */
84 0x0085, /* R44 - Analogue Left Input 0 */
85 0x0085, /* R45 - Analogue Right Input 0 */
86 0x0044, /* R46 - Analogue Left Input 1 */
87 0x0044, /* R47 - Analogue Right Input 1 */
88 0x0000, /* R48 */
89 0x0000, /* R49 */
90 0x0008, /* R50 - Analogue Left Mix 0 */
91 0x0004, /* R51 - Analogue Right Mix 0 */
92 0x0000, /* R52 - Analogue Spk Mix Left 0 */
93 0x0000, /* R53 - Analogue Spk Mix Left 1 */
94 0x0000, /* R54 - Analogue Spk Mix Right 0 */
95 0x0000, /* R55 - Analogue Spk Mix Right 1 */
96 0x0000, /* R56 */
97 0x002D, /* R57 - Analogue OUT1 Left */
98 0x002D, /* R58 - Analogue OUT1 Right */
99 0x0039, /* R59 - Analogue OUT2 Left */
100 0x0039, /* R60 - Analogue OUT2 Right */
101 0x0100, /* R61 */
102 0x0139, /* R62 - Analogue OUT3 Left */
103 0x0139, /* R63 - Analogue OUT3 Right */
104 0x0000, /* R64 */
105 0x0000, /* R65 - Analogue SPK Output Control 0 */
106 0x0000, /* R66 */
107 0x0010, /* R67 - DC Servo 0 */
108 0x0100, /* R68 */
109 0x00A4, /* R69 - DC Servo 2 */
110 0x0807, /* R70 */
111 0x0000, /* R71 */
112 0x0000, /* R72 */
113 0x0000, /* R73 */
114 0x0000, /* R74 */
115 0x0000, /* R75 */
116 0x0000, /* R76 */
117 0x0000, /* R77 */
118 0x0000, /* R78 */
119 0x000E, /* R79 */
120 0x0000, /* R80 */
121 0x0000, /* R81 */
122 0x0000, /* R82 */
123 0x0000, /* R83 */
124 0x0000, /* R84 */
125 0x0000, /* R85 */
126 0x0000, /* R86 */
127 0x0006, /* R87 */
128 0x0000, /* R88 */
129 0x0000, /* R89 */
130 0x0000, /* R90 - Analogue HP 0 */
131 0x0060, /* R91 */
132 0x0000, /* R92 */
133 0x0000, /* R93 */
134 0x0000, /* R94 - Analogue Lineout 0 */
135 0x0060, /* R95 */
136 0x0000, /* R96 */
137 0x0000, /* R97 */
138 0x0000, /* R98 - Charge Pump 0 */
139 0x1F25, /* R99 */
140 0x2B19, /* R100 */
141 0x01C0, /* R101 */
142 0x01EF, /* R102 */
143 0x2B00, /* R103 */
144 0x0000, /* R104 - Class W 0 */
145 0x01C0, /* R105 */
146 0x1C10, /* R106 */
147 0x0000, /* R107 */
148 0x0000, /* R108 - Write Sequencer 0 */
149 0x0000, /* R109 - Write Sequencer 1 */
150 0x0000, /* R110 - Write Sequencer 2 */
151 0x0000, /* R111 - Write Sequencer 3 */
152 0x0000, /* R112 - Write Sequencer 4 */
153 0x0000, /* R113 */
154 0x0000, /* R114 - Control Interface */
155 0x0000, /* R115 */
156 0x00A8, /* R116 - GPIO Control 1 */
157 0x00A8, /* R117 - GPIO Control 2 */
158 0x00A8, /* R118 - GPIO Control 3 */
159 0x0220, /* R119 - GPIO Control 4 */
160 0x01A0, /* R120 - GPIO Control 5 */
161 0x0000, /* R121 - Interrupt Status 1 */
162 0xFFFF, /* R122 - Interrupt Status 1 Mask */
163 0x0000, /* R123 - Interrupt Polarity 1 */
164 0x0000, /* R124 */
165 0x0003, /* R125 */
166 0x0000, /* R126 - Interrupt Control */
167 0x0000, /* R127 */
168 0x0005, /* R128 */
169 0x0000, /* R129 - Control Interface Test 1 */
170 0x0000, /* R130 */
171 0x0000, /* R131 */
172 0x0000, /* R132 */
173 0x0000, /* R133 */
174 0x0000, /* R134 */
175 0x03FF, /* R135 */
176 0x0007, /* R136 */
177 0x0040, /* R137 */
178 0x0000, /* R138 */
179 0x0000, /* R139 */
180 0x0000, /* R140 */
181 0x0000, /* R141 */
182 0x0000, /* R142 */
183 0x0000, /* R143 */
184 0x0000, /* R144 */
185 0x0000, /* R145 */
186 0x0000, /* R146 */
187 0x0000, /* R147 */
188 0x4000, /* R148 */
189 0x6810, /* R149 - Charge Pump Test 1 */
190 0x0004, /* R150 */
191 0x0000, /* R151 */
192 0x0000, /* R152 */
193 0x0000, /* R153 */
194 0x0000, /* R154 */
195 0x0000, /* R155 */
196 0x0000, /* R156 */
197 0x0000, /* R157 */
198 0x0000, /* R158 */
199 0x0000, /* R159 */
200 0x0000, /* R160 */
201 0x0000, /* R161 */
202 0x0000, /* R162 */
203 0x0000, /* R163 */
204 0x0028, /* R164 - Clock Rate Test 4 */
205 0x0004, /* R165 */
206 0x0000, /* R166 */
207 0x0060, /* R167 */
208 0x0000, /* R168 */
209 0x0000, /* R169 */
210 0x0000, /* R170 */
211 0x0000, /* R171 */
212 0x0000, /* R172 - Analogue Output Bias 0 */
213};
214
d58d5d55 215struct wm8903_priv {
f0fba2ad 216
d58d5d55
MB		 217 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
218
219 int sysclk;
f0fba2ad 220 int irq;
d58d5d55 221
69fff9bb
MB		 222 int fs;
223 int deemph;
224
f2c1fe09 225 /* Reference count */
d58d5d55 226 int class_w_users;
d58d5d55 227
8abd16a6
MB		 228 struct completion wseq;
229
7245387e
MB		 230 struct snd_soc_jack *mic_jack;
231 int mic_det;
232 int mic_short;
233 int mic_last_report;
234 int mic_delay;
d58d5d55
MB		 235};
236
8d50e447 237static int wm8903_volatile_register(unsigned int reg)
f1c0a02f
MB		 238{
239 switch (reg) {
240 case WM8903_SW_RESET_AND_ID:
241 case WM8903_REVISION_NUMBER:
242 case WM8903_INTERRUPT_STATUS_1:
243 case WM8903_WRITE_SEQUENCER_4:
8d50e447 244 return 1;
f1c0a02f
MB		 245
246 default:
f1c0a02f 247 return 0;
8d50e447 248 }
f1c0a02f
MB		 249}
250
251static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
252{
253 u16 reg[5];
b2c812e2 254 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 255
256 BUG_ON(start > 48);
257
37f88e84 258 /* Enable the sequencer if it's not already on */
8d50e447 259 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 260 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
261 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 262
f0fba2ad 263 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 264
8d50e447 265 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 266 start | WM8903_WSEQ_START);
267
268 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 269 * that will break us out of the poll early.
f1c0a02f
MB		 270 */
271 do {
8abd16a6
MB		 272 wait_for_completion_timeout(&wm8903->wseq,
273 msecs_to_jiffies(10));
f1c0a02f 274
8d50e447 275 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 276 } while (reg[4] & WM8903_WSEQ_BUSY);
277
f0fba2ad 278 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 279
37f88e84
MB		 280 /* Disable the sequencer again if we enabled it */
281 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 282
283 return 0;
284}
285
286static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
287{
288 int i;
289
290 /* There really ought to be something better we can do here :/ */
291 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 292 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 293}
294
295static void wm8903_reset(struct snd_soc_codec *codec)
296{
8d50e447 297 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 298 memcpy(codec->reg_cache, wm8903_reg_defaults,
299 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 300}
301
302#define WM8903_OUTPUT_SHORT 0x8
303#define WM8903_OUTPUT_OUT 0x4
304#define WM8903_OUTPUT_INT 0x2
305#define WM8903_OUTPUT_IN 0x1
306
42768a12
MB		 307static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
308 struct snd_kcontrol *kcontrol, int event)
309{
310 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
311 mdelay(4);
312
313 return 0;
314}
315
f1c0a02f
MB		 316/*
317 * Event for headphone and line out amplifier power changes. Special
318 * power up/down sequences are required in order to maximise pop/click
319 * performance.
320 */
321static int wm8903_output_event(struct snd_soc_dapm_widget *w,
322 struct snd_kcontrol *kcontrol, int event)
323{
324 struct snd_soc_codec *codec = w->codec;
f1c0a02f 325 u16 val;
0bc286e2 326 u16 reg;
d7d5c547
MB		 327 u16 dcs_reg;
328 u16 dcs_bit;
0bc286e2 329 int shift;
f1c0a02f
MB		 330
331 switch (w->reg) {
332 case WM8903_POWER_MANAGEMENT_2:
333 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 334 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 335 break;
336 case WM8903_POWER_MANAGEMENT_3:
337 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 338 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 339 break;
340 default:
341 BUG();
1e297a19 342 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 343 }
344
345 switch (w->shift) {
346 case 0:
347 shift = 0;
348 break;
349 case 1:
350 shift = 4;
351 break;
352 default:
353 BUG();
1e297a19 354 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 355 }
356
357 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 358 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 359
360 /* Short the output */
361 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 362 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 363 }
364
365 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 366 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 367
368 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 369 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 370
371 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 372 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 373
374 /* Turn on the output ENA_OUTP */
375 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 376 snd_soc_write(codec, reg, val);
f1c0a02f 377
d7d5c547 378 /* Enable the DC servo */
8d50e447 379 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 380 dcs_reg |= dcs_bit;
8d50e447 381 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 382
f1c0a02f
MB		 383 /* Remove the short */
384 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 385 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 386 }
387
388 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 389 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 390
391 /* Short the output */
392 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 393 snd_soc_write(codec, reg, val);
f1c0a02f 394
d7d5c547 395 /* Disable the DC servo */
8d50e447 396 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 397 dcs_reg &= ~dcs_bit;
8d50e447 398 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 399
f1c0a02f
MB		 400 /* Then disable the intermediate and output stages */
401 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
402 WM8903_OUTPUT_IN) << shift);
8d50e447 403 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 404 }
405
f1c0a02f
MB		 406 return 0;
407}
408
409/*
410 * When used with DAC outputs only the WM8903 charge pump supports
411 * operation in class W mode, providing very low power consumption
412 * when used with digital sources. Enable and disable this mode
413 * automatically depending on the mixer configuration.
414 *
415 * All the relevant controls are simple switches.
416 */
417static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
418 struct snd_ctl_elem_value *ucontrol)
419{
420 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
421 struct snd_soc_codec *codec = widget->codec;
b2c812e2 422 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 423 u16 reg;
424 int ret;
425
8d50e447 426 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 427
428 /* Turn it off if we're about to enable bypass */
429 if (ucontrol->value.integer.value[0]) {
430 if (wm8903->class_w_users == 0) {
f0fba2ad 431 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 432 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 433 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
434 }
435 wm8903->class_w_users++;
436 }
437
438 /* Implement the change */
439 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
440
441 /* If we've just disabled the last bypass path turn Class W on */
442 if (!ucontrol->value.integer.value[0]) {
443 if (wm8903->class_w_users == 1) {
f0fba2ad 444 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 445 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 446 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
447 }
448 wm8903->class_w_users--;
449 }
450
f0fba2ad 451 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 452 wm8903->class_w_users);
453
454 return ret;
455}
456
457#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
458{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
459 .info = snd_soc_info_volsw, \
460 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
461 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
462
463
69fff9bb
MB		 464static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
465
466static int wm8903_set_deemph(struct snd_soc_codec *codec)
467{
468 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
469 int val, i, best;
470
471 /* If we're using deemphasis select the nearest available sample
472 * rate.
473 */
474 if (wm8903->deemph) {
475 best = 1;
476 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
477 if (abs(wm8903_deemph[i] - wm8903->fs) <
478 abs(wm8903_deemph[best] - wm8903->fs))
479 best = i;
480 }
481
482 val = best << WM8903_DEEMPH_SHIFT;
483 } else {
484 best = 0;
485 val = 0;
486 }
487
488 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
489 best, wm8903_deemph[best]);
490
491 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
492 WM8903_DEEMPH_MASK, val);
493}
494
495static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
496 struct snd_ctl_elem_value *ucontrol)
497{
498 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
499 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
500
501 ucontrol->value.enumerated.item[0] = wm8903->deemph;
502
503 return 0;
504}
505
506static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
507 struct snd_ctl_elem_value *ucontrol)
508{
509 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
510 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
511 int deemph = ucontrol->value.enumerated.item[0];
512 int ret = 0;
513
514 if (deemph > 1)
515 return -EINVAL;
516
517 mutex_lock(&codec->mutex);
518 if (wm8903->deemph != deemph) {
519 wm8903->deemph = deemph;
520
521 wm8903_set_deemph(codec);
522
523 ret = 1;
524 }
525 mutex_unlock(&codec->mutex);
526
527 return ret;
528}
529
f1c0a02f
MB		 530/* ALSA can only do steps of .01dB */
531static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
532
291ce18c 533static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 534static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
535
536static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
537static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
538static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
539static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
540static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
541
460f4aae
MB		 542static const char *hpf_mode_text[] = {
543 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
544};
545
546static const struct soc_enum hpf_mode =
547 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
548
dcf9ada3
MB		 549static const char *osr_text[] = {
550 "Low power", "High performance"
551};
552
553static const struct soc_enum adc_osr =
554 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
555
556static const struct soc_enum dac_osr =
557 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
558
f1c0a02f
MB		 559static const char *drc_slope_text[] = {
560 "1", "1/2", "1/4", "1/8", "1/16", "0"
561};
562
563static const struct soc_enum drc_slope_r0 =
564 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
565
566static const struct soc_enum drc_slope_r1 =
567 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
568
569static const char *drc_attack_text[] = {
570 "instantaneous",
571 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
572 "46.4ms", "92.8ms", "185.6ms"
573};
574
575static const struct soc_enum drc_attack =
576 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
577
578static const char *drc_decay_text[] = {
579 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
580 "23.87s", "47.56s"
581};
582
583static const struct soc_enum drc_decay =
584 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
585
586static const char *drc_ff_delay_text[] = {
587 "5 samples", "9 samples"
588};
589
590static const struct soc_enum drc_ff_delay =
591 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
592
593static const char *drc_qr_decay_text[] = {
594 "0.725ms", "1.45ms", "5.8ms"
595};
596
597static const struct soc_enum drc_qr_decay =
598 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
599
600static const char *drc_smoothing_text[] = {
601 "Low", "Medium", "High"
602};
603
604static const struct soc_enum drc_smoothing =
605 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
606
607static const char *soft_mute_text[] = {
608 "Fast (fs/2)", "Slow (fs/32)"
609};
610
611static const struct soc_enum soft_mute =
612 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
613
614static const char *mute_mode_text[] = {
615 "Hard", "Soft"
616};
617
618static const struct soc_enum mute_mode =
619 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
620
f1c0a02f
MB		 621static const char *companding_text[] = {
622 "ulaw", "alaw"
623};
624
625static const struct soc_enum dac_companding =
626 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
627
628static const struct soc_enum adc_companding =
629 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
630
631static const char *input_mode_text[] = {
632 "Single-Ended", "Differential Line", "Differential Mic"
633};
634
635static const struct soc_enum linput_mode_enum =
636 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
637
638static const struct soc_enum rinput_mode_enum =
639 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
640
641static const char *linput_mux_text[] = {
642 "IN1L", "IN2L", "IN3L"
643};
644
645static const struct soc_enum linput_enum =
646 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
647
648static const struct soc_enum linput_inv_enum =
649 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
650
651static const char *rinput_mux_text[] = {
652 "IN1R", "IN2R", "IN3R"
653};
654
655static const struct soc_enum rinput_enum =
656 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
657
658static const struct soc_enum rinput_inv_enum =
659 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
660
661
291ce18c
MB		 662static const char *sidetone_text[] = {
663 "None", "Left", "Right"
664};
665
666static const struct soc_enum lsidetone_enum =
667 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
668
669static const struct soc_enum rsidetone_enum =
670 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
671
f1c0a02f
MB		 672static const struct snd_kcontrol_new wm8903_snd_controls[] = {
673
674/* Input PGAs - No TLV since the scale depends on PGA mode */
675SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 676 7, 1, 1),
f1c0a02f
MB		 677SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
678 0, 31, 0),
679SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
680 6, 1, 0),
681
682SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 683 7, 1, 1),
f1c0a02f
MB		 684SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
685 0, 31, 0),
686SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
687 6, 1, 0),
688
689/* ADCs */
dcf9ada3 690SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 691SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
692SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 693SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
694SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
695SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 696SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 697 drc_tlv_thresh),
698SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
699SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
700SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
701SOC_ENUM("DRC Attack Rate", drc_attack),
702SOC_ENUM("DRC Decay Rate", drc_decay),
703SOC_ENUM("DRC FF Delay", drc_ff_delay),
704SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
705SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 706SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 707SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
708SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
709SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 710SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 711SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
712
713SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
714 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
715SOC_ENUM("ADC Companding Mode", adc_companding),
716SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
717
291ce18c
MB		 718SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
719 12, 0, digital_sidetone_tlv),
720
f1c0a02f 721/* DAC */
dcf9ada3 722SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 723SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
724 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
725SOC_ENUM("DAC Soft Mute Rate", soft_mute),
726SOC_ENUM("DAC Mute Mode", mute_mode),
727SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 728SOC_ENUM("DAC Companding Mode", dac_companding),
729SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 730SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
731 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 732
733/* Headphones */
734SOC_DOUBLE_R("Headphone Switch",
735 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
736 8, 1, 1),
737SOC_DOUBLE_R("Headphone ZC Switch",
738 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
739 6, 1, 0),
740SOC_DOUBLE_R_TLV("Headphone Volume",
741 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
742 0, 63, 0, out_tlv),
743
744/* Line out */
745SOC_DOUBLE_R("Line Out Switch",
746 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
747 8, 1, 1),
748SOC_DOUBLE_R("Line Out ZC Switch",
749 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
750 6, 1, 0),
751SOC_DOUBLE_R_TLV("Line Out Volume",
752 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
753 0, 63, 0, out_tlv),
754
755/* Speaker */
756SOC_DOUBLE_R("Speaker Switch",
757 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
758SOC_DOUBLE_R("Speaker ZC Switch",
759 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
760SOC_DOUBLE_R_TLV("Speaker Volume",
761 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
762 0, 63, 0, out_tlv),
763};
764
f1c0a02f
MB		 765static const struct snd_kcontrol_new linput_mode_mux =
766 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
767
768static const struct snd_kcontrol_new rinput_mode_mux =
769 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
770
771static const struct snd_kcontrol_new linput_mux =
772 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
773
774static const struct snd_kcontrol_new linput_inv_mux =
775 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
776
777static const struct snd_kcontrol_new rinput_mux =
778 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
779
780static const struct snd_kcontrol_new rinput_inv_mux =
781 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
782
291ce18c
MB		 783static const struct snd_kcontrol_new lsidetone_mux =
784 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
785
786static const struct snd_kcontrol_new rsidetone_mux =
787 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
788
f1c0a02f
MB		 789static const struct snd_kcontrol_new left_output_mixer[] = {
790SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
791SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
792SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 793SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 794};
795
796static const struct snd_kcontrol_new right_output_mixer[] = {
797SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
798SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
799SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 800SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 801};
802
803static const struct snd_kcontrol_new left_speaker_mixer[] = {
804SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
805SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
806SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
807SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 808 0, 1, 0),
f1c0a02f
MB		 809};
810
811static const struct snd_kcontrol_new right_speaker_mixer[] = {
812SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
813SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
814SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
815 1, 1, 0),
816SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 817 0, 1, 0),
f1c0a02f
MB		 818};
819
820static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
821SND_SOC_DAPM_INPUT("IN1L"),
822SND_SOC_DAPM_INPUT("IN1R"),
823SND_SOC_DAPM_INPUT("IN2L"),
824SND_SOC_DAPM_INPUT("IN2R"),
825SND_SOC_DAPM_INPUT("IN3L"),
826SND_SOC_DAPM_INPUT("IN3R"),
827
828SND_SOC_DAPM_OUTPUT("HPOUTL"),
829SND_SOC_DAPM_OUTPUT("HPOUTR"),
830SND_SOC_DAPM_OUTPUT("LINEOUTL"),
831SND_SOC_DAPM_OUTPUT("LINEOUTR"),
832SND_SOC_DAPM_OUTPUT("LOP"),
833SND_SOC_DAPM_OUTPUT("LON"),
834SND_SOC_DAPM_OUTPUT("ROP"),
835SND_SOC_DAPM_OUTPUT("RON"),
836
837SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
838
839SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
840SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
841 &linput_inv_mux),
842SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
843
844SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
845SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
846 &rinput_inv_mux),
847SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
848
849SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
850SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
851
852SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
853SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
854
291ce18c
MB		 855SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
856SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
857
f1c0a02f
MB		 858SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
859SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
860
861SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
862 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
863SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
864 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
865
866SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
867 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
868SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
869 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
870
871SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
872 1, 0, NULL, 0, wm8903_output_event,
873 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 874 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 875SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
876 0, 0, NULL, 0, wm8903_output_event,
877 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 878 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 879
880SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
881 NULL, 0, wm8903_output_event,
882 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 883 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 884SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
885 NULL, 0, wm8903_output_event,
886 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 887 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 888
889SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
890 NULL, 0),
891SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
892 NULL, 0),
893
42768a12
MB		 894SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
895 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 896SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 897};
898
899static const struct snd_soc_dapm_route intercon[] = {
900
901 { "Left Input Mux", "IN1L", "IN1L" },
902 { "Left Input Mux", "IN2L", "IN2L" },
903 { "Left Input Mux", "IN3L", "IN3L" },
904
905 { "Left Input Inverting Mux", "IN1L", "IN1L" },
906 { "Left Input Inverting Mux", "IN2L", "IN2L" },
907 { "Left Input Inverting Mux", "IN3L", "IN3L" },
908
909 { "Right Input Mux", "IN1R", "IN1R" },
910 { "Right Input Mux", "IN2R", "IN2R" },
911 { "Right Input Mux", "IN3R", "IN3R" },
912
913 { "Right Input Inverting Mux", "IN1R", "IN1R" },
914 { "Right Input Inverting Mux", "IN2R", "IN2R" },
915 { "Right Input Inverting Mux", "IN3R", "IN3R" },
916
917 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
918 { "Left Input Mode Mux", "Differential Line",
919 "Left Input Mux" },
920 { "Left Input Mode Mux", "Differential Line",
921 "Left Input Inverting Mux" },
922 { "Left Input Mode Mux", "Differential Mic",
923 "Left Input Mux" },
924 { "Left Input Mode Mux", "Differential Mic",
925 "Left Input Inverting Mux" },
926
927 { "Right Input Mode Mux", "Single-Ended",
928 "Right Input Inverting Mux" },
929 { "Right Input Mode Mux", "Differential Line",
930 "Right Input Mux" },
931 { "Right Input Mode Mux", "Differential Line",
932 "Right Input Inverting Mux" },
933 { "Right Input Mode Mux", "Differential Mic",
934 "Right Input Mux" },
935 { "Right Input Mode Mux", "Differential Mic",
936 "Right Input Inverting Mux" },
937
938 { "Left Input PGA", NULL, "Left Input Mode Mux" },
939 { "Right Input PGA", NULL, "Right Input Mode Mux" },
940
941 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 942 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 943 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 944 { "ADCR", NULL, "CLK_DSP" },
945
291ce18c
MB		 946 { "DACL Sidetone", "Left", "ADCL" },
947 { "DACL Sidetone", "Right", "ADCR" },
948 { "DACR Sidetone", "Left", "ADCL" },
949 { "DACR Sidetone", "Right", "ADCR" },
950
951 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 952 { "DACL", NULL, "CLK_DSP" },
291ce18c 953 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 954 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 955
956 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
957 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
958 { "Left Output Mixer", "DACL Switch", "DACL" },
959 { "Left Output Mixer", "DACR Switch", "DACR" },
960
961 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
962 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
963 { "Right Output Mixer", "DACL Switch", "DACL" },
964 { "Right Output Mixer", "DACR Switch", "DACR" },
965
966 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
967 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
968 { "Left Speaker Mixer", "DACL Switch", "DACL" },
969 { "Left Speaker Mixer", "DACR Switch", "DACR" },
970
971 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
972 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
973 { "Right Speaker Mixer", "DACL Switch", "DACL" },
974 { "Right Speaker Mixer", "DACR Switch", "DACR" },
975
976 { "Left Line Output PGA", NULL, "Left Output Mixer" },
977 { "Right Line Output PGA", NULL, "Right Output Mixer" },
978
979 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
980 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
981
982 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
983 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
984
985 { "HPOUTL", NULL, "Left Headphone Output PGA" },
986 { "HPOUTR", NULL, "Right Headphone Output PGA" },
987
988 { "LINEOUTL", NULL, "Left Line Output PGA" },
989 { "LINEOUTR", NULL, "Right Line Output PGA" },
990
991 { "LOP", NULL, "Left Speaker PGA" },
992 { "LON", NULL, "Left Speaker PGA" },
993
994 { "ROP", NULL, "Right Speaker PGA" },
995 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 996
997 { "Left Headphone Output PGA", NULL, "Charge Pump" },
998 { "Right Headphone Output PGA", NULL, "Charge Pump" },
999 { "Left Line Output PGA", NULL, "Charge Pump" },
1000 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1001};
1002
1003static int wm8903_add_widgets(struct snd_soc_codec *codec)
1004{
ce6120cc 1005 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 1006
ce6120cc
LG		 1007 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1008 ARRAY_SIZE(wm8903_dapm_widgets));
1009 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 1010
f1c0a02f
MB		 1011 return 0;
1012}
1013
1014static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1015 enum snd_soc_bias_level level)
1016{
f1c0a02f
MB		 1017 u16 reg, reg2;
1018
1019 switch (level) {
1020 case SND_SOC_BIAS_ON:
1021 case SND_SOC_BIAS_PREPARE:
8d50e447 1022 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1023 reg &= ~(WM8903_VMID_RES_MASK);
1024 reg |= WM8903_VMID_RES_50K;
8d50e447 1025 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1026 break;
1027
1028 case SND_SOC_BIAS_STANDBY:
ce6120cc 1029 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 1030 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 1031 WM8903_CLK_SYS_ENA);
1032
4dbfe809 1033 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 1034 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1035 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1036 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 1037
f1c0a02f
MB		 1038 wm8903_run_sequence(codec, 0);
1039 wm8903_sync_reg_cache(codec, codec->reg_cache);
1040
1041 /* Enable low impedence charge pump output */
8d50e447 1042 reg = snd_soc_read(codec,
f1c0a02f 1043 WM8903_CONTROL_INTERFACE_TEST_1);
8d50e447 1044 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f 1045 reg | WM8903_TEST_KEY);
8d50e447
MB		 1046 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
1047 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
f1c0a02f 1048 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
8d50e447 1049 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f
MB		 1050 reg);
1051
1052 /* By default no bypass paths are enabled so
1053 * enable Class W support.
1054 */
f0fba2ad 1055 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 1056 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 1057 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1058 }
1059
8d50e447 1060 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1061 reg &= ~(WM8903_VMID_RES_MASK);
1062 reg |= WM8903_VMID_RES_250K;
8d50e447 1063 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1064 break;
1065
1066 case SND_SOC_BIAS_OFF:
1067 wm8903_run_sequence(codec, 32);
8d50e447 1068 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 1069 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 1070 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1071 break;
1072 }
1073
ce6120cc 1074 codec->dapm.bias_level = level;
f1c0a02f
MB		 1075
1076 return 0;
1077}
1078
1079static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1080 int clk_id, unsigned int freq, int dir)
1081{
1082 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1083 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1084
1085 wm8903->sysclk = freq;
1086
1087 return 0;
1088}
1089
1090static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1091 unsigned int fmt)
1092{
1093 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1094 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1095
1096 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1097 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1098
1099 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1100 case SND_SOC_DAIFMT_CBS_CFS:
1101 break;
1102 case SND_SOC_DAIFMT_CBS_CFM:
1103 aif1 |= WM8903_LRCLK_DIR;
1104 break;
1105 case SND_SOC_DAIFMT_CBM_CFM:
1106 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1107 break;
1108 case SND_SOC_DAIFMT_CBM_CFS:
1109 aif1 |= WM8903_BCLK_DIR;
1110 break;
1111 default:
1112 return -EINVAL;
1113 }
1114
1115 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1116 case SND_SOC_DAIFMT_DSP_A:
1117 aif1 |= 0x3;
1118 break;
1119 case SND_SOC_DAIFMT_DSP_B:
1120 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1121 break;
1122 case SND_SOC_DAIFMT_I2S:
1123 aif1 |= 0x2;
1124 break;
1125 case SND_SOC_DAIFMT_RIGHT_J:
1126 aif1 |= 0x1;
1127 break;
1128 case SND_SOC_DAIFMT_LEFT_J:
1129 break;
1130 default:
1131 return -EINVAL;
1132 }
1133
1134 /* Clock inversion */
1135 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1136 case SND_SOC_DAIFMT_DSP_A:
1137 case SND_SOC_DAIFMT_DSP_B:
1138 /* frame inversion not valid for DSP modes */
1139 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1140 case SND_SOC_DAIFMT_NB_NF:
1141 break;
1142 case SND_SOC_DAIFMT_IB_NF:
1143 aif1 |= WM8903_AIF_BCLK_INV;
1144 break;
1145 default:
1146 return -EINVAL;
1147 }
1148 break;
1149 case SND_SOC_DAIFMT_I2S:
1150 case SND_SOC_DAIFMT_RIGHT_J:
1151 case SND_SOC_DAIFMT_LEFT_J:
1152 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1153 case SND_SOC_DAIFMT_NB_NF:
1154 break;
1155 case SND_SOC_DAIFMT_IB_IF:
1156 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1157 break;
1158 case SND_SOC_DAIFMT_IB_NF:
1159 aif1 |= WM8903_AIF_BCLK_INV;
1160 break;
1161 case SND_SOC_DAIFMT_NB_IF:
1162 aif1 |= WM8903_AIF_LRCLK_INV;
1163 break;
1164 default:
1165 return -EINVAL;
1166 }
1167 break;
1168 default:
1169 return -EINVAL;
1170 }
1171
8d50e447 1172 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1173
1174 return 0;
1175}
1176
1177static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1178{
1179 struct snd_soc_codec *codec = codec_dai->codec;
1180 u16 reg;
1181
8d50e447 1182 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1183
1184 if (mute)
1185 reg |= WM8903_DAC_MUTE;
1186 else
1187 reg &= ~WM8903_DAC_MUTE;
1188
8d50e447 1189 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1190
1191 return 0;
1192}
1193
1194/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1195 * for optimal performance so we list the lower rates first and match
1196 * on the last match we find. */
1197static struct {
1198 int div;
1199 int rate;
1200 int mode;
1201 int mclk_div;
1202} clk_sys_ratios[] = {
1203 { 64, 0x0, 0x0, 1 },
1204 { 68, 0x0, 0x1, 1 },
1205 { 125, 0x0, 0x2, 1 },
1206 { 128, 0x1, 0x0, 1 },
1207 { 136, 0x1, 0x1, 1 },
1208 { 192, 0x2, 0x0, 1 },
1209 { 204, 0x2, 0x1, 1 },
1210
1211 { 64, 0x0, 0x0, 2 },
1212 { 68, 0x0, 0x1, 2 },
1213 { 125, 0x0, 0x2, 2 },
1214 { 128, 0x1, 0x0, 2 },
1215 { 136, 0x1, 0x1, 2 },
1216 { 192, 0x2, 0x0, 2 },
1217 { 204, 0x2, 0x1, 2 },
1218
1219 { 250, 0x2, 0x2, 1 },
1220 { 256, 0x3, 0x0, 1 },
1221 { 272, 0x3, 0x1, 1 },
1222 { 384, 0x4, 0x0, 1 },
1223 { 408, 0x4, 0x1, 1 },
1224 { 375, 0x4, 0x2, 1 },
1225 { 512, 0x5, 0x0, 1 },
1226 { 544, 0x5, 0x1, 1 },
1227 { 500, 0x5, 0x2, 1 },
1228 { 768, 0x6, 0x0, 1 },
1229 { 816, 0x6, 0x1, 1 },
1230 { 750, 0x6, 0x2, 1 },
1231 { 1024, 0x7, 0x0, 1 },
1232 { 1088, 0x7, 0x1, 1 },
1233 { 1000, 0x7, 0x2, 1 },
1234 { 1408, 0x8, 0x0, 1 },
1235 { 1496, 0x8, 0x1, 1 },
1236 { 1536, 0x9, 0x0, 1 },
1237 { 1632, 0x9, 0x1, 1 },
1238 { 1500, 0x9, 0x2, 1 },
1239
1240 { 250, 0x2, 0x2, 2 },
1241 { 256, 0x3, 0x0, 2 },
1242 { 272, 0x3, 0x1, 2 },
1243 { 384, 0x4, 0x0, 2 },
1244 { 408, 0x4, 0x1, 2 },
1245 { 375, 0x4, 0x2, 2 },
1246 { 512, 0x5, 0x0, 2 },
1247 { 544, 0x5, 0x1, 2 },
1248 { 500, 0x5, 0x2, 2 },
1249 { 768, 0x6, 0x0, 2 },
1250 { 816, 0x6, 0x1, 2 },
1251 { 750, 0x6, 0x2, 2 },
1252 { 1024, 0x7, 0x0, 2 },
1253 { 1088, 0x7, 0x1, 2 },
1254 { 1000, 0x7, 0x2, 2 },
1255 { 1408, 0x8, 0x0, 2 },
1256 { 1496, 0x8, 0x1, 2 },
1257 { 1536, 0x9, 0x0, 2 },
1258 { 1632, 0x9, 0x1, 2 },
1259 { 1500, 0x9, 0x2, 2 },
1260};
1261
1262/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1263static struct {
1264 int ratio;
1265 int div;
1266} bclk_divs[] = {
1267 { 10, 0 },
f1c0a02f
MB		 1268 { 20, 2 },
1269 { 30, 3 },
1270 { 40, 4 },
1271 { 50, 5 },
f1c0a02f
MB		 1272 { 60, 7 },
1273 { 80, 8 },
1274 { 100, 9 },
f1c0a02f
MB		 1275 { 120, 11 },
1276 { 160, 12 },
1277 { 200, 13 },
1278 { 220, 14 },
1279 { 240, 15 },
f1c0a02f
MB		 1280 { 300, 17 },
1281 { 320, 18 },
1282 { 440, 19 },
1283 { 480, 20 },
1284};
1285
1286/* Sample rates for DSP */
1287static struct {
1288 int rate;
1289 int value;
1290} sample_rates[] = {
1291 { 8000, 0 },
1292 { 11025, 1 },
1293 { 12000, 2 },
1294 { 16000, 3 },
1295 { 22050, 4 },
1296 { 24000, 5 },
1297 { 32000, 6 },
1298 { 44100, 7 },
1299 { 48000, 8 },
1300 { 88200, 9 },
1301 { 96000, 10 },
1302 { 0, 0 },
1303};
1304
f1c0a02f 1305static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1306 struct snd_pcm_hw_params *params,
1307 struct snd_soc_dai *dai)
f1c0a02f
MB		 1308{
1309 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1310 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1311 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1312 int fs = params_rate(params);
1313 int bclk;
1314 int bclk_div;
1315 int i;
1316 int dsp_config;
1317 int clk_config;
1318 int best_val;
1319 int cur_val;
1320 int clk_sys;
1321
8d50e447
MB		 1322 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1323 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1324 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1325 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1326 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1327 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1328
9e79261f
MB		 1329 /* Enable sloping stopband filter for low sample rates */
1330 if (fs <= 24000)
1331 dac_digital1 |= WM8903_DAC_SB_FILT;
1332 else
1333 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1334
f1c0a02f
MB		 1335 /* Configure sample rate logic for DSP - choose nearest rate */
1336 dsp_config = 0;
1337 best_val = abs(sample_rates[dsp_config].rate - fs);
1338 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1339 cur_val = abs(sample_rates[i].rate - fs);
1340 if (cur_val <= best_val) {
1341 dsp_config = i;
1342 best_val = cur_val;
1343 }
1344 }
1345
f0fba2ad 1346 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1347 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1348 clock1 |= sample_rates[dsp_config].value;
1349
1350 aif1 &= ~WM8903_AIF_WL_MASK;
1351 bclk = 2 * fs;
1352 switch (params_format(params)) {
1353 case SNDRV_PCM_FORMAT_S16_LE:
1354 bclk *= 16;
1355 break;
1356 case SNDRV_PCM_FORMAT_S20_3LE:
1357 bclk *= 20;
1358 aif1 |= 0x4;
1359 break;
1360 case SNDRV_PCM_FORMAT_S24_LE:
1361 bclk *= 24;
1362 aif1 |= 0x8;
1363 break;
1364 case SNDRV_PCM_FORMAT_S32_LE:
1365 bclk *= 32;
1366 aif1 |= 0xc;
1367 break;
1368 default:
1369 return -EINVAL;
1370 }
1371
f0fba2ad 1372 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1373 wm8903->sysclk, fs);
1374
1375 /* We may not have an MCLK which allows us to generate exactly
1376 * the clock we want, particularly with USB derived inputs, so
1377 * approximate.
1378 */
1379 clk_config = 0;
1380 best_val = abs((wm8903->sysclk /
1381 (clk_sys_ratios[0].mclk_div *
1382 clk_sys_ratios[0].div)) - fs);
1383 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1384 cur_val = abs((wm8903->sysclk /
1385 (clk_sys_ratios[i].mclk_div *
1386 clk_sys_ratios[i].div)) - fs);
1387
1388 if (cur_val <= best_val) {
1389 clk_config = i;
1390 best_val = cur_val;
1391 }
1392 }
1393
1394 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1395 clock0 |= WM8903_MCLKDIV2;
1396 clk_sys = wm8903->sysclk / 2;
1397 } else {
1398 clock0 &= ~WM8903_MCLKDIV2;
1399 clk_sys = wm8903->sysclk;
1400 }
1401
1402 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1403 WM8903_CLK_SYS_MODE_MASK);
1404 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1405 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1406
f0fba2ad 1407 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1408 clk_sys_ratios[clk_config].rate,
1409 clk_sys_ratios[clk_config].mode,
1410 clk_sys_ratios[clk_config].div);
1411
f0fba2ad 1412 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1413
1414 /* We may not get quite the right frequency if using
1415 * approximate clocks so look for the closest match that is
1416 * higher than the target (we need to ensure that there enough
1417 * BCLKs to clock out the samples).
1418 */
1419 bclk_div = 0;
1420 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1421 i = 1;
1422 while (i < ARRAY_SIZE(bclk_divs)) {
1423 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1424 if (cur_val < 0) /* BCLK table is sorted */
1425 break;
1426 bclk_div = i;
1427 best_val = cur_val;
1428 i++;
1429 }
1430
1431 aif2 &= ~WM8903_BCLK_DIV_MASK;
1432 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1433
f0fba2ad 1434 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1435 bclk_divs[bclk_div].ratio / 10, bclk,
1436 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1437
1438 aif2 |= bclk_divs[bclk_div].div;
1439 aif3 |= bclk / fs;
1440
69fff9bb
MB		 1441 wm8903->fs = params_rate(params);
1442 wm8903_set_deemph(codec);
1443
8d50e447
MB		 1444 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1445 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1446 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1447 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1448 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1449 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1450
1451 return 0;
1452}
1453
7245387e
MB		 1454/**
1455 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1456 *
1457 * @codec: WM8903 codec
1458 * @jack: jack to report detection events on
1459 * @det: value to report for presence detection
1460 * @shrt: value to report for short detection
1461 *
1462 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1463 * being used to bring out signals to the processor then only platform
1464 * data configuration is needed for WM8903 and processor GPIOs should
1465 * be configured using snd_soc_jack_add_gpios() instead.
1466 *
1467 * The current threasholds for detection should be configured using
1468 * micdet_cfg in the platform data. Using this function will force on
1469 * the microphone bias for the device.
1470 */
1471int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1472 int det, int shrt)
1473{
b2c812e2 1474 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1475 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1476
1477 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1478 det, shrt);
1479
1480 /* Store the configuration */
1481 wm8903->mic_jack = jack;
1482 wm8903->mic_det = det;
1483 wm8903->mic_short = shrt;
1484
1485 /* Enable interrupts we've got a report configured for */
1486 if (det)
1487 irq_mask &= ~WM8903_MICDET_EINT;
1488 if (shrt)
1489 irq_mask &= ~WM8903_MICSHRT_EINT;
1490
1491 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1492 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1493 irq_mask);
1494
69266866
MB		 1495 if (det && shrt) {
1496 /* Enable mic detection, this may not have been set through
1497 * platform data (eg, if the defaults are OK). */
1498 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1499 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1500 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1501 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1502 } else {
1503 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1504 WM8903_MICDET_ENA, 0);
1505 }
7245387e
MB		 1506
1507 return 0;
1508}
1509EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1510
8abd16a6
MB		 1511static irqreturn_t wm8903_irq(int irq, void *data)
1512{
f0fba2ad
LG		 1513 struct snd_soc_codec *codec = data;
1514 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1515 int mic_report;
1516 int int_pol;
1517 int int_val = 0;
1518 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1519
7245387e 1520 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1521
7245387e 1522 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1523 dev_dbg(codec->dev, "Write sequencer done\n");
1524 complete(&wm8903->wseq);
1525 }
1526
7245387e
MB		 1527 /*
1528 * The rest is microphone jack detection. We need to manually
1529 * invert the polarity of the interrupt after each event - to
1530 * simplify the code keep track of the last state we reported
1531 * and just invert the relevant bits in both the report and
1532 * the polarity register.
1533 */
1534 mic_report = wm8903->mic_last_report;
1535 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1536
2bbb5d66
MB		 1537 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1538 trace_snd_soc_jack_irq(dev_name(codec->dev));
1539
7245387e
MB		 1540 if (int_val & WM8903_MICSHRT_EINT) {
1541 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1542
1543 mic_report ^= wm8903->mic_short;
1544 int_pol ^= WM8903_MICSHRT_INV;
1545 }
1546
1547 if (int_val & WM8903_MICDET_EINT) {
1548 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1549
1550 mic_report ^= wm8903->mic_det;
1551 int_pol ^= WM8903_MICDET_INV;
1552
1553 msleep(wm8903->mic_delay);
1554 }
1555
1556 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1557 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1558
1559 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1560 wm8903->mic_short | wm8903->mic_det);
1561
1562 wm8903->mic_last_report = mic_report;
1563
8abd16a6
MB		 1564 return IRQ_HANDLED;
1565}
1566
f1c0a02f
MB		 1567#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1568 SNDRV_PCM_RATE_11025 | \
1569 SNDRV_PCM_RATE_16000 | \
1570 SNDRV_PCM_RATE_22050 | \
1571 SNDRV_PCM_RATE_32000 | \
1572 SNDRV_PCM_RATE_44100 | \
1573 SNDRV_PCM_RATE_48000 | \
1574 SNDRV_PCM_RATE_88200 | \
1575 SNDRV_PCM_RATE_96000)
1576
1577#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1578 SNDRV_PCM_RATE_11025 | \
1579 SNDRV_PCM_RATE_16000 | \
1580 SNDRV_PCM_RATE_22050 | \
1581 SNDRV_PCM_RATE_32000 | \
1582 SNDRV_PCM_RATE_44100 | \
1583 SNDRV_PCM_RATE_48000)
1584
1585#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1586 SNDRV_PCM_FMTBIT_S20_3LE |\
1587 SNDRV_PCM_FMTBIT_S24_LE)
1588
6335d055 1589static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1590 .hw_params = wm8903_hw_params,
1591 .digital_mute = wm8903_digital_mute,
1592 .set_fmt = wm8903_set_dai_fmt,
1593 .set_sysclk = wm8903_set_dai_sysclk,
1594};
1595
f0fba2ad
LG		 1596static struct snd_soc_dai_driver wm8903_dai = {
1597 .name = "wm8903-hifi",
f1c0a02f
MB		 1598 .playback = {
1599 .stream_name = "Playback",
1600 .channels_min = 2,
1601 .channels_max = 2,
1602 .rates = WM8903_PLAYBACK_RATES,
1603 .formats = WM8903_FORMATS,
1604 },
1605 .capture = {
1606 .stream_name = "Capture",
1607 .channels_min = 2,
1608 .channels_max = 2,
1609 .rates = WM8903_CAPTURE_RATES,
1610 .formats = WM8903_FORMATS,
1611 },
6335d055 1612 .ops = &wm8903_dai_ops,
0d960e88 1613 .symmetric_rates = 1,
f1c0a02f 1614};
f1c0a02f 1615
f0fba2ad 1616static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1617{
f1c0a02f
MB		 1618 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1619
1620 return 0;
1621}
1622
f0fba2ad 1623static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1624{
f1c0a02f
MB		 1625 int i;
1626 u16 *reg_cache = codec->reg_cache;
40aa7030 1627 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1628 GFP_KERNEL);
1629
1630 /* Bring the codec back up to standby first to minimise pop/clicks */
1631 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1632
1633 /* Sync back everything else */
1634 if (tmp_cache) {
1635 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1636 if (tmp_cache[i] != reg_cache[i])
8d50e447 1637 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1638 kfree(tmp_cache);
f1c0a02f 1639 } else {
f0fba2ad 1640 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1641 }
1642
1643 return 0;
1644}
1645
f0fba2ad 1646static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1647{
f0fba2ad
LG		 1648 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1649 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1650 int ret, i;
8abd16a6 1651 int trigger, irq_pol;
f1c0a02f
MB		 1652 u16 val;
1653
8abd16a6 1654 init_completion(&wm8903->wseq);
d58d5d55 1655
8d50e447
MB		 1656 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1657 if (ret != 0) {
f0fba2ad
LG		 1658 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1659 return ret;
8d50e447
MB		 1660 }
1661
1662 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1663 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1664 dev_err(codec->dev,
d58d5d55
MB		 1665 "Device with ID register %x is not a WM8903\n", val);
1666 return -ENODEV;
f1c0a02f
MB		 1667 }
1668
8d50e447 1669 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
f0fba2ad 1670 dev_info(codec->dev, "WM8903 revision %d\n",
f1c0a02f
MB		 1671 val & WM8903_CHIP_REV_MASK);
1672
1673 wm8903_reset(codec);
1674
37f88e84 1675 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1676 if (pdata) {
1677 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1678 if (!pdata->gpio_cfg[i])
1679 continue;
1680
1681 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1682 pdata->gpio_cfg[i] & 0xffff);
1683 }
37f88e84
MB		 1684
1685 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1686 pdata->micdet_cfg);
1687
1688 /* Microphone detection needs the WSEQ clock */
1689 if (pdata->micdet_cfg)
1690 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1691 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1692
1693 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1694 }
8abd16a6 1695
f0fba2ad 1696 if (wm8903->irq) {
8abd16a6
MB		 1697 if (pdata && pdata->irq_active_low) {
1698 trigger = IRQF_TRIGGER_LOW;
1699 irq_pol = WM8903_IRQ_POL;
1700 } else {
1701 trigger = IRQF_TRIGGER_HIGH;
1702 irq_pol = 0;
1703 }
1704
1705 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1706 WM8903_IRQ_POL, irq_pol);
1707
f0fba2ad 1708 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1709 trigger | IRQF_ONESHOT,
f0fba2ad 1710 "wm8903", codec);
8abd16a6 1711 if (ret != 0) {
f0fba2ad 1712 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1713 ret);
f0fba2ad 1714 return ret;
8abd16a6
MB		 1715 }
1716
1717 /* Enable write sequencer interrupts */
1718 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1719 WM8903_IM_WSEQ_BUSY_EINT, 0);
1720 }
73b34ead 1721
f1c0a02f
MB		 1722 /* power on device */
1723 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1724
1725 /* Latch volume update bits */
8d50e447 1726 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1727 val |= WM8903_ADCVU;
8d50e447
MB		 1728 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1729 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1730
8d50e447 1731 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1732 val |= WM8903_DACVU;
8d50e447
MB		 1733 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1734 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1735
8d50e447 1736 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1737 val |= WM8903_HPOUTVU;
8d50e447
MB		 1738 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1739 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1740
8d50e447 1741 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1742 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1743 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1744 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1745
8d50e447 1746 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1747 val |= WM8903_SPKVU;
8d50e447
MB		 1748 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1749 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1750
1751 /* Enable DAC soft mute by default */
8d50e447 1752 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1753 val |= WM8903_DAC_MUTEMODE;
8d50e447 1754 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1755
f0fba2ad
LG		 1756 snd_soc_add_controls(codec, wm8903_snd_controls,
1757 ARRAY_SIZE(wm8903_snd_controls));
1758 wm8903_add_widgets(codec);
f1c0a02f 1759
f1c0a02f
MB		 1760 return ret;
1761}
1762
f0fba2ad
LG		 1763/* power down chip */
1764static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1765{
f0fba2ad
LG		 1766 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1767 return 0;
1768}
f1c0a02f 1769
f0fba2ad
LG		 1770static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1771 .probe = wm8903_probe,
1772 .remove = wm8903_remove,
1773 .suspend = wm8903_suspend,
1774 .resume = wm8903_resume,
1775 .set_bias_level = wm8903_set_bias_level,
1776 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1777 .reg_word_size = sizeof(u16),
1778 .reg_cache_default = wm8903_reg_defaults,
1779 .volatile_register = wm8903_volatile_register,
1780};
f1c0a02f 1781
f0fba2ad
LG		 1782#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1783static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1784 const struct i2c_device_id *id)
1785{
1786 struct wm8903_priv *wm8903;
1787 int ret;
f1c0a02f 1788
f0fba2ad
LG		 1789 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1790 if (wm8903 == NULL)
1791 return -ENOMEM;
8abd16a6 1792
f0fba2ad 1793 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 1794 wm8903->irq = i2c->irq;
d58d5d55 1795
f0fba2ad
LG		 1796 ret = snd_soc_register_codec(&i2c->dev,
1797 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1798 if (ret < 0)
1799 kfree(wm8903);
1800 return ret;
1801}
f1c0a02f 1802
f0fba2ad
LG		 1803static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1804{
1805 snd_soc_unregister_codec(&client->dev);
1806 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 1807 return 0;
1808}
1809
f1c0a02f 1810static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 1811 { "wm8903", 0 },
1812 { }
f1c0a02f
MB		 1813};
1814MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1815
1816static struct i2c_driver wm8903_i2c_driver = {
1817 .driver = {
f0fba2ad 1818 .name = "wm8903-codec",
f1c0a02f
MB		 1819 .owner = THIS_MODULE,
1820 },
f0fba2ad
LG		 1821 .probe = wm8903_i2c_probe,
1822 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1823 .id_table = wm8903_i2c_id,
1824};
f0fba2ad 1825#endif
f1c0a02f 1826
f0fba2ad 1827static int __init wm8903_modinit(void)
f1c0a02f 1828{
f1c0a02f 1829 int ret = 0;
f0fba2ad
LG		 1830#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1831 ret = i2c_add_driver(&wm8903_i2c_driver);
1832 if (ret != 0) {
1833 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1834 ret);
f1c0a02f 1835 }
f0fba2ad 1836#endif
f1c0a02f 1837 return ret;
64089b84
MB		 1838}
1839module_init(wm8903_modinit);
1840
1841static void __exit wm8903_exit(void)
1842{
f0fba2ad 1843#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 1844 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 1845#endif
64089b84
MB		 1846}
1847module_exit(wm8903_exit);
1848
f1c0a02f
MB		 1849MODULE_DESCRIPTION("ASoC WM8903 driver");
1850MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1851MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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