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ASoC: Use delayed work to debounce WM8350 jack IRQs
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
f1c0a02f 14 * - Digital microphone support.
f1c0a02f
MB		 15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
8abd16a6 20#include <linux/completion.h>
f1c0a02f
MB		 21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
5a0e3ad6 25#include <linux/slab.h>
f1c0a02f 26#include <sound/core.h>
7245387e 27#include <sound/jack.h>
f1c0a02f
MB		 28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/tlv.h>
31#include <sound/soc.h>
f1c0a02f 32#include <sound/initval.h>
8abd16a6 33#include <sound/wm8903.h>
f1c0a02f
MB		 34
35#include "wm8903.h"
36
f1c0a02f
MB		 37/* Register defaults at reset */
38static u16 wm8903_reg_defaults[] = {
39 0x8903, /* R0 - SW Reset and ID */
40 0x0000, /* R1 - Revision Number */
41 0x0000, /* R2 */
42 0x0000, /* R3 */
43 0x0018, /* R4 - Bias Control 0 */
44 0x0000, /* R5 - VMID Control 0 */
45 0x0000, /* R6 - Mic Bias Control 0 */
46 0x0000, /* R7 */
47 0x0001, /* R8 - Analogue DAC 0 */
48 0x0000, /* R9 */
49 0x0001, /* R10 - Analogue ADC 0 */
50 0x0000, /* R11 */
51 0x0000, /* R12 - Power Management 0 */
52 0x0000, /* R13 - Power Management 1 */
53 0x0000, /* R14 - Power Management 2 */
54 0x0000, /* R15 - Power Management 3 */
55 0x0000, /* R16 - Power Management 4 */
56 0x0000, /* R17 - Power Management 5 */
57 0x0000, /* R18 - Power Management 6 */
58 0x0000, /* R19 */
59 0x0400, /* R20 - Clock Rates 0 */
60 0x0D07, /* R21 - Clock Rates 1 */
61 0x0000, /* R22 - Clock Rates 2 */
62 0x0000, /* R23 */
63 0x0050, /* R24 - Audio Interface 0 */
64 0x0242, /* R25 - Audio Interface 1 */
65 0x0008, /* R26 - Audio Interface 2 */
66 0x0022, /* R27 - Audio Interface 3 */
67 0x0000, /* R28 */
68 0x0000, /* R29 */
69 0x00C0, /* R30 - DAC Digital Volume Left */
70 0x00C0, /* R31 - DAC Digital Volume Right */
71 0x0000, /* R32 - DAC Digital 0 */
72 0x0000, /* R33 - DAC Digital 1 */
73 0x0000, /* R34 */
74 0x0000, /* R35 */
75 0x00C0, /* R36 - ADC Digital Volume Left */
76 0x00C0, /* R37 - ADC Digital Volume Right */
77 0x0000, /* R38 - ADC Digital 0 */
78 0x0073, /* R39 - Digital Microphone 0 */
79 0x09BF, /* R40 - DRC 0 */
80 0x3241, /* R41 - DRC 1 */
81 0x0020, /* R42 - DRC 2 */
82 0x0000, /* R43 - DRC 3 */
83 0x0085, /* R44 - Analogue Left Input 0 */
84 0x0085, /* R45 - Analogue Right Input 0 */
85 0x0044, /* R46 - Analogue Left Input 1 */
86 0x0044, /* R47 - Analogue Right Input 1 */
87 0x0000, /* R48 */
88 0x0000, /* R49 */
89 0x0008, /* R50 - Analogue Left Mix 0 */
90 0x0004, /* R51 - Analogue Right Mix 0 */
91 0x0000, /* R52 - Analogue Spk Mix Left 0 */
92 0x0000, /* R53 - Analogue Spk Mix Left 1 */
93 0x0000, /* R54 - Analogue Spk Mix Right 0 */
94 0x0000, /* R55 - Analogue Spk Mix Right 1 */
95 0x0000, /* R56 */
96 0x002D, /* R57 - Analogue OUT1 Left */
97 0x002D, /* R58 - Analogue OUT1 Right */
98 0x0039, /* R59 - Analogue OUT2 Left */
99 0x0039, /* R60 - Analogue OUT2 Right */
100 0x0100, /* R61 */
101 0x0139, /* R62 - Analogue OUT3 Left */
102 0x0139, /* R63 - Analogue OUT3 Right */
103 0x0000, /* R64 */
104 0x0000, /* R65 - Analogue SPK Output Control 0 */
105 0x0000, /* R66 */
106 0x0010, /* R67 - DC Servo 0 */
107 0x0100, /* R68 */
108 0x00A4, /* R69 - DC Servo 2 */
109 0x0807, /* R70 */
110 0x0000, /* R71 */
111 0x0000, /* R72 */
112 0x0000, /* R73 */
113 0x0000, /* R74 */
114 0x0000, /* R75 */
115 0x0000, /* R76 */
116 0x0000, /* R77 */
117 0x0000, /* R78 */
118 0x000E, /* R79 */
119 0x0000, /* R80 */
120 0x0000, /* R81 */
121 0x0000, /* R82 */
122 0x0000, /* R83 */
123 0x0000, /* R84 */
124 0x0000, /* R85 */
125 0x0000, /* R86 */
126 0x0006, /* R87 */
127 0x0000, /* R88 */
128 0x0000, /* R89 */
129 0x0000, /* R90 - Analogue HP 0 */
130 0x0060, /* R91 */
131 0x0000, /* R92 */
132 0x0000, /* R93 */
133 0x0000, /* R94 - Analogue Lineout 0 */
134 0x0060, /* R95 */
135 0x0000, /* R96 */
136 0x0000, /* R97 */
137 0x0000, /* R98 - Charge Pump 0 */
138 0x1F25, /* R99 */
139 0x2B19, /* R100 */
140 0x01C0, /* R101 */
141 0x01EF, /* R102 */
142 0x2B00, /* R103 */
143 0x0000, /* R104 - Class W 0 */
144 0x01C0, /* R105 */
145 0x1C10, /* R106 */
146 0x0000, /* R107 */
147 0x0000, /* R108 - Write Sequencer 0 */
148 0x0000, /* R109 - Write Sequencer 1 */
149 0x0000, /* R110 - Write Sequencer 2 */
150 0x0000, /* R111 - Write Sequencer 3 */
151 0x0000, /* R112 - Write Sequencer 4 */
152 0x0000, /* R113 */
153 0x0000, /* R114 - Control Interface */
154 0x0000, /* R115 */
155 0x00A8, /* R116 - GPIO Control 1 */
156 0x00A8, /* R117 - GPIO Control 2 */
157 0x00A8, /* R118 - GPIO Control 3 */
158 0x0220, /* R119 - GPIO Control 4 */
159 0x01A0, /* R120 - GPIO Control 5 */
160 0x0000, /* R121 - Interrupt Status 1 */
161 0xFFFF, /* R122 - Interrupt Status 1 Mask */
162 0x0000, /* R123 - Interrupt Polarity 1 */
163 0x0000, /* R124 */
164 0x0003, /* R125 */
165 0x0000, /* R126 - Interrupt Control */
166 0x0000, /* R127 */
167 0x0005, /* R128 */
168 0x0000, /* R129 - Control Interface Test 1 */
169 0x0000, /* R130 */
170 0x0000, /* R131 */
171 0x0000, /* R132 */
172 0x0000, /* R133 */
173 0x0000, /* R134 */
174 0x03FF, /* R135 */
175 0x0007, /* R136 */
176 0x0040, /* R137 */
177 0x0000, /* R138 */
178 0x0000, /* R139 */
179 0x0000, /* R140 */
180 0x0000, /* R141 */
181 0x0000, /* R142 */
182 0x0000, /* R143 */
183 0x0000, /* R144 */
184 0x0000, /* R145 */
185 0x0000, /* R146 */
186 0x0000, /* R147 */
187 0x4000, /* R148 */
188 0x6810, /* R149 - Charge Pump Test 1 */
189 0x0004, /* R150 */
190 0x0000, /* R151 */
191 0x0000, /* R152 */
192 0x0000, /* R153 */
193 0x0000, /* R154 */
194 0x0000, /* R155 */
195 0x0000, /* R156 */
196 0x0000, /* R157 */
197 0x0000, /* R158 */
198 0x0000, /* R159 */
199 0x0000, /* R160 */
200 0x0000, /* R161 */
201 0x0000, /* R162 */
202 0x0000, /* R163 */
203 0x0028, /* R164 - Clock Rate Test 4 */
204 0x0004, /* R165 */
205 0x0000, /* R166 */
206 0x0060, /* R167 */
207 0x0000, /* R168 */
208 0x0000, /* R169 */
209 0x0000, /* R170 */
210 0x0000, /* R171 */
211 0x0000, /* R172 - Analogue Output Bias 0 */
212};
213
d58d5d55 214struct wm8903_priv {
f0fba2ad 215
d58d5d55
MB		 216 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
217
218 int sysclk;
f0fba2ad 219 int irq;
d58d5d55 220
69fff9bb
MB		 221 int fs;
222 int deemph;
223
f2c1fe09 224 /* Reference count */
d58d5d55 225 int class_w_users;
d58d5d55 226
8abd16a6
MB		 227 struct completion wseq;
228
7245387e
MB		 229 struct snd_soc_jack *mic_jack;
230 int mic_det;
231 int mic_short;
232 int mic_last_report;
233 int mic_delay;
d58d5d55
MB		 234};
235
8d50e447 236static int wm8903_volatile_register(unsigned int reg)
f1c0a02f
MB		 237{
238 switch (reg) {
239 case WM8903_SW_RESET_AND_ID:
240 case WM8903_REVISION_NUMBER:
241 case WM8903_INTERRUPT_STATUS_1:
242 case WM8903_WRITE_SEQUENCER_4:
8d50e447 243 return 1;
f1c0a02f
MB		 244
245 default:
f1c0a02f 246 return 0;
8d50e447 247 }
f1c0a02f
MB		 248}
249
250static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
251{
252 u16 reg[5];
b2c812e2 253 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 254
255 BUG_ON(start > 48);
256
37f88e84 257 /* Enable the sequencer if it's not already on */
8d50e447 258 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 259 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
260 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 261
f0fba2ad 262 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 263
8d50e447 264 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 265 start | WM8903_WSEQ_START);
266
267 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 268 * that will break us out of the poll early.
f1c0a02f
MB		 269 */
270 do {
8abd16a6
MB		 271 wait_for_completion_timeout(&wm8903->wseq,
272 msecs_to_jiffies(10));
f1c0a02f 273
8d50e447 274 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 275 } while (reg[4] & WM8903_WSEQ_BUSY);
276
f0fba2ad 277 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 278
37f88e84
MB		 279 /* Disable the sequencer again if we enabled it */
280 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 281
282 return 0;
283}
284
285static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
286{
287 int i;
288
289 /* There really ought to be something better we can do here :/ */
290 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 291 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 292}
293
294static void wm8903_reset(struct snd_soc_codec *codec)
295{
8d50e447 296 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 297 memcpy(codec->reg_cache, wm8903_reg_defaults,
298 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 299}
300
301#define WM8903_OUTPUT_SHORT 0x8
302#define WM8903_OUTPUT_OUT 0x4
303#define WM8903_OUTPUT_INT 0x2
304#define WM8903_OUTPUT_IN 0x1
305
42768a12
MB		 306static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
307 struct snd_kcontrol *kcontrol, int event)
308{
309 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
310 mdelay(4);
311
312 return 0;
313}
314
f1c0a02f
MB		 315/*
316 * Event for headphone and line out amplifier power changes. Special
317 * power up/down sequences are required in order to maximise pop/click
318 * performance.
319 */
320static int wm8903_output_event(struct snd_soc_dapm_widget *w,
321 struct snd_kcontrol *kcontrol, int event)
322{
323 struct snd_soc_codec *codec = w->codec;
f1c0a02f 324 u16 val;
0bc286e2 325 u16 reg;
d7d5c547
MB		 326 u16 dcs_reg;
327 u16 dcs_bit;
0bc286e2 328 int shift;
f1c0a02f
MB		 329
330 switch (w->reg) {
331 case WM8903_POWER_MANAGEMENT_2:
332 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 333 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 334 break;
335 case WM8903_POWER_MANAGEMENT_3:
336 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 337 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 338 break;
339 default:
340 BUG();
1e297a19 341 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 342 }
343
344 switch (w->shift) {
345 case 0:
346 shift = 0;
347 break;
348 case 1:
349 shift = 4;
350 break;
351 default:
352 BUG();
1e297a19 353 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 354 }
355
356 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 357 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 358
359 /* Short the output */
360 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 361 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 362 }
363
364 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 365 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 366
367 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 368 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 369
370 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 371 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 372
373 /* Turn on the output ENA_OUTP */
374 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 375 snd_soc_write(codec, reg, val);
f1c0a02f 376
d7d5c547 377 /* Enable the DC servo */
8d50e447 378 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 379 dcs_reg |= dcs_bit;
8d50e447 380 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 381
f1c0a02f
MB		 382 /* Remove the short */
383 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 384 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 385 }
386
387 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 388 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 389
390 /* Short the output */
391 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 392 snd_soc_write(codec, reg, val);
f1c0a02f 393
d7d5c547 394 /* Disable the DC servo */
8d50e447 395 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 396 dcs_reg &= ~dcs_bit;
8d50e447 397 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 398
f1c0a02f
MB		 399 /* Then disable the intermediate and output stages */
400 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
401 WM8903_OUTPUT_IN) << shift);
8d50e447 402 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 403 }
404
f1c0a02f
MB		 405 return 0;
406}
407
408/*
409 * When used with DAC outputs only the WM8903 charge pump supports
410 * operation in class W mode, providing very low power consumption
411 * when used with digital sources. Enable and disable this mode
412 * automatically depending on the mixer configuration.
413 *
414 * All the relevant controls are simple switches.
415 */
416static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
417 struct snd_ctl_elem_value *ucontrol)
418{
419 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
420 struct snd_soc_codec *codec = widget->codec;
b2c812e2 421 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 422 u16 reg;
423 int ret;
424
8d50e447 425 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 426
427 /* Turn it off if we're about to enable bypass */
428 if (ucontrol->value.integer.value[0]) {
429 if (wm8903->class_w_users == 0) {
f0fba2ad 430 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 431 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 432 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
433 }
434 wm8903->class_w_users++;
435 }
436
437 /* Implement the change */
438 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
439
440 /* If we've just disabled the last bypass path turn Class W on */
441 if (!ucontrol->value.integer.value[0]) {
442 if (wm8903->class_w_users == 1) {
f0fba2ad 443 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 444 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 445 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
446 }
447 wm8903->class_w_users--;
448 }
449
f0fba2ad 450 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 451 wm8903->class_w_users);
452
453 return ret;
454}
455
456#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
457{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
458 .info = snd_soc_info_volsw, \
459 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
460 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
461
462
69fff9bb
MB		 463static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
464
465static int wm8903_set_deemph(struct snd_soc_codec *codec)
466{
467 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
468 int val, i, best;
469
470 /* If we're using deemphasis select the nearest available sample
471 * rate.
472 */
473 if (wm8903->deemph) {
474 best = 1;
475 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
476 if (abs(wm8903_deemph[i] - wm8903->fs) <
477 abs(wm8903_deemph[best] - wm8903->fs))
478 best = i;
479 }
480
481 val = best << WM8903_DEEMPH_SHIFT;
482 } else {
483 best = 0;
484 val = 0;
485 }
486
487 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
488 best, wm8903_deemph[best]);
489
490 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
491 WM8903_DEEMPH_MASK, val);
492}
493
494static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
495 struct snd_ctl_elem_value *ucontrol)
496{
497 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
498 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
499
500 ucontrol->value.enumerated.item[0] = wm8903->deemph;
501
502 return 0;
503}
504
505static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
506 struct snd_ctl_elem_value *ucontrol)
507{
508 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
509 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
510 int deemph = ucontrol->value.enumerated.item[0];
511 int ret = 0;
512
513 if (deemph > 1)
514 return -EINVAL;
515
516 mutex_lock(&codec->mutex);
517 if (wm8903->deemph != deemph) {
518 wm8903->deemph = deemph;
519
520 wm8903_set_deemph(codec);
521
522 ret = 1;
523 }
524 mutex_unlock(&codec->mutex);
525
526 return ret;
527}
528
f1c0a02f
MB		 529/* ALSA can only do steps of .01dB */
530static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
531
291ce18c 532static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 533static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
534
535static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
536static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
537static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
538static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
539static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
540
460f4aae
MB		 541static const char *hpf_mode_text[] = {
542 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
543};
544
545static const struct soc_enum hpf_mode =
546 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
547
dcf9ada3
MB		 548static const char *osr_text[] = {
549 "Low power", "High performance"
550};
551
552static const struct soc_enum adc_osr =
553 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
554
555static const struct soc_enum dac_osr =
556 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
557
f1c0a02f
MB		 558static const char *drc_slope_text[] = {
559 "1", "1/2", "1/4", "1/8", "1/16", "0"
560};
561
562static const struct soc_enum drc_slope_r0 =
563 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
564
565static const struct soc_enum drc_slope_r1 =
566 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
567
568static const char *drc_attack_text[] = {
569 "instantaneous",
570 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
571 "46.4ms", "92.8ms", "185.6ms"
572};
573
574static const struct soc_enum drc_attack =
575 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
576
577static const char *drc_decay_text[] = {
578 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
579 "23.87s", "47.56s"
580};
581
582static const struct soc_enum drc_decay =
583 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
584
585static const char *drc_ff_delay_text[] = {
586 "5 samples", "9 samples"
587};
588
589static const struct soc_enum drc_ff_delay =
590 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
591
592static const char *drc_qr_decay_text[] = {
593 "0.725ms", "1.45ms", "5.8ms"
594};
595
596static const struct soc_enum drc_qr_decay =
597 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
598
599static const char *drc_smoothing_text[] = {
600 "Low", "Medium", "High"
601};
602
603static const struct soc_enum drc_smoothing =
604 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
605
606static const char *soft_mute_text[] = {
607 "Fast (fs/2)", "Slow (fs/32)"
608};
609
610static const struct soc_enum soft_mute =
611 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
612
613static const char *mute_mode_text[] = {
614 "Hard", "Soft"
615};
616
617static const struct soc_enum mute_mode =
618 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
619
f1c0a02f
MB		 620static const char *companding_text[] = {
621 "ulaw", "alaw"
622};
623
624static const struct soc_enum dac_companding =
625 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
626
627static const struct soc_enum adc_companding =
628 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
629
630static const char *input_mode_text[] = {
631 "Single-Ended", "Differential Line", "Differential Mic"
632};
633
634static const struct soc_enum linput_mode_enum =
635 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
636
637static const struct soc_enum rinput_mode_enum =
638 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
639
640static const char *linput_mux_text[] = {
641 "IN1L", "IN2L", "IN3L"
642};
643
644static const struct soc_enum linput_enum =
645 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
646
647static const struct soc_enum linput_inv_enum =
648 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
649
650static const char *rinput_mux_text[] = {
651 "IN1R", "IN2R", "IN3R"
652};
653
654static const struct soc_enum rinput_enum =
655 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
656
657static const struct soc_enum rinput_inv_enum =
658 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
659
660
291ce18c
MB		 661static const char *sidetone_text[] = {
662 "None", "Left", "Right"
663};
664
665static const struct soc_enum lsidetone_enum =
666 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
667
668static const struct soc_enum rsidetone_enum =
669 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
670
f1c0a02f
MB		 671static const struct snd_kcontrol_new wm8903_snd_controls[] = {
672
673/* Input PGAs - No TLV since the scale depends on PGA mode */
674SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 675 7, 1, 1),
f1c0a02f
MB		 676SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
677 0, 31, 0),
678SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
679 6, 1, 0),
680
681SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 682 7, 1, 1),
f1c0a02f
MB		 683SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
684 0, 31, 0),
685SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
686 6, 1, 0),
687
688/* ADCs */
dcf9ada3 689SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 690SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
691SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 692SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
693SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
694SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 695SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 696 drc_tlv_thresh),
697SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
698SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
699SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
700SOC_ENUM("DRC Attack Rate", drc_attack),
701SOC_ENUM("DRC Decay Rate", drc_decay),
702SOC_ENUM("DRC FF Delay", drc_ff_delay),
703SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
704SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 705SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 706SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
707SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
708SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 709SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 710SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
711
712SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
713 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
714SOC_ENUM("ADC Companding Mode", adc_companding),
715SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
716
291ce18c
MB		 717SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
718 12, 0, digital_sidetone_tlv),
719
f1c0a02f 720/* DAC */
dcf9ada3 721SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 722SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
723 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
724SOC_ENUM("DAC Soft Mute Rate", soft_mute),
725SOC_ENUM("DAC Mute Mode", mute_mode),
726SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 727SOC_ENUM("DAC Companding Mode", dac_companding),
728SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 729SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
730 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 731
732/* Headphones */
733SOC_DOUBLE_R("Headphone Switch",
734 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
735 8, 1, 1),
736SOC_DOUBLE_R("Headphone ZC Switch",
737 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
738 6, 1, 0),
739SOC_DOUBLE_R_TLV("Headphone Volume",
740 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
741 0, 63, 0, out_tlv),
742
743/* Line out */
744SOC_DOUBLE_R("Line Out Switch",
745 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
746 8, 1, 1),
747SOC_DOUBLE_R("Line Out ZC Switch",
748 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
749 6, 1, 0),
750SOC_DOUBLE_R_TLV("Line Out Volume",
751 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
752 0, 63, 0, out_tlv),
753
754/* Speaker */
755SOC_DOUBLE_R("Speaker Switch",
756 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
757SOC_DOUBLE_R("Speaker ZC Switch",
758 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
759SOC_DOUBLE_R_TLV("Speaker Volume",
760 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
761 0, 63, 0, out_tlv),
762};
763
f1c0a02f
MB		 764static const struct snd_kcontrol_new linput_mode_mux =
765 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
766
767static const struct snd_kcontrol_new rinput_mode_mux =
768 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
769
770static const struct snd_kcontrol_new linput_mux =
771 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
772
773static const struct snd_kcontrol_new linput_inv_mux =
774 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
775
776static const struct snd_kcontrol_new rinput_mux =
777 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
778
779static const struct snd_kcontrol_new rinput_inv_mux =
780 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
781
291ce18c
MB		 782static const struct snd_kcontrol_new lsidetone_mux =
783 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
784
785static const struct snd_kcontrol_new rsidetone_mux =
786 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
787
f1c0a02f
MB		 788static const struct snd_kcontrol_new left_output_mixer[] = {
789SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
790SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
791SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 792SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 793};
794
795static const struct snd_kcontrol_new right_output_mixer[] = {
796SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
797SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
798SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 799SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 800};
801
802static const struct snd_kcontrol_new left_speaker_mixer[] = {
803SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
804SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
805SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
806SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 807 0, 1, 0),
f1c0a02f
MB		 808};
809
810static const struct snd_kcontrol_new right_speaker_mixer[] = {
811SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
812SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
813SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
814 1, 1, 0),
815SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 816 0, 1, 0),
f1c0a02f
MB		 817};
818
819static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
820SND_SOC_DAPM_INPUT("IN1L"),
821SND_SOC_DAPM_INPUT("IN1R"),
822SND_SOC_DAPM_INPUT("IN2L"),
823SND_SOC_DAPM_INPUT("IN2R"),
824SND_SOC_DAPM_INPUT("IN3L"),
825SND_SOC_DAPM_INPUT("IN3R"),
826
827SND_SOC_DAPM_OUTPUT("HPOUTL"),
828SND_SOC_DAPM_OUTPUT("HPOUTR"),
829SND_SOC_DAPM_OUTPUT("LINEOUTL"),
830SND_SOC_DAPM_OUTPUT("LINEOUTR"),
831SND_SOC_DAPM_OUTPUT("LOP"),
832SND_SOC_DAPM_OUTPUT("LON"),
833SND_SOC_DAPM_OUTPUT("ROP"),
834SND_SOC_DAPM_OUTPUT("RON"),
835
836SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
837
838SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
839SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
840 &linput_inv_mux),
841SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
842
843SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
844SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
845 &rinput_inv_mux),
846SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
847
848SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
849SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
850
851SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
852SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
853
291ce18c
MB		 854SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
855SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
856
f1c0a02f
MB		 857SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
858SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
859
860SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
861 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
862SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
863 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
864
865SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
866 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
867SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
868 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
869
870SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
871 1, 0, NULL, 0, wm8903_output_event,
872 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 873 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 874SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
875 0, 0, NULL, 0, wm8903_output_event,
876 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 877 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 878
879SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
880 NULL, 0, wm8903_output_event,
881 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 882 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 883SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
884 NULL, 0, wm8903_output_event,
885 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 886 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 887
888SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
889 NULL, 0),
890SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
891 NULL, 0),
892
42768a12
MB		 893SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
894 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 895SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 896};
897
898static const struct snd_soc_dapm_route intercon[] = {
899
900 { "Left Input Mux", "IN1L", "IN1L" },
901 { "Left Input Mux", "IN2L", "IN2L" },
902 { "Left Input Mux", "IN3L", "IN3L" },
903
904 { "Left Input Inverting Mux", "IN1L", "IN1L" },
905 { "Left Input Inverting Mux", "IN2L", "IN2L" },
906 { "Left Input Inverting Mux", "IN3L", "IN3L" },
907
908 { "Right Input Mux", "IN1R", "IN1R" },
909 { "Right Input Mux", "IN2R", "IN2R" },
910 { "Right Input Mux", "IN3R", "IN3R" },
911
912 { "Right Input Inverting Mux", "IN1R", "IN1R" },
913 { "Right Input Inverting Mux", "IN2R", "IN2R" },
914 { "Right Input Inverting Mux", "IN3R", "IN3R" },
915
916 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
917 { "Left Input Mode Mux", "Differential Line",
918 "Left Input Mux" },
919 { "Left Input Mode Mux", "Differential Line",
920 "Left Input Inverting Mux" },
921 { "Left Input Mode Mux", "Differential Mic",
922 "Left Input Mux" },
923 { "Left Input Mode Mux", "Differential Mic",
924 "Left Input Inverting Mux" },
925
926 { "Right Input Mode Mux", "Single-Ended",
927 "Right Input Inverting Mux" },
928 { "Right Input Mode Mux", "Differential Line",
929 "Right Input Mux" },
930 { "Right Input Mode Mux", "Differential Line",
931 "Right Input Inverting Mux" },
932 { "Right Input Mode Mux", "Differential Mic",
933 "Right Input Mux" },
934 { "Right Input Mode Mux", "Differential Mic",
935 "Right Input Inverting Mux" },
936
937 { "Left Input PGA", NULL, "Left Input Mode Mux" },
938 { "Right Input PGA", NULL, "Right Input Mode Mux" },
939
940 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 941 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 942 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 943 { "ADCR", NULL, "CLK_DSP" },
944
291ce18c
MB		 945 { "DACL Sidetone", "Left", "ADCL" },
946 { "DACL Sidetone", "Right", "ADCR" },
947 { "DACR Sidetone", "Left", "ADCL" },
948 { "DACR Sidetone", "Right", "ADCR" },
949
950 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 951 { "DACL", NULL, "CLK_DSP" },
291ce18c 952 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 953 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 954
955 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
956 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
957 { "Left Output Mixer", "DACL Switch", "DACL" },
958 { "Left Output Mixer", "DACR Switch", "DACR" },
959
960 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
961 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
962 { "Right Output Mixer", "DACL Switch", "DACL" },
963 { "Right Output Mixer", "DACR Switch", "DACR" },
964
965 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
966 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
967 { "Left Speaker Mixer", "DACL Switch", "DACL" },
968 { "Left Speaker Mixer", "DACR Switch", "DACR" },
969
970 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
971 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
972 { "Right Speaker Mixer", "DACL Switch", "DACL" },
973 { "Right Speaker Mixer", "DACR Switch", "DACR" },
974
975 { "Left Line Output PGA", NULL, "Left Output Mixer" },
976 { "Right Line Output PGA", NULL, "Right Output Mixer" },
977
978 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
979 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
980
981 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
982 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
983
984 { "HPOUTL", NULL, "Left Headphone Output PGA" },
985 { "HPOUTR", NULL, "Right Headphone Output PGA" },
986
987 { "LINEOUTL", NULL, "Left Line Output PGA" },
988 { "LINEOUTR", NULL, "Right Line Output PGA" },
989
990 { "LOP", NULL, "Left Speaker PGA" },
991 { "LON", NULL, "Left Speaker PGA" },
992
993 { "ROP", NULL, "Right Speaker PGA" },
994 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 995
996 { "Left Headphone Output PGA", NULL, "Charge Pump" },
997 { "Right Headphone Output PGA", NULL, "Charge Pump" },
998 { "Left Line Output PGA", NULL, "Charge Pump" },
999 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1000};
1001
1002static int wm8903_add_widgets(struct snd_soc_codec *codec)
1003{
ce6120cc 1004 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 1005
ce6120cc
LG		 1006 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1007 ARRAY_SIZE(wm8903_dapm_widgets));
1008 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 1009
f1c0a02f
MB		 1010 return 0;
1011}
1012
1013static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1014 enum snd_soc_bias_level level)
1015{
f1c0a02f
MB		 1016 u16 reg, reg2;
1017
1018 switch (level) {
1019 case SND_SOC_BIAS_ON:
1020 case SND_SOC_BIAS_PREPARE:
8d50e447 1021 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1022 reg &= ~(WM8903_VMID_RES_MASK);
1023 reg |= WM8903_VMID_RES_50K;
8d50e447 1024 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1025 break;
1026
1027 case SND_SOC_BIAS_STANDBY:
ce6120cc 1028 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 1029 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 1030 WM8903_CLK_SYS_ENA);
1031
4dbfe809 1032 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 1033 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1034 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1035 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 1036
f1c0a02f
MB		 1037 wm8903_run_sequence(codec, 0);
1038 wm8903_sync_reg_cache(codec, codec->reg_cache);
1039
1040 /* Enable low impedence charge pump output */
8d50e447 1041 reg = snd_soc_read(codec,
f1c0a02f 1042 WM8903_CONTROL_INTERFACE_TEST_1);
8d50e447 1043 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f 1044 reg | WM8903_TEST_KEY);
8d50e447
MB		 1045 reg2 = snd_soc_read(codec, WM8903_CHARGE_PUMP_TEST_1);
1046 snd_soc_write(codec, WM8903_CHARGE_PUMP_TEST_1,
f1c0a02f 1047 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
8d50e447 1048 snd_soc_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
f1c0a02f
MB		 1049 reg);
1050
1051 /* By default no bypass paths are enabled so
1052 * enable Class W support.
1053 */
f0fba2ad 1054 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 1055 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 1056 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1057 }
1058
8d50e447 1059 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1060 reg &= ~(WM8903_VMID_RES_MASK);
1061 reg |= WM8903_VMID_RES_250K;
8d50e447 1062 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1063 break;
1064
1065 case SND_SOC_BIAS_OFF:
1066 wm8903_run_sequence(codec, 32);
8d50e447 1067 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 1068 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 1069 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1070 break;
1071 }
1072
ce6120cc 1073 codec->dapm.bias_level = level;
f1c0a02f
MB		 1074
1075 return 0;
1076}
1077
1078static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1079 int clk_id, unsigned int freq, int dir)
1080{
1081 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1082 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1083
1084 wm8903->sysclk = freq;
1085
1086 return 0;
1087}
1088
1089static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1090 unsigned int fmt)
1091{
1092 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1093 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1094
1095 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1096 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1097
1098 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1099 case SND_SOC_DAIFMT_CBS_CFS:
1100 break;
1101 case SND_SOC_DAIFMT_CBS_CFM:
1102 aif1 |= WM8903_LRCLK_DIR;
1103 break;
1104 case SND_SOC_DAIFMT_CBM_CFM:
1105 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1106 break;
1107 case SND_SOC_DAIFMT_CBM_CFS:
1108 aif1 |= WM8903_BCLK_DIR;
1109 break;
1110 default:
1111 return -EINVAL;
1112 }
1113
1114 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1115 case SND_SOC_DAIFMT_DSP_A:
1116 aif1 |= 0x3;
1117 break;
1118 case SND_SOC_DAIFMT_DSP_B:
1119 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1120 break;
1121 case SND_SOC_DAIFMT_I2S:
1122 aif1 |= 0x2;
1123 break;
1124 case SND_SOC_DAIFMT_RIGHT_J:
1125 aif1 |= 0x1;
1126 break;
1127 case SND_SOC_DAIFMT_LEFT_J:
1128 break;
1129 default:
1130 return -EINVAL;
1131 }
1132
1133 /* Clock inversion */
1134 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1135 case SND_SOC_DAIFMT_DSP_A:
1136 case SND_SOC_DAIFMT_DSP_B:
1137 /* frame inversion not valid for DSP modes */
1138 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1139 case SND_SOC_DAIFMT_NB_NF:
1140 break;
1141 case SND_SOC_DAIFMT_IB_NF:
1142 aif1 |= WM8903_AIF_BCLK_INV;
1143 break;
1144 default:
1145 return -EINVAL;
1146 }
1147 break;
1148 case SND_SOC_DAIFMT_I2S:
1149 case SND_SOC_DAIFMT_RIGHT_J:
1150 case SND_SOC_DAIFMT_LEFT_J:
1151 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1152 case SND_SOC_DAIFMT_NB_NF:
1153 break;
1154 case SND_SOC_DAIFMT_IB_IF:
1155 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1156 break;
1157 case SND_SOC_DAIFMT_IB_NF:
1158 aif1 |= WM8903_AIF_BCLK_INV;
1159 break;
1160 case SND_SOC_DAIFMT_NB_IF:
1161 aif1 |= WM8903_AIF_LRCLK_INV;
1162 break;
1163 default:
1164 return -EINVAL;
1165 }
1166 break;
1167 default:
1168 return -EINVAL;
1169 }
1170
8d50e447 1171 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1172
1173 return 0;
1174}
1175
1176static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1177{
1178 struct snd_soc_codec *codec = codec_dai->codec;
1179 u16 reg;
1180
8d50e447 1181 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1182
1183 if (mute)
1184 reg |= WM8903_DAC_MUTE;
1185 else
1186 reg &= ~WM8903_DAC_MUTE;
1187
8d50e447 1188 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1189
1190 return 0;
1191}
1192
1193/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1194 * for optimal performance so we list the lower rates first and match
1195 * on the last match we find. */
1196static struct {
1197 int div;
1198 int rate;
1199 int mode;
1200 int mclk_div;
1201} clk_sys_ratios[] = {
1202 { 64, 0x0, 0x0, 1 },
1203 { 68, 0x0, 0x1, 1 },
1204 { 125, 0x0, 0x2, 1 },
1205 { 128, 0x1, 0x0, 1 },
1206 { 136, 0x1, 0x1, 1 },
1207 { 192, 0x2, 0x0, 1 },
1208 { 204, 0x2, 0x1, 1 },
1209
1210 { 64, 0x0, 0x0, 2 },
1211 { 68, 0x0, 0x1, 2 },
1212 { 125, 0x0, 0x2, 2 },
1213 { 128, 0x1, 0x0, 2 },
1214 { 136, 0x1, 0x1, 2 },
1215 { 192, 0x2, 0x0, 2 },
1216 { 204, 0x2, 0x1, 2 },
1217
1218 { 250, 0x2, 0x2, 1 },
1219 { 256, 0x3, 0x0, 1 },
1220 { 272, 0x3, 0x1, 1 },
1221 { 384, 0x4, 0x0, 1 },
1222 { 408, 0x4, 0x1, 1 },
1223 { 375, 0x4, 0x2, 1 },
1224 { 512, 0x5, 0x0, 1 },
1225 { 544, 0x5, 0x1, 1 },
1226 { 500, 0x5, 0x2, 1 },
1227 { 768, 0x6, 0x0, 1 },
1228 { 816, 0x6, 0x1, 1 },
1229 { 750, 0x6, 0x2, 1 },
1230 { 1024, 0x7, 0x0, 1 },
1231 { 1088, 0x7, 0x1, 1 },
1232 { 1000, 0x7, 0x2, 1 },
1233 { 1408, 0x8, 0x0, 1 },
1234 { 1496, 0x8, 0x1, 1 },
1235 { 1536, 0x9, 0x0, 1 },
1236 { 1632, 0x9, 0x1, 1 },
1237 { 1500, 0x9, 0x2, 1 },
1238
1239 { 250, 0x2, 0x2, 2 },
1240 { 256, 0x3, 0x0, 2 },
1241 { 272, 0x3, 0x1, 2 },
1242 { 384, 0x4, 0x0, 2 },
1243 { 408, 0x4, 0x1, 2 },
1244 { 375, 0x4, 0x2, 2 },
1245 { 512, 0x5, 0x0, 2 },
1246 { 544, 0x5, 0x1, 2 },
1247 { 500, 0x5, 0x2, 2 },
1248 { 768, 0x6, 0x0, 2 },
1249 { 816, 0x6, 0x1, 2 },
1250 { 750, 0x6, 0x2, 2 },
1251 { 1024, 0x7, 0x0, 2 },
1252 { 1088, 0x7, 0x1, 2 },
1253 { 1000, 0x7, 0x2, 2 },
1254 { 1408, 0x8, 0x0, 2 },
1255 { 1496, 0x8, 0x1, 2 },
1256 { 1536, 0x9, 0x0, 2 },
1257 { 1632, 0x9, 0x1, 2 },
1258 { 1500, 0x9, 0x2, 2 },
1259};
1260
1261/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1262static struct {
1263 int ratio;
1264 int div;
1265} bclk_divs[] = {
1266 { 10, 0 },
f1c0a02f
MB		 1267 { 20, 2 },
1268 { 30, 3 },
1269 { 40, 4 },
1270 { 50, 5 },
f1c0a02f
MB		 1271 { 60, 7 },
1272 { 80, 8 },
1273 { 100, 9 },
f1c0a02f
MB		 1274 { 120, 11 },
1275 { 160, 12 },
1276 { 200, 13 },
1277 { 220, 14 },
1278 { 240, 15 },
f1c0a02f
MB		 1279 { 300, 17 },
1280 { 320, 18 },
1281 { 440, 19 },
1282 { 480, 20 },
1283};
1284
1285/* Sample rates for DSP */
1286static struct {
1287 int rate;
1288 int value;
1289} sample_rates[] = {
1290 { 8000, 0 },
1291 { 11025, 1 },
1292 { 12000, 2 },
1293 { 16000, 3 },
1294 { 22050, 4 },
1295 { 24000, 5 },
1296 { 32000, 6 },
1297 { 44100, 7 },
1298 { 48000, 8 },
1299 { 88200, 9 },
1300 { 96000, 10 },
1301 { 0, 0 },
1302};
1303
f1c0a02f 1304static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1305 struct snd_pcm_hw_params *params,
1306 struct snd_soc_dai *dai)
f1c0a02f
MB		 1307{
1308 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1309 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1310 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1311 int fs = params_rate(params);
1312 int bclk;
1313 int bclk_div;
1314 int i;
1315 int dsp_config;
1316 int clk_config;
1317 int best_val;
1318 int cur_val;
1319 int clk_sys;
1320
8d50e447
MB		 1321 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1322 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1323 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1324 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1325 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1326 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1327
9e79261f
MB		 1328 /* Enable sloping stopband filter for low sample rates */
1329 if (fs <= 24000)
1330 dac_digital1 |= WM8903_DAC_SB_FILT;
1331 else
1332 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1333
f1c0a02f
MB		 1334 /* Configure sample rate logic for DSP - choose nearest rate */
1335 dsp_config = 0;
1336 best_val = abs(sample_rates[dsp_config].rate - fs);
1337 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1338 cur_val = abs(sample_rates[i].rate - fs);
1339 if (cur_val <= best_val) {
1340 dsp_config = i;
1341 best_val = cur_val;
1342 }
1343 }
1344
f0fba2ad 1345 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1346 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1347 clock1 |= sample_rates[dsp_config].value;
1348
1349 aif1 &= ~WM8903_AIF_WL_MASK;
1350 bclk = 2 * fs;
1351 switch (params_format(params)) {
1352 case SNDRV_PCM_FORMAT_S16_LE:
1353 bclk *= 16;
1354 break;
1355 case SNDRV_PCM_FORMAT_S20_3LE:
1356 bclk *= 20;
1357 aif1 |= 0x4;
1358 break;
1359 case SNDRV_PCM_FORMAT_S24_LE:
1360 bclk *= 24;
1361 aif1 |= 0x8;
1362 break;
1363 case SNDRV_PCM_FORMAT_S32_LE:
1364 bclk *= 32;
1365 aif1 |= 0xc;
1366 break;
1367 default:
1368 return -EINVAL;
1369 }
1370
f0fba2ad 1371 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1372 wm8903->sysclk, fs);
1373
1374 /* We may not have an MCLK which allows us to generate exactly
1375 * the clock we want, particularly with USB derived inputs, so
1376 * approximate.
1377 */
1378 clk_config = 0;
1379 best_val = abs((wm8903->sysclk /
1380 (clk_sys_ratios[0].mclk_div *
1381 clk_sys_ratios[0].div)) - fs);
1382 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1383 cur_val = abs((wm8903->sysclk /
1384 (clk_sys_ratios[i].mclk_div *
1385 clk_sys_ratios[i].div)) - fs);
1386
1387 if (cur_val <= best_val) {
1388 clk_config = i;
1389 best_val = cur_val;
1390 }
1391 }
1392
1393 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1394 clock0 |= WM8903_MCLKDIV2;
1395 clk_sys = wm8903->sysclk / 2;
1396 } else {
1397 clock0 &= ~WM8903_MCLKDIV2;
1398 clk_sys = wm8903->sysclk;
1399 }
1400
1401 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1402 WM8903_CLK_SYS_MODE_MASK);
1403 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1404 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1405
f0fba2ad 1406 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1407 clk_sys_ratios[clk_config].rate,
1408 clk_sys_ratios[clk_config].mode,
1409 clk_sys_ratios[clk_config].div);
1410
f0fba2ad 1411 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1412
1413 /* We may not get quite the right frequency if using
1414 * approximate clocks so look for the closest match that is
1415 * higher than the target (we need to ensure that there enough
1416 * BCLKs to clock out the samples).
1417 */
1418 bclk_div = 0;
1419 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1420 i = 1;
1421 while (i < ARRAY_SIZE(bclk_divs)) {
1422 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1423 if (cur_val < 0) /* BCLK table is sorted */
1424 break;
1425 bclk_div = i;
1426 best_val = cur_val;
1427 i++;
1428 }
1429
1430 aif2 &= ~WM8903_BCLK_DIV_MASK;
1431 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1432
f0fba2ad 1433 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1434 bclk_divs[bclk_div].ratio / 10, bclk,
1435 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1436
1437 aif2 |= bclk_divs[bclk_div].div;
1438 aif3 |= bclk / fs;
1439
69fff9bb
MB		 1440 wm8903->fs = params_rate(params);
1441 wm8903_set_deemph(codec);
1442
8d50e447
MB		 1443 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1444 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1445 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1446 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1447 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1448 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1449
1450 return 0;
1451}
1452
7245387e
MB		 1453/**
1454 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1455 *
1456 * @codec: WM8903 codec
1457 * @jack: jack to report detection events on
1458 * @det: value to report for presence detection
1459 * @shrt: value to report for short detection
1460 *
1461 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1462 * being used to bring out signals to the processor then only platform
1463 * data configuration is needed for WM8903 and processor GPIOs should
1464 * be configured using snd_soc_jack_add_gpios() instead.
1465 *
1466 * The current threasholds for detection should be configured using
1467 * micdet_cfg in the platform data. Using this function will force on
1468 * the microphone bias for the device.
1469 */
1470int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1471 int det, int shrt)
1472{
b2c812e2 1473 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1474 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1475
1476 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1477 det, shrt);
1478
1479 /* Store the configuration */
1480 wm8903->mic_jack = jack;
1481 wm8903->mic_det = det;
1482 wm8903->mic_short = shrt;
1483
1484 /* Enable interrupts we've got a report configured for */
1485 if (det)
1486 irq_mask &= ~WM8903_MICDET_EINT;
1487 if (shrt)
1488 irq_mask &= ~WM8903_MICSHRT_EINT;
1489
1490 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1491 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1492 irq_mask);
1493
69266866
MB		 1494 if (det && shrt) {
1495 /* Enable mic detection, this may not have been set through
1496 * platform data (eg, if the defaults are OK). */
1497 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1498 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1499 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1500 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1501 } else {
1502 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1503 WM8903_MICDET_ENA, 0);
1504 }
7245387e
MB		 1505
1506 return 0;
1507}
1508EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1509
8abd16a6
MB		 1510static irqreturn_t wm8903_irq(int irq, void *data)
1511{
f0fba2ad
LG		 1512 struct snd_soc_codec *codec = data;
1513 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1514 int mic_report;
1515 int int_pol;
1516 int int_val = 0;
1517 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1518
7245387e 1519 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1520
7245387e 1521 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1522 dev_dbg(codec->dev, "Write sequencer done\n");
1523 complete(&wm8903->wseq);
1524 }
1525
7245387e
MB		 1526 /*
1527 * The rest is microphone jack detection. We need to manually
1528 * invert the polarity of the interrupt after each event - to
1529 * simplify the code keep track of the last state we reported
1530 * and just invert the relevant bits in both the report and
1531 * the polarity register.
1532 */
1533 mic_report = wm8903->mic_last_report;
1534 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1535
1536 if (int_val & WM8903_MICSHRT_EINT) {
1537 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1538
1539 mic_report ^= wm8903->mic_short;
1540 int_pol ^= WM8903_MICSHRT_INV;
1541 }
1542
1543 if (int_val & WM8903_MICDET_EINT) {
1544 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1545
1546 mic_report ^= wm8903->mic_det;
1547 int_pol ^= WM8903_MICDET_INV;
1548
1549 msleep(wm8903->mic_delay);
1550 }
1551
1552 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1553 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1554
1555 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1556 wm8903->mic_short | wm8903->mic_det);
1557
1558 wm8903->mic_last_report = mic_report;
1559
8abd16a6
MB		 1560 return IRQ_HANDLED;
1561}
1562
f1c0a02f
MB		 1563#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1564 SNDRV_PCM_RATE_11025 | \
1565 SNDRV_PCM_RATE_16000 | \
1566 SNDRV_PCM_RATE_22050 | \
1567 SNDRV_PCM_RATE_32000 | \
1568 SNDRV_PCM_RATE_44100 | \
1569 SNDRV_PCM_RATE_48000 | \
1570 SNDRV_PCM_RATE_88200 | \
1571 SNDRV_PCM_RATE_96000)
1572
1573#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1574 SNDRV_PCM_RATE_11025 | \
1575 SNDRV_PCM_RATE_16000 | \
1576 SNDRV_PCM_RATE_22050 | \
1577 SNDRV_PCM_RATE_32000 | \
1578 SNDRV_PCM_RATE_44100 | \
1579 SNDRV_PCM_RATE_48000)
1580
1581#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1582 SNDRV_PCM_FMTBIT_S20_3LE |\
1583 SNDRV_PCM_FMTBIT_S24_LE)
1584
6335d055 1585static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1586 .hw_params = wm8903_hw_params,
1587 .digital_mute = wm8903_digital_mute,
1588 .set_fmt = wm8903_set_dai_fmt,
1589 .set_sysclk = wm8903_set_dai_sysclk,
1590};
1591
f0fba2ad
LG		 1592static struct snd_soc_dai_driver wm8903_dai = {
1593 .name = "wm8903-hifi",
f1c0a02f
MB		 1594 .playback = {
1595 .stream_name = "Playback",
1596 .channels_min = 2,
1597 .channels_max = 2,
1598 .rates = WM8903_PLAYBACK_RATES,
1599 .formats = WM8903_FORMATS,
1600 },
1601 .capture = {
1602 .stream_name = "Capture",
1603 .channels_min = 2,
1604 .channels_max = 2,
1605 .rates = WM8903_CAPTURE_RATES,
1606 .formats = WM8903_FORMATS,
1607 },
6335d055 1608 .ops = &wm8903_dai_ops,
0d960e88 1609 .symmetric_rates = 1,
f1c0a02f 1610};
f1c0a02f 1611
f0fba2ad 1612static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1613{
f1c0a02f
MB		 1614 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1615
1616 return 0;
1617}
1618
f0fba2ad 1619static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1620{
f1c0a02f
MB		 1621 int i;
1622 u16 *reg_cache = codec->reg_cache;
40aa7030 1623 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1624 GFP_KERNEL);
1625
1626 /* Bring the codec back up to standby first to minimise pop/clicks */
1627 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1628
1629 /* Sync back everything else */
1630 if (tmp_cache) {
1631 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1632 if (tmp_cache[i] != reg_cache[i])
8d50e447 1633 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1634 kfree(tmp_cache);
f1c0a02f 1635 } else {
f0fba2ad 1636 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1637 }
1638
1639 return 0;
1640}
1641
f0fba2ad 1642static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1643{
f0fba2ad
LG		 1644 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1645 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1646 int ret, i;
8abd16a6 1647 int trigger, irq_pol;
f1c0a02f
MB		 1648 u16 val;
1649
8abd16a6 1650 init_completion(&wm8903->wseq);
d58d5d55 1651
8d50e447
MB		 1652 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1653 if (ret != 0) {
f0fba2ad
LG		 1654 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1655 return ret;
8d50e447
MB		 1656 }
1657
1658 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1659 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1660 dev_err(codec->dev,
d58d5d55
MB		 1661 "Device with ID register %x is not a WM8903\n", val);
1662 return -ENODEV;
f1c0a02f
MB		 1663 }
1664
8d50e447 1665 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
f0fba2ad 1666 dev_info(codec->dev, "WM8903 revision %d\n",
f1c0a02f
MB		 1667 val & WM8903_CHIP_REV_MASK);
1668
1669 wm8903_reset(codec);
1670
37f88e84 1671 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1672 if (pdata) {
1673 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1674 if (!pdata->gpio_cfg[i])
1675 continue;
1676
1677 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1678 pdata->gpio_cfg[i] & 0xffff);
1679 }
37f88e84
MB		 1680
1681 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1682 pdata->micdet_cfg);
1683
1684 /* Microphone detection needs the WSEQ clock */
1685 if (pdata->micdet_cfg)
1686 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1687 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1688
1689 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1690 }
8abd16a6 1691
f0fba2ad 1692 if (wm8903->irq) {
8abd16a6
MB		 1693 if (pdata && pdata->irq_active_low) {
1694 trigger = IRQF_TRIGGER_LOW;
1695 irq_pol = WM8903_IRQ_POL;
1696 } else {
1697 trigger = IRQF_TRIGGER_HIGH;
1698 irq_pol = 0;
1699 }
1700
1701 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1702 WM8903_IRQ_POL, irq_pol);
1703
f0fba2ad 1704 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1705 trigger | IRQF_ONESHOT,
f0fba2ad 1706 "wm8903", codec);
8abd16a6 1707 if (ret != 0) {
f0fba2ad 1708 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1709 ret);
f0fba2ad 1710 return ret;
8abd16a6
MB		 1711 }
1712
1713 /* Enable write sequencer interrupts */
1714 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1715 WM8903_IM_WSEQ_BUSY_EINT, 0);
1716 }
73b34ead 1717
f1c0a02f
MB		 1718 /* power on device */
1719 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1720
1721 /* Latch volume update bits */
8d50e447 1722 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1723 val |= WM8903_ADCVU;
8d50e447
MB		 1724 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1725 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1726
8d50e447 1727 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1728 val |= WM8903_DACVU;
8d50e447
MB		 1729 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1730 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1731
8d50e447 1732 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1733 val |= WM8903_HPOUTVU;
8d50e447
MB		 1734 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1735 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1736
8d50e447 1737 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1738 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1739 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1740 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1741
8d50e447 1742 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1743 val |= WM8903_SPKVU;
8d50e447
MB		 1744 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1745 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1746
1747 /* Enable DAC soft mute by default */
8d50e447 1748 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1749 val |= WM8903_DAC_MUTEMODE;
8d50e447 1750 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1751
f0fba2ad
LG		 1752 snd_soc_add_controls(codec, wm8903_snd_controls,
1753 ARRAY_SIZE(wm8903_snd_controls));
1754 wm8903_add_widgets(codec);
f1c0a02f 1755
f1c0a02f
MB		 1756 return ret;
1757}
1758
f0fba2ad
LG		 1759/* power down chip */
1760static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1761{
f0fba2ad
LG		 1762 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1763 return 0;
1764}
f1c0a02f 1765
f0fba2ad
LG		 1766static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1767 .probe = wm8903_probe,
1768 .remove = wm8903_remove,
1769 .suspend = wm8903_suspend,
1770 .resume = wm8903_resume,
1771 .set_bias_level = wm8903_set_bias_level,
1772 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1773 .reg_word_size = sizeof(u16),
1774 .reg_cache_default = wm8903_reg_defaults,
1775 .volatile_register = wm8903_volatile_register,
1776};
f1c0a02f 1777
f0fba2ad
LG		 1778#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1779static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1780 const struct i2c_device_id *id)
1781{
1782 struct wm8903_priv *wm8903;
1783 int ret;
f1c0a02f 1784
f0fba2ad
LG		 1785 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1786 if (wm8903 == NULL)
1787 return -ENOMEM;
8abd16a6 1788
f0fba2ad 1789 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 1790 wm8903->irq = i2c->irq;
d58d5d55 1791
f0fba2ad
LG		 1792 ret = snd_soc_register_codec(&i2c->dev,
1793 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1794 if (ret < 0)
1795 kfree(wm8903);
1796 return ret;
1797}
f1c0a02f 1798
f0fba2ad
LG		 1799static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1800{
1801 snd_soc_unregister_codec(&client->dev);
1802 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 1803 return 0;
1804}
1805
f1c0a02f 1806static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 1807 { "wm8903", 0 },
1808 { }
f1c0a02f
MB		 1809};
1810MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1811
1812static struct i2c_driver wm8903_i2c_driver = {
1813 .driver = {
f0fba2ad 1814 .name = "wm8903-codec",
f1c0a02f
MB		 1815 .owner = THIS_MODULE,
1816 },
f0fba2ad
LG		 1817 .probe = wm8903_i2c_probe,
1818 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1819 .id_table = wm8903_i2c_id,
1820};
f0fba2ad 1821#endif
f1c0a02f 1822
f0fba2ad 1823static int __init wm8903_modinit(void)
f1c0a02f 1824{
f1c0a02f 1825 int ret = 0;
f0fba2ad
LG		 1826#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1827 ret = i2c_add_driver(&wm8903_i2c_driver);
1828 if (ret != 0) {
1829 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1830 ret);
f1c0a02f 1831 }
f0fba2ad 1832#endif
f1c0a02f 1833 return ret;
64089b84
MB		 1834}
1835module_init(wm8903_modinit);
1836
1837static void __exit wm8903_exit(void)
1838{
f0fba2ad 1839#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 1840 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 1841#endif
64089b84
MB		 1842}
1843module_exit(wm8903_exit);
1844
f1c0a02f
MB		 1845MODULE_DESCRIPTION("ASoC WM8903 driver");
1846MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1847MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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