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ASoC: Remove redundant rate constraint for WM8903
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
14 * - Mic detect.
15 * - Digital microphone support.
16 * - Interrupt support (mic detect and sequencer).
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/pm.h>
24#include <linux/i2c.h>
25#include <linux/platform_device.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/tlv.h>
30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/initval.h>
33
34#include "wm8903.h"
35
f1c0a02f
MB		 36/* Register defaults at reset */
37static u16 wm8903_reg_defaults[] = {
38 0x8903, /* R0 - SW Reset and ID */
39 0x0000, /* R1 - Revision Number */
40 0x0000, /* R2 */
41 0x0000, /* R3 */
42 0x0018, /* R4 - Bias Control 0 */
43 0x0000, /* R5 - VMID Control 0 */
44 0x0000, /* R6 - Mic Bias Control 0 */
45 0x0000, /* R7 */
46 0x0001, /* R8 - Analogue DAC 0 */
47 0x0000, /* R9 */
48 0x0001, /* R10 - Analogue ADC 0 */
49 0x0000, /* R11 */
50 0x0000, /* R12 - Power Management 0 */
51 0x0000, /* R13 - Power Management 1 */
52 0x0000, /* R14 - Power Management 2 */
53 0x0000, /* R15 - Power Management 3 */
54 0x0000, /* R16 - Power Management 4 */
55 0x0000, /* R17 - Power Management 5 */
56 0x0000, /* R18 - Power Management 6 */
57 0x0000, /* R19 */
58 0x0400, /* R20 - Clock Rates 0 */
59 0x0D07, /* R21 - Clock Rates 1 */
60 0x0000, /* R22 - Clock Rates 2 */
61 0x0000, /* R23 */
62 0x0050, /* R24 - Audio Interface 0 */
63 0x0242, /* R25 - Audio Interface 1 */
64 0x0008, /* R26 - Audio Interface 2 */
65 0x0022, /* R27 - Audio Interface 3 */
66 0x0000, /* R28 */
67 0x0000, /* R29 */
68 0x00C0, /* R30 - DAC Digital Volume Left */
69 0x00C0, /* R31 - DAC Digital Volume Right */
70 0x0000, /* R32 - DAC Digital 0 */
71 0x0000, /* R33 - DAC Digital 1 */
72 0x0000, /* R34 */
73 0x0000, /* R35 */
74 0x00C0, /* R36 - ADC Digital Volume Left */
75 0x00C0, /* R37 - ADC Digital Volume Right */
76 0x0000, /* R38 - ADC Digital 0 */
77 0x0073, /* R39 - Digital Microphone 0 */
78 0x09BF, /* R40 - DRC 0 */
79 0x3241, /* R41 - DRC 1 */
80 0x0020, /* R42 - DRC 2 */
81 0x0000, /* R43 - DRC 3 */
82 0x0085, /* R44 - Analogue Left Input 0 */
83 0x0085, /* R45 - Analogue Right Input 0 */
84 0x0044, /* R46 - Analogue Left Input 1 */
85 0x0044, /* R47 - Analogue Right Input 1 */
86 0x0000, /* R48 */
87 0x0000, /* R49 */
88 0x0008, /* R50 - Analogue Left Mix 0 */
89 0x0004, /* R51 - Analogue Right Mix 0 */
90 0x0000, /* R52 - Analogue Spk Mix Left 0 */
91 0x0000, /* R53 - Analogue Spk Mix Left 1 */
92 0x0000, /* R54 - Analogue Spk Mix Right 0 */
93 0x0000, /* R55 - Analogue Spk Mix Right 1 */
94 0x0000, /* R56 */
95 0x002D, /* R57 - Analogue OUT1 Left */
96 0x002D, /* R58 - Analogue OUT1 Right */
97 0x0039, /* R59 - Analogue OUT2 Left */
98 0x0039, /* R60 - Analogue OUT2 Right */
99 0x0100, /* R61 */
100 0x0139, /* R62 - Analogue OUT3 Left */
101 0x0139, /* R63 - Analogue OUT3 Right */
102 0x0000, /* R64 */
103 0x0000, /* R65 - Analogue SPK Output Control 0 */
104 0x0000, /* R66 */
105 0x0010, /* R67 - DC Servo 0 */
106 0x0100, /* R68 */
107 0x00A4, /* R69 - DC Servo 2 */
108 0x0807, /* R70 */
109 0x0000, /* R71 */
110 0x0000, /* R72 */
111 0x0000, /* R73 */
112 0x0000, /* R74 */
113 0x0000, /* R75 */
114 0x0000, /* R76 */
115 0x0000, /* R77 */
116 0x0000, /* R78 */
117 0x000E, /* R79 */
118 0x0000, /* R80 */
119 0x0000, /* R81 */
120 0x0000, /* R82 */
121 0x0000, /* R83 */
122 0x0000, /* R84 */
123 0x0000, /* R85 */
124 0x0000, /* R86 */
125 0x0006, /* R87 */
126 0x0000, /* R88 */
127 0x0000, /* R89 */
128 0x0000, /* R90 - Analogue HP 0 */
129 0x0060, /* R91 */
130 0x0000, /* R92 */
131 0x0000, /* R93 */
132 0x0000, /* R94 - Analogue Lineout 0 */
133 0x0060, /* R95 */
134 0x0000, /* R96 */
135 0x0000, /* R97 */
136 0x0000, /* R98 - Charge Pump 0 */
137 0x1F25, /* R99 */
138 0x2B19, /* R100 */
139 0x01C0, /* R101 */
140 0x01EF, /* R102 */
141 0x2B00, /* R103 */
142 0x0000, /* R104 - Class W 0 */
143 0x01C0, /* R105 */
144 0x1C10, /* R106 */
145 0x0000, /* R107 */
146 0x0000, /* R108 - Write Sequencer 0 */
147 0x0000, /* R109 - Write Sequencer 1 */
148 0x0000, /* R110 - Write Sequencer 2 */
149 0x0000, /* R111 - Write Sequencer 3 */
150 0x0000, /* R112 - Write Sequencer 4 */
151 0x0000, /* R113 */
152 0x0000, /* R114 - Control Interface */
153 0x0000, /* R115 */
154 0x00A8, /* R116 - GPIO Control 1 */
155 0x00A8, /* R117 - GPIO Control 2 */
156 0x00A8, /* R118 - GPIO Control 3 */
157 0x0220, /* R119 - GPIO Control 4 */
158 0x01A0, /* R120 - GPIO Control 5 */
159 0x0000, /* R121 - Interrupt Status 1 */
160 0xFFFF, /* R122 - Interrupt Status 1 Mask */
161 0x0000, /* R123 - Interrupt Polarity 1 */
162 0x0000, /* R124 */
163 0x0003, /* R125 */
164 0x0000, /* R126 - Interrupt Control */
165 0x0000, /* R127 */
166 0x0005, /* R128 */
167 0x0000, /* R129 - Control Interface Test 1 */
168 0x0000, /* R130 */
169 0x0000, /* R131 */
170 0x0000, /* R132 */
171 0x0000, /* R133 */
172 0x0000, /* R134 */
173 0x03FF, /* R135 */
174 0x0007, /* R136 */
175 0x0040, /* R137 */
176 0x0000, /* R138 */
177 0x0000, /* R139 */
178 0x0000, /* R140 */
179 0x0000, /* R141 */
180 0x0000, /* R142 */
181 0x0000, /* R143 */
182 0x0000, /* R144 */
183 0x0000, /* R145 */
184 0x0000, /* R146 */
185 0x0000, /* R147 */
186 0x4000, /* R148 */
187 0x6810, /* R149 - Charge Pump Test 1 */
188 0x0004, /* R150 */
189 0x0000, /* R151 */
190 0x0000, /* R152 */
191 0x0000, /* R153 */
192 0x0000, /* R154 */
193 0x0000, /* R155 */
194 0x0000, /* R156 */
195 0x0000, /* R157 */
196 0x0000, /* R158 */
197 0x0000, /* R159 */
198 0x0000, /* R160 */
199 0x0000, /* R161 */
200 0x0000, /* R162 */
201 0x0000, /* R163 */
202 0x0028, /* R164 - Clock Rate Test 4 */
203 0x0004, /* R165 */
204 0x0000, /* R166 */
205 0x0060, /* R167 */
206 0x0000, /* R168 */
207 0x0000, /* R169 */
208 0x0000, /* R170 */
209 0x0000, /* R171 */
210 0x0000, /* R172 - Analogue Output Bias 0 */
211};
212
d58d5d55
MB		 213struct wm8903_priv {
214 struct snd_soc_codec codec;
215 u16 reg_cache[ARRAY_SIZE(wm8903_reg_defaults)];
216
217 int sysclk;
218
219 /* Reference counts */
d58d5d55
MB		 220 int class_w_users;
221 int playback_active;
222 int capture_active;
223
224 struct snd_pcm_substream *master_substream;
225 struct snd_pcm_substream *slave_substream;
226};
227
228
f1c0a02f
MB		 229static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
230 unsigned int reg)
231{
232 u16 *cache = codec->reg_cache;
233
234 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
235
236 return cache[reg];
237}
238
239static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
240{
241 struct i2c_msg xfer[2];
242 u16 data;
243 int ret;
244 struct i2c_client *client = codec->control_data;
245
246 /* Write register */
247 xfer[0].addr = client->addr;
248 xfer[0].flags = 0;
249 xfer[0].len = 1;
250 xfer[0].buf = &reg;
251
252 /* Read data */
253 xfer[1].addr = client->addr;
254 xfer[1].flags = I2C_M_RD;
255 xfer[1].len = 2;
256 xfer[1].buf = (u8 *)&data;
257
258 ret = i2c_transfer(client->adapter, xfer, 2);
259 if (ret != 2) {
260 pr_err("i2c_transfer returned %d\n", ret);
261 return 0;
262 }
263
264 return (data >> 8) | ((data & 0xff) << 8);
265}
266
267static unsigned int wm8903_read(struct snd_soc_codec *codec,
268 unsigned int reg)
269{
270 switch (reg) {
271 case WM8903_SW_RESET_AND_ID:
272 case WM8903_REVISION_NUMBER:
273 case WM8903_INTERRUPT_STATUS_1:
274 case WM8903_WRITE_SEQUENCER_4:
275 return wm8903_hw_read(codec, reg);
276
277 default:
278 return wm8903_read_reg_cache(codec, reg);
279 }
280}
281
282static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
283 u16 reg, unsigned int value)
284{
285 u16 *cache = codec->reg_cache;
286
287 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
288
289 switch (reg) {
290 case WM8903_SW_RESET_AND_ID:
291 case WM8903_REVISION_NUMBER:
292 break;
293
294 default:
295 cache[reg] = value;
296 break;
297 }
298}
299
300static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
301 unsigned int value)
302{
303 u8 data[3];
304
305 wm8903_write_reg_cache(codec, reg, value);
306
307 /* Data format is 1 byte of address followed by 2 bytes of data */
308 data[0] = reg;
309 data[1] = (value >> 8) & 0xff;
310 data[2] = value & 0xff;
311
312 if (codec->hw_write(codec->control_data, data, 3) == 2)
313 return 0;
314 else
315 return -EIO;
316}
317
318static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
319{
320 u16 reg[5];
321 struct i2c_client *i2c = codec->control_data;
322
323 BUG_ON(start > 48);
324
325 /* Enable the sequencer */
326 reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0);
327 reg[0] |= WM8903_WSEQ_ENA;
328 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
329
330 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
331
332 wm8903_write(codec, WM8903_WRITE_SEQUENCER_3,
333 start | WM8903_WSEQ_START);
334
335 /* Wait for it to complete. If we have the interrupt wired up then
336 * we could block waiting for an interrupt, though polling may still
337 * be desirable for diagnostic purposes.
338 */
339 do {
340 msleep(10);
341
342 reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4);
343 } while (reg[4] & WM8903_WSEQ_BUSY);
344
345 dev_dbg(&i2c->dev, "Sequence complete\n");
346
347 /* Disable the sequencer again */
348 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0,
349 reg[0] & ~WM8903_WSEQ_ENA);
350
351 return 0;
352}
353
354static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
355{
356 int i;
357
358 /* There really ought to be something better we can do here :/ */
359 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
360 cache[i] = wm8903_hw_read(codec, i);
361}
362
363static void wm8903_reset(struct snd_soc_codec *codec)
364{
365 wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 366 memcpy(codec->reg_cache, wm8903_reg_defaults,
367 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 368}
369
370#define WM8903_OUTPUT_SHORT 0x8
371#define WM8903_OUTPUT_OUT 0x4
372#define WM8903_OUTPUT_INT 0x2
373#define WM8903_OUTPUT_IN 0x1
374
42768a12
MB		 375static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
376 struct snd_kcontrol *kcontrol, int event)
377{
378 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
379 mdelay(4);
380
381 return 0;
382}
383
f1c0a02f
MB		 384/*
385 * Event for headphone and line out amplifier power changes. Special
386 * power up/down sequences are required in order to maximise pop/click
387 * performance.
388 */
389static int wm8903_output_event(struct snd_soc_dapm_widget *w,
390 struct snd_kcontrol *kcontrol, int event)
391{
392 struct snd_soc_codec *codec = w->codec;
f1c0a02f 393 u16 val;
0bc286e2 394 u16 reg;
d7d5c547
MB		 395 u16 dcs_reg;
396 u16 dcs_bit;
0bc286e2 397 int shift;
f1c0a02f
MB		 398
399 switch (w->reg) {
400 case WM8903_POWER_MANAGEMENT_2:
401 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 402 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 403 break;
404 case WM8903_POWER_MANAGEMENT_3:
405 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 406 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 407 break;
408 default:
409 BUG();
1e297a19 410 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 411 }
412
413 switch (w->shift) {
414 case 0:
415 shift = 0;
416 break;
417 case 1:
418 shift = 4;
419 break;
420 default:
421 BUG();
1e297a19 422 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 423 }
424
425 if (event & SND_SOC_DAPM_PRE_PMU) {
426 val = wm8903_read(codec, reg);
427
428 /* Short the output */
429 val &= ~(WM8903_OUTPUT_SHORT << shift);
430 wm8903_write(codec, reg, val);
f1c0a02f
MB		 431 }
432
433 if (event & SND_SOC_DAPM_POST_PMU) {
434 val = wm8903_read(codec, reg);
435
436 val |= (WM8903_OUTPUT_IN << shift);
437 wm8903_write(codec, reg, val);
438
439 val |= (WM8903_OUTPUT_INT << shift);
440 wm8903_write(codec, reg, val);
441
442 /* Turn on the output ENA_OUTP */
443 val |= (WM8903_OUTPUT_OUT << shift);
444 wm8903_write(codec, reg, val);
445
d7d5c547
MB		 446 /* Enable the DC servo */
447 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0);
448 dcs_reg |= dcs_bit;
449 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg);
450
f1c0a02f
MB		 451 /* Remove the short */
452 val |= (WM8903_OUTPUT_SHORT << shift);
453 wm8903_write(codec, reg, val);
454 }
455
456 if (event & SND_SOC_DAPM_PRE_PMD) {
457 val = wm8903_read(codec, reg);
458
459 /* Short the output */
460 val &= ~(WM8903_OUTPUT_SHORT << shift);
461 wm8903_write(codec, reg, val);
462
d7d5c547
MB		 463 /* Disable the DC servo */
464 dcs_reg = wm8903_read(codec, WM8903_DC_SERVO_0);
465 dcs_reg &= ~dcs_bit;
466 wm8903_write(codec, WM8903_DC_SERVO_0, dcs_reg);
467
f1c0a02f
MB		 468 /* Then disable the intermediate and output stages */
469 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
470 WM8903_OUTPUT_IN) << shift);
471 wm8903_write(codec, reg, val);
472 }
473
f1c0a02f
MB		 474 return 0;
475}
476
477/*
478 * When used with DAC outputs only the WM8903 charge pump supports
479 * operation in class W mode, providing very low power consumption
480 * when used with digital sources. Enable and disable this mode
481 * automatically depending on the mixer configuration.
482 *
483 * All the relevant controls are simple switches.
484 */
485static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
489 struct snd_soc_codec *codec = widget->codec;
490 struct wm8903_priv *wm8903 = codec->private_data;
491 struct i2c_client *i2c = codec->control_data;
492 u16 reg;
493 int ret;
494
495 reg = wm8903_read(codec, WM8903_CLASS_W_0);
496
497 /* Turn it off if we're about to enable bypass */
498 if (ucontrol->value.integer.value[0]) {
499 if (wm8903->class_w_users == 0) {
500 dev_dbg(&i2c->dev, "Disabling Class W\n");
501 wm8903_write(codec, WM8903_CLASS_W_0, reg &
502 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
503 }
504 wm8903->class_w_users++;
505 }
506
507 /* Implement the change */
508 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
509
510 /* If we've just disabled the last bypass path turn Class W on */
511 if (!ucontrol->value.integer.value[0]) {
512 if (wm8903->class_w_users == 1) {
513 dev_dbg(&i2c->dev, "Enabling Class W\n");
514 wm8903_write(codec, WM8903_CLASS_W_0, reg |
515 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
516 }
517 wm8903->class_w_users--;
518 }
519
520 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
521 wm8903->class_w_users);
522
523 return ret;
524}
525
526#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
527{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
528 .info = snd_soc_info_volsw, \
529 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
530 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
531
532
533/* ALSA can only do steps of .01dB */
534static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
535
536static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
537
538static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
539static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
540static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
541static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
542static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
543
544static const char *drc_slope_text[] = {
545 "1", "1/2", "1/4", "1/8", "1/16", "0"
546};
547
548static const struct soc_enum drc_slope_r0 =
549 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
550
551static const struct soc_enum drc_slope_r1 =
552 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
553
554static const char *drc_attack_text[] = {
555 "instantaneous",
556 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
557 "46.4ms", "92.8ms", "185.6ms"
558};
559
560static const struct soc_enum drc_attack =
561 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
562
563static const char *drc_decay_text[] = {
564 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
565 "23.87s", "47.56s"
566};
567
568static const struct soc_enum drc_decay =
569 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
570
571static const char *drc_ff_delay_text[] = {
572 "5 samples", "9 samples"
573};
574
575static const struct soc_enum drc_ff_delay =
576 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
577
578static const char *drc_qr_decay_text[] = {
579 "0.725ms", "1.45ms", "5.8ms"
580};
581
582static const struct soc_enum drc_qr_decay =
583 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
584
585static const char *drc_smoothing_text[] = {
586 "Low", "Medium", "High"
587};
588
589static const struct soc_enum drc_smoothing =
590 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
591
592static const char *soft_mute_text[] = {
593 "Fast (fs/2)", "Slow (fs/32)"
594};
595
596static const struct soc_enum soft_mute =
597 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
598
599static const char *mute_mode_text[] = {
600 "Hard", "Soft"
601};
602
603static const struct soc_enum mute_mode =
604 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
605
606static const char *dac_deemphasis_text[] = {
607 "Disabled", "32kHz", "44.1kHz", "48kHz"
608};
609
610static const struct soc_enum dac_deemphasis =
611 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
612
613static const char *companding_text[] = {
614 "ulaw", "alaw"
615};
616
617static const struct soc_enum dac_companding =
618 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
619
620static const struct soc_enum adc_companding =
621 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
622
623static const char *input_mode_text[] = {
624 "Single-Ended", "Differential Line", "Differential Mic"
625};
626
627static const struct soc_enum linput_mode_enum =
628 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
629
630static const struct soc_enum rinput_mode_enum =
631 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
632
633static const char *linput_mux_text[] = {
634 "IN1L", "IN2L", "IN3L"
635};
636
637static const struct soc_enum linput_enum =
638 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
639
640static const struct soc_enum linput_inv_enum =
641 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
642
643static const char *rinput_mux_text[] = {
644 "IN1R", "IN2R", "IN3R"
645};
646
647static const struct soc_enum rinput_enum =
648 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
649
650static const struct soc_enum rinput_inv_enum =
651 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
652
653
654static const struct snd_kcontrol_new wm8903_snd_controls[] = {
655
656/* Input PGAs - No TLV since the scale depends on PGA mode */
657SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 658 7, 1, 1),
f1c0a02f
MB		 659SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
660 0, 31, 0),
661SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
662 6, 1, 0),
663
664SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 665 7, 1, 1),
f1c0a02f
MB		 666SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
667 0, 31, 0),
668SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
669 6, 1, 0),
670
671/* ADCs */
672SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
673SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
674SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
675SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1,
676 drc_tlv_thresh),
677SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
678SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
679SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
680SOC_ENUM("DRC Attack Rate", drc_attack),
681SOC_ENUM("DRC Decay Rate", drc_decay),
682SOC_ENUM("DRC FF Delay", drc_ff_delay),
683SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
684SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
685SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
686SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
687SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
688SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
689SOC_ENUM("DRC Smoothing Threashold", drc_smoothing),
690SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
691
692SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
693 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
694SOC_ENUM("ADC Companding Mode", adc_companding),
695SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
696
697/* DAC */
698SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
699 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
700SOC_ENUM("DAC Soft Mute Rate", soft_mute),
701SOC_ENUM("DAC Mute Mode", mute_mode),
702SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
703SOC_ENUM("DAC De-emphasis", dac_deemphasis),
704SOC_SINGLE("DAC Sloping Stopband Filter Switch",
705 WM8903_DAC_DIGITAL_1, 11, 1, 0),
706SOC_ENUM("DAC Companding Mode", dac_companding),
707SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
708
709/* Headphones */
710SOC_DOUBLE_R("Headphone Switch",
711 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
712 8, 1, 1),
713SOC_DOUBLE_R("Headphone ZC Switch",
714 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
715 6, 1, 0),
716SOC_DOUBLE_R_TLV("Headphone Volume",
717 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
718 0, 63, 0, out_tlv),
719
720/* Line out */
721SOC_DOUBLE_R("Line Out Switch",
722 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
723 8, 1, 1),
724SOC_DOUBLE_R("Line Out ZC Switch",
725 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
726 6, 1, 0),
727SOC_DOUBLE_R_TLV("Line Out Volume",
728 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
729 0, 63, 0, out_tlv),
730
731/* Speaker */
732SOC_DOUBLE_R("Speaker Switch",
733 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
734SOC_DOUBLE_R("Speaker ZC Switch",
735 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
736SOC_DOUBLE_R_TLV("Speaker Volume",
737 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
738 0, 63, 0, out_tlv),
739};
740
f1c0a02f
MB		 741static const struct snd_kcontrol_new linput_mode_mux =
742 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
743
744static const struct snd_kcontrol_new rinput_mode_mux =
745 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
746
747static const struct snd_kcontrol_new linput_mux =
748 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
749
750static const struct snd_kcontrol_new linput_inv_mux =
751 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
752
753static const struct snd_kcontrol_new rinput_mux =
754 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
755
756static const struct snd_kcontrol_new rinput_inv_mux =
757 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
758
759static const struct snd_kcontrol_new left_output_mixer[] = {
760SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
761SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
762SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 763SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 764};
765
766static const struct snd_kcontrol_new right_output_mixer[] = {
767SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
768SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
769SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 770SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 771};
772
773static const struct snd_kcontrol_new left_speaker_mixer[] = {
774SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
775SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
776SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
777SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 778 0, 1, 0),
f1c0a02f
MB		 779};
780
781static const struct snd_kcontrol_new right_speaker_mixer[] = {
782SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
783SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
784SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
785 1, 1, 0),
786SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 787 0, 1, 0),
f1c0a02f
MB		 788};
789
790static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
791SND_SOC_DAPM_INPUT("IN1L"),
792SND_SOC_DAPM_INPUT("IN1R"),
793SND_SOC_DAPM_INPUT("IN2L"),
794SND_SOC_DAPM_INPUT("IN2R"),
795SND_SOC_DAPM_INPUT("IN3L"),
796SND_SOC_DAPM_INPUT("IN3R"),
797
798SND_SOC_DAPM_OUTPUT("HPOUTL"),
799SND_SOC_DAPM_OUTPUT("HPOUTR"),
800SND_SOC_DAPM_OUTPUT("LINEOUTL"),
801SND_SOC_DAPM_OUTPUT("LINEOUTR"),
802SND_SOC_DAPM_OUTPUT("LOP"),
803SND_SOC_DAPM_OUTPUT("LON"),
804SND_SOC_DAPM_OUTPUT("ROP"),
805SND_SOC_DAPM_OUTPUT("RON"),
806
807SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
808
809SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
810SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
811 &linput_inv_mux),
812SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
813
814SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
815SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
816 &rinput_inv_mux),
817SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
818
819SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
820SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
821
822SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
823SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
824
825SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
826SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
827
828SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
829 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
830SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
831 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
832
833SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
834 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
835SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
836 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
837
838SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
839 1, 0, NULL, 0, wm8903_output_event,
840 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 841 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 842SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
843 0, 0, NULL, 0, wm8903_output_event,
844 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 845 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 846
847SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
848 NULL, 0, wm8903_output_event,
849 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 850 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 851SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
852 NULL, 0, wm8903_output_event,
853 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 854 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 855
856SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
857 NULL, 0),
858SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
859 NULL, 0),
860
42768a12
MB		 861SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
862 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 863SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 864};
865
866static const struct snd_soc_dapm_route intercon[] = {
867
868 { "Left Input Mux", "IN1L", "IN1L" },
869 { "Left Input Mux", "IN2L", "IN2L" },
870 { "Left Input Mux", "IN3L", "IN3L" },
871
872 { "Left Input Inverting Mux", "IN1L", "IN1L" },
873 { "Left Input Inverting Mux", "IN2L", "IN2L" },
874 { "Left Input Inverting Mux", "IN3L", "IN3L" },
875
876 { "Right Input Mux", "IN1R", "IN1R" },
877 { "Right Input Mux", "IN2R", "IN2R" },
878 { "Right Input Mux", "IN3R", "IN3R" },
879
880 { "Right Input Inverting Mux", "IN1R", "IN1R" },
881 { "Right Input Inverting Mux", "IN2R", "IN2R" },
882 { "Right Input Inverting Mux", "IN3R", "IN3R" },
883
884 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
885 { "Left Input Mode Mux", "Differential Line",
886 "Left Input Mux" },
887 { "Left Input Mode Mux", "Differential Line",
888 "Left Input Inverting Mux" },
889 { "Left Input Mode Mux", "Differential Mic",
890 "Left Input Mux" },
891 { "Left Input Mode Mux", "Differential Mic",
892 "Left Input Inverting Mux" },
893
894 { "Right Input Mode Mux", "Single-Ended",
895 "Right Input Inverting Mux" },
896 { "Right Input Mode Mux", "Differential Line",
897 "Right Input Mux" },
898 { "Right Input Mode Mux", "Differential Line",
899 "Right Input Inverting Mux" },
900 { "Right Input Mode Mux", "Differential Mic",
901 "Right Input Mux" },
902 { "Right Input Mode Mux", "Differential Mic",
903 "Right Input Inverting Mux" },
904
905 { "Left Input PGA", NULL, "Left Input Mode Mux" },
906 { "Right Input PGA", NULL, "Right Input Mode Mux" },
907
908 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 909 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 910 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 911 { "ADCR", NULL, "CLK_DSP" },
912
913 { "DACL", NULL, "CLK_DSP" },
914 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 915
916 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
917 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
918 { "Left Output Mixer", "DACL Switch", "DACL" },
919 { "Left Output Mixer", "DACR Switch", "DACR" },
920
921 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
922 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
923 { "Right Output Mixer", "DACL Switch", "DACL" },
924 { "Right Output Mixer", "DACR Switch", "DACR" },
925
926 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
927 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
928 { "Left Speaker Mixer", "DACL Switch", "DACL" },
929 { "Left Speaker Mixer", "DACR Switch", "DACR" },
930
931 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
932 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
933 { "Right Speaker Mixer", "DACL Switch", "DACL" },
934 { "Right Speaker Mixer", "DACR Switch", "DACR" },
935
936 { "Left Line Output PGA", NULL, "Left Output Mixer" },
937 { "Right Line Output PGA", NULL, "Right Output Mixer" },
938
939 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
940 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
941
942 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
943 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
944
945 { "HPOUTL", NULL, "Left Headphone Output PGA" },
946 { "HPOUTR", NULL, "Right Headphone Output PGA" },
947
948 { "LINEOUTL", NULL, "Left Line Output PGA" },
949 { "LINEOUTR", NULL, "Right Line Output PGA" },
950
951 { "LOP", NULL, "Left Speaker PGA" },
952 { "LON", NULL, "Left Speaker PGA" },
953
954 { "ROP", NULL, "Right Speaker PGA" },
955 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 956
957 { "Left Headphone Output PGA", NULL, "Charge Pump" },
958 { "Right Headphone Output PGA", NULL, "Charge Pump" },
959 { "Left Line Output PGA", NULL, "Charge Pump" },
960 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 961};
962
963static int wm8903_add_widgets(struct snd_soc_codec *codec)
964{
965 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
966 ARRAY_SIZE(wm8903_dapm_widgets));
967
968 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
969
970 snd_soc_dapm_new_widgets(codec);
971
972 return 0;
973}
974
975static int wm8903_set_bias_level(struct snd_soc_codec *codec,
976 enum snd_soc_bias_level level)
977{
978 struct i2c_client *i2c = codec->control_data;
979 u16 reg, reg2;
980
981 switch (level) {
982 case SND_SOC_BIAS_ON:
983 case SND_SOC_BIAS_PREPARE:
984 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
985 reg &= ~(WM8903_VMID_RES_MASK);
986 reg |= WM8903_VMID_RES_50K;
987 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
988 break;
989
990 case SND_SOC_BIAS_STANDBY:
991 if (codec->bias_level == SND_SOC_BIAS_OFF) {
3b1228ab
MB		 992 wm8903_write(codec, WM8903_CLOCK_RATES_2,
993 WM8903_CLK_SYS_ENA);
994
4dbfe809
MB		 995 /* Change DC servo dither level in startup sequence */
996 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
997 wm8903_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
998 wm8903_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
999
f1c0a02f
MB		 1000 wm8903_run_sequence(codec, 0);
1001 wm8903_sync_reg_cache(codec, codec->reg_cache);
1002
1003 /* Enable low impedence charge pump output */
1004 reg = wm8903_read(codec,
1005 WM8903_CONTROL_INTERFACE_TEST_1);
1006 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1007 reg | WM8903_TEST_KEY);
1008 reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1);
1009 wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1,
1010 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
1011 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1012 reg);
1013
1014 /* By default no bypass paths are enabled so
1015 * enable Class W support.
1016 */
1017 dev_dbg(&i2c->dev, "Enabling Class W\n");
1018 wm8903_write(codec, WM8903_CLASS_W_0, reg |
1019 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1020 }
1021
1022 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
1023 reg &= ~(WM8903_VMID_RES_MASK);
1024 reg |= WM8903_VMID_RES_250K;
1025 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
1026 break;
1027
1028 case SND_SOC_BIAS_OFF:
1029 wm8903_run_sequence(codec, 32);
3b1228ab
MB		 1030 reg = wm8903_read(codec, WM8903_CLOCK_RATES_2);
1031 reg &= ~WM8903_CLK_SYS_ENA;
1032 wm8903_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1033 break;
1034 }
1035
1036 codec->bias_level = level;
1037
1038 return 0;
1039}
1040
1041static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1042 int clk_id, unsigned int freq, int dir)
1043{
1044 struct snd_soc_codec *codec = codec_dai->codec;
1045 struct wm8903_priv *wm8903 = codec->private_data;
1046
1047 wm8903->sysclk = freq;
1048
1049 return 0;
1050}
1051
1052static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1053 unsigned int fmt)
1054{
1055 struct snd_soc_codec *codec = codec_dai->codec;
1056 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1057
1058 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1059 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1060
1061 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1062 case SND_SOC_DAIFMT_CBS_CFS:
1063 break;
1064 case SND_SOC_DAIFMT_CBS_CFM:
1065 aif1 |= WM8903_LRCLK_DIR;
1066 break;
1067 case SND_SOC_DAIFMT_CBM_CFM:
1068 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1069 break;
1070 case SND_SOC_DAIFMT_CBM_CFS:
1071 aif1 |= WM8903_BCLK_DIR;
1072 break;
1073 default:
1074 return -EINVAL;
1075 }
1076
1077 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1078 case SND_SOC_DAIFMT_DSP_A:
1079 aif1 |= 0x3;
1080 break;
1081 case SND_SOC_DAIFMT_DSP_B:
1082 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1083 break;
1084 case SND_SOC_DAIFMT_I2S:
1085 aif1 |= 0x2;
1086 break;
1087 case SND_SOC_DAIFMT_RIGHT_J:
1088 aif1 |= 0x1;
1089 break;
1090 case SND_SOC_DAIFMT_LEFT_J:
1091 break;
1092 default:
1093 return -EINVAL;
1094 }
1095
1096 /* Clock inversion */
1097 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1098 case SND_SOC_DAIFMT_DSP_A:
1099 case SND_SOC_DAIFMT_DSP_B:
1100 /* frame inversion not valid for DSP modes */
1101 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1102 case SND_SOC_DAIFMT_NB_NF:
1103 break;
1104 case SND_SOC_DAIFMT_IB_NF:
1105 aif1 |= WM8903_AIF_BCLK_INV;
1106 break;
1107 default:
1108 return -EINVAL;
1109 }
1110 break;
1111 case SND_SOC_DAIFMT_I2S:
1112 case SND_SOC_DAIFMT_RIGHT_J:
1113 case SND_SOC_DAIFMT_LEFT_J:
1114 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1115 case SND_SOC_DAIFMT_NB_NF:
1116 break;
1117 case SND_SOC_DAIFMT_IB_IF:
1118 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1119 break;
1120 case SND_SOC_DAIFMT_IB_NF:
1121 aif1 |= WM8903_AIF_BCLK_INV;
1122 break;
1123 case SND_SOC_DAIFMT_NB_IF:
1124 aif1 |= WM8903_AIF_LRCLK_INV;
1125 break;
1126 default:
1127 return -EINVAL;
1128 }
1129 break;
1130 default:
1131 return -EINVAL;
1132 }
1133
1134 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1135
1136 return 0;
1137}
1138
1139static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1140{
1141 struct snd_soc_codec *codec = codec_dai->codec;
1142 u16 reg;
1143
1144 reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1145
1146 if (mute)
1147 reg |= WM8903_DAC_MUTE;
1148 else
1149 reg &= ~WM8903_DAC_MUTE;
1150
1151 wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg);
1152
1153 return 0;
1154}
1155
1156/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1157 * for optimal performance so we list the lower rates first and match
1158 * on the last match we find. */
1159static struct {
1160 int div;
1161 int rate;
1162 int mode;
1163 int mclk_div;
1164} clk_sys_ratios[] = {
1165 { 64, 0x0, 0x0, 1 },
1166 { 68, 0x0, 0x1, 1 },
1167 { 125, 0x0, 0x2, 1 },
1168 { 128, 0x1, 0x0, 1 },
1169 { 136, 0x1, 0x1, 1 },
1170 { 192, 0x2, 0x0, 1 },
1171 { 204, 0x2, 0x1, 1 },
1172
1173 { 64, 0x0, 0x0, 2 },
1174 { 68, 0x0, 0x1, 2 },
1175 { 125, 0x0, 0x2, 2 },
1176 { 128, 0x1, 0x0, 2 },
1177 { 136, 0x1, 0x1, 2 },
1178 { 192, 0x2, 0x0, 2 },
1179 { 204, 0x2, 0x1, 2 },
1180
1181 { 250, 0x2, 0x2, 1 },
1182 { 256, 0x3, 0x0, 1 },
1183 { 272, 0x3, 0x1, 1 },
1184 { 384, 0x4, 0x0, 1 },
1185 { 408, 0x4, 0x1, 1 },
1186 { 375, 0x4, 0x2, 1 },
1187 { 512, 0x5, 0x0, 1 },
1188 { 544, 0x5, 0x1, 1 },
1189 { 500, 0x5, 0x2, 1 },
1190 { 768, 0x6, 0x0, 1 },
1191 { 816, 0x6, 0x1, 1 },
1192 { 750, 0x6, 0x2, 1 },
1193 { 1024, 0x7, 0x0, 1 },
1194 { 1088, 0x7, 0x1, 1 },
1195 { 1000, 0x7, 0x2, 1 },
1196 { 1408, 0x8, 0x0, 1 },
1197 { 1496, 0x8, 0x1, 1 },
1198 { 1536, 0x9, 0x0, 1 },
1199 { 1632, 0x9, 0x1, 1 },
1200 { 1500, 0x9, 0x2, 1 },
1201
1202 { 250, 0x2, 0x2, 2 },
1203 { 256, 0x3, 0x0, 2 },
1204 { 272, 0x3, 0x1, 2 },
1205 { 384, 0x4, 0x0, 2 },
1206 { 408, 0x4, 0x1, 2 },
1207 { 375, 0x4, 0x2, 2 },
1208 { 512, 0x5, 0x0, 2 },
1209 { 544, 0x5, 0x1, 2 },
1210 { 500, 0x5, 0x2, 2 },
1211 { 768, 0x6, 0x0, 2 },
1212 { 816, 0x6, 0x1, 2 },
1213 { 750, 0x6, 0x2, 2 },
1214 { 1024, 0x7, 0x0, 2 },
1215 { 1088, 0x7, 0x1, 2 },
1216 { 1000, 0x7, 0x2, 2 },
1217 { 1408, 0x8, 0x0, 2 },
1218 { 1496, 0x8, 0x1, 2 },
1219 { 1536, 0x9, 0x0, 2 },
1220 { 1632, 0x9, 0x1, 2 },
1221 { 1500, 0x9, 0x2, 2 },
1222};
1223
1224/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1225static struct {
1226 int ratio;
1227 int div;
1228} bclk_divs[] = {
1229 { 10, 0 },
1230 { 15, 1 },
1231 { 20, 2 },
1232 { 30, 3 },
1233 { 40, 4 },
1234 { 50, 5 },
1235 { 55, 6 },
1236 { 60, 7 },
1237 { 80, 8 },
1238 { 100, 9 },
1239 { 110, 10 },
1240 { 120, 11 },
1241 { 160, 12 },
1242 { 200, 13 },
1243 { 220, 14 },
1244 { 240, 15 },
1245 { 250, 16 },
1246 { 300, 17 },
1247 { 320, 18 },
1248 { 440, 19 },
1249 { 480, 20 },
1250};
1251
1252/* Sample rates for DSP */
1253static struct {
1254 int rate;
1255 int value;
1256} sample_rates[] = {
1257 { 8000, 0 },
1258 { 11025, 1 },
1259 { 12000, 2 },
1260 { 16000, 3 },
1261 { 22050, 4 },
1262 { 24000, 5 },
1263 { 32000, 6 },
1264 { 44100, 7 },
1265 { 48000, 8 },
1266 { 88200, 9 },
1267 { 96000, 10 },
1268 { 0, 0 },
1269};
1270
dee89c4d
MB		 1271static int wm8903_startup(struct snd_pcm_substream *substream,
1272 struct snd_soc_dai *dai)
f1c0a02f
MB		 1273{
1274 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1275 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1276 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1277 struct wm8903_priv *wm8903 = codec->private_data;
1278 struct i2c_client *i2c = codec->control_data;
1279 struct snd_pcm_runtime *master_runtime;
1280
1281 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1282 wm8903->playback_active++;
1283 else
1284 wm8903->capture_active++;
1285
1286 /* The DAI has shared clocks so if we already have a playback or
1287 * capture going then constrain this substream to match it.
1288 */
1289 if (wm8903->master_substream) {
1290 master_runtime = wm8903->master_substream->runtime;
1291
727fb909
MB		 1292 dev_dbg(&i2c->dev, "Constraining to %d bits\n",
1293 master_runtime->sample_bits);
f1c0a02f
MB		 1294
1295 snd_pcm_hw_constraint_minmax(substream->runtime,
1296 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1297 master_runtime->sample_bits,
1298 master_runtime->sample_bits);
1299
1300 wm8903->slave_substream = substream;
1301 } else
1302 wm8903->master_substream = substream;
1303
1304 return 0;
1305}
1306
dee89c4d
MB		 1307static void wm8903_shutdown(struct snd_pcm_substream *substream,
1308 struct snd_soc_dai *dai)
f1c0a02f
MB		 1309{
1310 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1311 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1312 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1313 struct wm8903_priv *wm8903 = codec->private_data;
1314
1315 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1316 wm8903->playback_active--;
1317 else
1318 wm8903->capture_active--;
1319
1320 if (wm8903->master_substream == substream)
1321 wm8903->master_substream = wm8903->slave_substream;
1322
1323 wm8903->slave_substream = NULL;
1324}
1325
1326static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1327 struct snd_pcm_hw_params *params,
1328 struct snd_soc_dai *dai)
f1c0a02f
MB		 1329{
1330 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1331 struct snd_soc_device *socdev = rtd->socdev;
6627a653 1332 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1333 struct wm8903_priv *wm8903 = codec->private_data;
1334 struct i2c_client *i2c = codec->control_data;
1335 int fs = params_rate(params);
1336 int bclk;
1337 int bclk_div;
1338 int i;
1339 int dsp_config;
1340 int clk_config;
1341 int best_val;
1342 int cur_val;
1343 int clk_sys;
1344
1345 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1346 u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2);
1347 u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3);
1348 u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0);
1349 u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1);
1350
1351 if (substream == wm8903->slave_substream) {
1352 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1353 return 0;
1354 }
1355
1356 /* Configure sample rate logic for DSP - choose nearest rate */
1357 dsp_config = 0;
1358 best_val = abs(sample_rates[dsp_config].rate - fs);
1359 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1360 cur_val = abs(sample_rates[i].rate - fs);
1361 if (cur_val <= best_val) {
1362 dsp_config = i;
1363 best_val = cur_val;
1364 }
1365 }
1366
1367 /* Constraints should stop us hitting this but let's make sure */
1368 if (wm8903->capture_active)
1369 switch (sample_rates[dsp_config].rate) {
1370 case 88200:
1371 case 96000:
1372 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1373 fs);
1374 return -EINVAL;
1375
1376 default:
1377 break;
1378 }
1379
1380 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1381 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1382 clock1 |= sample_rates[dsp_config].value;
1383
1384 aif1 &= ~WM8903_AIF_WL_MASK;
1385 bclk = 2 * fs;
1386 switch (params_format(params)) {
1387 case SNDRV_PCM_FORMAT_S16_LE:
1388 bclk *= 16;
1389 break;
1390 case SNDRV_PCM_FORMAT_S20_3LE:
1391 bclk *= 20;
1392 aif1 |= 0x4;
1393 break;
1394 case SNDRV_PCM_FORMAT_S24_LE:
1395 bclk *= 24;
1396 aif1 |= 0x8;
1397 break;
1398 case SNDRV_PCM_FORMAT_S32_LE:
1399 bclk *= 32;
1400 aif1 |= 0xc;
1401 break;
1402 default:
1403 return -EINVAL;
1404 }
1405
1406 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1407 wm8903->sysclk, fs);
1408
1409 /* We may not have an MCLK which allows us to generate exactly
1410 * the clock we want, particularly with USB derived inputs, so
1411 * approximate.
1412 */
1413 clk_config = 0;
1414 best_val = abs((wm8903->sysclk /
1415 (clk_sys_ratios[0].mclk_div *
1416 clk_sys_ratios[0].div)) - fs);
1417 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1418 cur_val = abs((wm8903->sysclk /
1419 (clk_sys_ratios[i].mclk_div *
1420 clk_sys_ratios[i].div)) - fs);
1421
1422 if (cur_val <= best_val) {
1423 clk_config = i;
1424 best_val = cur_val;
1425 }
1426 }
1427
1428 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1429 clock0 |= WM8903_MCLKDIV2;
1430 clk_sys = wm8903->sysclk / 2;
1431 } else {
1432 clock0 &= ~WM8903_MCLKDIV2;
1433 clk_sys = wm8903->sysclk;
1434 }
1435
1436 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1437 WM8903_CLK_SYS_MODE_MASK);
1438 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1439 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1440
1441 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1442 clk_sys_ratios[clk_config].rate,
1443 clk_sys_ratios[clk_config].mode,
1444 clk_sys_ratios[clk_config].div);
1445
1446 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1447
1448 /* We may not get quite the right frequency if using
1449 * approximate clocks so look for the closest match that is
1450 * higher than the target (we need to ensure that there enough
1451 * BCLKs to clock out the samples).
1452 */
1453 bclk_div = 0;
1454 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1455 i = 1;
1456 while (i < ARRAY_SIZE(bclk_divs)) {
1457 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1458 if (cur_val < 0) /* BCLK table is sorted */
1459 break;
1460 bclk_div = i;
1461 best_val = cur_val;
1462 i++;
1463 }
1464
1465 aif2 &= ~WM8903_BCLK_DIV_MASK;
1466 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1467
1468 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1469 bclk_divs[bclk_div].ratio / 10, bclk,
1470 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1471
1472 aif2 |= bclk_divs[bclk_div].div;
1473 aif3 |= bclk / fs;
1474
1475 wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0);
1476 wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1);
1477 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1478 wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1479 wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1480
1481 return 0;
1482}
1483
1484#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1485 SNDRV_PCM_RATE_11025 | \
1486 SNDRV_PCM_RATE_16000 | \
1487 SNDRV_PCM_RATE_22050 | \
1488 SNDRV_PCM_RATE_32000 | \
1489 SNDRV_PCM_RATE_44100 | \
1490 SNDRV_PCM_RATE_48000 | \
1491 SNDRV_PCM_RATE_88200 | \
1492 SNDRV_PCM_RATE_96000)
1493
1494#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1495 SNDRV_PCM_RATE_11025 | \
1496 SNDRV_PCM_RATE_16000 | \
1497 SNDRV_PCM_RATE_22050 | \
1498 SNDRV_PCM_RATE_32000 | \
1499 SNDRV_PCM_RATE_44100 | \
1500 SNDRV_PCM_RATE_48000)
1501
1502#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1503 SNDRV_PCM_FMTBIT_S20_3LE |\
1504 SNDRV_PCM_FMTBIT_S24_LE)
1505
6335d055
EM		 1506static struct snd_soc_dai_ops wm8903_dai_ops = {
1507 .startup = wm8903_startup,
1508 .shutdown = wm8903_shutdown,
1509 .hw_params = wm8903_hw_params,
1510 .digital_mute = wm8903_digital_mute,
1511 .set_fmt = wm8903_set_dai_fmt,
1512 .set_sysclk = wm8903_set_dai_sysclk,
1513};
1514
f1c0a02f
MB		 1515struct snd_soc_dai wm8903_dai = {
1516 .name = "WM8903",
1517 .playback = {
1518 .stream_name = "Playback",
1519 .channels_min = 2,
1520 .channels_max = 2,
1521 .rates = WM8903_PLAYBACK_RATES,
1522 .formats = WM8903_FORMATS,
1523 },
1524 .capture = {
1525 .stream_name = "Capture",
1526 .channels_min = 2,
1527 .channels_max = 2,
1528 .rates = WM8903_CAPTURE_RATES,
1529 .formats = WM8903_FORMATS,
1530 },
6335d055 1531 .ops = &wm8903_dai_ops,
0d960e88 1532 .symmetric_rates = 1,
f1c0a02f
MB		 1533};
1534EXPORT_SYMBOL_GPL(wm8903_dai);
1535
1536static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1537{
1538 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1539 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1540
1541 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1542
1543 return 0;
1544}
1545
1546static int wm8903_resume(struct platform_device *pdev)
1547{
1548 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1549 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1550 struct i2c_client *i2c = codec->control_data;
1551 int i;
1552 u16 *reg_cache = codec->reg_cache;
1553 u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults),
1554 GFP_KERNEL);
1555
1556 /* Bring the codec back up to standby first to minimise pop/clicks */
1557 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1558 wm8903_set_bias_level(codec, codec->suspend_bias_level);
1559
1560 /* Sync back everything else */
1561 if (tmp_cache) {
1562 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1563 if (tmp_cache[i] != reg_cache[i])
1564 wm8903_write(codec, i, tmp_cache[i]);
1565 } else {
1566 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1567 }
1568
1569 return 0;
1570}
1571
d58d5d55
MB		 1572static struct snd_soc_codec *wm8903_codec;
1573
c6f29811
MB		 1574static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1575 const struct i2c_device_id *id)
f1c0a02f 1576{
d58d5d55
MB		 1577 struct wm8903_priv *wm8903;
1578 struct snd_soc_codec *codec;
1579 int ret;
f1c0a02f
MB		 1580 u16 val;
1581
d58d5d55
MB		 1582 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1583 if (wm8903 == NULL)
1584 return -ENOMEM;
f1c0a02f 1585
d58d5d55
MB		 1586 codec = &wm8903->codec;
1587
1588 mutex_init(&codec->mutex);
1589 INIT_LIST_HEAD(&codec->dapm_widgets);
1590 INIT_LIST_HEAD(&codec->dapm_paths);
1591
1592 codec->dev = &i2c->dev;
f1c0a02f
MB		 1593 codec->name = "WM8903";
1594 codec->owner = THIS_MODULE;
1595 codec->read = wm8903_read;
1596 codec->write = wm8903_write;
d58d5d55 1597 codec->hw_write = (hw_write_t)i2c_master_send;
f1c0a02f
MB		 1598 codec->bias_level = SND_SOC_BIAS_OFF;
1599 codec->set_bias_level = wm8903_set_bias_level;
1600 codec->dai = &wm8903_dai;
1601 codec->num_dai = 1;
d58d5d55
MB		 1602 codec->reg_cache_size = ARRAY_SIZE(wm8903->reg_cache);
1603 codec->reg_cache = &wm8903->reg_cache[0];
1604 codec->private_data = wm8903;
1605
1606 i2c_set_clientdata(i2c, codec);
1607 codec->control_data = i2c;
1608
1609 val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID);
1610 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1611 dev_err(&i2c->dev,
1612 "Device with ID register %x is not a WM8903\n", val);
1613 return -ENODEV;
f1c0a02f
MB		 1614 }
1615
1616 val = wm8903_read(codec, WM8903_REVISION_NUMBER);
1617 dev_info(&i2c->dev, "WM8903 revision %d\n",
1618 val & WM8903_CHIP_REV_MASK);
1619
1620 wm8903_reset(codec);
1621
f1c0a02f
MB		 1622 /* power on device */
1623 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1624
1625 /* Latch volume update bits */
1626 val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1627 val |= WM8903_ADCVU;
1628 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1629 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1630
1631 val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1632 val |= WM8903_DACVU;
1633 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1634 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1635
1636 val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1637 val |= WM8903_HPOUTVU;
1638 wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1639 wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1640
1641 val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1642 val |= WM8903_LINEOUTVU;
1643 wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1644 wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1645
1646 val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1647 val |= WM8903_SPKVU;
1648 wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1649 wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1650
1651 /* Enable DAC soft mute by default */
1652 val = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1653 val |= WM8903_DAC_MUTEMODE;
1654 wm8903_write(codec, WM8903_DAC_DIGITAL_1, val);
1655
d58d5d55
MB		 1656 wm8903_dai.dev = &i2c->dev;
1657 wm8903_codec = codec;
1658
1659 ret = snd_soc_register_codec(codec);
1660 if (ret != 0) {
1661 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
1662 goto err;
1663 }
1664
1665 ret = snd_soc_register_dai(&wm8903_dai);
1666 if (ret != 0) {
1667 dev_err(&i2c->dev, "Failed to register DAI: %d\n", ret);
1668 goto err_codec;
f1c0a02f
MB		 1669 }
1670
1671 return ret;
1672
d58d5d55
MB		 1673err_codec:
1674 snd_soc_unregister_codec(codec);
1675err:
1676 wm8903_codec = NULL;
1677 kfree(wm8903);
f1c0a02f
MB		 1678 return ret;
1679}
1680
c6f29811 1681static __devexit int wm8903_i2c_remove(struct i2c_client *client)
f1c0a02f 1682{
d58d5d55 1683 struct snd_soc_codec *codec = i2c_get_clientdata(client);
f1c0a02f 1684
d58d5d55
MB		 1685 snd_soc_unregister_dai(&wm8903_dai);
1686 snd_soc_unregister_codec(codec);
f1c0a02f 1687
d58d5d55 1688 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f1c0a02f 1689
d58d5d55
MB		 1690 kfree(codec->private_data);
1691
1692 wm8903_codec = NULL;
1693 wm8903_dai.dev = NULL;
f1c0a02f 1694
f1c0a02f
MB		 1695 return 0;
1696}
1697
1698/* i2c codec control layer */
1699static const struct i2c_device_id wm8903_i2c_id[] = {
1700 { "wm8903", 0 },
1701 { }
1702};
1703MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1704
1705static struct i2c_driver wm8903_i2c_driver = {
1706 .driver = {
1707 .name = "WM8903",
1708 .owner = THIS_MODULE,
1709 },
1710 .probe = wm8903_i2c_probe,
c6f29811 1711 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1712 .id_table = wm8903_i2c_id,
1713};
1714
f1c0a02f
MB		 1715static int wm8903_probe(struct platform_device *pdev)
1716{
1717 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
f1c0a02f
MB		 1718 int ret = 0;
1719
d58d5d55
MB		 1720 if (!wm8903_codec) {
1721 dev_err(&pdev->dev, "I2C device not yet probed\n");
1722 goto err;
f1c0a02f
MB		 1723 }
1724
6627a653 1725 socdev->card->codec = wm8903_codec;
f1c0a02f 1726
d58d5d55
MB		 1727 /* register pcms */
1728 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1729 if (ret < 0) {
1730 dev_err(&pdev->dev, "failed to create pcms\n");
1731 goto err;
f1c0a02f
MB		 1732 }
1733
6627a653 1734 snd_soc_add_controls(socdev->card->codec, wm8903_snd_controls,
3e8e1952 1735 ARRAY_SIZE(wm8903_snd_controls));
6627a653 1736 wm8903_add_widgets(socdev->card->codec);
f1c0a02f 1737
d58d5d55
MB		 1738 ret = snd_soc_init_card(socdev);
1739 if (ret < 0) {
1740 dev_err(&pdev->dev, "wm8903: failed to register card\n");
1741 goto card_err;
f1c0a02f
MB		 1742 }
1743
1744 return ret;
1745
d58d5d55
MB		 1746card_err:
1747 snd_soc_free_pcms(socdev);
1748 snd_soc_dapm_free(socdev);
1749err:
f1c0a02f
MB		 1750 return ret;
1751}
1752
1753/* power down chip */
1754static int wm8903_remove(struct platform_device *pdev)
1755{
1756 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
6627a653 1757 struct snd_soc_codec *codec = socdev->card->codec;
f1c0a02f
MB		 1758
1759 if (codec->control_data)
1760 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1761
1762 snd_soc_free_pcms(socdev);
1763 snd_soc_dapm_free(socdev);
f1c0a02f
MB		 1764
1765 return 0;
1766}
1767
1768struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1769 .probe = wm8903_probe,
1770 .remove = wm8903_remove,
1771 .suspend = wm8903_suspend,
1772 .resume = wm8903_resume,
1773};
1774EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1775
c9b3a40f 1776static int __init wm8903_modinit(void)
64089b84 1777{
d58d5d55 1778 return i2c_add_driver(&wm8903_i2c_driver);
64089b84
MB		 1779}
1780module_init(wm8903_modinit);
1781
1782static void __exit wm8903_exit(void)
1783{
d58d5d55 1784 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 1785}
1786module_exit(wm8903_exit);
1787
f1c0a02f
MB		 1788MODULE_DESCRIPTION("ASoC WM8903 driver");
1789MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1790MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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