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ASoC: Convert WM8900 to do more work at I2C probe time
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
14 * - Mic detect.
15 * - Digital microphone support.
16 * - Interrupt support (mic detect and sequencer).
17 */
18
19#include <linux/module.h>
20#include <linux/moduleparam.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/pm.h>
24#include <linux/i2c.h>
25#include <linux/platform_device.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/tlv.h>
30#include <sound/soc.h>
31#include <sound/soc-dapm.h>
32#include <sound/initval.h>
33
34#include "wm8903.h"
35
36struct wm8903_priv {
37 int sysclk;
38
39 /* Reference counts */
40 int charge_pump_users;
41 int class_w_users;
42 int playback_active;
43 int capture_active;
44
45 struct snd_pcm_substream *master_substream;
46 struct snd_pcm_substream *slave_substream;
47};
48
49/* Register defaults at reset */
50static u16 wm8903_reg_defaults[] = {
51 0x8903, /* R0 - SW Reset and ID */
52 0x0000, /* R1 - Revision Number */
53 0x0000, /* R2 */
54 0x0000, /* R3 */
55 0x0018, /* R4 - Bias Control 0 */
56 0x0000, /* R5 - VMID Control 0 */
57 0x0000, /* R6 - Mic Bias Control 0 */
58 0x0000, /* R7 */
59 0x0001, /* R8 - Analogue DAC 0 */
60 0x0000, /* R9 */
61 0x0001, /* R10 - Analogue ADC 0 */
62 0x0000, /* R11 */
63 0x0000, /* R12 - Power Management 0 */
64 0x0000, /* R13 - Power Management 1 */
65 0x0000, /* R14 - Power Management 2 */
66 0x0000, /* R15 - Power Management 3 */
67 0x0000, /* R16 - Power Management 4 */
68 0x0000, /* R17 - Power Management 5 */
69 0x0000, /* R18 - Power Management 6 */
70 0x0000, /* R19 */
71 0x0400, /* R20 - Clock Rates 0 */
72 0x0D07, /* R21 - Clock Rates 1 */
73 0x0000, /* R22 - Clock Rates 2 */
74 0x0000, /* R23 */
75 0x0050, /* R24 - Audio Interface 0 */
76 0x0242, /* R25 - Audio Interface 1 */
77 0x0008, /* R26 - Audio Interface 2 */
78 0x0022, /* R27 - Audio Interface 3 */
79 0x0000, /* R28 */
80 0x0000, /* R29 */
81 0x00C0, /* R30 - DAC Digital Volume Left */
82 0x00C0, /* R31 - DAC Digital Volume Right */
83 0x0000, /* R32 - DAC Digital 0 */
84 0x0000, /* R33 - DAC Digital 1 */
85 0x0000, /* R34 */
86 0x0000, /* R35 */
87 0x00C0, /* R36 - ADC Digital Volume Left */
88 0x00C0, /* R37 - ADC Digital Volume Right */
89 0x0000, /* R38 - ADC Digital 0 */
90 0x0073, /* R39 - Digital Microphone 0 */
91 0x09BF, /* R40 - DRC 0 */
92 0x3241, /* R41 - DRC 1 */
93 0x0020, /* R42 - DRC 2 */
94 0x0000, /* R43 - DRC 3 */
95 0x0085, /* R44 - Analogue Left Input 0 */
96 0x0085, /* R45 - Analogue Right Input 0 */
97 0x0044, /* R46 - Analogue Left Input 1 */
98 0x0044, /* R47 - Analogue Right Input 1 */
99 0x0000, /* R48 */
100 0x0000, /* R49 */
101 0x0008, /* R50 - Analogue Left Mix 0 */
102 0x0004, /* R51 - Analogue Right Mix 0 */
103 0x0000, /* R52 - Analogue Spk Mix Left 0 */
104 0x0000, /* R53 - Analogue Spk Mix Left 1 */
105 0x0000, /* R54 - Analogue Spk Mix Right 0 */
106 0x0000, /* R55 - Analogue Spk Mix Right 1 */
107 0x0000, /* R56 */
108 0x002D, /* R57 - Analogue OUT1 Left */
109 0x002D, /* R58 - Analogue OUT1 Right */
110 0x0039, /* R59 - Analogue OUT2 Left */
111 0x0039, /* R60 - Analogue OUT2 Right */
112 0x0100, /* R61 */
113 0x0139, /* R62 - Analogue OUT3 Left */
114 0x0139, /* R63 - Analogue OUT3 Right */
115 0x0000, /* R64 */
116 0x0000, /* R65 - Analogue SPK Output Control 0 */
117 0x0000, /* R66 */
118 0x0010, /* R67 - DC Servo 0 */
119 0x0100, /* R68 */
120 0x00A4, /* R69 - DC Servo 2 */
121 0x0807, /* R70 */
122 0x0000, /* R71 */
123 0x0000, /* R72 */
124 0x0000, /* R73 */
125 0x0000, /* R74 */
126 0x0000, /* R75 */
127 0x0000, /* R76 */
128 0x0000, /* R77 */
129 0x0000, /* R78 */
130 0x000E, /* R79 */
131 0x0000, /* R80 */
132 0x0000, /* R81 */
133 0x0000, /* R82 */
134 0x0000, /* R83 */
135 0x0000, /* R84 */
136 0x0000, /* R85 */
137 0x0000, /* R86 */
138 0x0006, /* R87 */
139 0x0000, /* R88 */
140 0x0000, /* R89 */
141 0x0000, /* R90 - Analogue HP 0 */
142 0x0060, /* R91 */
143 0x0000, /* R92 */
144 0x0000, /* R93 */
145 0x0000, /* R94 - Analogue Lineout 0 */
146 0x0060, /* R95 */
147 0x0000, /* R96 */
148 0x0000, /* R97 */
149 0x0000, /* R98 - Charge Pump 0 */
150 0x1F25, /* R99 */
151 0x2B19, /* R100 */
152 0x01C0, /* R101 */
153 0x01EF, /* R102 */
154 0x2B00, /* R103 */
155 0x0000, /* R104 - Class W 0 */
156 0x01C0, /* R105 */
157 0x1C10, /* R106 */
158 0x0000, /* R107 */
159 0x0000, /* R108 - Write Sequencer 0 */
160 0x0000, /* R109 - Write Sequencer 1 */
161 0x0000, /* R110 - Write Sequencer 2 */
162 0x0000, /* R111 - Write Sequencer 3 */
163 0x0000, /* R112 - Write Sequencer 4 */
164 0x0000, /* R113 */
165 0x0000, /* R114 - Control Interface */
166 0x0000, /* R115 */
167 0x00A8, /* R116 - GPIO Control 1 */
168 0x00A8, /* R117 - GPIO Control 2 */
169 0x00A8, /* R118 - GPIO Control 3 */
170 0x0220, /* R119 - GPIO Control 4 */
171 0x01A0, /* R120 - GPIO Control 5 */
172 0x0000, /* R121 - Interrupt Status 1 */
173 0xFFFF, /* R122 - Interrupt Status 1 Mask */
174 0x0000, /* R123 - Interrupt Polarity 1 */
175 0x0000, /* R124 */
176 0x0003, /* R125 */
177 0x0000, /* R126 - Interrupt Control */
178 0x0000, /* R127 */
179 0x0005, /* R128 */
180 0x0000, /* R129 - Control Interface Test 1 */
181 0x0000, /* R130 */
182 0x0000, /* R131 */
183 0x0000, /* R132 */
184 0x0000, /* R133 */
185 0x0000, /* R134 */
186 0x03FF, /* R135 */
187 0x0007, /* R136 */
188 0x0040, /* R137 */
189 0x0000, /* R138 */
190 0x0000, /* R139 */
191 0x0000, /* R140 */
192 0x0000, /* R141 */
193 0x0000, /* R142 */
194 0x0000, /* R143 */
195 0x0000, /* R144 */
196 0x0000, /* R145 */
197 0x0000, /* R146 */
198 0x0000, /* R147 */
199 0x4000, /* R148 */
200 0x6810, /* R149 - Charge Pump Test 1 */
201 0x0004, /* R150 */
202 0x0000, /* R151 */
203 0x0000, /* R152 */
204 0x0000, /* R153 */
205 0x0000, /* R154 */
206 0x0000, /* R155 */
207 0x0000, /* R156 */
208 0x0000, /* R157 */
209 0x0000, /* R158 */
210 0x0000, /* R159 */
211 0x0000, /* R160 */
212 0x0000, /* R161 */
213 0x0000, /* R162 */
214 0x0000, /* R163 */
215 0x0028, /* R164 - Clock Rate Test 4 */
216 0x0004, /* R165 */
217 0x0000, /* R166 */
218 0x0060, /* R167 */
219 0x0000, /* R168 */
220 0x0000, /* R169 */
221 0x0000, /* R170 */
222 0x0000, /* R171 */
223 0x0000, /* R172 - Analogue Output Bias 0 */
224};
225
226static unsigned int wm8903_read_reg_cache(struct snd_soc_codec *codec,
227 unsigned int reg)
228{
229 u16 *cache = codec->reg_cache;
230
231 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
232
233 return cache[reg];
234}
235
236static unsigned int wm8903_hw_read(struct snd_soc_codec *codec, u8 reg)
237{
238 struct i2c_msg xfer[2];
239 u16 data;
240 int ret;
241 struct i2c_client *client = codec->control_data;
242
243 /* Write register */
244 xfer[0].addr = client->addr;
245 xfer[0].flags = 0;
246 xfer[0].len = 1;
247 xfer[0].buf = &reg;
248
249 /* Read data */
250 xfer[1].addr = client->addr;
251 xfer[1].flags = I2C_M_RD;
252 xfer[1].len = 2;
253 xfer[1].buf = (u8 *)&data;
254
255 ret = i2c_transfer(client->adapter, xfer, 2);
256 if (ret != 2) {
257 pr_err("i2c_transfer returned %d\n", ret);
258 return 0;
259 }
260
261 return (data >> 8) | ((data & 0xff) << 8);
262}
263
264static unsigned int wm8903_read(struct snd_soc_codec *codec,
265 unsigned int reg)
266{
267 switch (reg) {
268 case WM8903_SW_RESET_AND_ID:
269 case WM8903_REVISION_NUMBER:
270 case WM8903_INTERRUPT_STATUS_1:
271 case WM8903_WRITE_SEQUENCER_4:
272 return wm8903_hw_read(codec, reg);
273
274 default:
275 return wm8903_read_reg_cache(codec, reg);
276 }
277}
278
279static void wm8903_write_reg_cache(struct snd_soc_codec *codec,
280 u16 reg, unsigned int value)
281{
282 u16 *cache = codec->reg_cache;
283
284 BUG_ON(reg >= ARRAY_SIZE(wm8903_reg_defaults));
285
286 switch (reg) {
287 case WM8903_SW_RESET_AND_ID:
288 case WM8903_REVISION_NUMBER:
289 break;
290
291 default:
292 cache[reg] = value;
293 break;
294 }
295}
296
297static int wm8903_write(struct snd_soc_codec *codec, unsigned int reg,
298 unsigned int value)
299{
300 u8 data[3];
301
302 wm8903_write_reg_cache(codec, reg, value);
303
304 /* Data format is 1 byte of address followed by 2 bytes of data */
305 data[0] = reg;
306 data[1] = (value >> 8) & 0xff;
307 data[2] = value & 0xff;
308
309 if (codec->hw_write(codec->control_data, data, 3) == 2)
310 return 0;
311 else
312 return -EIO;
313}
314
315static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
316{
317 u16 reg[5];
318 struct i2c_client *i2c = codec->control_data;
319
320 BUG_ON(start > 48);
321
322 /* Enable the sequencer */
323 reg[0] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_0);
324 reg[0] |= WM8903_WSEQ_ENA;
325 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
326
327 dev_dbg(&i2c->dev, "Starting sequence at %d\n", start);
328
329 wm8903_write(codec, WM8903_WRITE_SEQUENCER_3,
330 start | WM8903_WSEQ_START);
331
332 /* Wait for it to complete. If we have the interrupt wired up then
333 * we could block waiting for an interrupt, though polling may still
334 * be desirable for diagnostic purposes.
335 */
336 do {
337 msleep(10);
338
339 reg[4] = wm8903_read(codec, WM8903_WRITE_SEQUENCER_4);
340 } while (reg[4] & WM8903_WSEQ_BUSY);
341
342 dev_dbg(&i2c->dev, "Sequence complete\n");
343
344 /* Disable the sequencer again */
345 wm8903_write(codec, WM8903_WRITE_SEQUENCER_0,
346 reg[0] & ~WM8903_WSEQ_ENA);
347
348 return 0;
349}
350
351static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
352{
353 int i;
354
355 /* There really ought to be something better we can do here :/ */
356 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
357 cache[i] = wm8903_hw_read(codec, i);
358}
359
360static void wm8903_reset(struct snd_soc_codec *codec)
361{
362 wm8903_write(codec, WM8903_SW_RESET_AND_ID, 0);
363}
364
365#define WM8903_OUTPUT_SHORT 0x8
366#define WM8903_OUTPUT_OUT 0x4
367#define WM8903_OUTPUT_INT 0x2
368#define WM8903_OUTPUT_IN 0x1
369
370/*
371 * Event for headphone and line out amplifier power changes. Special
372 * power up/down sequences are required in order to maximise pop/click
373 * performance.
374 */
375static int wm8903_output_event(struct snd_soc_dapm_widget *w,
376 struct snd_kcontrol *kcontrol, int event)
377{
378 struct snd_soc_codec *codec = w->codec;
379 struct wm8903_priv *wm8903 = codec->private_data;
380 struct i2c_client *i2c = codec->control_data;
381 u16 val;
0bc286e2
TI		 382 u16 reg;
383 int shift;
f1c0a02f
MB		 384 u16 cp_reg = wm8903_read(codec, WM8903_CHARGE_PUMP_0);
385
386 switch (w->reg) {
387 case WM8903_POWER_MANAGEMENT_2:
388 reg = WM8903_ANALOGUE_HP_0;
389 break;
390 case WM8903_POWER_MANAGEMENT_3:
391 reg = WM8903_ANALOGUE_LINEOUT_0;
392 break;
393 default:
394 BUG();
1e297a19 395 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 396 }
397
398 switch (w->shift) {
399 case 0:
400 shift = 0;
401 break;
402 case 1:
403 shift = 4;
404 break;
405 default:
406 BUG();
1e297a19 407 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 408 }
409
410 if (event & SND_SOC_DAPM_PRE_PMU) {
411 val = wm8903_read(codec, reg);
412
413 /* Short the output */
414 val &= ~(WM8903_OUTPUT_SHORT << shift);
415 wm8903_write(codec, reg, val);
416
417 wm8903->charge_pump_users++;
418
419 dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
420 wm8903->charge_pump_users);
421
422 if (wm8903->charge_pump_users == 1) {
423 dev_dbg(&i2c->dev, "Enabling charge pump\n");
424 wm8903_write(codec, WM8903_CHARGE_PUMP_0,
425 cp_reg | WM8903_CP_ENA);
426 mdelay(4);
427 }
428 }
429
430 if (event & SND_SOC_DAPM_POST_PMU) {
431 val = wm8903_read(codec, reg);
432
433 val |= (WM8903_OUTPUT_IN << shift);
434 wm8903_write(codec, reg, val);
435
436 val |= (WM8903_OUTPUT_INT << shift);
437 wm8903_write(codec, reg, val);
438
439 /* Turn on the output ENA_OUTP */
440 val |= (WM8903_OUTPUT_OUT << shift);
441 wm8903_write(codec, reg, val);
442
443 /* Remove the short */
444 val |= (WM8903_OUTPUT_SHORT << shift);
445 wm8903_write(codec, reg, val);
446 }
447
448 if (event & SND_SOC_DAPM_PRE_PMD) {
449 val = wm8903_read(codec, reg);
450
451 /* Short the output */
452 val &= ~(WM8903_OUTPUT_SHORT << shift);
453 wm8903_write(codec, reg, val);
454
455 /* Then disable the intermediate and output stages */
456 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
457 WM8903_OUTPUT_IN) << shift);
458 wm8903_write(codec, reg, val);
459 }
460
461 if (event & SND_SOC_DAPM_POST_PMD) {
462 wm8903->charge_pump_users--;
463
464 dev_dbg(&i2c->dev, "Charge pump use count now %d\n",
465 wm8903->charge_pump_users);
466
467 if (wm8903->charge_pump_users == 0) {
468 dev_dbg(&i2c->dev, "Disabling charge pump\n");
469 wm8903_write(codec, WM8903_CHARGE_PUMP_0,
470 cp_reg & ~WM8903_CP_ENA);
471 }
472 }
473
474 return 0;
475}
476
477/*
478 * When used with DAC outputs only the WM8903 charge pump supports
479 * operation in class W mode, providing very low power consumption
480 * when used with digital sources. Enable and disable this mode
481 * automatically depending on the mixer configuration.
482 *
483 * All the relevant controls are simple switches.
484 */
485static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
486 struct snd_ctl_elem_value *ucontrol)
487{
488 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
489 struct snd_soc_codec *codec = widget->codec;
490 struct wm8903_priv *wm8903 = codec->private_data;
491 struct i2c_client *i2c = codec->control_data;
492 u16 reg;
493 int ret;
494
495 reg = wm8903_read(codec, WM8903_CLASS_W_0);
496
497 /* Turn it off if we're about to enable bypass */
498 if (ucontrol->value.integer.value[0]) {
499 if (wm8903->class_w_users == 0) {
500 dev_dbg(&i2c->dev, "Disabling Class W\n");
501 wm8903_write(codec, WM8903_CLASS_W_0, reg &
502 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
503 }
504 wm8903->class_w_users++;
505 }
506
507 /* Implement the change */
508 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
509
510 /* If we've just disabled the last bypass path turn Class W on */
511 if (!ucontrol->value.integer.value[0]) {
512 if (wm8903->class_w_users == 1) {
513 dev_dbg(&i2c->dev, "Enabling Class W\n");
514 wm8903_write(codec, WM8903_CLASS_W_0, reg |
515 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
516 }
517 wm8903->class_w_users--;
518 }
519
520 dev_dbg(&i2c->dev, "Bypass use count now %d\n",
521 wm8903->class_w_users);
522
523 return ret;
524}
525
526#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
527{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
528 .info = snd_soc_info_volsw, \
529 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
530 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
531
532
533/* ALSA can only do steps of .01dB */
534static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
535
536static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
537
538static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
539static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
540static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
541static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
542static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
543
544static const char *drc_slope_text[] = {
545 "1", "1/2", "1/4", "1/8", "1/16", "0"
546};
547
548static const struct soc_enum drc_slope_r0 =
549 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
550
551static const struct soc_enum drc_slope_r1 =
552 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
553
554static const char *drc_attack_text[] = {
555 "instantaneous",
556 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
557 "46.4ms", "92.8ms", "185.6ms"
558};
559
560static const struct soc_enum drc_attack =
561 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
562
563static const char *drc_decay_text[] = {
564 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
565 "23.87s", "47.56s"
566};
567
568static const struct soc_enum drc_decay =
569 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
570
571static const char *drc_ff_delay_text[] = {
572 "5 samples", "9 samples"
573};
574
575static const struct soc_enum drc_ff_delay =
576 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
577
578static const char *drc_qr_decay_text[] = {
579 "0.725ms", "1.45ms", "5.8ms"
580};
581
582static const struct soc_enum drc_qr_decay =
583 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
584
585static const char *drc_smoothing_text[] = {
586 "Low", "Medium", "High"
587};
588
589static const struct soc_enum drc_smoothing =
590 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
591
592static const char *soft_mute_text[] = {
593 "Fast (fs/2)", "Slow (fs/32)"
594};
595
596static const struct soc_enum soft_mute =
597 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
598
599static const char *mute_mode_text[] = {
600 "Hard", "Soft"
601};
602
603static const struct soc_enum mute_mode =
604 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
605
606static const char *dac_deemphasis_text[] = {
607 "Disabled", "32kHz", "44.1kHz", "48kHz"
608};
609
610static const struct soc_enum dac_deemphasis =
611 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 1, 4, dac_deemphasis_text);
612
613static const char *companding_text[] = {
614 "ulaw", "alaw"
615};
616
617static const struct soc_enum dac_companding =
618 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
619
620static const struct soc_enum adc_companding =
621 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
622
623static const char *input_mode_text[] = {
624 "Single-Ended", "Differential Line", "Differential Mic"
625};
626
627static const struct soc_enum linput_mode_enum =
628 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
629
630static const struct soc_enum rinput_mode_enum =
631 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
632
633static const char *linput_mux_text[] = {
634 "IN1L", "IN2L", "IN3L"
635};
636
637static const struct soc_enum linput_enum =
638 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
639
640static const struct soc_enum linput_inv_enum =
641 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
642
643static const char *rinput_mux_text[] = {
644 "IN1R", "IN2R", "IN3R"
645};
646
647static const struct soc_enum rinput_enum =
648 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
649
650static const struct soc_enum rinput_inv_enum =
651 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
652
653
654static const struct snd_kcontrol_new wm8903_snd_controls[] = {
655
656/* Input PGAs - No TLV since the scale depends on PGA mode */
657SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 658 7, 1, 1),
f1c0a02f
MB		 659SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
660 0, 31, 0),
661SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
662 6, 1, 0),
663
664SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 665 7, 1, 1),
f1c0a02f
MB		 666SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
667 0, 31, 0),
668SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
669 6, 1, 0),
670
671/* ADCs */
672SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
673SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
674SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
675SOC_SINGLE_TLV("DRC Compressor Threashold Volume", WM8903_DRC_3, 5, 124, 1,
676 drc_tlv_thresh),
677SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
678SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
679SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
680SOC_ENUM("DRC Attack Rate", drc_attack),
681SOC_ENUM("DRC Decay Rate", drc_decay),
682SOC_ENUM("DRC FF Delay", drc_ff_delay),
683SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
684SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
685SOC_SINGLE_TLV("DRC QR Threashold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
686SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
687SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
688SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
689SOC_ENUM("DRC Smoothing Threashold", drc_smoothing),
690SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
691
692SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
693 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
694SOC_ENUM("ADC Companding Mode", adc_companding),
695SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
696
697/* DAC */
698SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
699 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
700SOC_ENUM("DAC Soft Mute Rate", soft_mute),
701SOC_ENUM("DAC Mute Mode", mute_mode),
702SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
703SOC_ENUM("DAC De-emphasis", dac_deemphasis),
704SOC_SINGLE("DAC Sloping Stopband Filter Switch",
705 WM8903_DAC_DIGITAL_1, 11, 1, 0),
706SOC_ENUM("DAC Companding Mode", dac_companding),
707SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
708
709/* Headphones */
710SOC_DOUBLE_R("Headphone Switch",
711 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
712 8, 1, 1),
713SOC_DOUBLE_R("Headphone ZC Switch",
714 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
715 6, 1, 0),
716SOC_DOUBLE_R_TLV("Headphone Volume",
717 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
718 0, 63, 0, out_tlv),
719
720/* Line out */
721SOC_DOUBLE_R("Line Out Switch",
722 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
723 8, 1, 1),
724SOC_DOUBLE_R("Line Out ZC Switch",
725 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
726 6, 1, 0),
727SOC_DOUBLE_R_TLV("Line Out Volume",
728 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
729 0, 63, 0, out_tlv),
730
731/* Speaker */
732SOC_DOUBLE_R("Speaker Switch",
733 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
734SOC_DOUBLE_R("Speaker ZC Switch",
735 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
736SOC_DOUBLE_R_TLV("Speaker Volume",
737 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
738 0, 63, 0, out_tlv),
739};
740
741static int wm8903_add_controls(struct snd_soc_codec *codec)
742{
743 int err, i;
744
745 for (i = 0; i < ARRAY_SIZE(wm8903_snd_controls); i++) {
746 err = snd_ctl_add(codec->card,
747 snd_soc_cnew(&wm8903_snd_controls[i],
748 codec, NULL));
749 if (err < 0)
750 return err;
751 }
752
753 return 0;
754}
755
756static const struct snd_kcontrol_new linput_mode_mux =
757 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
758
759static const struct snd_kcontrol_new rinput_mode_mux =
760 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
761
762static const struct snd_kcontrol_new linput_mux =
763 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
764
765static const struct snd_kcontrol_new linput_inv_mux =
766 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
767
768static const struct snd_kcontrol_new rinput_mux =
769 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
770
771static const struct snd_kcontrol_new rinput_inv_mux =
772 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
773
774static const struct snd_kcontrol_new left_output_mixer[] = {
775SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
776SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
777SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 778SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 779};
780
781static const struct snd_kcontrol_new right_output_mixer[] = {
782SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
783SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
784SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 785SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 786};
787
788static const struct snd_kcontrol_new left_speaker_mixer[] = {
789SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
790SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
791SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
792SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 793 0, 1, 0),
f1c0a02f
MB		 794};
795
796static const struct snd_kcontrol_new right_speaker_mixer[] = {
797SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
798SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
799SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
800 1, 1, 0),
801SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 802 0, 1, 0),
f1c0a02f
MB		 803};
804
805static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
806SND_SOC_DAPM_INPUT("IN1L"),
807SND_SOC_DAPM_INPUT("IN1R"),
808SND_SOC_DAPM_INPUT("IN2L"),
809SND_SOC_DAPM_INPUT("IN2R"),
810SND_SOC_DAPM_INPUT("IN3L"),
811SND_SOC_DAPM_INPUT("IN3R"),
812
813SND_SOC_DAPM_OUTPUT("HPOUTL"),
814SND_SOC_DAPM_OUTPUT("HPOUTR"),
815SND_SOC_DAPM_OUTPUT("LINEOUTL"),
816SND_SOC_DAPM_OUTPUT("LINEOUTR"),
817SND_SOC_DAPM_OUTPUT("LOP"),
818SND_SOC_DAPM_OUTPUT("LON"),
819SND_SOC_DAPM_OUTPUT("ROP"),
820SND_SOC_DAPM_OUTPUT("RON"),
821
822SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
823
824SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
825SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
826 &linput_inv_mux),
827SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
828
829SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
830SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
831 &rinput_inv_mux),
832SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
833
834SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
835SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
836
837SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
838SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
839
840SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
841SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
842
843SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
844 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
845SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
846 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
847
848SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
849 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
850SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
851 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
852
853SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
854 1, 0, NULL, 0, wm8903_output_event,
855 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
856 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
857SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
858 0, 0, NULL, 0, wm8903_output_event,
859 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
860 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
861
862SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
863 NULL, 0, wm8903_output_event,
864 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
865 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
866SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
867 NULL, 0, wm8903_output_event,
868 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
869 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
870
871SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
872 NULL, 0),
873SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
874 NULL, 0),
875
876};
877
878static const struct snd_soc_dapm_route intercon[] = {
879
880 { "Left Input Mux", "IN1L", "IN1L" },
881 { "Left Input Mux", "IN2L", "IN2L" },
882 { "Left Input Mux", "IN3L", "IN3L" },
883
884 { "Left Input Inverting Mux", "IN1L", "IN1L" },
885 { "Left Input Inverting Mux", "IN2L", "IN2L" },
886 { "Left Input Inverting Mux", "IN3L", "IN3L" },
887
888 { "Right Input Mux", "IN1R", "IN1R" },
889 { "Right Input Mux", "IN2R", "IN2R" },
890 { "Right Input Mux", "IN3R", "IN3R" },
891
892 { "Right Input Inverting Mux", "IN1R", "IN1R" },
893 { "Right Input Inverting Mux", "IN2R", "IN2R" },
894 { "Right Input Inverting Mux", "IN3R", "IN3R" },
895
896 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
897 { "Left Input Mode Mux", "Differential Line",
898 "Left Input Mux" },
899 { "Left Input Mode Mux", "Differential Line",
900 "Left Input Inverting Mux" },
901 { "Left Input Mode Mux", "Differential Mic",
902 "Left Input Mux" },
903 { "Left Input Mode Mux", "Differential Mic",
904 "Left Input Inverting Mux" },
905
906 { "Right Input Mode Mux", "Single-Ended",
907 "Right Input Inverting Mux" },
908 { "Right Input Mode Mux", "Differential Line",
909 "Right Input Mux" },
910 { "Right Input Mode Mux", "Differential Line",
911 "Right Input Inverting Mux" },
912 { "Right Input Mode Mux", "Differential Mic",
913 "Right Input Mux" },
914 { "Right Input Mode Mux", "Differential Mic",
915 "Right Input Inverting Mux" },
916
917 { "Left Input PGA", NULL, "Left Input Mode Mux" },
918 { "Right Input PGA", NULL, "Right Input Mode Mux" },
919
920 { "ADCL", NULL, "Left Input PGA" },
921 { "ADCR", NULL, "Right Input PGA" },
922
923 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
924 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
925 { "Left Output Mixer", "DACL Switch", "DACL" },
926 { "Left Output Mixer", "DACR Switch", "DACR" },
927
928 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
929 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
930 { "Right Output Mixer", "DACL Switch", "DACL" },
931 { "Right Output Mixer", "DACR Switch", "DACR" },
932
933 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
934 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
935 { "Left Speaker Mixer", "DACL Switch", "DACL" },
936 { "Left Speaker Mixer", "DACR Switch", "DACR" },
937
938 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
939 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
940 { "Right Speaker Mixer", "DACL Switch", "DACL" },
941 { "Right Speaker Mixer", "DACR Switch", "DACR" },
942
943 { "Left Line Output PGA", NULL, "Left Output Mixer" },
944 { "Right Line Output PGA", NULL, "Right Output Mixer" },
945
946 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
947 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
948
949 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
950 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
951
952 { "HPOUTL", NULL, "Left Headphone Output PGA" },
953 { "HPOUTR", NULL, "Right Headphone Output PGA" },
954
955 { "LINEOUTL", NULL, "Left Line Output PGA" },
956 { "LINEOUTR", NULL, "Right Line Output PGA" },
957
958 { "LOP", NULL, "Left Speaker PGA" },
959 { "LON", NULL, "Left Speaker PGA" },
960
961 { "ROP", NULL, "Right Speaker PGA" },
962 { "RON", NULL, "Right Speaker PGA" },
963};
964
965static int wm8903_add_widgets(struct snd_soc_codec *codec)
966{
967 snd_soc_dapm_new_controls(codec, wm8903_dapm_widgets,
968 ARRAY_SIZE(wm8903_dapm_widgets));
969
970 snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
971
972 snd_soc_dapm_new_widgets(codec);
973
974 return 0;
975}
976
977static int wm8903_set_bias_level(struct snd_soc_codec *codec,
978 enum snd_soc_bias_level level)
979{
980 struct i2c_client *i2c = codec->control_data;
981 u16 reg, reg2;
982
983 switch (level) {
984 case SND_SOC_BIAS_ON:
985 case SND_SOC_BIAS_PREPARE:
986 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
987 reg &= ~(WM8903_VMID_RES_MASK);
988 reg |= WM8903_VMID_RES_50K;
989 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
990 break;
991
992 case SND_SOC_BIAS_STANDBY:
993 if (codec->bias_level == SND_SOC_BIAS_OFF) {
994 wm8903_run_sequence(codec, 0);
995 wm8903_sync_reg_cache(codec, codec->reg_cache);
996
997 /* Enable low impedence charge pump output */
998 reg = wm8903_read(codec,
999 WM8903_CONTROL_INTERFACE_TEST_1);
1000 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1001 reg | WM8903_TEST_KEY);
1002 reg2 = wm8903_read(codec, WM8903_CHARGE_PUMP_TEST_1);
1003 wm8903_write(codec, WM8903_CHARGE_PUMP_TEST_1,
1004 reg2 | WM8903_CP_SW_KELVIN_MODE_MASK);
1005 wm8903_write(codec, WM8903_CONTROL_INTERFACE_TEST_1,
1006 reg);
1007
1008 /* By default no bypass paths are enabled so
1009 * enable Class W support.
1010 */
1011 dev_dbg(&i2c->dev, "Enabling Class W\n");
1012 wm8903_write(codec, WM8903_CLASS_W_0, reg |
1013 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
1014 }
1015
1016 reg = wm8903_read(codec, WM8903_VMID_CONTROL_0);
1017 reg &= ~(WM8903_VMID_RES_MASK);
1018 reg |= WM8903_VMID_RES_250K;
1019 wm8903_write(codec, WM8903_VMID_CONTROL_0, reg);
1020 break;
1021
1022 case SND_SOC_BIAS_OFF:
1023 wm8903_run_sequence(codec, 32);
1024 break;
1025 }
1026
1027 codec->bias_level = level;
1028
1029 return 0;
1030}
1031
1032static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1033 int clk_id, unsigned int freq, int dir)
1034{
1035 struct snd_soc_codec *codec = codec_dai->codec;
1036 struct wm8903_priv *wm8903 = codec->private_data;
1037
1038 wm8903->sysclk = freq;
1039
1040 return 0;
1041}
1042
1043static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1044 unsigned int fmt)
1045{
1046 struct snd_soc_codec *codec = codec_dai->codec;
1047 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1048
1049 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1050 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1051
1052 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1053 case SND_SOC_DAIFMT_CBS_CFS:
1054 break;
1055 case SND_SOC_DAIFMT_CBS_CFM:
1056 aif1 |= WM8903_LRCLK_DIR;
1057 break;
1058 case SND_SOC_DAIFMT_CBM_CFM:
1059 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1060 break;
1061 case SND_SOC_DAIFMT_CBM_CFS:
1062 aif1 |= WM8903_BCLK_DIR;
1063 break;
1064 default:
1065 return -EINVAL;
1066 }
1067
1068 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1069 case SND_SOC_DAIFMT_DSP_A:
1070 aif1 |= 0x3;
1071 break;
1072 case SND_SOC_DAIFMT_DSP_B:
1073 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1074 break;
1075 case SND_SOC_DAIFMT_I2S:
1076 aif1 |= 0x2;
1077 break;
1078 case SND_SOC_DAIFMT_RIGHT_J:
1079 aif1 |= 0x1;
1080 break;
1081 case SND_SOC_DAIFMT_LEFT_J:
1082 break;
1083 default:
1084 return -EINVAL;
1085 }
1086
1087 /* Clock inversion */
1088 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1089 case SND_SOC_DAIFMT_DSP_A:
1090 case SND_SOC_DAIFMT_DSP_B:
1091 /* frame inversion not valid for DSP modes */
1092 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1093 case SND_SOC_DAIFMT_NB_NF:
1094 break;
1095 case SND_SOC_DAIFMT_IB_NF:
1096 aif1 |= WM8903_AIF_BCLK_INV;
1097 break;
1098 default:
1099 return -EINVAL;
1100 }
1101 break;
1102 case SND_SOC_DAIFMT_I2S:
1103 case SND_SOC_DAIFMT_RIGHT_J:
1104 case SND_SOC_DAIFMT_LEFT_J:
1105 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1106 case SND_SOC_DAIFMT_NB_NF:
1107 break;
1108 case SND_SOC_DAIFMT_IB_IF:
1109 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1110 break;
1111 case SND_SOC_DAIFMT_IB_NF:
1112 aif1 |= WM8903_AIF_BCLK_INV;
1113 break;
1114 case SND_SOC_DAIFMT_NB_IF:
1115 aif1 |= WM8903_AIF_LRCLK_INV;
1116 break;
1117 default:
1118 return -EINVAL;
1119 }
1120 break;
1121 default:
1122 return -EINVAL;
1123 }
1124
1125 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1126
1127 return 0;
1128}
1129
1130static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1131{
1132 struct snd_soc_codec *codec = codec_dai->codec;
1133 u16 reg;
1134
1135 reg = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1136
1137 if (mute)
1138 reg |= WM8903_DAC_MUTE;
1139 else
1140 reg &= ~WM8903_DAC_MUTE;
1141
1142 wm8903_write(codec, WM8903_DAC_DIGITAL_1, reg);
1143
1144 return 0;
1145}
1146
1147/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1148 * for optimal performance so we list the lower rates first and match
1149 * on the last match we find. */
1150static struct {
1151 int div;
1152 int rate;
1153 int mode;
1154 int mclk_div;
1155} clk_sys_ratios[] = {
1156 { 64, 0x0, 0x0, 1 },
1157 { 68, 0x0, 0x1, 1 },
1158 { 125, 0x0, 0x2, 1 },
1159 { 128, 0x1, 0x0, 1 },
1160 { 136, 0x1, 0x1, 1 },
1161 { 192, 0x2, 0x0, 1 },
1162 { 204, 0x2, 0x1, 1 },
1163
1164 { 64, 0x0, 0x0, 2 },
1165 { 68, 0x0, 0x1, 2 },
1166 { 125, 0x0, 0x2, 2 },
1167 { 128, 0x1, 0x0, 2 },
1168 { 136, 0x1, 0x1, 2 },
1169 { 192, 0x2, 0x0, 2 },
1170 { 204, 0x2, 0x1, 2 },
1171
1172 { 250, 0x2, 0x2, 1 },
1173 { 256, 0x3, 0x0, 1 },
1174 { 272, 0x3, 0x1, 1 },
1175 { 384, 0x4, 0x0, 1 },
1176 { 408, 0x4, 0x1, 1 },
1177 { 375, 0x4, 0x2, 1 },
1178 { 512, 0x5, 0x0, 1 },
1179 { 544, 0x5, 0x1, 1 },
1180 { 500, 0x5, 0x2, 1 },
1181 { 768, 0x6, 0x0, 1 },
1182 { 816, 0x6, 0x1, 1 },
1183 { 750, 0x6, 0x2, 1 },
1184 { 1024, 0x7, 0x0, 1 },
1185 { 1088, 0x7, 0x1, 1 },
1186 { 1000, 0x7, 0x2, 1 },
1187 { 1408, 0x8, 0x0, 1 },
1188 { 1496, 0x8, 0x1, 1 },
1189 { 1536, 0x9, 0x0, 1 },
1190 { 1632, 0x9, 0x1, 1 },
1191 { 1500, 0x9, 0x2, 1 },
1192
1193 { 250, 0x2, 0x2, 2 },
1194 { 256, 0x3, 0x0, 2 },
1195 { 272, 0x3, 0x1, 2 },
1196 { 384, 0x4, 0x0, 2 },
1197 { 408, 0x4, 0x1, 2 },
1198 { 375, 0x4, 0x2, 2 },
1199 { 512, 0x5, 0x0, 2 },
1200 { 544, 0x5, 0x1, 2 },
1201 { 500, 0x5, 0x2, 2 },
1202 { 768, 0x6, 0x0, 2 },
1203 { 816, 0x6, 0x1, 2 },
1204 { 750, 0x6, 0x2, 2 },
1205 { 1024, 0x7, 0x0, 2 },
1206 { 1088, 0x7, 0x1, 2 },
1207 { 1000, 0x7, 0x2, 2 },
1208 { 1408, 0x8, 0x0, 2 },
1209 { 1496, 0x8, 0x1, 2 },
1210 { 1536, 0x9, 0x0, 2 },
1211 { 1632, 0x9, 0x1, 2 },
1212 { 1500, 0x9, 0x2, 2 },
1213};
1214
1215/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1216static struct {
1217 int ratio;
1218 int div;
1219} bclk_divs[] = {
1220 { 10, 0 },
1221 { 15, 1 },
1222 { 20, 2 },
1223 { 30, 3 },
1224 { 40, 4 },
1225 { 50, 5 },
1226 { 55, 6 },
1227 { 60, 7 },
1228 { 80, 8 },
1229 { 100, 9 },
1230 { 110, 10 },
1231 { 120, 11 },
1232 { 160, 12 },
1233 { 200, 13 },
1234 { 220, 14 },
1235 { 240, 15 },
1236 { 250, 16 },
1237 { 300, 17 },
1238 { 320, 18 },
1239 { 440, 19 },
1240 { 480, 20 },
1241};
1242
1243/* Sample rates for DSP */
1244static struct {
1245 int rate;
1246 int value;
1247} sample_rates[] = {
1248 { 8000, 0 },
1249 { 11025, 1 },
1250 { 12000, 2 },
1251 { 16000, 3 },
1252 { 22050, 4 },
1253 { 24000, 5 },
1254 { 32000, 6 },
1255 { 44100, 7 },
1256 { 48000, 8 },
1257 { 88200, 9 },
1258 { 96000, 10 },
1259 { 0, 0 },
1260};
1261
dee89c4d
MB		 1262static int wm8903_startup(struct snd_pcm_substream *substream,
1263 struct snd_soc_dai *dai)
f1c0a02f
MB		 1264{
1265 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1266 struct snd_soc_device *socdev = rtd->socdev;
1267 struct snd_soc_codec *codec = socdev->codec;
1268 struct wm8903_priv *wm8903 = codec->private_data;
1269 struct i2c_client *i2c = codec->control_data;
1270 struct snd_pcm_runtime *master_runtime;
1271
1272 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1273 wm8903->playback_active++;
1274 else
1275 wm8903->capture_active++;
1276
1277 /* The DAI has shared clocks so if we already have a playback or
1278 * capture going then constrain this substream to match it.
1279 */
1280 if (wm8903->master_substream) {
1281 master_runtime = wm8903->master_substream->runtime;
1282
1283 dev_dbg(&i2c->dev, "Constraining to %d bits at %dHz\n",
1284 master_runtime->sample_bits,
1285 master_runtime->rate);
1286
1287 snd_pcm_hw_constraint_minmax(substream->runtime,
1288 SNDRV_PCM_HW_PARAM_RATE,
1289 master_runtime->rate,
1290 master_runtime->rate);
1291
1292 snd_pcm_hw_constraint_minmax(substream->runtime,
1293 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1294 master_runtime->sample_bits,
1295 master_runtime->sample_bits);
1296
1297 wm8903->slave_substream = substream;
1298 } else
1299 wm8903->master_substream = substream;
1300
1301 return 0;
1302}
1303
dee89c4d
MB		 1304static void wm8903_shutdown(struct snd_pcm_substream *substream,
1305 struct snd_soc_dai *dai)
f1c0a02f
MB		 1306{
1307 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1308 struct snd_soc_device *socdev = rtd->socdev;
1309 struct snd_soc_codec *codec = socdev->codec;
1310 struct wm8903_priv *wm8903 = codec->private_data;
1311
1312 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1313 wm8903->playback_active--;
1314 else
1315 wm8903->capture_active--;
1316
1317 if (wm8903->master_substream == substream)
1318 wm8903->master_substream = wm8903->slave_substream;
1319
1320 wm8903->slave_substream = NULL;
1321}
1322
1323static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1324 struct snd_pcm_hw_params *params,
1325 struct snd_soc_dai *dai)
f1c0a02f
MB		 1326{
1327 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1328 struct snd_soc_device *socdev = rtd->socdev;
1329 struct snd_soc_codec *codec = socdev->codec;
1330 struct wm8903_priv *wm8903 = codec->private_data;
1331 struct i2c_client *i2c = codec->control_data;
1332 int fs = params_rate(params);
1333 int bclk;
1334 int bclk_div;
1335 int i;
1336 int dsp_config;
1337 int clk_config;
1338 int best_val;
1339 int cur_val;
1340 int clk_sys;
1341
1342 u16 aif1 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_1);
1343 u16 aif2 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_2);
1344 u16 aif3 = wm8903_read(codec, WM8903_AUDIO_INTERFACE_3);
1345 u16 clock0 = wm8903_read(codec, WM8903_CLOCK_RATES_0);
1346 u16 clock1 = wm8903_read(codec, WM8903_CLOCK_RATES_1);
1347
1348 if (substream == wm8903->slave_substream) {
1349 dev_dbg(&i2c->dev, "Ignoring hw_params for slave substream\n");
1350 return 0;
1351 }
1352
1353 /* Configure sample rate logic for DSP - choose nearest rate */
1354 dsp_config = 0;
1355 best_val = abs(sample_rates[dsp_config].rate - fs);
1356 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1357 cur_val = abs(sample_rates[i].rate - fs);
1358 if (cur_val <= best_val) {
1359 dsp_config = i;
1360 best_val = cur_val;
1361 }
1362 }
1363
1364 /* Constraints should stop us hitting this but let's make sure */
1365 if (wm8903->capture_active)
1366 switch (sample_rates[dsp_config].rate) {
1367 case 88200:
1368 case 96000:
1369 dev_err(&i2c->dev, "%dHz unsupported by ADC\n",
1370 fs);
1371 return -EINVAL;
1372
1373 default:
1374 break;
1375 }
1376
1377 dev_dbg(&i2c->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
1378 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1379 clock1 |= sample_rates[dsp_config].value;
1380
1381 aif1 &= ~WM8903_AIF_WL_MASK;
1382 bclk = 2 * fs;
1383 switch (params_format(params)) {
1384 case SNDRV_PCM_FORMAT_S16_LE:
1385 bclk *= 16;
1386 break;
1387 case SNDRV_PCM_FORMAT_S20_3LE:
1388 bclk *= 20;
1389 aif1 |= 0x4;
1390 break;
1391 case SNDRV_PCM_FORMAT_S24_LE:
1392 bclk *= 24;
1393 aif1 |= 0x8;
1394 break;
1395 case SNDRV_PCM_FORMAT_S32_LE:
1396 bclk *= 32;
1397 aif1 |= 0xc;
1398 break;
1399 default:
1400 return -EINVAL;
1401 }
1402
1403 dev_dbg(&i2c->dev, "MCLK = %dHz, target sample rate = %dHz\n",
1404 wm8903->sysclk, fs);
1405
1406 /* We may not have an MCLK which allows us to generate exactly
1407 * the clock we want, particularly with USB derived inputs, so
1408 * approximate.
1409 */
1410 clk_config = 0;
1411 best_val = abs((wm8903->sysclk /
1412 (clk_sys_ratios[0].mclk_div *
1413 clk_sys_ratios[0].div)) - fs);
1414 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1415 cur_val = abs((wm8903->sysclk /
1416 (clk_sys_ratios[i].mclk_div *
1417 clk_sys_ratios[i].div)) - fs);
1418
1419 if (cur_val <= best_val) {
1420 clk_config = i;
1421 best_val = cur_val;
1422 }
1423 }
1424
1425 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1426 clock0 |= WM8903_MCLKDIV2;
1427 clk_sys = wm8903->sysclk / 2;
1428 } else {
1429 clock0 &= ~WM8903_MCLKDIV2;
1430 clk_sys = wm8903->sysclk;
1431 }
1432
1433 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1434 WM8903_CLK_SYS_MODE_MASK);
1435 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1436 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1437
1438 dev_dbg(&i2c->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
1439 clk_sys_ratios[clk_config].rate,
1440 clk_sys_ratios[clk_config].mode,
1441 clk_sys_ratios[clk_config].div);
1442
1443 dev_dbg(&i2c->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
1444
1445 /* We may not get quite the right frequency if using
1446 * approximate clocks so look for the closest match that is
1447 * higher than the target (we need to ensure that there enough
1448 * BCLKs to clock out the samples).
1449 */
1450 bclk_div = 0;
1451 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1452 i = 1;
1453 while (i < ARRAY_SIZE(bclk_divs)) {
1454 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1455 if (cur_val < 0) /* BCLK table is sorted */
1456 break;
1457 bclk_div = i;
1458 best_val = cur_val;
1459 i++;
1460 }
1461
1462 aif2 &= ~WM8903_BCLK_DIV_MASK;
1463 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1464
1465 dev_dbg(&i2c->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
1466 bclk_divs[bclk_div].ratio / 10, bclk,
1467 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1468
1469 aif2 |= bclk_divs[bclk_div].div;
1470 aif3 |= bclk / fs;
1471
1472 wm8903_write(codec, WM8903_CLOCK_RATES_0, clock0);
1473 wm8903_write(codec, WM8903_CLOCK_RATES_1, clock1);
1474 wm8903_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1475 wm8903_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1476 wm8903_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1477
1478 return 0;
1479}
1480
1481#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1482 SNDRV_PCM_RATE_11025 | \
1483 SNDRV_PCM_RATE_16000 | \
1484 SNDRV_PCM_RATE_22050 | \
1485 SNDRV_PCM_RATE_32000 | \
1486 SNDRV_PCM_RATE_44100 | \
1487 SNDRV_PCM_RATE_48000 | \
1488 SNDRV_PCM_RATE_88200 | \
1489 SNDRV_PCM_RATE_96000)
1490
1491#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1492 SNDRV_PCM_RATE_11025 | \
1493 SNDRV_PCM_RATE_16000 | \
1494 SNDRV_PCM_RATE_22050 | \
1495 SNDRV_PCM_RATE_32000 | \
1496 SNDRV_PCM_RATE_44100 | \
1497 SNDRV_PCM_RATE_48000)
1498
1499#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1500 SNDRV_PCM_FMTBIT_S20_3LE |\
1501 SNDRV_PCM_FMTBIT_S24_LE)
1502
1503struct snd_soc_dai wm8903_dai = {
1504 .name = "WM8903",
1505 .playback = {
1506 .stream_name = "Playback",
1507 .channels_min = 2,
1508 .channels_max = 2,
1509 .rates = WM8903_PLAYBACK_RATES,
1510 .formats = WM8903_FORMATS,
1511 },
1512 .capture = {
1513 .stream_name = "Capture",
1514 .channels_min = 2,
1515 .channels_max = 2,
1516 .rates = WM8903_CAPTURE_RATES,
1517 .formats = WM8903_FORMATS,
1518 },
1519 .ops = {
1520 .startup = wm8903_startup,
1521 .shutdown = wm8903_shutdown,
1522 .hw_params = wm8903_hw_params,
f1c0a02f
MB		 1523 .digital_mute = wm8903_digital_mute,
1524 .set_fmt = wm8903_set_dai_fmt,
1525 .set_sysclk = wm8903_set_dai_sysclk
1526 }
1527};
1528EXPORT_SYMBOL_GPL(wm8903_dai);
1529
1530static int wm8903_suspend(struct platform_device *pdev, pm_message_t state)
1531{
1532 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1533 struct snd_soc_codec *codec = socdev->codec;
1534
1535 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1536
1537 return 0;
1538}
1539
1540static int wm8903_resume(struct platform_device *pdev)
1541{
1542 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1543 struct snd_soc_codec *codec = socdev->codec;
1544 struct i2c_client *i2c = codec->control_data;
1545 int i;
1546 u16 *reg_cache = codec->reg_cache;
1547 u16 *tmp_cache = kmemdup(codec->reg_cache, sizeof(wm8903_reg_defaults),
1548 GFP_KERNEL);
1549
1550 /* Bring the codec back up to standby first to minimise pop/clicks */
1551 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1552 wm8903_set_bias_level(codec, codec->suspend_bias_level);
1553
1554 /* Sync back everything else */
1555 if (tmp_cache) {
1556 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1557 if (tmp_cache[i] != reg_cache[i])
1558 wm8903_write(codec, i, tmp_cache[i]);
1559 } else {
1560 dev_err(&i2c->dev, "Failed to allocate temporary cache\n");
1561 }
1562
1563 return 0;
1564}
1565
1566/*
1567 * initialise the WM8903 driver
1568 * register the mixer and dsp interfaces with the kernel
1569 */
1570static int wm8903_init(struct snd_soc_device *socdev)
1571{
1572 struct snd_soc_codec *codec = socdev->codec;
1573 struct i2c_client *i2c = codec->control_data;
1574 int ret = 0;
1575 u16 val;
1576
1577 val = wm8903_hw_read(codec, WM8903_SW_RESET_AND_ID);
1578 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
1579 dev_err(&i2c->dev,
1580 "Device with ID register %x is not a WM8903\n", val);
1581 return -ENODEV;
1582 }
1583
1584 codec->name = "WM8903";
1585 codec->owner = THIS_MODULE;
1586 codec->read = wm8903_read;
1587 codec->write = wm8903_write;
1588 codec->bias_level = SND_SOC_BIAS_OFF;
1589 codec->set_bias_level = wm8903_set_bias_level;
1590 codec->dai = &wm8903_dai;
1591 codec->num_dai = 1;
1592 codec->reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults);
1593 codec->reg_cache = kmemdup(wm8903_reg_defaults,
1594 sizeof(wm8903_reg_defaults),
1595 GFP_KERNEL);
1596 if (codec->reg_cache == NULL) {
1597 dev_err(&i2c->dev, "Failed to allocate register cache\n");
1598 return -ENOMEM;
1599 }
1600
1601 val = wm8903_read(codec, WM8903_REVISION_NUMBER);
1602 dev_info(&i2c->dev, "WM8903 revision %d\n",
1603 val & WM8903_CHIP_REV_MASK);
1604
1605 wm8903_reset(codec);
1606
1607 /* register pcms */
1608 ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
1609 if (ret < 0) {
1610 dev_err(&i2c->dev, "failed to create pcms\n");
1611 goto pcm_err;
1612 }
1613
1614 /* SYSCLK is required for pretty much anything */
1615 wm8903_write(codec, WM8903_CLOCK_RATES_2, WM8903_CLK_SYS_ENA);
1616
1617 /* power on device */
1618 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1619
1620 /* Latch volume update bits */
1621 val = wm8903_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
1622 val |= WM8903_ADCVU;
1623 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1624 wm8903_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
1625
1626 val = wm8903_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
1627 val |= WM8903_DACVU;
1628 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1629 wm8903_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
1630
1631 val = wm8903_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
1632 val |= WM8903_HPOUTVU;
1633 wm8903_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1634 wm8903_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
1635
1636 val = wm8903_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
1637 val |= WM8903_LINEOUTVU;
1638 wm8903_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1639 wm8903_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
1640
1641 val = wm8903_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
1642 val |= WM8903_SPKVU;
1643 wm8903_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1644 wm8903_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
1645
1646 /* Enable DAC soft mute by default */
1647 val = wm8903_read(codec, WM8903_DAC_DIGITAL_1);
1648 val |= WM8903_DAC_MUTEMODE;
1649 wm8903_write(codec, WM8903_DAC_DIGITAL_1, val);
1650
1651 wm8903_add_controls(codec);
1652 wm8903_add_widgets(codec);
968a6025 1653 ret = snd_soc_init_card(socdev);
f1c0a02f
MB		 1654 if (ret < 0) {
1655 dev_err(&i2c->dev, "wm8903: failed to register card\n");
1656 goto card_err;
1657 }
1658
1659 return ret;
1660
1661card_err:
1662 snd_soc_free_pcms(socdev);
1663 snd_soc_dapm_free(socdev);
1664pcm_err:
1665 kfree(codec->reg_cache);
1666 return ret;
1667}
1668
1669static struct snd_soc_device *wm8903_socdev;
1670
1671static int wm8903_i2c_probe(struct i2c_client *i2c,
1672 const struct i2c_device_id *id)
1673{
1674 struct snd_soc_device *socdev = wm8903_socdev;
1675 struct snd_soc_codec *codec = socdev->codec;
1676 int ret;
1677
1678 i2c_set_clientdata(i2c, codec);
1679 codec->control_data = i2c;
1680
1681 ret = wm8903_init(socdev);
1682 if (ret < 0)
1683 dev_err(&i2c->dev, "Device initialisation failed\n");
1684
1685 return ret;
1686}
1687
1688static int wm8903_i2c_remove(struct i2c_client *client)
1689{
1690 struct snd_soc_codec *codec = i2c_get_clientdata(client);
1691 kfree(codec->reg_cache);
1692 return 0;
1693}
1694
1695/* i2c codec control layer */
1696static const struct i2c_device_id wm8903_i2c_id[] = {
1697 { "wm8903", 0 },
1698 { }
1699};
1700MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1701
1702static struct i2c_driver wm8903_i2c_driver = {
1703 .driver = {
1704 .name = "WM8903",
1705 .owner = THIS_MODULE,
1706 },
1707 .probe = wm8903_i2c_probe,
1708 .remove = wm8903_i2c_remove,
1709 .id_table = wm8903_i2c_id,
1710};
1711
f1c0a02f
MB		 1712static int wm8903_probe(struct platform_device *pdev)
1713{
1714 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1715 struct wm8903_setup_data *setup;
1716 struct snd_soc_codec *codec;
1717 struct wm8903_priv *wm8903;
1718 struct i2c_board_info board_info;
1719 struct i2c_adapter *adapter;
acdfc9e3 1720 struct i2c_client *i2c_client;
f1c0a02f
MB		 1721 int ret = 0;
1722
1723 setup = socdev->codec_data;
1724
1725 if (!setup->i2c_address) {
1726 dev_err(&pdev->dev, "No codec address provided\n");
1727 return -ENODEV;
1728 }
1729
1730 codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
1731 if (codec == NULL)
1732 return -ENOMEM;
1733
1734 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1735 if (wm8903 == NULL) {
1736 ret = -ENOMEM;
1737 goto err_codec;
1738 }
1739
1740 codec->private_data = wm8903;
1741 socdev->codec = codec;
1742 mutex_init(&codec->mutex);
1743 INIT_LIST_HEAD(&codec->dapm_widgets);
1744 INIT_LIST_HEAD(&codec->dapm_paths);
1745
1746 wm8903_socdev = socdev;
1747
1748 codec->hw_write = (hw_write_t)i2c_master_send;
1749 ret = i2c_add_driver(&wm8903_i2c_driver);
1750 if (ret != 0) {
acdfc9e3 1751 dev_err(&pdev->dev, "can't add i2c driver\n");
f1c0a02f
MB		 1752 goto err_priv;
1753 } else {
1754 memset(&board_info, 0, sizeof(board_info));
1755 strlcpy(board_info.type, "wm8903", I2C_NAME_SIZE);
1756 board_info.addr = setup->i2c_address;
1757
1758 adapter = i2c_get_adapter(setup->i2c_bus);
1759 if (!adapter) {
1760 dev_err(&pdev->dev, "Can't get I2C bus %d\n",
1761 setup->i2c_bus);
acdfc9e3 1762 ret = -ENODEV;
f1c0a02f
MB		 1763 goto err_adapter;
1764 }
1765
acdfc9e3 1766 i2c_client = i2c_new_device(adapter, &board_info);
f1c0a02f 1767 i2c_put_adapter(adapter);
acdfc9e3 1768 if (i2c_client == NULL) {
f1c0a02f
MB		 1769 dev_err(&pdev->dev,
1770 "I2C driver registration failed\n");
1771 ret = -ENODEV;
1772 goto err_adapter;
1773 }
1774 }
1775
1776 return ret;
1777
1778err_adapter:
1779 i2c_del_driver(&wm8903_i2c_driver);
1780err_priv:
1781 kfree(codec->private_data);
1782err_codec:
1783 kfree(codec);
1784 return ret;
1785}
1786
1787/* power down chip */
1788static int wm8903_remove(struct platform_device *pdev)
1789{
1790 struct snd_soc_device *socdev = platform_get_drvdata(pdev);
1791 struct snd_soc_codec *codec = socdev->codec;
1792
1793 if (codec->control_data)
1794 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1795
1796 snd_soc_free_pcms(socdev);
1797 snd_soc_dapm_free(socdev);
acdfc9e3 1798 i2c_unregister_device(socdev->codec->control_data);
f1c0a02f
MB		 1799 i2c_del_driver(&wm8903_i2c_driver);
1800 kfree(codec->private_data);
1801 kfree(codec);
1802
1803 return 0;
1804}
1805
1806struct snd_soc_codec_device soc_codec_dev_wm8903 = {
1807 .probe = wm8903_probe,
1808 .remove = wm8903_remove,
1809 .suspend = wm8903_suspend,
1810 .resume = wm8903_resume,
1811};
1812EXPORT_SYMBOL_GPL(soc_codec_dev_wm8903);
1813
c9b3a40f 1814static int __init wm8903_modinit(void)
64089b84
MB		 1815{
1816 return snd_soc_register_dai(&wm8903_dai);
1817}
1818module_init(wm8903_modinit);
1819
1820static void __exit wm8903_exit(void)
1821{
1822 snd_soc_unregister_dai(&wm8903_dai);
1823}
1824module_exit(wm8903_exit);
1825
f1c0a02f
MB		 1826MODULE_DESCRIPTION("ASoC WM8903 driver");
1827MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1828MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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