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ASoC: Don't resync WM8903 register cache on reset
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
7cfe5617 5 * Copyright 2011 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
5a0e3ad6 26#include <linux/slab.h>
f1c0a02f 27#include <sound/core.h>
7245387e 28#include <sound/jack.h>
f1c0a02f
MB		 29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/tlv.h>
32#include <sound/soc.h>
f1c0a02f 33#include <sound/initval.h>
8abd16a6 34#include <sound/wm8903.h>
2bbb5d66 35#include <trace/events/asoc.h>
f1c0a02f
MB		 36
37#include "wm8903.h"
38
f1c0a02f
MB		 39/* Register defaults at reset */
40static u16 wm8903_reg_defaults[] = {
41 0x8903, /* R0 - SW Reset and ID */
42 0x0000, /* R1 - Revision Number */
43 0x0000, /* R2 */
44 0x0000, /* R3 */
45 0x0018, /* R4 - Bias Control 0 */
46 0x0000, /* R5 - VMID Control 0 */
47 0x0000, /* R6 - Mic Bias Control 0 */
48 0x0000, /* R7 */
49 0x0001, /* R8 - Analogue DAC 0 */
50 0x0000, /* R9 */
51 0x0001, /* R10 - Analogue ADC 0 */
52 0x0000, /* R11 */
53 0x0000, /* R12 - Power Management 0 */
54 0x0000, /* R13 - Power Management 1 */
55 0x0000, /* R14 - Power Management 2 */
56 0x0000, /* R15 - Power Management 3 */
57 0x0000, /* R16 - Power Management 4 */
58 0x0000, /* R17 - Power Management 5 */
59 0x0000, /* R18 - Power Management 6 */
60 0x0000, /* R19 */
61 0x0400, /* R20 - Clock Rates 0 */
62 0x0D07, /* R21 - Clock Rates 1 */
63 0x0000, /* R22 - Clock Rates 2 */
64 0x0000, /* R23 */
65 0x0050, /* R24 - Audio Interface 0 */
66 0x0242, /* R25 - Audio Interface 1 */
67 0x0008, /* R26 - Audio Interface 2 */
68 0x0022, /* R27 - Audio Interface 3 */
69 0x0000, /* R28 */
70 0x0000, /* R29 */
71 0x00C0, /* R30 - DAC Digital Volume Left */
72 0x00C0, /* R31 - DAC Digital Volume Right */
73 0x0000, /* R32 - DAC Digital 0 */
74 0x0000, /* R33 - DAC Digital 1 */
75 0x0000, /* R34 */
76 0x0000, /* R35 */
77 0x00C0, /* R36 - ADC Digital Volume Left */
78 0x00C0, /* R37 - ADC Digital Volume Right */
79 0x0000, /* R38 - ADC Digital 0 */
80 0x0073, /* R39 - Digital Microphone 0 */
81 0x09BF, /* R40 - DRC 0 */
82 0x3241, /* R41 - DRC 1 */
83 0x0020, /* R42 - DRC 2 */
84 0x0000, /* R43 - DRC 3 */
85 0x0085, /* R44 - Analogue Left Input 0 */
86 0x0085, /* R45 - Analogue Right Input 0 */
87 0x0044, /* R46 - Analogue Left Input 1 */
88 0x0044, /* R47 - Analogue Right Input 1 */
89 0x0000, /* R48 */
90 0x0000, /* R49 */
91 0x0008, /* R50 - Analogue Left Mix 0 */
92 0x0004, /* R51 - Analogue Right Mix 0 */
93 0x0000, /* R52 - Analogue Spk Mix Left 0 */
94 0x0000, /* R53 - Analogue Spk Mix Left 1 */
95 0x0000, /* R54 - Analogue Spk Mix Right 0 */
96 0x0000, /* R55 - Analogue Spk Mix Right 1 */
97 0x0000, /* R56 */
98 0x002D, /* R57 - Analogue OUT1 Left */
99 0x002D, /* R58 - Analogue OUT1 Right */
100 0x0039, /* R59 - Analogue OUT2 Left */
101 0x0039, /* R60 - Analogue OUT2 Right */
102 0x0100, /* R61 */
103 0x0139, /* R62 - Analogue OUT3 Left */
104 0x0139, /* R63 - Analogue OUT3 Right */
105 0x0000, /* R64 */
106 0x0000, /* R65 - Analogue SPK Output Control 0 */
107 0x0000, /* R66 */
108 0x0010, /* R67 - DC Servo 0 */
109 0x0100, /* R68 */
110 0x00A4, /* R69 - DC Servo 2 */
111 0x0807, /* R70 */
112 0x0000, /* R71 */
113 0x0000, /* R72 */
114 0x0000, /* R73 */
115 0x0000, /* R74 */
116 0x0000, /* R75 */
117 0x0000, /* R76 */
118 0x0000, /* R77 */
119 0x0000, /* R78 */
120 0x000E, /* R79 */
121 0x0000, /* R80 */
122 0x0000, /* R81 */
123 0x0000, /* R82 */
124 0x0000, /* R83 */
125 0x0000, /* R84 */
126 0x0000, /* R85 */
127 0x0000, /* R86 */
128 0x0006, /* R87 */
129 0x0000, /* R88 */
130 0x0000, /* R89 */
131 0x0000, /* R90 - Analogue HP 0 */
132 0x0060, /* R91 */
133 0x0000, /* R92 */
134 0x0000, /* R93 */
135 0x0000, /* R94 - Analogue Lineout 0 */
136 0x0060, /* R95 */
137 0x0000, /* R96 */
138 0x0000, /* R97 */
139 0x0000, /* R98 - Charge Pump 0 */
140 0x1F25, /* R99 */
141 0x2B19, /* R100 */
142 0x01C0, /* R101 */
143 0x01EF, /* R102 */
144 0x2B00, /* R103 */
145 0x0000, /* R104 - Class W 0 */
146 0x01C0, /* R105 */
147 0x1C10, /* R106 */
148 0x0000, /* R107 */
149 0x0000, /* R108 - Write Sequencer 0 */
150 0x0000, /* R109 - Write Sequencer 1 */
151 0x0000, /* R110 - Write Sequencer 2 */
152 0x0000, /* R111 - Write Sequencer 3 */
153 0x0000, /* R112 - Write Sequencer 4 */
154 0x0000, /* R113 */
155 0x0000, /* R114 - Control Interface */
156 0x0000, /* R115 */
157 0x00A8, /* R116 - GPIO Control 1 */
158 0x00A8, /* R117 - GPIO Control 2 */
159 0x00A8, /* R118 - GPIO Control 3 */
160 0x0220, /* R119 - GPIO Control 4 */
161 0x01A0, /* R120 - GPIO Control 5 */
162 0x0000, /* R121 - Interrupt Status 1 */
163 0xFFFF, /* R122 - Interrupt Status 1 Mask */
164 0x0000, /* R123 - Interrupt Polarity 1 */
165 0x0000, /* R124 */
166 0x0003, /* R125 */
167 0x0000, /* R126 - Interrupt Control */
168 0x0000, /* R127 */
169 0x0005, /* R128 */
170 0x0000, /* R129 - Control Interface Test 1 */
171 0x0000, /* R130 */
172 0x0000, /* R131 */
173 0x0000, /* R132 */
174 0x0000, /* R133 */
175 0x0000, /* R134 */
176 0x03FF, /* R135 */
177 0x0007, /* R136 */
178 0x0040, /* R137 */
179 0x0000, /* R138 */
180 0x0000, /* R139 */
181 0x0000, /* R140 */
182 0x0000, /* R141 */
183 0x0000, /* R142 */
184 0x0000, /* R143 */
185 0x0000, /* R144 */
186 0x0000, /* R145 */
187 0x0000, /* R146 */
188 0x0000, /* R147 */
189 0x4000, /* R148 */
190 0x6810, /* R149 - Charge Pump Test 1 */
191 0x0004, /* R150 */
192 0x0000, /* R151 */
193 0x0000, /* R152 */
194 0x0000, /* R153 */
195 0x0000, /* R154 */
196 0x0000, /* R155 */
197 0x0000, /* R156 */
198 0x0000, /* R157 */
199 0x0000, /* R158 */
200 0x0000, /* R159 */
201 0x0000, /* R160 */
202 0x0000, /* R161 */
203 0x0000, /* R162 */
204 0x0000, /* R163 */
205 0x0028, /* R164 - Clock Rate Test 4 */
206 0x0004, /* R165 */
207 0x0000, /* R166 */
208 0x0060, /* R167 */
209 0x0000, /* R168 */
210 0x0000, /* R169 */
211 0x0000, /* R170 */
212 0x0000, /* R171 */
213 0x0000, /* R172 - Analogue Output Bias 0 */
214};
215
d58d5d55 216struct wm8903_priv {
7cfe5617 217 struct snd_soc_codec *codec;
f0fba2ad 218
d58d5d55 219 int sysclk;
f0fba2ad 220 int irq;
d58d5d55 221
69fff9bb
MB		 222 int fs;
223 int deemph;
224
c5b6a9fe
MB		 225 int dcs_pending;
226 int dcs_cache[4];
227
f2c1fe09 228 /* Reference count */
d58d5d55 229 int class_w_users;
d58d5d55 230
7245387e
MB		 231 struct snd_soc_jack *mic_jack;
232 int mic_det;
233 int mic_short;
234 int mic_last_report;
235 int mic_delay;
7cfe5617
SW		 236
237#ifdef CONFIG_GPIOLIB
238 struct gpio_chip gpio_chip;
239#endif
d58d5d55
MB		 240};
241
d4754ec9 242static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 243{
244 switch (reg) {
245 case WM8903_SW_RESET_AND_ID:
246 case WM8903_REVISION_NUMBER:
247 case WM8903_INTERRUPT_STATUS_1:
248 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 249 case WM8903_DC_SERVO_READBACK_1:
250 case WM8903_DC_SERVO_READBACK_2:
251 case WM8903_DC_SERVO_READBACK_3:
252 case WM8903_DC_SERVO_READBACK_4:
8d50e447 253 return 1;
f1c0a02f
MB		 254
255 default:
f1c0a02f 256 return 0;
8d50e447 257 }
f1c0a02f
MB		 258}
259
f1c0a02f
MB		 260static void wm8903_reset(struct snd_soc_codec *codec)
261{
8d50e447 262 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
f1c0a02f
MB		 263}
264
42768a12
MB		 265static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
266 struct snd_kcontrol *kcontrol, int event)
267{
268 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
269 mdelay(4);
270
271 return 0;
272}
273
c5b6a9fe
MB		 274static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
275 struct snd_kcontrol *kcontrol, int event)
276{
277 struct snd_soc_codec *codec = w->codec;
278 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
279
280 switch (event) {
281 case SND_SOC_DAPM_POST_PMU:
282 wm8903->dcs_pending |= 1 << w->shift;
283 break;
284 case SND_SOC_DAPM_PRE_PMD:
285 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
286 1 << w->shift, 0);
287 break;
288 }
289
290 return 0;
291}
292
293#define WM8903_DCS_MODE_WRITE_STOP 0
294#define WM8903_DCS_MODE_START_STOP 2
295
296static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
297 enum snd_soc_dapm_type event, int subseq)
298{
299 struct snd_soc_codec *codec = container_of(dapm,
300 struct snd_soc_codec, dapm);
301 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
302 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
303 int i, val;
304
305 /* Complete any pending DC servo starts */
306 if (wm8903->dcs_pending) {
307 dev_dbg(codec->dev, "Starting DC servo for %x\n",
308 wm8903->dcs_pending);
309
310 /* If we've no cached values then we need to do startup */
311 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
312 if (!(wm8903->dcs_pending & (1 << i)))
313 continue;
314
315 if (wm8903->dcs_cache[i]) {
316 dev_dbg(codec->dev,
317 "Restore DC servo %d value %x\n",
318 3 - i, wm8903->dcs_cache[i]);
319
320 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
321 wm8903->dcs_cache[i] & 0xff);
322 } else {
323 dev_dbg(codec->dev,
324 "Calibrate DC servo %d\n", 3 - i);
325 dcs_mode = WM8903_DCS_MODE_START_STOP;
326 }
327 }
328
329 /* Don't trust the cache for analogue */
330 if (wm8903->class_w_users)
331 dcs_mode = WM8903_DCS_MODE_START_STOP;
332
333 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
334 WM8903_DCS_MODE_MASK, dcs_mode);
335
336 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
337 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
338
339 switch (dcs_mode) {
340 case WM8903_DCS_MODE_WRITE_STOP:
341 break;
342
343 case WM8903_DCS_MODE_START_STOP:
344 msleep(270);
345
346 /* Cache the measured offsets for digital */
347 if (wm8903->class_w_users)
348 break;
349
350 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
351 if (!(wm8903->dcs_pending & (1 << i)))
352 continue;
353
354 val = snd_soc_read(codec,
355 WM8903_DC_SERVO_READBACK_1 + i);
356 dev_dbg(codec->dev, "DC servo %d: %x\n",
357 3 - i, val);
358 wm8903->dcs_cache[i] = val;
359 }
360 break;
361
362 default:
363 pr_warn("DCS mode %d delay not set\n", dcs_mode);
364 break;
365 }
366
367 wm8903->dcs_pending = 0;
368 }
369}
370
f1c0a02f
MB		 371/*
372 * When used with DAC outputs only the WM8903 charge pump supports
373 * operation in class W mode, providing very low power consumption
374 * when used with digital sources. Enable and disable this mode
375 * automatically depending on the mixer configuration.
376 *
377 * All the relevant controls are simple switches.
378 */
379static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
380 struct snd_ctl_elem_value *ucontrol)
381{
9d03545d
JN		 382 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
383 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
f1c0a02f 384 struct snd_soc_codec *codec = widget->codec;
b2c812e2 385 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 386 u16 reg;
387 int ret;
388
8d50e447 389 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 390
391 /* Turn it off if we're about to enable bypass */
392 if (ucontrol->value.integer.value[0]) {
393 if (wm8903->class_w_users == 0) {
f0fba2ad 394 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 395 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 396 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
397 }
398 wm8903->class_w_users++;
399 }
400
401 /* Implement the change */
402 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
403
404 /* If we've just disabled the last bypass path turn Class W on */
405 if (!ucontrol->value.integer.value[0]) {
406 if (wm8903->class_w_users == 1) {
f0fba2ad 407 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 408 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 409 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
410 }
411 wm8903->class_w_users--;
412 }
413
f0fba2ad 414 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 415 wm8903->class_w_users);
416
417 return ret;
418}
419
420#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
421{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
422 .info = snd_soc_info_volsw, \
423 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
424 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
425
426
69fff9bb
MB		 427static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
428
429static int wm8903_set_deemph(struct snd_soc_codec *codec)
430{
431 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
432 int val, i, best;
433
434 /* If we're using deemphasis select the nearest available sample
435 * rate.
436 */
437 if (wm8903->deemph) {
438 best = 1;
439 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
440 if (abs(wm8903_deemph[i] - wm8903->fs) <
441 abs(wm8903_deemph[best] - wm8903->fs))
442 best = i;
443 }
444
445 val = best << WM8903_DEEMPH_SHIFT;
446 } else {
447 best = 0;
448 val = 0;
449 }
450
451 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
452 best, wm8903_deemph[best]);
453
454 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
455 WM8903_DEEMPH_MASK, val);
456}
457
458static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
459 struct snd_ctl_elem_value *ucontrol)
460{
461 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
462 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
463
464 ucontrol->value.enumerated.item[0] = wm8903->deemph;
465
466 return 0;
467}
468
469static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
470 struct snd_ctl_elem_value *ucontrol)
471{
472 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
473 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
474 int deemph = ucontrol->value.enumerated.item[0];
475 int ret = 0;
476
477 if (deemph > 1)
478 return -EINVAL;
479
480 mutex_lock(&codec->mutex);
481 if (wm8903->deemph != deemph) {
482 wm8903->deemph = deemph;
483
484 wm8903_set_deemph(codec);
485
486 ret = 1;
487 }
488 mutex_unlock(&codec->mutex);
489
490 return ret;
491}
492
f1c0a02f
MB		 493/* ALSA can only do steps of .01dB */
494static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
495
291ce18c 496static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 497static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
498
499static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
500static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
501static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
502static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
503static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
504
460f4aae
MB		 505static const char *hpf_mode_text[] = {
506 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
507};
508
509static const struct soc_enum hpf_mode =
510 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
511
dcf9ada3
MB		 512static const char *osr_text[] = {
513 "Low power", "High performance"
514};
515
516static const struct soc_enum adc_osr =
517 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
518
519static const struct soc_enum dac_osr =
520 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
521
f1c0a02f
MB		 522static const char *drc_slope_text[] = {
523 "1", "1/2", "1/4", "1/8", "1/16", "0"
524};
525
526static const struct soc_enum drc_slope_r0 =
527 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
528
529static const struct soc_enum drc_slope_r1 =
530 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
531
532static const char *drc_attack_text[] = {
533 "instantaneous",
534 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
535 "46.4ms", "92.8ms", "185.6ms"
536};
537
538static const struct soc_enum drc_attack =
539 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
540
541static const char *drc_decay_text[] = {
542 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
543 "23.87s", "47.56s"
544};
545
546static const struct soc_enum drc_decay =
547 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
548
549static const char *drc_ff_delay_text[] = {
550 "5 samples", "9 samples"
551};
552
553static const struct soc_enum drc_ff_delay =
554 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
555
556static const char *drc_qr_decay_text[] = {
557 "0.725ms", "1.45ms", "5.8ms"
558};
559
560static const struct soc_enum drc_qr_decay =
561 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
562
563static const char *drc_smoothing_text[] = {
564 "Low", "Medium", "High"
565};
566
567static const struct soc_enum drc_smoothing =
568 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
569
570static const char *soft_mute_text[] = {
571 "Fast (fs/2)", "Slow (fs/32)"
572};
573
574static const struct soc_enum soft_mute =
575 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
576
577static const char *mute_mode_text[] = {
578 "Hard", "Soft"
579};
580
581static const struct soc_enum mute_mode =
582 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
583
f1c0a02f
MB		 584static const char *companding_text[] = {
585 "ulaw", "alaw"
586};
587
588static const struct soc_enum dac_companding =
589 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
590
591static const struct soc_enum adc_companding =
592 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
593
594static const char *input_mode_text[] = {
595 "Single-Ended", "Differential Line", "Differential Mic"
596};
597
598static const struct soc_enum linput_mode_enum =
599 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
600
601static const struct soc_enum rinput_mode_enum =
602 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
603
604static const char *linput_mux_text[] = {
605 "IN1L", "IN2L", "IN3L"
606};
607
608static const struct soc_enum linput_enum =
609 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
610
611static const struct soc_enum linput_inv_enum =
612 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
613
614static const char *rinput_mux_text[] = {
615 "IN1R", "IN2R", "IN3R"
616};
617
618static const struct soc_enum rinput_enum =
619 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
620
621static const struct soc_enum rinput_inv_enum =
622 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
623
624
291ce18c
MB		 625static const char *sidetone_text[] = {
626 "None", "Left", "Right"
627};
628
629static const struct soc_enum lsidetone_enum =
630 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
631
632static const struct soc_enum rsidetone_enum =
633 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
634
97945c46
SW		 635static const char *adcinput_text[] = {
636 "ADC", "DMIC"
637};
638
639static const struct soc_enum adcinput_enum =
640 SOC_ENUM_SINGLE(WM8903_CLOCK_RATE_TEST_4, 9, 2, adcinput_text);
641
1e113bf9
MB		 642static const char *aif_text[] = {
643 "Left", "Right"
644};
645
646static const struct soc_enum lcapture_enum =
647 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 7, 2, aif_text);
648
649static const struct soc_enum rcapture_enum =
650 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 6, 2, aif_text);
651
652static const struct soc_enum lplay_enum =
653 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 5, 2, aif_text);
654
655static const struct soc_enum rplay_enum =
656 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 4, 2, aif_text);
657
f1c0a02f
MB		 658static const struct snd_kcontrol_new wm8903_snd_controls[] = {
659
660/* Input PGAs - No TLV since the scale depends on PGA mode */
661SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 662 7, 1, 1),
f1c0a02f
MB		 663SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
664 0, 31, 0),
665SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
666 6, 1, 0),
667
668SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 669 7, 1, 1),
f1c0a02f
MB		 670SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
671 0, 31, 0),
672SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
673 6, 1, 0),
674
675/* ADCs */
dcf9ada3 676SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 677SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
678SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 679SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
680SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
681SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 682SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 683 drc_tlv_thresh),
684SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
685SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
686SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
687SOC_ENUM("DRC Attack Rate", drc_attack),
688SOC_ENUM("DRC Decay Rate", drc_decay),
689SOC_ENUM("DRC FF Delay", drc_ff_delay),
690SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
691SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 692SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 693SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
694SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
695SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 696SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 697SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
698
699SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
61bf35b9 700 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
f1c0a02f
MB		 701SOC_ENUM("ADC Companding Mode", adc_companding),
702SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
703
291ce18c
MB		 704SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
705 12, 0, digital_sidetone_tlv),
706
f1c0a02f 707/* DAC */
dcf9ada3 708SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 709SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
710 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
711SOC_ENUM("DAC Soft Mute Rate", soft_mute),
712SOC_ENUM("DAC Mute Mode", mute_mode),
713SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 714SOC_ENUM("DAC Companding Mode", dac_companding),
715SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 716SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
717 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 718
719/* Headphones */
720SOC_DOUBLE_R("Headphone Switch",
721 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
722 8, 1, 1),
723SOC_DOUBLE_R("Headphone ZC Switch",
724 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
725 6, 1, 0),
726SOC_DOUBLE_R_TLV("Headphone Volume",
727 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
728 0, 63, 0, out_tlv),
729
730/* Line out */
731SOC_DOUBLE_R("Line Out Switch",
732 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
733 8, 1, 1),
734SOC_DOUBLE_R("Line Out ZC Switch",
735 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
736 6, 1, 0),
737SOC_DOUBLE_R_TLV("Line Out Volume",
738 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
739 0, 63, 0, out_tlv),
740
741/* Speaker */
742SOC_DOUBLE_R("Speaker Switch",
743 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
744SOC_DOUBLE_R("Speaker ZC Switch",
745 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
746SOC_DOUBLE_R_TLV("Speaker Volume",
747 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
748 0, 63, 0, out_tlv),
749};
750
f1c0a02f
MB		 751static const struct snd_kcontrol_new linput_mode_mux =
752 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
753
754static const struct snd_kcontrol_new rinput_mode_mux =
755 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
756
757static const struct snd_kcontrol_new linput_mux =
758 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
759
760static const struct snd_kcontrol_new linput_inv_mux =
761 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
762
763static const struct snd_kcontrol_new rinput_mux =
764 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
765
766static const struct snd_kcontrol_new rinput_inv_mux =
767 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
768
291ce18c
MB		 769static const struct snd_kcontrol_new lsidetone_mux =
770 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
771
772static const struct snd_kcontrol_new rsidetone_mux =
773 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
774
97945c46
SW		 775static const struct snd_kcontrol_new adcinput_mux =
776 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
777
1e113bf9
MB		 778static const struct snd_kcontrol_new lcapture_mux =
779 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
780
781static const struct snd_kcontrol_new rcapture_mux =
782 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
783
784static const struct snd_kcontrol_new lplay_mux =
785 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
786
787static const struct snd_kcontrol_new rplay_mux =
788 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
789
f1c0a02f
MB		 790static const struct snd_kcontrol_new left_output_mixer[] = {
791SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
792SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
793SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 794SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 795};
796
797static const struct snd_kcontrol_new right_output_mixer[] = {
798SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
799SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
800SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 801SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 802};
803
804static const struct snd_kcontrol_new left_speaker_mixer[] = {
805SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
806SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
807SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
808SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 809 0, 1, 0),
f1c0a02f
MB		 810};
811
812static const struct snd_kcontrol_new right_speaker_mixer[] = {
813SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
814SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
815SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
816 1, 1, 0),
817SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 818 0, 1, 0),
f1c0a02f
MB		 819};
820
821static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
822SND_SOC_DAPM_INPUT("IN1L"),
823SND_SOC_DAPM_INPUT("IN1R"),
824SND_SOC_DAPM_INPUT("IN2L"),
825SND_SOC_DAPM_INPUT("IN2R"),
826SND_SOC_DAPM_INPUT("IN3L"),
827SND_SOC_DAPM_INPUT("IN3R"),
97945c46 828SND_SOC_DAPM_INPUT("DMICDAT"),
f1c0a02f
MB		 829
830SND_SOC_DAPM_OUTPUT("HPOUTL"),
831SND_SOC_DAPM_OUTPUT("HPOUTR"),
832SND_SOC_DAPM_OUTPUT("LINEOUTL"),
833SND_SOC_DAPM_OUTPUT("LINEOUTR"),
834SND_SOC_DAPM_OUTPUT("LOP"),
835SND_SOC_DAPM_OUTPUT("LON"),
836SND_SOC_DAPM_OUTPUT("ROP"),
837SND_SOC_DAPM_OUTPUT("RON"),
838
5032dc34 839SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
f1c0a02f
MB		 840
841SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
842SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
843 &linput_inv_mux),
844SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
845
846SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
847SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
848 &rinput_inv_mux),
849SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
850
851SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
852SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
853
97945c46
SW		 854SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
855SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
856
1e113bf9
MB		 857SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
858SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
859
860SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
861SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
862
863SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
864SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 865
291ce18c
MB		 866SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
867SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
868
1e113bf9
MB		 869SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
870SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
871
872SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
873SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
874
875SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
876SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 877
878SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
879 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
880SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
881 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
882
883SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
884 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
885SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
886 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
887
1b877cb5
DL		 888SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
889 1, 0, NULL, 0),
890SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 891 0, 0, NULL, 0),
892
1b877cb5 893SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 894 NULL, 0),
1b877cb5 895SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 896 NULL, 0),
897
898SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
899SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 900SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
901SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 902SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
903SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 904SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
905SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 906
907SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
908 NULL, 0),
909SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
910 NULL, 0),
1b877cb5
DL		 911SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
912 NULL, 0),
913SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 914 NULL, 0),
915SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
916 NULL, 0),
917SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
918 NULL, 0),
1b877cb5
DL		 919SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
920 NULL, 0),
921SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 922 NULL, 0),
923
c5b6a9fe
MB		 924SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
925SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
926 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
927SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
928 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
929SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
930 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
931SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
932 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 933
934SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
935 NULL, 0),
936SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
937 NULL, 0),
938
42768a12
MB		 939SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
940 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 941SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 942SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 943};
944
ecd01512 945static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 946
2c8be5a2 947 { "CLK_DSP", NULL, "CLK_SYS" },
5032dc34 948 { "MICBIAS", NULL, "CLK_SYS" },
2c8be5a2
MB		 949 { "HPL_DCS", NULL, "CLK_SYS" },
950 { "HPR_DCS", NULL, "CLK_SYS" },
951 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
952 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
953
f1c0a02f
MB		 954 { "Left Input Mux", "IN1L", "IN1L" },
955 { "Left Input Mux", "IN2L", "IN2L" },
956 { "Left Input Mux", "IN3L", "IN3L" },
957
958 { "Left Input Inverting Mux", "IN1L", "IN1L" },
959 { "Left Input Inverting Mux", "IN2L", "IN2L" },
960 { "Left Input Inverting Mux", "IN3L", "IN3L" },
961
962 { "Right Input Mux", "IN1R", "IN1R" },
963 { "Right Input Mux", "IN2R", "IN2R" },
964 { "Right Input Mux", "IN3R", "IN3R" },
965
966 { "Right Input Inverting Mux", "IN1R", "IN1R" },
967 { "Right Input Inverting Mux", "IN2R", "IN2R" },
968 { "Right Input Inverting Mux", "IN3R", "IN3R" },
969
970 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
971 { "Left Input Mode Mux", "Differential Line",
972 "Left Input Mux" },
973 { "Left Input Mode Mux", "Differential Line",
974 "Left Input Inverting Mux" },
975 { "Left Input Mode Mux", "Differential Mic",
976 "Left Input Mux" },
977 { "Left Input Mode Mux", "Differential Mic",
978 "Left Input Inverting Mux" },
979
980 { "Right Input Mode Mux", "Single-Ended",
981 "Right Input Inverting Mux" },
982 { "Right Input Mode Mux", "Differential Line",
983 "Right Input Mux" },
984 { "Right Input Mode Mux", "Differential Line",
985 "Right Input Inverting Mux" },
986 { "Right Input Mode Mux", "Differential Mic",
987 "Right Input Mux" },
988 { "Right Input Mode Mux", "Differential Mic",
989 "Right Input Inverting Mux" },
990
991 { "Left Input PGA", NULL, "Left Input Mode Mux" },
992 { "Right Input PGA", NULL, "Right Input Mode Mux" },
993
97945c46
SW		 994 { "Left ADC Input", "ADC", "Left Input PGA" },
995 { "Left ADC Input", "DMIC", "DMICDAT" },
996 { "Right ADC Input", "ADC", "Right Input PGA" },
997 { "Right ADC Input", "DMIC", "DMICDAT" },
998
1e113bf9
MB		 999 { "Left Capture Mux", "Left", "ADCL" },
1000 { "Left Capture Mux", "Right", "ADCR" },
1001
1002 { "Right Capture Mux", "Left", "ADCL" },
1003 { "Right Capture Mux", "Right", "ADCR" },
1004
1005 { "AIFTXL", NULL, "Left Capture Mux" },
1006 { "AIFTXR", NULL, "Right Capture Mux" },
1007
97945c46 1008 { "ADCL", NULL, "Left ADC Input" },
c2aef4ff 1009 { "ADCL", NULL, "CLK_DSP" },
97945c46 1010 { "ADCR", NULL, "Right ADC Input" },
c2aef4ff
MB		 1011 { "ADCR", NULL, "CLK_DSP" },
1012
1e113bf9
MB		 1013 { "Left Playback Mux", "Left", "AIFRXL" },
1014 { "Left Playback Mux", "Right", "AIFRXR" },
1015
1016 { "Right Playback Mux", "Left", "AIFRXL" },
1017 { "Right Playback Mux", "Right", "AIFRXR" },
1018
291ce18c
MB		 1019 { "DACL Sidetone", "Left", "ADCL" },
1020 { "DACL Sidetone", "Right", "ADCR" },
1021 { "DACR Sidetone", "Left", "ADCL" },
1022 { "DACR Sidetone", "Right", "ADCR" },
1023
1e113bf9 1024 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1025 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1026 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1027
1028 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1029 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1030 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1031
1032 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1033 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1034 { "Left Output Mixer", "DACL Switch", "DACL" },
1035 { "Left Output Mixer", "DACR Switch", "DACR" },
1036
1037 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1038 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1039 { "Right Output Mixer", "DACL Switch", "DACL" },
1040 { "Right Output Mixer", "DACR Switch", "DACR" },
1041
1042 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1043 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1044 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1045 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1046
1047 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1048 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1049 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1050 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1051
1052 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1053 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1054
1055 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1056 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1057
1058 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1059 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1060
1b877cb5
DL		 1061 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1062 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1063 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1064 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1065 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1066 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1067 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1068 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1069
c5b6a9fe
MB		 1070 { "HPL_DCS", NULL, "DCS Master" },
1071 { "HPR_DCS", NULL, "DCS Master" },
1072 { "LINEOUTL_DCS", NULL, "DCS Master" },
1073 { "LINEOUTR_DCS", NULL, "DCS Master" },
1074
13a9983e
MB		 1075 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1076 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1077 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1078 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1079
1080 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1081 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1082 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1083 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1084
1085 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1086 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1087 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1088 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1089
1090 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1091 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1092 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1093 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1094
1095 { "LOP", NULL, "Left Speaker PGA" },
1096 { "LON", NULL, "Left Speaker PGA" },
1097
1098 { "ROP", NULL, "Right Speaker PGA" },
1099 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 1100
1101 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1102 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1103 { "Left Line Output PGA", NULL, "Charge Pump" },
1104 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1105};
1106
f1c0a02f
MB		 1107static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1108 enum snd_soc_bias_level level)
1109{
f1c0a02f
MB		 1110 switch (level) {
1111 case SND_SOC_BIAS_ON:
66daaa59 1112 break;
22f226dd 1113
f1c0a02f 1114 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1115 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1116 WM8903_VMID_RES_MASK,
1117 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1118 break;
1119
1120 case SND_SOC_BIAS_STANDBY:
ce6120cc 1121 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1122 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1123 WM8903_POBCTRL | WM8903_ISEL_MASK |
1124 WM8903_STARTUP_BIAS_ENA |
1125 WM8903_BIAS_ENA,
1126 WM8903_POBCTRL |
1127 (2 << WM8903_ISEL_SHIFT) |
1128 WM8903_STARTUP_BIAS_ENA);
1129
1130 snd_soc_update_bits(codec,
1131 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1132 WM8903_SPK_DISCHARGE,
1133 WM8903_SPK_DISCHARGE);
1134
1135 msleep(33);
1136
1137 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1138 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1139 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1140
1141 snd_soc_update_bits(codec,
1142 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1143 WM8903_SPK_DISCHARGE, 0);
1144
1145 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1146 WM8903_VMID_TIE_ENA |
1147 WM8903_BUFIO_ENA |
1148 WM8903_VMID_IO_ENA |
1149 WM8903_VMID_SOFT_MASK |
1150 WM8903_VMID_RES_MASK |
1151 WM8903_VMID_BUF_ENA,
1152 WM8903_VMID_TIE_ENA |
1153 WM8903_BUFIO_ENA |
1154 WM8903_VMID_IO_ENA |
1155 (2 << WM8903_VMID_SOFT_SHIFT) |
1156 WM8903_VMID_RES_250K |
1157 WM8903_VMID_BUF_ENA);
1158
1159 msleep(129);
1160
1161 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1162 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1163 0);
1164
1165 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1166 WM8903_VMID_SOFT_MASK, 0);
1167
1168 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1169 WM8903_VMID_RES_MASK,
1170 WM8903_VMID_RES_50K);
1171
1172 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1173 WM8903_BIAS_ENA | WM8903_POBCTRL,
1174 WM8903_BIAS_ENA);
f1c0a02f 1175
f1c0a02f
MB		 1176 /* By default no bypass paths are enabled so
1177 * enable Class W support.
1178 */
f0fba2ad 1179 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1180 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1181 WM8903_CP_DYN_FREQ |
1182 WM8903_CP_DYN_V,
1183 WM8903_CP_DYN_FREQ |
1184 WM8903_CP_DYN_V);
f1c0a02f
MB		 1185 }
1186
66daaa59
MB		 1187 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1188 WM8903_VMID_RES_MASK,
1189 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1190 break;
1191
1192 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1193 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1194 WM8903_BIAS_ENA, 0);
1195
1196 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1197 WM8903_VMID_SOFT_MASK,
1198 2 << WM8903_VMID_SOFT_SHIFT);
1199
1200 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1201 WM8903_VMID_BUF_ENA, 0);
1202
1203 msleep(290);
1204
1205 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1206 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1207 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1208 WM8903_VMID_SOFT_MASK |
1209 WM8903_VMID_BUF_ENA, 0);
1210
1211 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1212 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1213 break;
1214 }
1215
ce6120cc 1216 codec->dapm.bias_level = level;
f1c0a02f
MB		 1217
1218 return 0;
1219}
1220
1221static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1222 int clk_id, unsigned int freq, int dir)
1223{
1224 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1225 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1226
1227 wm8903->sysclk = freq;
1228
1229 return 0;
1230}
1231
1232static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1233 unsigned int fmt)
1234{
1235 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1236 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1237
1238 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1239 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1240
1241 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1242 case SND_SOC_DAIFMT_CBS_CFS:
1243 break;
1244 case SND_SOC_DAIFMT_CBS_CFM:
1245 aif1 |= WM8903_LRCLK_DIR;
1246 break;
1247 case SND_SOC_DAIFMT_CBM_CFM:
1248 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1249 break;
1250 case SND_SOC_DAIFMT_CBM_CFS:
1251 aif1 |= WM8903_BCLK_DIR;
1252 break;
1253 default:
1254 return -EINVAL;
1255 }
1256
1257 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1258 case SND_SOC_DAIFMT_DSP_A:
1259 aif1 |= 0x3;
1260 break;
1261 case SND_SOC_DAIFMT_DSP_B:
1262 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1263 break;
1264 case SND_SOC_DAIFMT_I2S:
1265 aif1 |= 0x2;
1266 break;
1267 case SND_SOC_DAIFMT_RIGHT_J:
1268 aif1 |= 0x1;
1269 break;
1270 case SND_SOC_DAIFMT_LEFT_J:
1271 break;
1272 default:
1273 return -EINVAL;
1274 }
1275
1276 /* Clock inversion */
1277 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1278 case SND_SOC_DAIFMT_DSP_A:
1279 case SND_SOC_DAIFMT_DSP_B:
1280 /* frame inversion not valid for DSP modes */
1281 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1282 case SND_SOC_DAIFMT_NB_NF:
1283 break;
1284 case SND_SOC_DAIFMT_IB_NF:
1285 aif1 |= WM8903_AIF_BCLK_INV;
1286 break;
1287 default:
1288 return -EINVAL;
1289 }
1290 break;
1291 case SND_SOC_DAIFMT_I2S:
1292 case SND_SOC_DAIFMT_RIGHT_J:
1293 case SND_SOC_DAIFMT_LEFT_J:
1294 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1295 case SND_SOC_DAIFMT_NB_NF:
1296 break;
1297 case SND_SOC_DAIFMT_IB_IF:
1298 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1299 break;
1300 case SND_SOC_DAIFMT_IB_NF:
1301 aif1 |= WM8903_AIF_BCLK_INV;
1302 break;
1303 case SND_SOC_DAIFMT_NB_IF:
1304 aif1 |= WM8903_AIF_LRCLK_INV;
1305 break;
1306 default:
1307 return -EINVAL;
1308 }
1309 break;
1310 default:
1311 return -EINVAL;
1312 }
1313
8d50e447 1314 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1315
1316 return 0;
1317}
1318
1319static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1320{
1321 struct snd_soc_codec *codec = codec_dai->codec;
1322 u16 reg;
1323
8d50e447 1324 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1325
1326 if (mute)
1327 reg |= WM8903_DAC_MUTE;
1328 else
1329 reg &= ~WM8903_DAC_MUTE;
1330
8d50e447 1331 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1332
1333 return 0;
1334}
1335
1336/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1337 * for optimal performance so we list the lower rates first and match
1338 * on the last match we find. */
1339static struct {
1340 int div;
1341 int rate;
1342 int mode;
1343 int mclk_div;
1344} clk_sys_ratios[] = {
1345 { 64, 0x0, 0x0, 1 },
1346 { 68, 0x0, 0x1, 1 },
1347 { 125, 0x0, 0x2, 1 },
1348 { 128, 0x1, 0x0, 1 },
1349 { 136, 0x1, 0x1, 1 },
1350 { 192, 0x2, 0x0, 1 },
1351 { 204, 0x2, 0x1, 1 },
1352
1353 { 64, 0x0, 0x0, 2 },
1354 { 68, 0x0, 0x1, 2 },
1355 { 125, 0x0, 0x2, 2 },
1356 { 128, 0x1, 0x0, 2 },
1357 { 136, 0x1, 0x1, 2 },
1358 { 192, 0x2, 0x0, 2 },
1359 { 204, 0x2, 0x1, 2 },
1360
1361 { 250, 0x2, 0x2, 1 },
1362 { 256, 0x3, 0x0, 1 },
1363 { 272, 0x3, 0x1, 1 },
1364 { 384, 0x4, 0x0, 1 },
1365 { 408, 0x4, 0x1, 1 },
1366 { 375, 0x4, 0x2, 1 },
1367 { 512, 0x5, 0x0, 1 },
1368 { 544, 0x5, 0x1, 1 },
1369 { 500, 0x5, 0x2, 1 },
1370 { 768, 0x6, 0x0, 1 },
1371 { 816, 0x6, 0x1, 1 },
1372 { 750, 0x6, 0x2, 1 },
1373 { 1024, 0x7, 0x0, 1 },
1374 { 1088, 0x7, 0x1, 1 },
1375 { 1000, 0x7, 0x2, 1 },
1376 { 1408, 0x8, 0x0, 1 },
1377 { 1496, 0x8, 0x1, 1 },
1378 { 1536, 0x9, 0x0, 1 },
1379 { 1632, 0x9, 0x1, 1 },
1380 { 1500, 0x9, 0x2, 1 },
1381
1382 { 250, 0x2, 0x2, 2 },
1383 { 256, 0x3, 0x0, 2 },
1384 { 272, 0x3, 0x1, 2 },
1385 { 384, 0x4, 0x0, 2 },
1386 { 408, 0x4, 0x1, 2 },
1387 { 375, 0x4, 0x2, 2 },
1388 { 512, 0x5, 0x0, 2 },
1389 { 544, 0x5, 0x1, 2 },
1390 { 500, 0x5, 0x2, 2 },
1391 { 768, 0x6, 0x0, 2 },
1392 { 816, 0x6, 0x1, 2 },
1393 { 750, 0x6, 0x2, 2 },
1394 { 1024, 0x7, 0x0, 2 },
1395 { 1088, 0x7, 0x1, 2 },
1396 { 1000, 0x7, 0x2, 2 },
1397 { 1408, 0x8, 0x0, 2 },
1398 { 1496, 0x8, 0x1, 2 },
1399 { 1536, 0x9, 0x0, 2 },
1400 { 1632, 0x9, 0x1, 2 },
1401 { 1500, 0x9, 0x2, 2 },
1402};
1403
1404/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1405static struct {
1406 int ratio;
1407 int div;
1408} bclk_divs[] = {
1409 { 10, 0 },
f1c0a02f
MB		 1410 { 20, 2 },
1411 { 30, 3 },
1412 { 40, 4 },
1413 { 50, 5 },
f1c0a02f
MB		 1414 { 60, 7 },
1415 { 80, 8 },
1416 { 100, 9 },
f1c0a02f
MB		 1417 { 120, 11 },
1418 { 160, 12 },
1419 { 200, 13 },
1420 { 220, 14 },
1421 { 240, 15 },
f1c0a02f
MB		 1422 { 300, 17 },
1423 { 320, 18 },
1424 { 440, 19 },
1425 { 480, 20 },
1426};
1427
1428/* Sample rates for DSP */
1429static struct {
1430 int rate;
1431 int value;
1432} sample_rates[] = {
1433 { 8000, 0 },
1434 { 11025, 1 },
1435 { 12000, 2 },
1436 { 16000, 3 },
1437 { 22050, 4 },
1438 { 24000, 5 },
1439 { 32000, 6 },
1440 { 44100, 7 },
1441 { 48000, 8 },
1442 { 88200, 9 },
1443 { 96000, 10 },
1444 { 0, 0 },
1445};
1446
f1c0a02f 1447static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1448 struct snd_pcm_hw_params *params,
1449 struct snd_soc_dai *dai)
f1c0a02f
MB		 1450{
1451 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1452 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1453 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1454 int fs = params_rate(params);
1455 int bclk;
1456 int bclk_div;
1457 int i;
1458 int dsp_config;
1459 int clk_config;
1460 int best_val;
1461 int cur_val;
1462 int clk_sys;
1463
8d50e447
MB		 1464 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1465 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1466 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1467 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1468 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1469 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1470
9e79261f
MB		 1471 /* Enable sloping stopband filter for low sample rates */
1472 if (fs <= 24000)
1473 dac_digital1 |= WM8903_DAC_SB_FILT;
1474 else
1475 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1476
f1c0a02f
MB		 1477 /* Configure sample rate logic for DSP - choose nearest rate */
1478 dsp_config = 0;
1479 best_val = abs(sample_rates[dsp_config].rate - fs);
1480 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1481 cur_val = abs(sample_rates[i].rate - fs);
1482 if (cur_val <= best_val) {
1483 dsp_config = i;
1484 best_val = cur_val;
1485 }
1486 }
1487
f0fba2ad 1488 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1489 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1490 clock1 |= sample_rates[dsp_config].value;
1491
1492 aif1 &= ~WM8903_AIF_WL_MASK;
1493 bclk = 2 * fs;
1494 switch (params_format(params)) {
1495 case SNDRV_PCM_FORMAT_S16_LE:
1496 bclk *= 16;
1497 break;
1498 case SNDRV_PCM_FORMAT_S20_3LE:
1499 bclk *= 20;
1500 aif1 |= 0x4;
1501 break;
1502 case SNDRV_PCM_FORMAT_S24_LE:
1503 bclk *= 24;
1504 aif1 |= 0x8;
1505 break;
1506 case SNDRV_PCM_FORMAT_S32_LE:
1507 bclk *= 32;
1508 aif1 |= 0xc;
1509 break;
1510 default:
1511 return -EINVAL;
1512 }
1513
f0fba2ad 1514 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1515 wm8903->sysclk, fs);
1516
1517 /* We may not have an MCLK which allows us to generate exactly
1518 * the clock we want, particularly with USB derived inputs, so
1519 * approximate.
1520 */
1521 clk_config = 0;
1522 best_val = abs((wm8903->sysclk /
1523 (clk_sys_ratios[0].mclk_div *
1524 clk_sys_ratios[0].div)) - fs);
1525 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1526 cur_val = abs((wm8903->sysclk /
1527 (clk_sys_ratios[i].mclk_div *
1528 clk_sys_ratios[i].div)) - fs);
1529
1530 if (cur_val <= best_val) {
1531 clk_config = i;
1532 best_val = cur_val;
1533 }
1534 }
1535
1536 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1537 clock0 |= WM8903_MCLKDIV2;
1538 clk_sys = wm8903->sysclk / 2;
1539 } else {
1540 clock0 &= ~WM8903_MCLKDIV2;
1541 clk_sys = wm8903->sysclk;
1542 }
1543
1544 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1545 WM8903_CLK_SYS_MODE_MASK);
1546 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1547 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1548
f0fba2ad 1549 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1550 clk_sys_ratios[clk_config].rate,
1551 clk_sys_ratios[clk_config].mode,
1552 clk_sys_ratios[clk_config].div);
1553
f0fba2ad 1554 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1555
1556 /* We may not get quite the right frequency if using
1557 * approximate clocks so look for the closest match that is
1558 * higher than the target (we need to ensure that there enough
1559 * BCLKs to clock out the samples).
1560 */
1561 bclk_div = 0;
1562 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1563 i = 1;
1564 while (i < ARRAY_SIZE(bclk_divs)) {
1565 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1566 if (cur_val < 0) /* BCLK table is sorted */
1567 break;
1568 bclk_div = i;
1569 best_val = cur_val;
1570 i++;
1571 }
1572
1573 aif2 &= ~WM8903_BCLK_DIV_MASK;
1574 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1575
f0fba2ad 1576 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1577 bclk_divs[bclk_div].ratio / 10, bclk,
1578 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1579
1580 aif2 |= bclk_divs[bclk_div].div;
1581 aif3 |= bclk / fs;
1582
69fff9bb
MB		 1583 wm8903->fs = params_rate(params);
1584 wm8903_set_deemph(codec);
1585
8d50e447
MB		 1586 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1587 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1588 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1589 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1590 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1591 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1592
1593 return 0;
1594}
1595
7245387e
MB		 1596/**
1597 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1598 *
1599 * @codec: WM8903 codec
1600 * @jack: jack to report detection events on
1601 * @det: value to report for presence detection
1602 * @shrt: value to report for short detection
1603 *
1604 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1605 * being used to bring out signals to the processor then only platform
1606 * data configuration is needed for WM8903 and processor GPIOs should
1607 * be configured using snd_soc_jack_add_gpios() instead.
1608 *
1609 * The current threasholds for detection should be configured using
1610 * micdet_cfg in the platform data. Using this function will force on
1611 * the microphone bias for the device.
1612 */
1613int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1614 int det, int shrt)
1615{
b2c812e2 1616 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1617 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1618
1619 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1620 det, shrt);
1621
1622 /* Store the configuration */
1623 wm8903->mic_jack = jack;
1624 wm8903->mic_det = det;
1625 wm8903->mic_short = shrt;
1626
1627 /* Enable interrupts we've got a report configured for */
1628 if (det)
1629 irq_mask &= ~WM8903_MICDET_EINT;
1630 if (shrt)
1631 irq_mask &= ~WM8903_MICSHRT_EINT;
1632
1633 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1634 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1635 irq_mask);
1636
3088e3b4 1637 if (det || shrt) {
69266866
MB		 1638 /* Enable mic detection, this may not have been set through
1639 * platform data (eg, if the defaults are OK). */
1640 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1641 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1642 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1643 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1644 } else {
1645 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1646 WM8903_MICDET_ENA, 0);
1647 }
7245387e
MB		 1648
1649 return 0;
1650}
1651EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1652
8abd16a6
MB		 1653static irqreturn_t wm8903_irq(int irq, void *data)
1654{
f0fba2ad
LG		 1655 struct snd_soc_codec *codec = data;
1656 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1657 int mic_report;
1658 int int_pol;
1659 int int_val = 0;
1660 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1661
7245387e 1662 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1663
7245387e 1664 if (int_val & WM8903_WSEQ_BUSY_EINT) {
b4d06f45 1665 dev_warn(codec->dev, "Write sequencer done\n");
8abd16a6
MB		 1666 }
1667
7245387e
MB		 1668 /*
1669 * The rest is microphone jack detection. We need to manually
1670 * invert the polarity of the interrupt after each event - to
1671 * simplify the code keep track of the last state we reported
1672 * and just invert the relevant bits in both the report and
1673 * the polarity register.
1674 */
1675 mic_report = wm8903->mic_last_report;
1676 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1677
1435b940 1678#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1679 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1680 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1681#endif
2bbb5d66 1682
7245387e
MB		 1683 if (int_val & WM8903_MICSHRT_EINT) {
1684 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1685
1686 mic_report ^= wm8903->mic_short;
1687 int_pol ^= WM8903_MICSHRT_INV;
1688 }
1689
1690 if (int_val & WM8903_MICDET_EINT) {
1691 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1692
1693 mic_report ^= wm8903->mic_det;
1694 int_pol ^= WM8903_MICDET_INV;
1695
1696 msleep(wm8903->mic_delay);
1697 }
1698
1699 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1700 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1701
1702 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1703 wm8903->mic_short | wm8903->mic_det);
1704
1705 wm8903->mic_last_report = mic_report;
1706
8abd16a6
MB		 1707 return IRQ_HANDLED;
1708}
1709
f1c0a02f
MB		 1710#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1711 SNDRV_PCM_RATE_11025 | \
1712 SNDRV_PCM_RATE_16000 | \
1713 SNDRV_PCM_RATE_22050 | \
1714 SNDRV_PCM_RATE_32000 | \
1715 SNDRV_PCM_RATE_44100 | \
1716 SNDRV_PCM_RATE_48000 | \
1717 SNDRV_PCM_RATE_88200 | \
1718 SNDRV_PCM_RATE_96000)
1719
1720#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1721 SNDRV_PCM_RATE_11025 | \
1722 SNDRV_PCM_RATE_16000 | \
1723 SNDRV_PCM_RATE_22050 | \
1724 SNDRV_PCM_RATE_32000 | \
1725 SNDRV_PCM_RATE_44100 | \
1726 SNDRV_PCM_RATE_48000)
1727
1728#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1729 SNDRV_PCM_FMTBIT_S20_3LE |\
1730 SNDRV_PCM_FMTBIT_S24_LE)
1731
85e7652d 1732static const struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1733 .hw_params = wm8903_hw_params,
1734 .digital_mute = wm8903_digital_mute,
1735 .set_fmt = wm8903_set_dai_fmt,
1736 .set_sysclk = wm8903_set_dai_sysclk,
1737};
1738
f0fba2ad
LG		 1739static struct snd_soc_dai_driver wm8903_dai = {
1740 .name = "wm8903-hifi",
f1c0a02f
MB		 1741 .playback = {
1742 .stream_name = "Playback",
1743 .channels_min = 2,
1744 .channels_max = 2,
1745 .rates = WM8903_PLAYBACK_RATES,
1746 .formats = WM8903_FORMATS,
1747 },
1748 .capture = {
1749 .stream_name = "Capture",
1750 .channels_min = 2,
1751 .channels_max = 2,
1752 .rates = WM8903_CAPTURE_RATES,
1753 .formats = WM8903_FORMATS,
1754 },
6335d055 1755 .ops = &wm8903_dai_ops,
0d960e88 1756 .symmetric_rates = 1,
f1c0a02f 1757};
f1c0a02f 1758
84b315ee 1759static int wm8903_suspend(struct snd_soc_codec *codec)
f1c0a02f 1760{
f1c0a02f
MB		 1761 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1762
1763 return 0;
1764}
1765
f0fba2ad 1766static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1767{
45e96755 1768 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f 1769
45e96755 1770 snd_soc_cache_sync(codec);
f1c0a02f 1771
45e96755 1772 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1773
1774 return 0;
1775}
1776
7cfe5617
SW		 1777#ifdef CONFIG_GPIOLIB
1778static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1779{
1780 return container_of(chip, struct wm8903_priv, gpio_chip);
1781}
1782
1783static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1784{
1785 if (offset >= WM8903_NUM_GPIO)
1786 return -EINVAL;
1787
1788 return 0;
1789}
1790
1791static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1792{
1793 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1794 struct snd_soc_codec *codec = wm8903->codec;
1795 unsigned int mask, val;
1796
1797 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1798 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1799 WM8903_GP1_DIR;
1800
1801 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1802 mask, val);
1803}
1804
1805static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1806{
1807 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1808 struct snd_soc_codec *codec = wm8903->codec;
1809 int reg;
1810
1811 reg = snd_soc_read(codec, WM8903_GPIO_CONTROL_1 + offset);
1812
1813 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1814}
1815
1816static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1817 unsigned offset, int value)
1818{
1819 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1820 struct snd_soc_codec *codec = wm8903->codec;
1821 unsigned int mask, val;
1822
1823 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1824 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1825 (value << WM8903_GP2_LVL_SHIFT);
1826
1827 return snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
1828 mask, val);
1829}
1830
1831static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1832{
1833 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
1834 struct snd_soc_codec *codec = wm8903->codec;
1835
1836 snd_soc_update_bits(codec, WM8903_GPIO_CONTROL_1 + offset,
c8059930
MB		 1837 WM8903_GP1_LVL_MASK,
1838 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1839}
1840
1841static struct gpio_chip wm8903_template_chip = {
1842 .label = "wm8903",
1843 .owner = THIS_MODULE,
1844 .request = wm8903_gpio_request,
1845 .direction_input = wm8903_gpio_direction_in,
1846 .get = wm8903_gpio_get,
1847 .direction_output = wm8903_gpio_direction_out,
1848 .set = wm8903_gpio_set,
1849 .can_sleep = 1,
1850};
1851
1852static void wm8903_init_gpio(struct snd_soc_codec *codec)
1853{
1854 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1855 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1856 int ret;
1857
1858 wm8903->gpio_chip = wm8903_template_chip;
1859 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
1860 wm8903->gpio_chip.dev = codec->dev;
1861
1862 if (pdata && pdata->gpio_base)
1863 wm8903->gpio_chip.base = pdata->gpio_base;
1864 else
1865 wm8903->gpio_chip.base = -1;
1866
1867 ret = gpiochip_add(&wm8903->gpio_chip);
1868 if (ret != 0)
1869 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
1870}
1871
1872static void wm8903_free_gpio(struct snd_soc_codec *codec)
1873{
1874 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
1875 int ret;
1876
1877 ret = gpiochip_remove(&wm8903->gpio_chip);
1878 if (ret != 0)
1879 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
1880}
1881#else
1882static void wm8903_init_gpio(struct snd_soc_codec *codec)
1883{
1884}
1885
1886static void wm8903_free_gpio(struct snd_soc_codec *codec)
1887{
1888}
1889#endif
1890
f0fba2ad 1891static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1892{
f0fba2ad
LG		 1893 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1894 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1895 int ret, i;
8abd16a6 1896 int trigger, irq_pol;
f1c0a02f
MB		 1897 u16 val;
1898
7cfe5617 1899 wm8903->codec = codec;
d58d5d55 1900
8d50e447
MB		 1901 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1902 if (ret != 0) {
f0fba2ad
LG		 1903 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1904 return ret;
8d50e447
MB		 1905 }
1906
1907 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1908 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1909 dev_err(codec->dev,
d58d5d55
MB		 1910 "Device with ID register %x is not a WM8903\n", val);
1911 return -ENODEV;
f1c0a02f
MB		 1912 }
1913
8d50e447 1914 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
1d8d62d6
MB		 1915 dev_info(codec->dev, "WM8903 revision %c\n",
1916 (val & WM8903_CHIP_REV_MASK) + 'A');
f1c0a02f
MB		 1917
1918 wm8903_reset(codec);
1919
37f88e84 1920 /* Set up GPIOs and microphone detection */
73b34ead 1921 if (pdata) {
905f6952
MB		 1922 bool mic_gpio = false;
1923
73b34ead 1924 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
6f526f0a 1925 if (pdata->gpio_cfg[i] > 0x7fff)
73b34ead
MB		 1926 continue;
1927
1928 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
6f526f0a 1929 pdata->gpio_cfg[i] & 0x7fff);
905f6952
MB		 1930
1931 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
1932 >> WM8903_GP1_FN_SHIFT;
1933
1934 switch (val) {
1935 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
1936 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
1937 mic_gpio = true;
1938 break;
1939 default:
1940 break;
1941 }
73b34ead 1942 }
37f88e84
MB		 1943
1944 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1945 pdata->micdet_cfg);
1946
1947 /* Microphone detection needs the WSEQ clock */
1948 if (pdata->micdet_cfg)
1949 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1950 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1951
905f6952
MB		 1952 /* If microphone detection is enabled by pdata but
1953 * detected via IRQ then interrupts can be lost before
1954 * the machine driver has set up microphone detection
1955 * IRQs as the IRQs are clear on read. The detection
1956 * will be enabled when the machine driver configures.
1957 */
1958 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
1959
37f88e84 1960 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1961 }
8abd16a6 1962
f0fba2ad 1963 if (wm8903->irq) {
8abd16a6
MB		 1964 if (pdata && pdata->irq_active_low) {
1965 trigger = IRQF_TRIGGER_LOW;
1966 irq_pol = WM8903_IRQ_POL;
1967 } else {
1968 trigger = IRQF_TRIGGER_HIGH;
1969 irq_pol = 0;
1970 }
1971
1972 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1973 WM8903_IRQ_POL, irq_pol);
1974
f0fba2ad 1975 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1976 trigger | IRQF_ONESHOT,
f0fba2ad 1977 "wm8903", codec);
8abd16a6 1978 if (ret != 0) {
f0fba2ad 1979 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1980 ret);
f0fba2ad 1981 return ret;
8abd16a6
MB		 1982 }
1983
1984 /* Enable write sequencer interrupts */
1985 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1986 WM8903_IM_WSEQ_BUSY_EINT, 0);
1987 }
73b34ead 1988
f1c0a02f
MB		 1989 /* power on device */
1990 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1991
1992 /* Latch volume update bits */
8d50e447 1993 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1994 val |= WM8903_ADCVU;
8d50e447
MB		 1995 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1996 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1997
8d50e447 1998 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1999 val |= WM8903_DACVU;
8d50e447
MB		 2000 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
2001 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 2002
8d50e447 2003 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 2004 val |= WM8903_HPOUTVU;
8d50e447
MB		 2005 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
2006 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 2007
8d50e447 2008 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 2009 val |= WM8903_LINEOUTVU;
8d50e447
MB		 2010 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
2011 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 2012
8d50e447 2013 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 2014 val |= WM8903_SPKVU;
8d50e447
MB		 2015 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
2016 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 2017
2018 /* Enable DAC soft mute by default */
e12adab0
MB		 2019 snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
2020 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2021 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
f1c0a02f 2022
7cfe5617
SW		 2023 wm8903_init_gpio(codec);
2024
f1c0a02f
MB		 2025 return ret;
2026}
2027
f0fba2ad
LG		 2028/* power down chip */
2029static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 2030{
f99847a6
SW		 2031 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
2032
7cfe5617 2033 wm8903_free_gpio(codec);
f0fba2ad 2034 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f99847a6
SW		 2035 if (wm8903->irq)
2036 free_irq(wm8903->irq, codec);
2037
f0fba2ad
LG		 2038 return 0;
2039}
f1c0a02f 2040
f0fba2ad
LG		 2041static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
2042 .probe = wm8903_probe,
2043 .remove = wm8903_remove,
2044 .suspend = wm8903_suspend,
2045 .resume = wm8903_resume,
2046 .set_bias_level = wm8903_set_bias_level,
2047 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
2048 .reg_word_size = sizeof(u16),
2049 .reg_cache_default = wm8903_reg_defaults,
2050 .volatile_register = wm8903_volatile_register,
c5b6a9fe 2051 .seq_notifier = wm8903_seq_notifier,
f4a10837
MB		 2052 .controls = wm8903_snd_controls,
2053 .num_controls = ARRAY_SIZE(wm8903_snd_controls),
ecd01512
MB		 2054 .dapm_widgets = wm8903_dapm_widgets,
2055 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
2056 .dapm_routes = wm8903_intercon,
2057 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 2058};
f1c0a02f 2059
f0fba2ad
LG		 2060static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
2061 const struct i2c_device_id *id)
2062{
2063 struct wm8903_priv *wm8903;
2064 int ret;
f1c0a02f 2065
2950cd22
MB		 2066 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv),
2067 GFP_KERNEL);
f0fba2ad
LG		 2068 if (wm8903 == NULL)
2069 return -ENOMEM;
8abd16a6 2070
f0fba2ad 2071 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 2072 wm8903->irq = i2c->irq;
d58d5d55 2073
f0fba2ad
LG		 2074 ret = snd_soc_register_codec(&i2c->dev,
2075 &soc_codec_dev_wm8903, &wm8903_dai, 1);
2950cd22 2076
f0fba2ad
LG		 2077 return ret;
2078}
f1c0a02f 2079
f0fba2ad
LG		 2080static __devexit int wm8903_i2c_remove(struct i2c_client *client)
2081{
2082 snd_soc_unregister_codec(&client->dev);
f1c0a02f
MB		 2083 return 0;
2084}
2085
f1c0a02f 2086static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2087 { "wm8903", 0 },
2088 { }
f1c0a02f
MB		 2089};
2090MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2091
2092static struct i2c_driver wm8903_i2c_driver = {
2093 .driver = {
4b592c91 2094 .name = "wm8903",
f1c0a02f
MB		 2095 .owner = THIS_MODULE,
2096 },
f0fba2ad
LG		 2097 .probe = wm8903_i2c_probe,
2098 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 2099 .id_table = wm8903_i2c_id,
2100};
2101
f0fba2ad 2102static int __init wm8903_modinit(void)
f1c0a02f 2103{
f1c0a02f 2104 int ret = 0;
f0fba2ad
LG		 2105 ret = i2c_add_driver(&wm8903_i2c_driver);
2106 if (ret != 0) {
2107 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
2108 ret);
f1c0a02f 2109 }
f1c0a02f 2110 return ret;
64089b84
MB		 2111}
2112module_init(wm8903_modinit);
2113
2114static void __exit wm8903_exit(void)
2115{
d58d5d55 2116 i2c_del_driver(&wm8903_i2c_driver);
64089b84
MB		 2117}
2118module_exit(wm8903_exit);
2119
f1c0a02f
MB		 2120MODULE_DESCRIPTION("ASoC WM8903 driver");
2121MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2122MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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