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ASoC: soc-cache: Apply the cache_bypass option
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
4 * Copyright 2008 Wolfson Microelectronics
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * TODO:
13 * - TDM mode configuration.
f1c0a02f 14 * - Digital microphone support.
f1c0a02f
MB		 15 */
16
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/init.h>
8abd16a6 20#include <linux/completion.h>
f1c0a02f
MB		 21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/platform_device.h>
5a0e3ad6 25#include <linux/slab.h>
f1c0a02f 26#include <sound/core.h>
7245387e 27#include <sound/jack.h>
f1c0a02f
MB		 28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/tlv.h>
31#include <sound/soc.h>
f1c0a02f 32#include <sound/initval.h>
8abd16a6 33#include <sound/wm8903.h>
2bbb5d66 34#include <trace/events/asoc.h>
f1c0a02f
MB		 35
36#include "wm8903.h"
37
f1c0a02f
MB		 38/* Register defaults at reset */
39static u16 wm8903_reg_defaults[] = {
40 0x8903, /* R0 - SW Reset and ID */
41 0x0000, /* R1 - Revision Number */
42 0x0000, /* R2 */
43 0x0000, /* R3 */
44 0x0018, /* R4 - Bias Control 0 */
45 0x0000, /* R5 - VMID Control 0 */
46 0x0000, /* R6 - Mic Bias Control 0 */
47 0x0000, /* R7 */
48 0x0001, /* R8 - Analogue DAC 0 */
49 0x0000, /* R9 */
50 0x0001, /* R10 - Analogue ADC 0 */
51 0x0000, /* R11 */
52 0x0000, /* R12 - Power Management 0 */
53 0x0000, /* R13 - Power Management 1 */
54 0x0000, /* R14 - Power Management 2 */
55 0x0000, /* R15 - Power Management 3 */
56 0x0000, /* R16 - Power Management 4 */
57 0x0000, /* R17 - Power Management 5 */
58 0x0000, /* R18 - Power Management 6 */
59 0x0000, /* R19 */
60 0x0400, /* R20 - Clock Rates 0 */
61 0x0D07, /* R21 - Clock Rates 1 */
62 0x0000, /* R22 - Clock Rates 2 */
63 0x0000, /* R23 */
64 0x0050, /* R24 - Audio Interface 0 */
65 0x0242, /* R25 - Audio Interface 1 */
66 0x0008, /* R26 - Audio Interface 2 */
67 0x0022, /* R27 - Audio Interface 3 */
68 0x0000, /* R28 */
69 0x0000, /* R29 */
70 0x00C0, /* R30 - DAC Digital Volume Left */
71 0x00C0, /* R31 - DAC Digital Volume Right */
72 0x0000, /* R32 - DAC Digital 0 */
73 0x0000, /* R33 - DAC Digital 1 */
74 0x0000, /* R34 */
75 0x0000, /* R35 */
76 0x00C0, /* R36 - ADC Digital Volume Left */
77 0x00C0, /* R37 - ADC Digital Volume Right */
78 0x0000, /* R38 - ADC Digital 0 */
79 0x0073, /* R39 - Digital Microphone 0 */
80 0x09BF, /* R40 - DRC 0 */
81 0x3241, /* R41 - DRC 1 */
82 0x0020, /* R42 - DRC 2 */
83 0x0000, /* R43 - DRC 3 */
84 0x0085, /* R44 - Analogue Left Input 0 */
85 0x0085, /* R45 - Analogue Right Input 0 */
86 0x0044, /* R46 - Analogue Left Input 1 */
87 0x0044, /* R47 - Analogue Right Input 1 */
88 0x0000, /* R48 */
89 0x0000, /* R49 */
90 0x0008, /* R50 - Analogue Left Mix 0 */
91 0x0004, /* R51 - Analogue Right Mix 0 */
92 0x0000, /* R52 - Analogue Spk Mix Left 0 */
93 0x0000, /* R53 - Analogue Spk Mix Left 1 */
94 0x0000, /* R54 - Analogue Spk Mix Right 0 */
95 0x0000, /* R55 - Analogue Spk Mix Right 1 */
96 0x0000, /* R56 */
97 0x002D, /* R57 - Analogue OUT1 Left */
98 0x002D, /* R58 - Analogue OUT1 Right */
99 0x0039, /* R59 - Analogue OUT2 Left */
100 0x0039, /* R60 - Analogue OUT2 Right */
101 0x0100, /* R61 */
102 0x0139, /* R62 - Analogue OUT3 Left */
103 0x0139, /* R63 - Analogue OUT3 Right */
104 0x0000, /* R64 */
105 0x0000, /* R65 - Analogue SPK Output Control 0 */
106 0x0000, /* R66 */
107 0x0010, /* R67 - DC Servo 0 */
108 0x0100, /* R68 */
109 0x00A4, /* R69 - DC Servo 2 */
110 0x0807, /* R70 */
111 0x0000, /* R71 */
112 0x0000, /* R72 */
113 0x0000, /* R73 */
114 0x0000, /* R74 */
115 0x0000, /* R75 */
116 0x0000, /* R76 */
117 0x0000, /* R77 */
118 0x0000, /* R78 */
119 0x000E, /* R79 */
120 0x0000, /* R80 */
121 0x0000, /* R81 */
122 0x0000, /* R82 */
123 0x0000, /* R83 */
124 0x0000, /* R84 */
125 0x0000, /* R85 */
126 0x0000, /* R86 */
127 0x0006, /* R87 */
128 0x0000, /* R88 */
129 0x0000, /* R89 */
130 0x0000, /* R90 - Analogue HP 0 */
131 0x0060, /* R91 */
132 0x0000, /* R92 */
133 0x0000, /* R93 */
134 0x0000, /* R94 - Analogue Lineout 0 */
135 0x0060, /* R95 */
136 0x0000, /* R96 */
137 0x0000, /* R97 */
138 0x0000, /* R98 - Charge Pump 0 */
139 0x1F25, /* R99 */
140 0x2B19, /* R100 */
141 0x01C0, /* R101 */
142 0x01EF, /* R102 */
143 0x2B00, /* R103 */
144 0x0000, /* R104 - Class W 0 */
145 0x01C0, /* R105 */
146 0x1C10, /* R106 */
147 0x0000, /* R107 */
148 0x0000, /* R108 - Write Sequencer 0 */
149 0x0000, /* R109 - Write Sequencer 1 */
150 0x0000, /* R110 - Write Sequencer 2 */
151 0x0000, /* R111 - Write Sequencer 3 */
152 0x0000, /* R112 - Write Sequencer 4 */
153 0x0000, /* R113 */
154 0x0000, /* R114 - Control Interface */
155 0x0000, /* R115 */
156 0x00A8, /* R116 - GPIO Control 1 */
157 0x00A8, /* R117 - GPIO Control 2 */
158 0x00A8, /* R118 - GPIO Control 3 */
159 0x0220, /* R119 - GPIO Control 4 */
160 0x01A0, /* R120 - GPIO Control 5 */
161 0x0000, /* R121 - Interrupt Status 1 */
162 0xFFFF, /* R122 - Interrupt Status 1 Mask */
163 0x0000, /* R123 - Interrupt Polarity 1 */
164 0x0000, /* R124 */
165 0x0003, /* R125 */
166 0x0000, /* R126 - Interrupt Control */
167 0x0000, /* R127 */
168 0x0005, /* R128 */
169 0x0000, /* R129 - Control Interface Test 1 */
170 0x0000, /* R130 */
171 0x0000, /* R131 */
172 0x0000, /* R132 */
173 0x0000, /* R133 */
174 0x0000, /* R134 */
175 0x03FF, /* R135 */
176 0x0007, /* R136 */
177 0x0040, /* R137 */
178 0x0000, /* R138 */
179 0x0000, /* R139 */
180 0x0000, /* R140 */
181 0x0000, /* R141 */
182 0x0000, /* R142 */
183 0x0000, /* R143 */
184 0x0000, /* R144 */
185 0x0000, /* R145 */
186 0x0000, /* R146 */
187 0x0000, /* R147 */
188 0x4000, /* R148 */
189 0x6810, /* R149 - Charge Pump Test 1 */
190 0x0004, /* R150 */
191 0x0000, /* R151 */
192 0x0000, /* R152 */
193 0x0000, /* R153 */
194 0x0000, /* R154 */
195 0x0000, /* R155 */
196 0x0000, /* R156 */
197 0x0000, /* R157 */
198 0x0000, /* R158 */
199 0x0000, /* R159 */
200 0x0000, /* R160 */
201 0x0000, /* R161 */
202 0x0000, /* R162 */
203 0x0000, /* R163 */
204 0x0028, /* R164 - Clock Rate Test 4 */
205 0x0004, /* R165 */
206 0x0000, /* R166 */
207 0x0060, /* R167 */
208 0x0000, /* R168 */
209 0x0000, /* R169 */
210 0x0000, /* R170 */
211 0x0000, /* R171 */
212 0x0000, /* R172 - Analogue Output Bias 0 */
213};
214
d58d5d55 215struct wm8903_priv {
f0fba2ad 216
d58d5d55 217 int sysclk;
f0fba2ad 218 int irq;
d58d5d55 219
69fff9bb
MB		 220 int fs;
221 int deemph;
222
f2c1fe09 223 /* Reference count */
d58d5d55 224 int class_w_users;
d58d5d55 225
8abd16a6
MB		 226 struct completion wseq;
227
7245387e
MB		 228 struct snd_soc_jack *mic_jack;
229 int mic_det;
230 int mic_short;
231 int mic_last_report;
232 int mic_delay;
d58d5d55
MB		 233};
234
d4754ec9 235static int wm8903_volatile_register(struct snd_soc_codec *codec, unsigned int reg)
f1c0a02f
MB		 236{
237 switch (reg) {
238 case WM8903_SW_RESET_AND_ID:
239 case WM8903_REVISION_NUMBER:
240 case WM8903_INTERRUPT_STATUS_1:
241 case WM8903_WRITE_SEQUENCER_4:
8d50e447 242 return 1;
f1c0a02f
MB		 243
244 default:
f1c0a02f 245 return 0;
8d50e447 246 }
f1c0a02f
MB		 247}
248
249static int wm8903_run_sequence(struct snd_soc_codec *codec, unsigned int start)
250{
251 u16 reg[5];
b2c812e2 252 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 253
254 BUG_ON(start > 48);
255
37f88e84 256 /* Enable the sequencer if it's not already on */
8d50e447 257 reg[0] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_0);
37f88e84
MB		 258 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0,
259 reg[0] | WM8903_WSEQ_ENA);
f1c0a02f 260
f0fba2ad 261 dev_dbg(codec->dev, "Starting sequence at %d\n", start);
f1c0a02f 262
8d50e447 263 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_3,
f1c0a02f
MB		 264 start | WM8903_WSEQ_START);
265
266 /* Wait for it to complete. If we have the interrupt wired up then
8abd16a6 267 * that will break us out of the poll early.
f1c0a02f
MB		 268 */
269 do {
8abd16a6
MB		 270 wait_for_completion_timeout(&wm8903->wseq,
271 msecs_to_jiffies(10));
f1c0a02f 272
8d50e447 273 reg[4] = snd_soc_read(codec, WM8903_WRITE_SEQUENCER_4);
f1c0a02f
MB		 274 } while (reg[4] & WM8903_WSEQ_BUSY);
275
f0fba2ad 276 dev_dbg(codec->dev, "Sequence complete\n");
f1c0a02f 277
37f88e84
MB		 278 /* Disable the sequencer again if we enabled it */
279 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, reg[0]);
f1c0a02f
MB		 280
281 return 0;
282}
283
284static void wm8903_sync_reg_cache(struct snd_soc_codec *codec, u16 *cache)
285{
286 int i;
287
288 /* There really ought to be something better we can do here :/ */
289 for (i = 0; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
8d50e447 290 cache[i] = codec->hw_read(codec, i);
f1c0a02f
MB		 291}
292
293static void wm8903_reset(struct snd_soc_codec *codec)
294{
8d50e447 295 snd_soc_write(codec, WM8903_SW_RESET_AND_ID, 0);
d58d5d55
MB		 296 memcpy(codec->reg_cache, wm8903_reg_defaults,
297 sizeof(wm8903_reg_defaults));
f1c0a02f
MB		 298}
299
300#define WM8903_OUTPUT_SHORT 0x8
301#define WM8903_OUTPUT_OUT 0x4
302#define WM8903_OUTPUT_INT 0x2
303#define WM8903_OUTPUT_IN 0x1
304
42768a12
MB		 305static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
306 struct snd_kcontrol *kcontrol, int event)
307{
308 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
309 mdelay(4);
310
311 return 0;
312}
313
f1c0a02f
MB		 314/*
315 * Event for headphone and line out amplifier power changes. Special
316 * power up/down sequences are required in order to maximise pop/click
317 * performance.
318 */
319static int wm8903_output_event(struct snd_soc_dapm_widget *w,
320 struct snd_kcontrol *kcontrol, int event)
321{
322 struct snd_soc_codec *codec = w->codec;
f1c0a02f 323 u16 val;
0bc286e2 324 u16 reg;
d7d5c547
MB		 325 u16 dcs_reg;
326 u16 dcs_bit;
0bc286e2 327 int shift;
f1c0a02f
MB		 328
329 switch (w->reg) {
330 case WM8903_POWER_MANAGEMENT_2:
331 reg = WM8903_ANALOGUE_HP_0;
d7d5c547 332 dcs_bit = 0 + w->shift;
f1c0a02f
MB		 333 break;
334 case WM8903_POWER_MANAGEMENT_3:
335 reg = WM8903_ANALOGUE_LINEOUT_0;
d7d5c547 336 dcs_bit = 2 + w->shift;
f1c0a02f
MB		 337 break;
338 default:
339 BUG();
1e297a19 340 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 341 }
342
343 switch (w->shift) {
344 case 0:
345 shift = 0;
346 break;
347 case 1:
348 shift = 4;
349 break;
350 default:
351 BUG();
1e297a19 352 return -EINVAL; /* Spurious warning from some compilers */
f1c0a02f
MB		 353 }
354
355 if (event & SND_SOC_DAPM_PRE_PMU) {
8d50e447 356 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 357
358 /* Short the output */
359 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 360 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 361 }
362
363 if (event & SND_SOC_DAPM_POST_PMU) {
8d50e447 364 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 365
366 val |= (WM8903_OUTPUT_IN << shift);
8d50e447 367 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 368
369 val |= (WM8903_OUTPUT_INT << shift);
8d50e447 370 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 371
372 /* Turn on the output ENA_OUTP */
373 val |= (WM8903_OUTPUT_OUT << shift);
8d50e447 374 snd_soc_write(codec, reg, val);
f1c0a02f 375
d7d5c547 376 /* Enable the DC servo */
8d50e447 377 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 378 dcs_reg |= dcs_bit;
8d50e447 379 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 380
f1c0a02f
MB		 381 /* Remove the short */
382 val |= (WM8903_OUTPUT_SHORT << shift);
8d50e447 383 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 384 }
385
386 if (event & SND_SOC_DAPM_PRE_PMD) {
8d50e447 387 val = snd_soc_read(codec, reg);
f1c0a02f
MB		 388
389 /* Short the output */
390 val &= ~(WM8903_OUTPUT_SHORT << shift);
8d50e447 391 snd_soc_write(codec, reg, val);
f1c0a02f 392
d7d5c547 393 /* Disable the DC servo */
8d50e447 394 dcs_reg = snd_soc_read(codec, WM8903_DC_SERVO_0);
d7d5c547 395 dcs_reg &= ~dcs_bit;
8d50e447 396 snd_soc_write(codec, WM8903_DC_SERVO_0, dcs_reg);
d7d5c547 397
f1c0a02f
MB		 398 /* Then disable the intermediate and output stages */
399 val &= ~((WM8903_OUTPUT_OUT | WM8903_OUTPUT_INT |
400 WM8903_OUTPUT_IN) << shift);
8d50e447 401 snd_soc_write(codec, reg, val);
f1c0a02f
MB		 402 }
403
f1c0a02f
MB		 404 return 0;
405}
406
407/*
408 * When used with DAC outputs only the WM8903 charge pump supports
409 * operation in class W mode, providing very low power consumption
410 * when used with digital sources. Enable and disable this mode
411 * automatically depending on the mixer configuration.
412 *
413 * All the relevant controls are simple switches.
414 */
415static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
416 struct snd_ctl_elem_value *ucontrol)
417{
418 struct snd_soc_dapm_widget *widget = snd_kcontrol_chip(kcontrol);
419 struct snd_soc_codec *codec = widget->codec;
b2c812e2 420 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 421 u16 reg;
422 int ret;
423
8d50e447 424 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 425
426 /* Turn it off if we're about to enable bypass */
427 if (ucontrol->value.integer.value[0]) {
428 if (wm8903->class_w_users == 0) {
f0fba2ad 429 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 430 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 431 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
432 }
433 wm8903->class_w_users++;
434 }
435
436 /* Implement the change */
437 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
438
439 /* If we've just disabled the last bypass path turn Class W on */
440 if (!ucontrol->value.integer.value[0]) {
441 if (wm8903->class_w_users == 1) {
f0fba2ad 442 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 443 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 444 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
445 }
446 wm8903->class_w_users--;
447 }
448
f0fba2ad 449 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 450 wm8903->class_w_users);
451
452 return ret;
453}
454
455#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
456{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
457 .info = snd_soc_info_volsw, \
458 .get = snd_soc_dapm_get_volsw, .put = wm8903_class_w_put, \
459 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
460
461
69fff9bb
MB		 462static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
463
464static int wm8903_set_deemph(struct snd_soc_codec *codec)
465{
466 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
467 int val, i, best;
468
469 /* If we're using deemphasis select the nearest available sample
470 * rate.
471 */
472 if (wm8903->deemph) {
473 best = 1;
474 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
475 if (abs(wm8903_deemph[i] - wm8903->fs) <
476 abs(wm8903_deemph[best] - wm8903->fs))
477 best = i;
478 }
479
480 val = best << WM8903_DEEMPH_SHIFT;
481 } else {
482 best = 0;
483 val = 0;
484 }
485
486 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
487 best, wm8903_deemph[best]);
488
489 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
490 WM8903_DEEMPH_MASK, val);
491}
492
493static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
494 struct snd_ctl_elem_value *ucontrol)
495{
496 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
497 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
498
499 ucontrol->value.enumerated.item[0] = wm8903->deemph;
500
501 return 0;
502}
503
504static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
505 struct snd_ctl_elem_value *ucontrol)
506{
507 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
508 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
509 int deemph = ucontrol->value.enumerated.item[0];
510 int ret = 0;
511
512 if (deemph > 1)
513 return -EINVAL;
514
515 mutex_lock(&codec->mutex);
516 if (wm8903->deemph != deemph) {
517 wm8903->deemph = deemph;
518
519 wm8903_set_deemph(codec);
520
521 ret = 1;
522 }
523 mutex_unlock(&codec->mutex);
524
525 return ret;
526}
527
f1c0a02f
MB		 528/* ALSA can only do steps of .01dB */
529static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
530
291ce18c 531static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 532static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
533
534static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
535static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
536static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
537static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
538static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
539
460f4aae
MB		 540static const char *hpf_mode_text[] = {
541 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
542};
543
544static const struct soc_enum hpf_mode =
545 SOC_ENUM_SINGLE(WM8903_ADC_DIGITAL_0, 5, 4, hpf_mode_text);
546
dcf9ada3
MB		 547static const char *osr_text[] = {
548 "Low power", "High performance"
549};
550
551static const struct soc_enum adc_osr =
552 SOC_ENUM_SINGLE(WM8903_ANALOGUE_ADC_0, 0, 2, osr_text);
553
554static const struct soc_enum dac_osr =
555 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 0, 2, osr_text);
556
f1c0a02f
MB		 557static const char *drc_slope_text[] = {
558 "1", "1/2", "1/4", "1/8", "1/16", "0"
559};
560
561static const struct soc_enum drc_slope_r0 =
562 SOC_ENUM_SINGLE(WM8903_DRC_2, 3, 6, drc_slope_text);
563
564static const struct soc_enum drc_slope_r1 =
565 SOC_ENUM_SINGLE(WM8903_DRC_2, 0, 6, drc_slope_text);
566
567static const char *drc_attack_text[] = {
568 "instantaneous",
569 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
570 "46.4ms", "92.8ms", "185.6ms"
571};
572
573static const struct soc_enum drc_attack =
574 SOC_ENUM_SINGLE(WM8903_DRC_1, 12, 11, drc_attack_text);
575
576static const char *drc_decay_text[] = {
577 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
578 "23.87s", "47.56s"
579};
580
581static const struct soc_enum drc_decay =
582 SOC_ENUM_SINGLE(WM8903_DRC_1, 8, 9, drc_decay_text);
583
584static const char *drc_ff_delay_text[] = {
585 "5 samples", "9 samples"
586};
587
588static const struct soc_enum drc_ff_delay =
589 SOC_ENUM_SINGLE(WM8903_DRC_0, 5, 2, drc_ff_delay_text);
590
591static const char *drc_qr_decay_text[] = {
592 "0.725ms", "1.45ms", "5.8ms"
593};
594
595static const struct soc_enum drc_qr_decay =
596 SOC_ENUM_SINGLE(WM8903_DRC_1, 4, 3, drc_qr_decay_text);
597
598static const char *drc_smoothing_text[] = {
599 "Low", "Medium", "High"
600};
601
602static const struct soc_enum drc_smoothing =
603 SOC_ENUM_SINGLE(WM8903_DRC_0, 11, 3, drc_smoothing_text);
604
605static const char *soft_mute_text[] = {
606 "Fast (fs/2)", "Slow (fs/32)"
607};
608
609static const struct soc_enum soft_mute =
610 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 10, 2, soft_mute_text);
611
612static const char *mute_mode_text[] = {
613 "Hard", "Soft"
614};
615
616static const struct soc_enum mute_mode =
617 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_1, 9, 2, mute_mode_text);
618
f1c0a02f
MB		 619static const char *companding_text[] = {
620 "ulaw", "alaw"
621};
622
623static const struct soc_enum dac_companding =
624 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 0, 2, companding_text);
625
626static const struct soc_enum adc_companding =
627 SOC_ENUM_SINGLE(WM8903_AUDIO_INTERFACE_0, 2, 2, companding_text);
628
629static const char *input_mode_text[] = {
630 "Single-Ended", "Differential Line", "Differential Mic"
631};
632
633static const struct soc_enum linput_mode_enum =
634 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 0, 3, input_mode_text);
635
636static const struct soc_enum rinput_mode_enum =
637 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 0, 3, input_mode_text);
638
639static const char *linput_mux_text[] = {
640 "IN1L", "IN2L", "IN3L"
641};
642
643static const struct soc_enum linput_enum =
644 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 2, 3, linput_mux_text);
645
646static const struct soc_enum linput_inv_enum =
647 SOC_ENUM_SINGLE(WM8903_ANALOGUE_LEFT_INPUT_1, 4, 3, linput_mux_text);
648
649static const char *rinput_mux_text[] = {
650 "IN1R", "IN2R", "IN3R"
651};
652
653static const struct soc_enum rinput_enum =
654 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 2, 3, rinput_mux_text);
655
656static const struct soc_enum rinput_inv_enum =
657 SOC_ENUM_SINGLE(WM8903_ANALOGUE_RIGHT_INPUT_1, 4, 3, rinput_mux_text);
658
659
291ce18c
MB		 660static const char *sidetone_text[] = {
661 "None", "Left", "Right"
662};
663
664static const struct soc_enum lsidetone_enum =
665 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 2, 3, sidetone_text);
666
667static const struct soc_enum rsidetone_enum =
668 SOC_ENUM_SINGLE(WM8903_DAC_DIGITAL_0, 0, 3, sidetone_text);
669
f1c0a02f
MB		 670static const struct snd_kcontrol_new wm8903_snd_controls[] = {
671
672/* Input PGAs - No TLV since the scale depends on PGA mode */
673SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 674 7, 1, 1),
f1c0a02f
MB		 675SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
676 0, 31, 0),
677SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
678 6, 1, 0),
679
680SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 681 7, 1, 1),
f1c0a02f
MB		 682SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
683 0, 31, 0),
684SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
685 6, 1, 0),
686
687/* ADCs */
dcf9ada3 688SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 689SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
690SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 691SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
692SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
693SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 694SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 695 drc_tlv_thresh),
696SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
697SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
698SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
699SOC_ENUM("DRC Attack Rate", drc_attack),
700SOC_ENUM("DRC Decay Rate", drc_decay),
701SOC_ENUM("DRC FF Delay", drc_ff_delay),
702SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
703SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 704SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 705SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
706SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
707SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 708SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 709SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
710
711SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
712 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 96, 0, digital_tlv),
713SOC_ENUM("ADC Companding Mode", adc_companding),
714SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
715
291ce18c
MB		 716SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
717 12, 0, digital_sidetone_tlv),
718
f1c0a02f 719/* DAC */
dcf9ada3 720SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 721SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
722 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
723SOC_ENUM("DAC Soft Mute Rate", soft_mute),
724SOC_ENUM("DAC Mute Mode", mute_mode),
725SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 726SOC_ENUM("DAC Companding Mode", dac_companding),
727SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
69fff9bb
MB		 728SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
729 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 730
731/* Headphones */
732SOC_DOUBLE_R("Headphone Switch",
733 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
734 8, 1, 1),
735SOC_DOUBLE_R("Headphone ZC Switch",
736 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
737 6, 1, 0),
738SOC_DOUBLE_R_TLV("Headphone Volume",
739 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
740 0, 63, 0, out_tlv),
741
742/* Line out */
743SOC_DOUBLE_R("Line Out Switch",
744 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
745 8, 1, 1),
746SOC_DOUBLE_R("Line Out ZC Switch",
747 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
748 6, 1, 0),
749SOC_DOUBLE_R_TLV("Line Out Volume",
750 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
751 0, 63, 0, out_tlv),
752
753/* Speaker */
754SOC_DOUBLE_R("Speaker Switch",
755 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
756SOC_DOUBLE_R("Speaker ZC Switch",
757 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
758SOC_DOUBLE_R_TLV("Speaker Volume",
759 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
760 0, 63, 0, out_tlv),
761};
762
f1c0a02f
MB		 763static const struct snd_kcontrol_new linput_mode_mux =
764 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
765
766static const struct snd_kcontrol_new rinput_mode_mux =
767 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
768
769static const struct snd_kcontrol_new linput_mux =
770 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
771
772static const struct snd_kcontrol_new linput_inv_mux =
773 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
774
775static const struct snd_kcontrol_new rinput_mux =
776 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
777
778static const struct snd_kcontrol_new rinput_inv_mux =
779 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
780
291ce18c
MB		 781static const struct snd_kcontrol_new lsidetone_mux =
782 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
783
784static const struct snd_kcontrol_new rsidetone_mux =
785 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
786
f1c0a02f
MB		 787static const struct snd_kcontrol_new left_output_mixer[] = {
788SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
789SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
790SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 791SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 792};
793
794static const struct snd_kcontrol_new right_output_mixer[] = {
795SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
796SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
797SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 798SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 799};
800
801static const struct snd_kcontrol_new left_speaker_mixer[] = {
802SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
803SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
804SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
805SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 806 0, 1, 0),
f1c0a02f
MB		 807};
808
809static const struct snd_kcontrol_new right_speaker_mixer[] = {
810SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
811SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
812SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
813 1, 1, 0),
814SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 815 0, 1, 0),
f1c0a02f
MB		 816};
817
818static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
819SND_SOC_DAPM_INPUT("IN1L"),
820SND_SOC_DAPM_INPUT("IN1R"),
821SND_SOC_DAPM_INPUT("IN2L"),
822SND_SOC_DAPM_INPUT("IN2R"),
823SND_SOC_DAPM_INPUT("IN3L"),
824SND_SOC_DAPM_INPUT("IN3R"),
825
826SND_SOC_DAPM_OUTPUT("HPOUTL"),
827SND_SOC_DAPM_OUTPUT("HPOUTR"),
828SND_SOC_DAPM_OUTPUT("LINEOUTL"),
829SND_SOC_DAPM_OUTPUT("LINEOUTR"),
830SND_SOC_DAPM_OUTPUT("LOP"),
831SND_SOC_DAPM_OUTPUT("LON"),
832SND_SOC_DAPM_OUTPUT("ROP"),
833SND_SOC_DAPM_OUTPUT("RON"),
834
835SND_SOC_DAPM_MICBIAS("Mic Bias", WM8903_MIC_BIAS_CONTROL_0, 0, 0),
836
837SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
838SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
839 &linput_inv_mux),
840SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
841
842SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
843SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
844 &rinput_inv_mux),
845SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
846
847SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
848SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
849
850SND_SOC_DAPM_ADC("ADCL", "Left HiFi Capture", WM8903_POWER_MANAGEMENT_6, 1, 0),
851SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8903_POWER_MANAGEMENT_6, 0, 0),
852
291ce18c
MB		 853SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
854SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
855
f1c0a02f
MB		 856SND_SOC_DAPM_DAC("DACL", "Left Playback", WM8903_POWER_MANAGEMENT_6, 3, 0),
857SND_SOC_DAPM_DAC("DACR", "Right Playback", WM8903_POWER_MANAGEMENT_6, 2, 0),
858
859SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
860 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
861SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
862 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
863
864SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
865 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
866SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
867 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
868
869SND_SOC_DAPM_PGA_E("Left Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
870 1, 0, NULL, 0, wm8903_output_event,
871 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 872 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 873SND_SOC_DAPM_PGA_E("Right Headphone Output PGA", WM8903_POWER_MANAGEMENT_2,
874 0, 0, NULL, 0, wm8903_output_event,
875 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 876 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 877
878SND_SOC_DAPM_PGA_E("Left Line Output PGA", WM8903_POWER_MANAGEMENT_3, 1, 0,
879 NULL, 0, wm8903_output_event,
880 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 881 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 882SND_SOC_DAPM_PGA_E("Right Line Output PGA", WM8903_POWER_MANAGEMENT_3, 0, 0,
883 NULL, 0, wm8903_output_event,
884 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
42768a12 885 SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 886
887SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
888 NULL, 0),
889SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
890 NULL, 0),
891
42768a12
MB		 892SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
893 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 894SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
f1c0a02f
MB		 895};
896
897static const struct snd_soc_dapm_route intercon[] = {
898
899 { "Left Input Mux", "IN1L", "IN1L" },
900 { "Left Input Mux", "IN2L", "IN2L" },
901 { "Left Input Mux", "IN3L", "IN3L" },
902
903 { "Left Input Inverting Mux", "IN1L", "IN1L" },
904 { "Left Input Inverting Mux", "IN2L", "IN2L" },
905 { "Left Input Inverting Mux", "IN3L", "IN3L" },
906
907 { "Right Input Mux", "IN1R", "IN1R" },
908 { "Right Input Mux", "IN2R", "IN2R" },
909 { "Right Input Mux", "IN3R", "IN3R" },
910
911 { "Right Input Inverting Mux", "IN1R", "IN1R" },
912 { "Right Input Inverting Mux", "IN2R", "IN2R" },
913 { "Right Input Inverting Mux", "IN3R", "IN3R" },
914
915 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
916 { "Left Input Mode Mux", "Differential Line",
917 "Left Input Mux" },
918 { "Left Input Mode Mux", "Differential Line",
919 "Left Input Inverting Mux" },
920 { "Left Input Mode Mux", "Differential Mic",
921 "Left Input Mux" },
922 { "Left Input Mode Mux", "Differential Mic",
923 "Left Input Inverting Mux" },
924
925 { "Right Input Mode Mux", "Single-Ended",
926 "Right Input Inverting Mux" },
927 { "Right Input Mode Mux", "Differential Line",
928 "Right Input Mux" },
929 { "Right Input Mode Mux", "Differential Line",
930 "Right Input Inverting Mux" },
931 { "Right Input Mode Mux", "Differential Mic",
932 "Right Input Mux" },
933 { "Right Input Mode Mux", "Differential Mic",
934 "Right Input Inverting Mux" },
935
936 { "Left Input PGA", NULL, "Left Input Mode Mux" },
937 { "Right Input PGA", NULL, "Right Input Mode Mux" },
938
939 { "ADCL", NULL, "Left Input PGA" },
c2aef4ff 940 { "ADCL", NULL, "CLK_DSP" },
f1c0a02f 941 { "ADCR", NULL, "Right Input PGA" },
c2aef4ff
MB		 942 { "ADCR", NULL, "CLK_DSP" },
943
291ce18c
MB		 944 { "DACL Sidetone", "Left", "ADCL" },
945 { "DACL Sidetone", "Right", "ADCR" },
946 { "DACR Sidetone", "Left", "ADCL" },
947 { "DACR Sidetone", "Right", "ADCR" },
948
949 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 950 { "DACL", NULL, "CLK_DSP" },
291ce18c 951 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 952 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 953
954 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
955 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
956 { "Left Output Mixer", "DACL Switch", "DACL" },
957 { "Left Output Mixer", "DACR Switch", "DACR" },
958
959 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
960 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
961 { "Right Output Mixer", "DACL Switch", "DACL" },
962 { "Right Output Mixer", "DACR Switch", "DACR" },
963
964 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
965 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
966 { "Left Speaker Mixer", "DACL Switch", "DACL" },
967 { "Left Speaker Mixer", "DACR Switch", "DACR" },
968
969 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
970 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
971 { "Right Speaker Mixer", "DACL Switch", "DACL" },
972 { "Right Speaker Mixer", "DACR Switch", "DACR" },
973
974 { "Left Line Output PGA", NULL, "Left Output Mixer" },
975 { "Right Line Output PGA", NULL, "Right Output Mixer" },
976
977 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
978 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
979
980 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
981 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
982
983 { "HPOUTL", NULL, "Left Headphone Output PGA" },
984 { "HPOUTR", NULL, "Right Headphone Output PGA" },
985
986 { "LINEOUTL", NULL, "Left Line Output PGA" },
987 { "LINEOUTR", NULL, "Right Line Output PGA" },
988
989 { "LOP", NULL, "Left Speaker PGA" },
990 { "LON", NULL, "Left Speaker PGA" },
991
992 { "ROP", NULL, "Right Speaker PGA" },
993 { "RON", NULL, "Right Speaker PGA" },
42768a12
MB		 994
995 { "Left Headphone Output PGA", NULL, "Charge Pump" },
996 { "Right Headphone Output PGA", NULL, "Charge Pump" },
997 { "Left Line Output PGA", NULL, "Charge Pump" },
998 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 999};
1000
1001static int wm8903_add_widgets(struct snd_soc_codec *codec)
1002{
ce6120cc 1003 struct snd_soc_dapm_context *dapm = &codec->dapm;
f1c0a02f 1004
ce6120cc
LG		 1005 snd_soc_dapm_new_controls(dapm, wm8903_dapm_widgets,
1006 ARRAY_SIZE(wm8903_dapm_widgets));
1007 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
f1c0a02f 1008
f1c0a02f
MB		 1009 return 0;
1010}
1011
1012static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1013 enum snd_soc_bias_level level)
1014{
524d7692 1015 u16 reg;
f1c0a02f
MB		 1016
1017 switch (level) {
1018 case SND_SOC_BIAS_ON:
1019 case SND_SOC_BIAS_PREPARE:
8d50e447 1020 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1021 reg &= ~(WM8903_VMID_RES_MASK);
1022 reg |= WM8903_VMID_RES_50K;
8d50e447 1023 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1024 break;
1025
1026 case SND_SOC_BIAS_STANDBY:
ce6120cc 1027 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
8d50e447 1028 snd_soc_write(codec, WM8903_CLOCK_RATES_2,
3b1228ab
MB		 1029 WM8903_CLK_SYS_ENA);
1030
4dbfe809 1031 /* Change DC servo dither level in startup sequence */
8d50e447
MB		 1032 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_0, 0x11);
1033 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_1, 0x1257);
1034 snd_soc_write(codec, WM8903_WRITE_SEQUENCER_2, 0x2);
4dbfe809 1035
f1c0a02f
MB		 1036 wm8903_run_sequence(codec, 0);
1037 wm8903_sync_reg_cache(codec, codec->reg_cache);
1038
f1c0a02f
MB		 1039 /* By default no bypass paths are enabled so
1040 * enable Class W support.
1041 */
f0fba2ad 1042 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1043 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1044 WM8903_CP_DYN_FREQ |
1045 WM8903_CP_DYN_V,
1046 WM8903_CP_DYN_FREQ |
1047 WM8903_CP_DYN_V);
f1c0a02f
MB		 1048 }
1049
8d50e447 1050 reg = snd_soc_read(codec, WM8903_VMID_CONTROL_0);
f1c0a02f
MB		 1051 reg &= ~(WM8903_VMID_RES_MASK);
1052 reg |= WM8903_VMID_RES_250K;
8d50e447 1053 snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
f1c0a02f
MB		 1054 break;
1055
1056 case SND_SOC_BIAS_OFF:
1057 wm8903_run_sequence(codec, 32);
8d50e447 1058 reg = snd_soc_read(codec, WM8903_CLOCK_RATES_2);
3b1228ab 1059 reg &= ~WM8903_CLK_SYS_ENA;
8d50e447 1060 snd_soc_write(codec, WM8903_CLOCK_RATES_2, reg);
f1c0a02f
MB		 1061 break;
1062 }
1063
ce6120cc 1064 codec->dapm.bias_level = level;
f1c0a02f
MB		 1065
1066 return 0;
1067}
1068
1069static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1070 int clk_id, unsigned int freq, int dir)
1071{
1072 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1073 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1074
1075 wm8903->sysclk = freq;
1076
1077 return 0;
1078}
1079
1080static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1081 unsigned int fmt)
1082{
1083 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1084 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1085
1086 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1087 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1088
1089 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1090 case SND_SOC_DAIFMT_CBS_CFS:
1091 break;
1092 case SND_SOC_DAIFMT_CBS_CFM:
1093 aif1 |= WM8903_LRCLK_DIR;
1094 break;
1095 case SND_SOC_DAIFMT_CBM_CFM:
1096 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1097 break;
1098 case SND_SOC_DAIFMT_CBM_CFS:
1099 aif1 |= WM8903_BCLK_DIR;
1100 break;
1101 default:
1102 return -EINVAL;
1103 }
1104
1105 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1106 case SND_SOC_DAIFMT_DSP_A:
1107 aif1 |= 0x3;
1108 break;
1109 case SND_SOC_DAIFMT_DSP_B:
1110 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1111 break;
1112 case SND_SOC_DAIFMT_I2S:
1113 aif1 |= 0x2;
1114 break;
1115 case SND_SOC_DAIFMT_RIGHT_J:
1116 aif1 |= 0x1;
1117 break;
1118 case SND_SOC_DAIFMT_LEFT_J:
1119 break;
1120 default:
1121 return -EINVAL;
1122 }
1123
1124 /* Clock inversion */
1125 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1126 case SND_SOC_DAIFMT_DSP_A:
1127 case SND_SOC_DAIFMT_DSP_B:
1128 /* frame inversion not valid for DSP modes */
1129 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1130 case SND_SOC_DAIFMT_NB_NF:
1131 break;
1132 case SND_SOC_DAIFMT_IB_NF:
1133 aif1 |= WM8903_AIF_BCLK_INV;
1134 break;
1135 default:
1136 return -EINVAL;
1137 }
1138 break;
1139 case SND_SOC_DAIFMT_I2S:
1140 case SND_SOC_DAIFMT_RIGHT_J:
1141 case SND_SOC_DAIFMT_LEFT_J:
1142 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1143 case SND_SOC_DAIFMT_NB_NF:
1144 break;
1145 case SND_SOC_DAIFMT_IB_IF:
1146 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1147 break;
1148 case SND_SOC_DAIFMT_IB_NF:
1149 aif1 |= WM8903_AIF_BCLK_INV;
1150 break;
1151 case SND_SOC_DAIFMT_NB_IF:
1152 aif1 |= WM8903_AIF_LRCLK_INV;
1153 break;
1154 default:
1155 return -EINVAL;
1156 }
1157 break;
1158 default:
1159 return -EINVAL;
1160 }
1161
8d50e447 1162 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1163
1164 return 0;
1165}
1166
1167static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1168{
1169 struct snd_soc_codec *codec = codec_dai->codec;
1170 u16 reg;
1171
8d50e447 1172 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1173
1174 if (mute)
1175 reg |= WM8903_DAC_MUTE;
1176 else
1177 reg &= ~WM8903_DAC_MUTE;
1178
8d50e447 1179 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1180
1181 return 0;
1182}
1183
1184/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1185 * for optimal performance so we list the lower rates first and match
1186 * on the last match we find. */
1187static struct {
1188 int div;
1189 int rate;
1190 int mode;
1191 int mclk_div;
1192} clk_sys_ratios[] = {
1193 { 64, 0x0, 0x0, 1 },
1194 { 68, 0x0, 0x1, 1 },
1195 { 125, 0x0, 0x2, 1 },
1196 { 128, 0x1, 0x0, 1 },
1197 { 136, 0x1, 0x1, 1 },
1198 { 192, 0x2, 0x0, 1 },
1199 { 204, 0x2, 0x1, 1 },
1200
1201 { 64, 0x0, 0x0, 2 },
1202 { 68, 0x0, 0x1, 2 },
1203 { 125, 0x0, 0x2, 2 },
1204 { 128, 0x1, 0x0, 2 },
1205 { 136, 0x1, 0x1, 2 },
1206 { 192, 0x2, 0x0, 2 },
1207 { 204, 0x2, 0x1, 2 },
1208
1209 { 250, 0x2, 0x2, 1 },
1210 { 256, 0x3, 0x0, 1 },
1211 { 272, 0x3, 0x1, 1 },
1212 { 384, 0x4, 0x0, 1 },
1213 { 408, 0x4, 0x1, 1 },
1214 { 375, 0x4, 0x2, 1 },
1215 { 512, 0x5, 0x0, 1 },
1216 { 544, 0x5, 0x1, 1 },
1217 { 500, 0x5, 0x2, 1 },
1218 { 768, 0x6, 0x0, 1 },
1219 { 816, 0x6, 0x1, 1 },
1220 { 750, 0x6, 0x2, 1 },
1221 { 1024, 0x7, 0x0, 1 },
1222 { 1088, 0x7, 0x1, 1 },
1223 { 1000, 0x7, 0x2, 1 },
1224 { 1408, 0x8, 0x0, 1 },
1225 { 1496, 0x8, 0x1, 1 },
1226 { 1536, 0x9, 0x0, 1 },
1227 { 1632, 0x9, 0x1, 1 },
1228 { 1500, 0x9, 0x2, 1 },
1229
1230 { 250, 0x2, 0x2, 2 },
1231 { 256, 0x3, 0x0, 2 },
1232 { 272, 0x3, 0x1, 2 },
1233 { 384, 0x4, 0x0, 2 },
1234 { 408, 0x4, 0x1, 2 },
1235 { 375, 0x4, 0x2, 2 },
1236 { 512, 0x5, 0x0, 2 },
1237 { 544, 0x5, 0x1, 2 },
1238 { 500, 0x5, 0x2, 2 },
1239 { 768, 0x6, 0x0, 2 },
1240 { 816, 0x6, 0x1, 2 },
1241 { 750, 0x6, 0x2, 2 },
1242 { 1024, 0x7, 0x0, 2 },
1243 { 1088, 0x7, 0x1, 2 },
1244 { 1000, 0x7, 0x2, 2 },
1245 { 1408, 0x8, 0x0, 2 },
1246 { 1496, 0x8, 0x1, 2 },
1247 { 1536, 0x9, 0x0, 2 },
1248 { 1632, 0x9, 0x1, 2 },
1249 { 1500, 0x9, 0x2, 2 },
1250};
1251
1252/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1253static struct {
1254 int ratio;
1255 int div;
1256} bclk_divs[] = {
1257 { 10, 0 },
f1c0a02f
MB		 1258 { 20, 2 },
1259 { 30, 3 },
1260 { 40, 4 },
1261 { 50, 5 },
f1c0a02f
MB		 1262 { 60, 7 },
1263 { 80, 8 },
1264 { 100, 9 },
f1c0a02f
MB		 1265 { 120, 11 },
1266 { 160, 12 },
1267 { 200, 13 },
1268 { 220, 14 },
1269 { 240, 15 },
f1c0a02f
MB		 1270 { 300, 17 },
1271 { 320, 18 },
1272 { 440, 19 },
1273 { 480, 20 },
1274};
1275
1276/* Sample rates for DSP */
1277static struct {
1278 int rate;
1279 int value;
1280} sample_rates[] = {
1281 { 8000, 0 },
1282 { 11025, 1 },
1283 { 12000, 2 },
1284 { 16000, 3 },
1285 { 22050, 4 },
1286 { 24000, 5 },
1287 { 32000, 6 },
1288 { 44100, 7 },
1289 { 48000, 8 },
1290 { 88200, 9 },
1291 { 96000, 10 },
1292 { 0, 0 },
1293};
1294
f1c0a02f 1295static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1296 struct snd_pcm_hw_params *params,
1297 struct snd_soc_dai *dai)
f1c0a02f
MB		 1298{
1299 struct snd_soc_pcm_runtime *rtd = substream->private_data;
f0fba2ad 1300 struct snd_soc_codec *codec =rtd->codec;
b2c812e2 1301 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1302 int fs = params_rate(params);
1303 int bclk;
1304 int bclk_div;
1305 int i;
1306 int dsp_config;
1307 int clk_config;
1308 int best_val;
1309 int cur_val;
1310 int clk_sys;
1311
8d50e447
MB		 1312 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1313 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1314 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1315 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1316 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1317 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1318
9e79261f
MB		 1319 /* Enable sloping stopband filter for low sample rates */
1320 if (fs <= 24000)
1321 dac_digital1 |= WM8903_DAC_SB_FILT;
1322 else
1323 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1324
f1c0a02f
MB		 1325 /* Configure sample rate logic for DSP - choose nearest rate */
1326 dsp_config = 0;
1327 best_val = abs(sample_rates[dsp_config].rate - fs);
1328 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1329 cur_val = abs(sample_rates[i].rate - fs);
1330 if (cur_val <= best_val) {
1331 dsp_config = i;
1332 best_val = cur_val;
1333 }
1334 }
1335
f0fba2ad 1336 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1337 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1338 clock1 |= sample_rates[dsp_config].value;
1339
1340 aif1 &= ~WM8903_AIF_WL_MASK;
1341 bclk = 2 * fs;
1342 switch (params_format(params)) {
1343 case SNDRV_PCM_FORMAT_S16_LE:
1344 bclk *= 16;
1345 break;
1346 case SNDRV_PCM_FORMAT_S20_3LE:
1347 bclk *= 20;
1348 aif1 |= 0x4;
1349 break;
1350 case SNDRV_PCM_FORMAT_S24_LE:
1351 bclk *= 24;
1352 aif1 |= 0x8;
1353 break;
1354 case SNDRV_PCM_FORMAT_S32_LE:
1355 bclk *= 32;
1356 aif1 |= 0xc;
1357 break;
1358 default:
1359 return -EINVAL;
1360 }
1361
f0fba2ad 1362 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1363 wm8903->sysclk, fs);
1364
1365 /* We may not have an MCLK which allows us to generate exactly
1366 * the clock we want, particularly with USB derived inputs, so
1367 * approximate.
1368 */
1369 clk_config = 0;
1370 best_val = abs((wm8903->sysclk /
1371 (clk_sys_ratios[0].mclk_div *
1372 clk_sys_ratios[0].div)) - fs);
1373 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1374 cur_val = abs((wm8903->sysclk /
1375 (clk_sys_ratios[i].mclk_div *
1376 clk_sys_ratios[i].div)) - fs);
1377
1378 if (cur_val <= best_val) {
1379 clk_config = i;
1380 best_val = cur_val;
1381 }
1382 }
1383
1384 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1385 clock0 |= WM8903_MCLKDIV2;
1386 clk_sys = wm8903->sysclk / 2;
1387 } else {
1388 clock0 &= ~WM8903_MCLKDIV2;
1389 clk_sys = wm8903->sysclk;
1390 }
1391
1392 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1393 WM8903_CLK_SYS_MODE_MASK);
1394 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1395 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1396
f0fba2ad 1397 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1398 clk_sys_ratios[clk_config].rate,
1399 clk_sys_ratios[clk_config].mode,
1400 clk_sys_ratios[clk_config].div);
1401
f0fba2ad 1402 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1403
1404 /* We may not get quite the right frequency if using
1405 * approximate clocks so look for the closest match that is
1406 * higher than the target (we need to ensure that there enough
1407 * BCLKs to clock out the samples).
1408 */
1409 bclk_div = 0;
1410 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1411 i = 1;
1412 while (i < ARRAY_SIZE(bclk_divs)) {
1413 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1414 if (cur_val < 0) /* BCLK table is sorted */
1415 break;
1416 bclk_div = i;
1417 best_val = cur_val;
1418 i++;
1419 }
1420
1421 aif2 &= ~WM8903_BCLK_DIV_MASK;
1422 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1423
f0fba2ad 1424 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1425 bclk_divs[bclk_div].ratio / 10, bclk,
1426 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1427
1428 aif2 |= bclk_divs[bclk_div].div;
1429 aif3 |= bclk / fs;
1430
69fff9bb
MB		 1431 wm8903->fs = params_rate(params);
1432 wm8903_set_deemph(codec);
1433
8d50e447
MB		 1434 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1435 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1436 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1437 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1438 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1439 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1440
1441 return 0;
1442}
1443
7245387e
MB		 1444/**
1445 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1446 *
1447 * @codec: WM8903 codec
1448 * @jack: jack to report detection events on
1449 * @det: value to report for presence detection
1450 * @shrt: value to report for short detection
1451 *
1452 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1453 * being used to bring out signals to the processor then only platform
1454 * data configuration is needed for WM8903 and processor GPIOs should
1455 * be configured using snd_soc_jack_add_gpios() instead.
1456 *
1457 * The current threasholds for detection should be configured using
1458 * micdet_cfg in the platform data. Using this function will force on
1459 * the microphone bias for the device.
1460 */
1461int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1462 int det, int shrt)
1463{
b2c812e2 1464 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1465 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1466
1467 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1468 det, shrt);
1469
1470 /* Store the configuration */
1471 wm8903->mic_jack = jack;
1472 wm8903->mic_det = det;
1473 wm8903->mic_short = shrt;
1474
1475 /* Enable interrupts we've got a report configured for */
1476 if (det)
1477 irq_mask &= ~WM8903_MICDET_EINT;
1478 if (shrt)
1479 irq_mask &= ~WM8903_MICSHRT_EINT;
1480
1481 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1482 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1483 irq_mask);
1484
69266866
MB		 1485 if (det && shrt) {
1486 /* Enable mic detection, this may not have been set through
1487 * platform data (eg, if the defaults are OK). */
1488 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1489 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1490 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1491 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1492 } else {
1493 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1494 WM8903_MICDET_ENA, 0);
1495 }
7245387e
MB		 1496
1497 return 0;
1498}
1499EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1500
8abd16a6
MB		 1501static irqreturn_t wm8903_irq(int irq, void *data)
1502{
f0fba2ad
LG		 1503 struct snd_soc_codec *codec = data;
1504 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
7245387e
MB		 1505 int mic_report;
1506 int int_pol;
1507 int int_val = 0;
1508 int mask = ~snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1_MASK);
8abd16a6 1509
7245387e 1510 int_val = snd_soc_read(codec, WM8903_INTERRUPT_STATUS_1) & mask;
8abd16a6 1511
7245387e 1512 if (int_val & WM8903_WSEQ_BUSY_EINT) {
8abd16a6
MB		 1513 dev_dbg(codec->dev, "Write sequencer done\n");
1514 complete(&wm8903->wseq);
1515 }
1516
7245387e
MB		 1517 /*
1518 * The rest is microphone jack detection. We need to manually
1519 * invert the polarity of the interrupt after each event - to
1520 * simplify the code keep track of the last state we reported
1521 * and just invert the relevant bits in both the report and
1522 * the polarity register.
1523 */
1524 mic_report = wm8903->mic_last_report;
1525 int_pol = snd_soc_read(codec, WM8903_INTERRUPT_POLARITY_1);
1526
1435b940 1527#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66
MB		 1528 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
1529 trace_snd_soc_jack_irq(dev_name(codec->dev));
1435b940 1530#endif
2bbb5d66 1531
7245387e
MB		 1532 if (int_val & WM8903_MICSHRT_EINT) {
1533 dev_dbg(codec->dev, "Microphone short (pol=%x)\n", int_pol);
1534
1535 mic_report ^= wm8903->mic_short;
1536 int_pol ^= WM8903_MICSHRT_INV;
1537 }
1538
1539 if (int_val & WM8903_MICDET_EINT) {
1540 dev_dbg(codec->dev, "Microphone detect (pol=%x)\n", int_pol);
1541
1542 mic_report ^= wm8903->mic_det;
1543 int_pol ^= WM8903_MICDET_INV;
1544
1545 msleep(wm8903->mic_delay);
1546 }
1547
1548 snd_soc_update_bits(codec, WM8903_INTERRUPT_POLARITY_1,
1549 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
1550
1551 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1552 wm8903->mic_short | wm8903->mic_det);
1553
1554 wm8903->mic_last_report = mic_report;
1555
8abd16a6
MB		 1556 return IRQ_HANDLED;
1557}
1558
f1c0a02f
MB		 1559#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1560 SNDRV_PCM_RATE_11025 | \
1561 SNDRV_PCM_RATE_16000 | \
1562 SNDRV_PCM_RATE_22050 | \
1563 SNDRV_PCM_RATE_32000 | \
1564 SNDRV_PCM_RATE_44100 | \
1565 SNDRV_PCM_RATE_48000 | \
1566 SNDRV_PCM_RATE_88200 | \
1567 SNDRV_PCM_RATE_96000)
1568
1569#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1570 SNDRV_PCM_RATE_11025 | \
1571 SNDRV_PCM_RATE_16000 | \
1572 SNDRV_PCM_RATE_22050 | \
1573 SNDRV_PCM_RATE_32000 | \
1574 SNDRV_PCM_RATE_44100 | \
1575 SNDRV_PCM_RATE_48000)
1576
1577#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1578 SNDRV_PCM_FMTBIT_S20_3LE |\
1579 SNDRV_PCM_FMTBIT_S24_LE)
1580
6335d055 1581static struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1582 .hw_params = wm8903_hw_params,
1583 .digital_mute = wm8903_digital_mute,
1584 .set_fmt = wm8903_set_dai_fmt,
1585 .set_sysclk = wm8903_set_dai_sysclk,
1586};
1587
f0fba2ad
LG		 1588static struct snd_soc_dai_driver wm8903_dai = {
1589 .name = "wm8903-hifi",
f1c0a02f
MB		 1590 .playback = {
1591 .stream_name = "Playback",
1592 .channels_min = 2,
1593 .channels_max = 2,
1594 .rates = WM8903_PLAYBACK_RATES,
1595 .formats = WM8903_FORMATS,
1596 },
1597 .capture = {
1598 .stream_name = "Capture",
1599 .channels_min = 2,
1600 .channels_max = 2,
1601 .rates = WM8903_CAPTURE_RATES,
1602 .formats = WM8903_FORMATS,
1603 },
6335d055 1604 .ops = &wm8903_dai_ops,
0d960e88 1605 .symmetric_rates = 1,
f1c0a02f 1606};
f1c0a02f 1607
f0fba2ad 1608static int wm8903_suspend(struct snd_soc_codec *codec, pm_message_t state)
f1c0a02f 1609{
f1c0a02f
MB		 1610 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1611
1612 return 0;
1613}
1614
f0fba2ad 1615static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1616{
f1c0a02f
MB		 1617 int i;
1618 u16 *reg_cache = codec->reg_cache;
40aa7030 1619 u16 *tmp_cache = kmemdup(reg_cache, sizeof(wm8903_reg_defaults),
f1c0a02f
MB		 1620 GFP_KERNEL);
1621
1622 /* Bring the codec back up to standby first to minimise pop/clicks */
1623 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1624
1625 /* Sync back everything else */
1626 if (tmp_cache) {
1627 for (i = 2; i < ARRAY_SIZE(wm8903_reg_defaults); i++)
1628 if (tmp_cache[i] != reg_cache[i])
8d50e447 1629 snd_soc_write(codec, i, tmp_cache[i]);
40aa7030 1630 kfree(tmp_cache);
f1c0a02f 1631 } else {
f0fba2ad 1632 dev_err(codec->dev, "Failed to allocate temporary cache\n");
f1c0a02f
MB		 1633 }
1634
1635 return 0;
1636}
1637
f0fba2ad 1638static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1639{
f0fba2ad
LG		 1640 struct wm8903_platform_data *pdata = dev_get_platdata(codec->dev);
1641 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
73b34ead 1642 int ret, i;
8abd16a6 1643 int trigger, irq_pol;
f1c0a02f
MB		 1644 u16 val;
1645
8abd16a6 1646 init_completion(&wm8903->wseq);
d58d5d55 1647
8d50e447
MB		 1648 ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_I2C);
1649 if (ret != 0) {
f0fba2ad
LG		 1650 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1651 return ret;
8d50e447
MB		 1652 }
1653
1654 val = snd_soc_read(codec, WM8903_SW_RESET_AND_ID);
d58d5d55 1655 if (val != wm8903_reg_defaults[WM8903_SW_RESET_AND_ID]) {
f0fba2ad 1656 dev_err(codec->dev,
d58d5d55
MB		 1657 "Device with ID register %x is not a WM8903\n", val);
1658 return -ENODEV;
f1c0a02f
MB		 1659 }
1660
8d50e447 1661 val = snd_soc_read(codec, WM8903_REVISION_NUMBER);
f0fba2ad 1662 dev_info(codec->dev, "WM8903 revision %d\n",
f1c0a02f
MB		 1663 val & WM8903_CHIP_REV_MASK);
1664
1665 wm8903_reset(codec);
1666
37f88e84 1667 /* Set up GPIOs and microphone detection */
73b34ead
MB		 1668 if (pdata) {
1669 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1670 if (!pdata->gpio_cfg[i])
1671 continue;
1672
1673 snd_soc_write(codec, WM8903_GPIO_CONTROL_1 + i,
1674 pdata->gpio_cfg[i] & 0xffff);
1675 }
37f88e84
MB		 1676
1677 snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0,
1678 pdata->micdet_cfg);
1679
1680 /* Microphone detection needs the WSEQ clock */
1681 if (pdata->micdet_cfg)
1682 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1683 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1684
1685 wm8903->mic_delay = pdata->micdet_delay;
73b34ead 1686 }
8abd16a6 1687
f0fba2ad 1688 if (wm8903->irq) {
8abd16a6
MB		 1689 if (pdata && pdata->irq_active_low) {
1690 trigger = IRQF_TRIGGER_LOW;
1691 irq_pol = WM8903_IRQ_POL;
1692 } else {
1693 trigger = IRQF_TRIGGER_HIGH;
1694 irq_pol = 0;
1695 }
1696
1697 snd_soc_update_bits(codec, WM8903_INTERRUPT_CONTROL,
1698 WM8903_IRQ_POL, irq_pol);
1699
f0fba2ad 1700 ret = request_threaded_irq(wm8903->irq, NULL, wm8903_irq,
8abd16a6 1701 trigger | IRQF_ONESHOT,
f0fba2ad 1702 "wm8903", codec);
8abd16a6 1703 if (ret != 0) {
f0fba2ad 1704 dev_err(codec->dev, "Failed to request IRQ: %d\n",
8abd16a6 1705 ret);
f0fba2ad 1706 return ret;
8abd16a6
MB		 1707 }
1708
1709 /* Enable write sequencer interrupts */
1710 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1711 WM8903_IM_WSEQ_BUSY_EINT, 0);
1712 }
73b34ead 1713
f1c0a02f
MB		 1714 /* power on device */
1715 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1716
1717 /* Latch volume update bits */
8d50e447 1718 val = snd_soc_read(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1719 val |= WM8903_ADCVU;
8d50e447
MB		 1720 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_LEFT, val);
1721 snd_soc_write(codec, WM8903_ADC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1722
8d50e447 1723 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT);
f1c0a02f 1724 val |= WM8903_DACVU;
8d50e447
MB		 1725 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_LEFT, val);
1726 snd_soc_write(codec, WM8903_DAC_DIGITAL_VOLUME_RIGHT, val);
f1c0a02f 1727
8d50e447 1728 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT1_LEFT);
f1c0a02f 1729 val |= WM8903_HPOUTVU;
8d50e447
MB		 1730 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_LEFT, val);
1731 snd_soc_write(codec, WM8903_ANALOGUE_OUT1_RIGHT, val);
f1c0a02f 1732
8d50e447 1733 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT2_LEFT);
f1c0a02f 1734 val |= WM8903_LINEOUTVU;
8d50e447
MB		 1735 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_LEFT, val);
1736 snd_soc_write(codec, WM8903_ANALOGUE_OUT2_RIGHT, val);
f1c0a02f 1737
8d50e447 1738 val = snd_soc_read(codec, WM8903_ANALOGUE_OUT3_LEFT);
f1c0a02f 1739 val |= WM8903_SPKVU;
8d50e447
MB		 1740 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_LEFT, val);
1741 snd_soc_write(codec, WM8903_ANALOGUE_OUT3_RIGHT, val);
f1c0a02f
MB		 1742
1743 /* Enable DAC soft mute by default */
8d50e447 1744 val = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1745 val |= WM8903_DAC_MUTEMODE;
8d50e447 1746 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, val);
f1c0a02f 1747
f0fba2ad
LG		 1748 snd_soc_add_controls(codec, wm8903_snd_controls,
1749 ARRAY_SIZE(wm8903_snd_controls));
1750 wm8903_add_widgets(codec);
f1c0a02f 1751
f1c0a02f
MB		 1752 return ret;
1753}
1754
f0fba2ad
LG		 1755/* power down chip */
1756static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1757{
f0fba2ad
LG		 1758 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1759 return 0;
1760}
f1c0a02f 1761
f0fba2ad
LG		 1762static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1763 .probe = wm8903_probe,
1764 .remove = wm8903_remove,
1765 .suspend = wm8903_suspend,
1766 .resume = wm8903_resume,
1767 .set_bias_level = wm8903_set_bias_level,
1768 .reg_cache_size = ARRAY_SIZE(wm8903_reg_defaults),
1769 .reg_word_size = sizeof(u16),
1770 .reg_cache_default = wm8903_reg_defaults,
1771 .volatile_register = wm8903_volatile_register,
1772};
f1c0a02f 1773
f0fba2ad
LG		 1774#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1775static __devinit int wm8903_i2c_probe(struct i2c_client *i2c,
1776 const struct i2c_device_id *id)
1777{
1778 struct wm8903_priv *wm8903;
1779 int ret;
f1c0a02f 1780
f0fba2ad
LG		 1781 wm8903 = kzalloc(sizeof(struct wm8903_priv), GFP_KERNEL);
1782 if (wm8903 == NULL)
1783 return -ENOMEM;
8abd16a6 1784
f0fba2ad 1785 i2c_set_clientdata(i2c, wm8903);
f0fba2ad 1786 wm8903->irq = i2c->irq;
d58d5d55 1787
f0fba2ad
LG		 1788 ret = snd_soc_register_codec(&i2c->dev,
1789 &soc_codec_dev_wm8903, &wm8903_dai, 1);
1790 if (ret < 0)
1791 kfree(wm8903);
1792 return ret;
1793}
f1c0a02f 1794
f0fba2ad
LG		 1795static __devexit int wm8903_i2c_remove(struct i2c_client *client)
1796{
1797 snd_soc_unregister_codec(&client->dev);
1798 kfree(i2c_get_clientdata(client));
f1c0a02f
MB		 1799 return 0;
1800}
1801
f1c0a02f 1802static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 1803 { "wm8903", 0 },
1804 { }
f1c0a02f
MB		 1805};
1806MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
1807
1808static struct i2c_driver wm8903_i2c_driver = {
1809 .driver = {
f0fba2ad 1810 .name = "wm8903-codec",
f1c0a02f
MB		 1811 .owner = THIS_MODULE,
1812 },
f0fba2ad
LG		 1813 .probe = wm8903_i2c_probe,
1814 .remove = __devexit_p(wm8903_i2c_remove),
f1c0a02f
MB		 1815 .id_table = wm8903_i2c_id,
1816};
f0fba2ad 1817#endif
f1c0a02f 1818
f0fba2ad 1819static int __init wm8903_modinit(void)
f1c0a02f 1820{
f1c0a02f 1821 int ret = 0;
f0fba2ad
LG		 1822#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1823 ret = i2c_add_driver(&wm8903_i2c_driver);
1824 if (ret != 0) {
1825 printk(KERN_ERR "Failed to register wm8903 I2C driver: %d\n",
1826 ret);
f1c0a02f 1827 }
f0fba2ad 1828#endif
f1c0a02f 1829 return ret;
64089b84
MB		 1830}
1831module_init(wm8903_modinit);
1832
1833static void __exit wm8903_exit(void)
1834{
f0fba2ad 1835#if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
d58d5d55 1836 i2c_del_driver(&wm8903_i2c_driver);
f0fba2ad 1837#endif
64089b84
MB		 1838}
1839module_exit(wm8903_exit);
1840
f1c0a02f
MB		 1841MODULE_DESCRIPTION("ASoC WM8903 driver");
1842MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
1843MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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