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ASoC: wm8731: Move the deemph lock to the driver level
[deliverable/linux.git] / sound / soc / codecs / wm8903.c
CommitLineData
f1c0a02f
MB		 1/*
2 * wm8903.c -- WM8903 ALSA SoC Audio driver
3 *
20c5fd39 4 * Copyright 2008-12 Wolfson Microelectronics
0bf79ef2 5 * Copyright 2011-2012 NVIDIA, Inc.
f1c0a02f
MB		 6 *
7 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * TODO:
14 * - TDM mode configuration.
f1c0a02f 15 * - Digital microphone support.
f1c0a02f
MB		 16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
8abd16a6 21#include <linux/completion.h>
f1c0a02f 22#include <linux/delay.h>
7cfe5617 23#include <linux/gpio.h>
f1c0a02f
MB		 24#include <linux/pm.h>
25#include <linux/i2c.h>
ee244ce4 26#include <linux/regmap.h>
5a0e3ad6 27#include <linux/slab.h>
9d35f3e1 28#include <linux/irq.h>
f1c0a02f 29#include <sound/core.h>
7245387e 30#include <sound/jack.h>
f1c0a02f
MB		 31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/tlv.h>
34#include <sound/soc.h>
f1c0a02f 35#include <sound/initval.h>
8abd16a6 36#include <sound/wm8903.h>
2bbb5d66 37#include <trace/events/asoc.h>
f1c0a02f
MB		 38
39#include "wm8903.h"
40
f1c0a02f 41/* Register defaults at reset */
ee244ce4
MB		 42static const struct reg_default wm8903_reg_defaults[] = {
43 { 4, 0x0018 }, /* R4 - Bias Control 0 */
44 { 5, 0x0000 }, /* R5 - VMID Control 0 */
45 { 6, 0x0000 }, /* R6 - Mic Bias Control 0 */
46 { 8, 0x0001 }, /* R8 - Analogue DAC 0 */
47 { 10, 0x0001 }, /* R10 - Analogue ADC 0 */
48 { 12, 0x0000 }, /* R12 - Power Management 0 */
49 { 13, 0x0000 }, /* R13 - Power Management 1 */
50 { 14, 0x0000 }, /* R14 - Power Management 2 */
51 { 15, 0x0000 }, /* R15 - Power Management 3 */
52 { 16, 0x0000 }, /* R16 - Power Management 4 */
53 { 17, 0x0000 }, /* R17 - Power Management 5 */
54 { 18, 0x0000 }, /* R18 - Power Management 6 */
55 { 20, 0x0400 }, /* R20 - Clock Rates 0 */
56 { 21, 0x0D07 }, /* R21 - Clock Rates 1 */
57 { 22, 0x0000 }, /* R22 - Clock Rates 2 */
58 { 24, 0x0050 }, /* R24 - Audio Interface 0 */
59 { 25, 0x0242 }, /* R25 - Audio Interface 1 */
60 { 26, 0x0008 }, /* R26 - Audio Interface 2 */
61 { 27, 0x0022 }, /* R27 - Audio Interface 3 */
62 { 30, 0x00C0 }, /* R30 - DAC Digital Volume Left */
63 { 31, 0x00C0 }, /* R31 - DAC Digital Volume Right */
64 { 32, 0x0000 }, /* R32 - DAC Digital 0 */
65 { 33, 0x0000 }, /* R33 - DAC Digital 1 */
66 { 36, 0x00C0 }, /* R36 - ADC Digital Volume Left */
67 { 37, 0x00C0 }, /* R37 - ADC Digital Volume Right */
68 { 38, 0x0000 }, /* R38 - ADC Digital 0 */
69 { 39, 0x0073 }, /* R39 - Digital Microphone 0 */
70 { 40, 0x09BF }, /* R40 - DRC 0 */
71 { 41, 0x3241 }, /* R41 - DRC 1 */
72 { 42, 0x0020 }, /* R42 - DRC 2 */
73 { 43, 0x0000 }, /* R43 - DRC 3 */
74 { 44, 0x0085 }, /* R44 - Analogue Left Input 0 */
75 { 45, 0x0085 }, /* R45 - Analogue Right Input 0 */
76 { 46, 0x0044 }, /* R46 - Analogue Left Input 1 */
77 { 47, 0x0044 }, /* R47 - Analogue Right Input 1 */
78 { 50, 0x0008 }, /* R50 - Analogue Left Mix 0 */
79 { 51, 0x0004 }, /* R51 - Analogue Right Mix 0 */
80 { 52, 0x0000 }, /* R52 - Analogue Spk Mix Left 0 */
81 { 53, 0x0000 }, /* R53 - Analogue Spk Mix Left 1 */
82 { 54, 0x0000 }, /* R54 - Analogue Spk Mix Right 0 */
83 { 55, 0x0000 }, /* R55 - Analogue Spk Mix Right 1 */
84 { 57, 0x002D }, /* R57 - Analogue OUT1 Left */
85 { 58, 0x002D }, /* R58 - Analogue OUT1 Right */
86 { 59, 0x0039 }, /* R59 - Analogue OUT2 Left */
87 { 60, 0x0039 }, /* R60 - Analogue OUT2 Right */
88 { 62, 0x0139 }, /* R62 - Analogue OUT3 Left */
89 { 63, 0x0139 }, /* R63 - Analogue OUT3 Right */
90 { 64, 0x0000 }, /* R65 - Analogue SPK Output Control 0 */
91 { 67, 0x0010 }, /* R67 - DC Servo 0 */
92 { 69, 0x00A4 }, /* R69 - DC Servo 2 */
93 { 90, 0x0000 }, /* R90 - Analogue HP 0 */
94 { 94, 0x0000 }, /* R94 - Analogue Lineout 0 */
95 { 98, 0x0000 }, /* R98 - Charge Pump 0 */
96 { 104, 0x0000 }, /* R104 - Class W 0 */
97 { 108, 0x0000 }, /* R108 - Write Sequencer 0 */
98 { 109, 0x0000 }, /* R109 - Write Sequencer 1 */
99 { 110, 0x0000 }, /* R110 - Write Sequencer 2 */
100 { 111, 0x0000 }, /* R111 - Write Sequencer 3 */
101 { 112, 0x0000 }, /* R112 - Write Sequencer 4 */
102 { 114, 0x0000 }, /* R114 - Control Interface */
103 { 116, 0x00A8 }, /* R116 - GPIO Control 1 */
104 { 117, 0x00A8 }, /* R117 - GPIO Control 2 */
105 { 118, 0x00A8 }, /* R118 - GPIO Control 3 */
106 { 119, 0x0220 }, /* R119 - GPIO Control 4 */
107 { 120, 0x01A0 }, /* R120 - GPIO Control 5 */
108 { 122, 0xFFFF }, /* R122 - Interrupt Status 1 Mask */
109 { 123, 0x0000 }, /* R123 - Interrupt Polarity 1 */
110 { 126, 0x0000 }, /* R126 - Interrupt Control */
111 { 129, 0x0000 }, /* R129 - Control Interface Test 1 */
112 { 149, 0x6810 }, /* R149 - Charge Pump Test 1 */
113 { 164, 0x0028 }, /* R164 - Clock Rate Test 4 */
114 { 172, 0x0000 }, /* R172 - Analogue Output Bias 0 */
f1c0a02f
MB		 115};
116
d58d5d55 117struct wm8903_priv {
c0eb27cf 118 struct wm8903_platform_data *pdata;
0bf79ef2 119 struct device *dev;
7cfe5617 120 struct snd_soc_codec *codec;
ee244ce4 121 struct regmap *regmap;
f0fba2ad 122
d58d5d55 123 int sysclk;
f0fba2ad 124 int irq;
d58d5d55 125
69fff9bb
MB		 126 int fs;
127 int deemph;
128
c5b6a9fe
MB		 129 int dcs_pending;
130 int dcs_cache[4];
131
f2c1fe09 132 /* Reference count */
d58d5d55 133 int class_w_users;
d58d5d55 134
7245387e
MB		 135 struct snd_soc_jack *mic_jack;
136 int mic_det;
137 int mic_short;
138 int mic_last_report;
139 int mic_delay;
7cfe5617
SW		 140
141#ifdef CONFIG_GPIOLIB
142 struct gpio_chip gpio_chip;
143#endif
d58d5d55
MB		 144};
145
ee244ce4
MB		 146static bool wm8903_readable_register(struct device *dev, unsigned int reg)
147{
148 switch (reg) {
149 case WM8903_SW_RESET_AND_ID:
150 case WM8903_REVISION_NUMBER:
151 case WM8903_BIAS_CONTROL_0:
152 case WM8903_VMID_CONTROL_0:
153 case WM8903_MIC_BIAS_CONTROL_0:
154 case WM8903_ANALOGUE_DAC_0:
155 case WM8903_ANALOGUE_ADC_0:
156 case WM8903_POWER_MANAGEMENT_0:
157 case WM8903_POWER_MANAGEMENT_1:
158 case WM8903_POWER_MANAGEMENT_2:
159 case WM8903_POWER_MANAGEMENT_3:
160 case WM8903_POWER_MANAGEMENT_4:
161 case WM8903_POWER_MANAGEMENT_5:
162 case WM8903_POWER_MANAGEMENT_6:
163 case WM8903_CLOCK_RATES_0:
164 case WM8903_CLOCK_RATES_1:
165 case WM8903_CLOCK_RATES_2:
166 case WM8903_AUDIO_INTERFACE_0:
167 case WM8903_AUDIO_INTERFACE_1:
168 case WM8903_AUDIO_INTERFACE_2:
169 case WM8903_AUDIO_INTERFACE_3:
170 case WM8903_DAC_DIGITAL_VOLUME_LEFT:
171 case WM8903_DAC_DIGITAL_VOLUME_RIGHT:
172 case WM8903_DAC_DIGITAL_0:
173 case WM8903_DAC_DIGITAL_1:
174 case WM8903_ADC_DIGITAL_VOLUME_LEFT:
175 case WM8903_ADC_DIGITAL_VOLUME_RIGHT:
176 case WM8903_ADC_DIGITAL_0:
177 case WM8903_DIGITAL_MICROPHONE_0:
178 case WM8903_DRC_0:
179 case WM8903_DRC_1:
180 case WM8903_DRC_2:
181 case WM8903_DRC_3:
182 case WM8903_ANALOGUE_LEFT_INPUT_0:
183 case WM8903_ANALOGUE_RIGHT_INPUT_0:
184 case WM8903_ANALOGUE_LEFT_INPUT_1:
185 case WM8903_ANALOGUE_RIGHT_INPUT_1:
186 case WM8903_ANALOGUE_LEFT_MIX_0:
187 case WM8903_ANALOGUE_RIGHT_MIX_0:
188 case WM8903_ANALOGUE_SPK_MIX_LEFT_0:
189 case WM8903_ANALOGUE_SPK_MIX_LEFT_1:
190 case WM8903_ANALOGUE_SPK_MIX_RIGHT_0:
191 case WM8903_ANALOGUE_SPK_MIX_RIGHT_1:
192 case WM8903_ANALOGUE_OUT1_LEFT:
193 case WM8903_ANALOGUE_OUT1_RIGHT:
194 case WM8903_ANALOGUE_OUT2_LEFT:
195 case WM8903_ANALOGUE_OUT2_RIGHT:
196 case WM8903_ANALOGUE_OUT3_LEFT:
197 case WM8903_ANALOGUE_OUT3_RIGHT:
198 case WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0:
199 case WM8903_DC_SERVO_0:
200 case WM8903_DC_SERVO_2:
201 case WM8903_DC_SERVO_READBACK_1:
202 case WM8903_DC_SERVO_READBACK_2:
203 case WM8903_DC_SERVO_READBACK_3:
204 case WM8903_DC_SERVO_READBACK_4:
205 case WM8903_ANALOGUE_HP_0:
206 case WM8903_ANALOGUE_LINEOUT_0:
207 case WM8903_CHARGE_PUMP_0:
208 case WM8903_CLASS_W_0:
209 case WM8903_WRITE_SEQUENCER_0:
210 case WM8903_WRITE_SEQUENCER_1:
211 case WM8903_WRITE_SEQUENCER_2:
212 case WM8903_WRITE_SEQUENCER_3:
213 case WM8903_WRITE_SEQUENCER_4:
214 case WM8903_CONTROL_INTERFACE:
215 case WM8903_GPIO_CONTROL_1:
216 case WM8903_GPIO_CONTROL_2:
217 case WM8903_GPIO_CONTROL_3:
218 case WM8903_GPIO_CONTROL_4:
219 case WM8903_GPIO_CONTROL_5:
220 case WM8903_INTERRUPT_STATUS_1:
221 case WM8903_INTERRUPT_STATUS_1_MASK:
222 case WM8903_INTERRUPT_POLARITY_1:
223 case WM8903_INTERRUPT_CONTROL:
224 case WM8903_CLOCK_RATE_TEST_4:
225 case WM8903_ANALOGUE_OUTPUT_BIAS_0:
226 return true;
227 default:
228 return false;
229 }
230}
231
232static bool wm8903_volatile_register(struct device *dev, unsigned int reg)
f1c0a02f
MB		 233{
234 switch (reg) {
235 case WM8903_SW_RESET_AND_ID:
236 case WM8903_REVISION_NUMBER:
237 case WM8903_INTERRUPT_STATUS_1:
238 case WM8903_WRITE_SEQUENCER_4:
c5b6a9fe
MB		 239 case WM8903_DC_SERVO_READBACK_1:
240 case WM8903_DC_SERVO_READBACK_2:
241 case WM8903_DC_SERVO_READBACK_3:
242 case WM8903_DC_SERVO_READBACK_4:
8d50e447 243 return 1;
f1c0a02f
MB		 244
245 default:
f1c0a02f 246 return 0;
8d50e447 247 }
f1c0a02f
MB		 248}
249
42768a12
MB		 250static int wm8903_cp_event(struct snd_soc_dapm_widget *w,
251 struct snd_kcontrol *kcontrol, int event)
252{
253 WARN_ON(event != SND_SOC_DAPM_POST_PMU);
254 mdelay(4);
255
256 return 0;
257}
258
c5b6a9fe
MB		 259static int wm8903_dcs_event(struct snd_soc_dapm_widget *w,
260 struct snd_kcontrol *kcontrol, int event)
261{
262 struct snd_soc_codec *codec = w->codec;
263 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
264
265 switch (event) {
266 case SND_SOC_DAPM_POST_PMU:
267 wm8903->dcs_pending |= 1 << w->shift;
268 break;
269 case SND_SOC_DAPM_PRE_PMD:
270 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
271 1 << w->shift, 0);
272 break;
273 }
274
275 return 0;
276}
277
278#define WM8903_DCS_MODE_WRITE_STOP 0
279#define WM8903_DCS_MODE_START_STOP 2
280
281static void wm8903_seq_notifier(struct snd_soc_dapm_context *dapm,
282 enum snd_soc_dapm_type event, int subseq)
283{
e73a2571 284 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(dapm);
c5b6a9fe
MB		 285 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
286 int dcs_mode = WM8903_DCS_MODE_WRITE_STOP;
287 int i, val;
288
289 /* Complete any pending DC servo starts */
290 if (wm8903->dcs_pending) {
291 dev_dbg(codec->dev, "Starting DC servo for %x\n",
292 wm8903->dcs_pending);
293
294 /* If we've no cached values then we need to do startup */
295 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
296 if (!(wm8903->dcs_pending & (1 << i)))
297 continue;
298
299 if (wm8903->dcs_cache[i]) {
300 dev_dbg(codec->dev,
301 "Restore DC servo %d value %x\n",
302 3 - i, wm8903->dcs_cache[i]);
303
304 snd_soc_write(codec, WM8903_DC_SERVO_4 + i,
305 wm8903->dcs_cache[i] & 0xff);
306 } else {
307 dev_dbg(codec->dev,
308 "Calibrate DC servo %d\n", 3 - i);
309 dcs_mode = WM8903_DCS_MODE_START_STOP;
310 }
311 }
312
313 /* Don't trust the cache for analogue */
314 if (wm8903->class_w_users)
315 dcs_mode = WM8903_DCS_MODE_START_STOP;
316
317 snd_soc_update_bits(codec, WM8903_DC_SERVO_2,
318 WM8903_DCS_MODE_MASK, dcs_mode);
319
320 snd_soc_update_bits(codec, WM8903_DC_SERVO_0,
321 WM8903_DCS_ENA_MASK, wm8903->dcs_pending);
322
323 switch (dcs_mode) {
324 case WM8903_DCS_MODE_WRITE_STOP:
325 break;
326
327 case WM8903_DCS_MODE_START_STOP:
328 msleep(270);
329
330 /* Cache the measured offsets for digital */
331 if (wm8903->class_w_users)
332 break;
333
334 for (i = 0; i < ARRAY_SIZE(wm8903->dcs_cache); i++) {
335 if (!(wm8903->dcs_pending & (1 << i)))
336 continue;
337
338 val = snd_soc_read(codec,
339 WM8903_DC_SERVO_READBACK_1 + i);
340 dev_dbg(codec->dev, "DC servo %d: %x\n",
341 3 - i, val);
342 wm8903->dcs_cache[i] = val;
343 }
344 break;
345
346 default:
347 pr_warn("DCS mode %d delay not set\n", dcs_mode);
348 break;
349 }
350
351 wm8903->dcs_pending = 0;
352 }
353}
354
f1c0a02f
MB		 355/*
356 * When used with DAC outputs only the WM8903 charge pump supports
357 * operation in class W mode, providing very low power consumption
358 * when used with digital sources. Enable and disable this mode
359 * automatically depending on the mixer configuration.
360 *
361 * All the relevant controls are simple switches.
362 */
363static int wm8903_class_w_put(struct snd_kcontrol *kcontrol,
364 struct snd_ctl_elem_value *ucontrol)
365{
eee5d7f9 366 struct snd_soc_codec *codec = snd_soc_dapm_kcontrol_codec(kcontrol);
b2c812e2 367 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 368 u16 reg;
369 int ret;
370
8d50e447 371 reg = snd_soc_read(codec, WM8903_CLASS_W_0);
f1c0a02f
MB		 372
373 /* Turn it off if we're about to enable bypass */
374 if (ucontrol->value.integer.value[0]) {
375 if (wm8903->class_w_users == 0) {
f0fba2ad 376 dev_dbg(codec->dev, "Disabling Class W\n");
8d50e447 377 snd_soc_write(codec, WM8903_CLASS_W_0, reg &
f1c0a02f
MB		 378 ~(WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V));
379 }
380 wm8903->class_w_users++;
381 }
382
383 /* Implement the change */
384 ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
385
386 /* If we've just disabled the last bypass path turn Class W on */
387 if (!ucontrol->value.integer.value[0]) {
388 if (wm8903->class_w_users == 1) {
f0fba2ad 389 dev_dbg(codec->dev, "Enabling Class W\n");
8d50e447 390 snd_soc_write(codec, WM8903_CLASS_W_0, reg |
f1c0a02f
MB		 391 WM8903_CP_DYN_FREQ | WM8903_CP_DYN_V);
392 }
393 wm8903->class_w_users--;
394 }
395
f0fba2ad 396 dev_dbg(codec->dev, "Bypass use count now %d\n",
f1c0a02f
MB		 397 wm8903->class_w_users);
398
399 return ret;
400}
401
402#define SOC_DAPM_SINGLE_W(xname, reg, shift, max, invert) \
ea3583d0
LPC		 403 SOC_SINGLE_EXT(xname, reg, shift, max, invert, \
404 snd_soc_dapm_get_volsw, wm8903_class_w_put)
f1c0a02f
MB		 405
406
69fff9bb
MB		 407static int wm8903_deemph[] = { 0, 32000, 44100, 48000 };
408
409static int wm8903_set_deemph(struct snd_soc_codec *codec)
410{
411 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
412 int val, i, best;
413
414 /* If we're using deemphasis select the nearest available sample
415 * rate.
416 */
417 if (wm8903->deemph) {
418 best = 1;
419 for (i = 2; i < ARRAY_SIZE(wm8903_deemph); i++) {
420 if (abs(wm8903_deemph[i] - wm8903->fs) <
421 abs(wm8903_deemph[best] - wm8903->fs))
422 best = i;
423 }
424
425 val = best << WM8903_DEEMPH_SHIFT;
426 } else {
427 best = 0;
428 val = 0;
429 }
430
431 dev_dbg(codec->dev, "Set deemphasis %d (%dHz)\n",
432 best, wm8903_deemph[best]);
433
434 return snd_soc_update_bits(codec, WM8903_DAC_DIGITAL_1,
435 WM8903_DEEMPH_MASK, val);
436}
437
438static int wm8903_get_deemph(struct snd_kcontrol *kcontrol,
439 struct snd_ctl_elem_value *ucontrol)
440{
ea53bf77 441 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
69fff9bb
MB		 442 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
443
444 ucontrol->value.enumerated.item[0] = wm8903->deemph;
445
446 return 0;
447}
448
449static int wm8903_put_deemph(struct snd_kcontrol *kcontrol,
450 struct snd_ctl_elem_value *ucontrol)
451{
ea53bf77 452 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
69fff9bb
MB		 453 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
454 int deemph = ucontrol->value.enumerated.item[0];
455 int ret = 0;
456
457 if (deemph > 1)
458 return -EINVAL;
459
460 mutex_lock(&codec->mutex);
461 if (wm8903->deemph != deemph) {
462 wm8903->deemph = deemph;
463
464 wm8903_set_deemph(codec);
465
466 ret = 1;
467 }
468 mutex_unlock(&codec->mutex);
469
470 return ret;
471}
472
f1c0a02f
MB		 473/* ALSA can only do steps of .01dB */
474static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
475
00aa0fac
AB		 476static const DECLARE_TLV_DB_SCALE(dac_boost_tlv, 0, 600, 0);
477
291ce18c 478static const DECLARE_TLV_DB_SCALE(digital_sidetone_tlv, -3600, 300, 0);
f1c0a02f
MB		 479static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
480
481static const DECLARE_TLV_DB_SCALE(drc_tlv_thresh, 0, 75, 0);
482static const DECLARE_TLV_DB_SCALE(drc_tlv_amp, -2250, 75, 0);
483static const DECLARE_TLV_DB_SCALE(drc_tlv_min, 0, 600, 0);
484static const DECLARE_TLV_DB_SCALE(drc_tlv_max, 1200, 600, 0);
485static const DECLARE_TLV_DB_SCALE(drc_tlv_startup, -300, 50, 0);
486
460f4aae
MB		 487static const char *hpf_mode_text[] = {
488 "Hi-fi", "Voice 1", "Voice 2", "Voice 3"
489};
490
a21bc5c5
TI		 491static SOC_ENUM_SINGLE_DECL(hpf_mode,
492 WM8903_ADC_DIGITAL_0, 5, hpf_mode_text);
460f4aae 493
dcf9ada3
MB		 494static const char *osr_text[] = {
495 "Low power", "High performance"
496};
497
a21bc5c5
TI		 498static SOC_ENUM_SINGLE_DECL(adc_osr,
499 WM8903_ANALOGUE_ADC_0, 0, osr_text);
dcf9ada3 500
a21bc5c5
TI		 501static SOC_ENUM_SINGLE_DECL(dac_osr,
502 WM8903_DAC_DIGITAL_1, 0, osr_text);
dcf9ada3 503
f1c0a02f
MB		 504static const char *drc_slope_text[] = {
505 "1", "1/2", "1/4", "1/8", "1/16", "0"
506};
507
a21bc5c5
TI		 508static SOC_ENUM_SINGLE_DECL(drc_slope_r0,
509 WM8903_DRC_2, 3, drc_slope_text);
f1c0a02f 510
a21bc5c5
TI		 511static SOC_ENUM_SINGLE_DECL(drc_slope_r1,
512 WM8903_DRC_2, 0, drc_slope_text);
f1c0a02f
MB		 513
514static const char *drc_attack_text[] = {
515 "instantaneous",
516 "363us", "762us", "1.45ms", "2.9ms", "5.8ms", "11.6ms", "23.2ms",
517 "46.4ms", "92.8ms", "185.6ms"
518};
519
a21bc5c5
TI		 520static SOC_ENUM_SINGLE_DECL(drc_attack,
521 WM8903_DRC_1, 12, drc_attack_text);
f1c0a02f
MB		 522
523static const char *drc_decay_text[] = {
524 "186ms", "372ms", "743ms", "1.49s", "2.97s", "5.94s", "11.89s",
525 "23.87s", "47.56s"
526};
527
a21bc5c5
TI		 528static SOC_ENUM_SINGLE_DECL(drc_decay,
529 WM8903_DRC_1, 8, drc_decay_text);
f1c0a02f
MB		 530
531static const char *drc_ff_delay_text[] = {
532 "5 samples", "9 samples"
533};
534
a21bc5c5
TI		 535static SOC_ENUM_SINGLE_DECL(drc_ff_delay,
536 WM8903_DRC_0, 5, drc_ff_delay_text);
f1c0a02f
MB		 537
538static const char *drc_qr_decay_text[] = {
539 "0.725ms", "1.45ms", "5.8ms"
540};
541
a21bc5c5
TI		 542static SOC_ENUM_SINGLE_DECL(drc_qr_decay,
543 WM8903_DRC_1, 4, drc_qr_decay_text);
f1c0a02f
MB		 544
545static const char *drc_smoothing_text[] = {
546 "Low", "Medium", "High"
547};
548
a21bc5c5
TI		 549static SOC_ENUM_SINGLE_DECL(drc_smoothing,
550 WM8903_DRC_0, 11, drc_smoothing_text);
f1c0a02f
MB		 551
552static const char *soft_mute_text[] = {
553 "Fast (fs/2)", "Slow (fs/32)"
554};
555
a21bc5c5
TI		 556static SOC_ENUM_SINGLE_DECL(soft_mute,
557 WM8903_DAC_DIGITAL_1, 10, soft_mute_text);
f1c0a02f
MB		 558
559static const char *mute_mode_text[] = {
560 "Hard", "Soft"
561};
562
a21bc5c5
TI		 563static SOC_ENUM_SINGLE_DECL(mute_mode,
564 WM8903_DAC_DIGITAL_1, 9, mute_mode_text);
f1c0a02f 565
f1c0a02f
MB		 566static const char *companding_text[] = {
567 "ulaw", "alaw"
568};
569
a21bc5c5
TI		 570static SOC_ENUM_SINGLE_DECL(dac_companding,
571 WM8903_AUDIO_INTERFACE_0, 0, companding_text);
f1c0a02f 572
a21bc5c5
TI		 573static SOC_ENUM_SINGLE_DECL(adc_companding,
574 WM8903_AUDIO_INTERFACE_0, 2, companding_text);
f1c0a02f
MB		 575
576static const char *input_mode_text[] = {
577 "Single-Ended", "Differential Line", "Differential Mic"
578};
579
a21bc5c5
TI		 580static SOC_ENUM_SINGLE_DECL(linput_mode_enum,
581 WM8903_ANALOGUE_LEFT_INPUT_1, 0, input_mode_text);
f1c0a02f 582
a21bc5c5
TI		 583static SOC_ENUM_SINGLE_DECL(rinput_mode_enum,
584 WM8903_ANALOGUE_RIGHT_INPUT_1, 0, input_mode_text);
f1c0a02f
MB		 585
586static const char *linput_mux_text[] = {
587 "IN1L", "IN2L", "IN3L"
588};
589
a21bc5c5
TI		 590static SOC_ENUM_SINGLE_DECL(linput_enum,
591 WM8903_ANALOGUE_LEFT_INPUT_1, 2, linput_mux_text);
f1c0a02f 592
a21bc5c5
TI		 593static SOC_ENUM_SINGLE_DECL(linput_inv_enum,
594 WM8903_ANALOGUE_LEFT_INPUT_1, 4, linput_mux_text);
f1c0a02f
MB		 595
596static const char *rinput_mux_text[] = {
597 "IN1R", "IN2R", "IN3R"
598};
599
a21bc5c5
TI		 600static SOC_ENUM_SINGLE_DECL(rinput_enum,
601 WM8903_ANALOGUE_RIGHT_INPUT_1, 2, rinput_mux_text);
f1c0a02f 602
a21bc5c5
TI		 603static SOC_ENUM_SINGLE_DECL(rinput_inv_enum,
604 WM8903_ANALOGUE_RIGHT_INPUT_1, 4, rinput_mux_text);
f1c0a02f
MB		 605
606
291ce18c
MB		 607static const char *sidetone_text[] = {
608 "None", "Left", "Right"
609};
610
a21bc5c5
TI		 611static SOC_ENUM_SINGLE_DECL(lsidetone_enum,
612 WM8903_DAC_DIGITAL_0, 2, sidetone_text);
291ce18c 613
a21bc5c5
TI		 614static SOC_ENUM_SINGLE_DECL(rsidetone_enum,
615 WM8903_DAC_DIGITAL_0, 0, sidetone_text);
291ce18c 616
97945c46
SW		 617static const char *adcinput_text[] = {
618 "ADC", "DMIC"
619};
620
a21bc5c5
TI		 621static SOC_ENUM_SINGLE_DECL(adcinput_enum,
622 WM8903_CLOCK_RATE_TEST_4, 9, adcinput_text);
97945c46 623
1e113bf9
MB		 624static const char *aif_text[] = {
625 "Left", "Right"
626};
627
a21bc5c5
TI		 628static SOC_ENUM_SINGLE_DECL(lcapture_enum,
629 WM8903_AUDIO_INTERFACE_0, 7, aif_text);
1e113bf9 630
a21bc5c5
TI		 631static SOC_ENUM_SINGLE_DECL(rcapture_enum,
632 WM8903_AUDIO_INTERFACE_0, 6, aif_text);
1e113bf9 633
a21bc5c5
TI		 634static SOC_ENUM_SINGLE_DECL(lplay_enum,
635 WM8903_AUDIO_INTERFACE_0, 5, aif_text);
1e113bf9 636
a21bc5c5
TI		 637static SOC_ENUM_SINGLE_DECL(rplay_enum,
638 WM8903_AUDIO_INTERFACE_0, 4, aif_text);
1e113bf9 639
f1c0a02f
MB		 640static const struct snd_kcontrol_new wm8903_snd_controls[] = {
641
642/* Input PGAs - No TLV since the scale depends on PGA mode */
643SOC_SINGLE("Left Input PGA Switch", WM8903_ANALOGUE_LEFT_INPUT_0,
5715952b 644 7, 1, 1),
f1c0a02f
MB		 645SOC_SINGLE("Left Input PGA Volume", WM8903_ANALOGUE_LEFT_INPUT_0,
646 0, 31, 0),
647SOC_SINGLE("Left Input PGA Common Mode Switch", WM8903_ANALOGUE_LEFT_INPUT_1,
648 6, 1, 0),
649
650SOC_SINGLE("Right Input PGA Switch", WM8903_ANALOGUE_RIGHT_INPUT_0,
5715952b 651 7, 1, 1),
f1c0a02f
MB		 652SOC_SINGLE("Right Input PGA Volume", WM8903_ANALOGUE_RIGHT_INPUT_0,
653 0, 31, 0),
654SOC_SINGLE("Right Input PGA Common Mode Switch", WM8903_ANALOGUE_RIGHT_INPUT_1,
655 6, 1, 0),
656
657/* ADCs */
dcf9ada3 658SOC_ENUM("ADC OSR", adc_osr),
460f4aae
MB		 659SOC_SINGLE("HPF Switch", WM8903_ADC_DIGITAL_0, 4, 1, 0),
660SOC_ENUM("HPF Mode", hpf_mode),
f1c0a02f
MB		 661SOC_SINGLE("DRC Switch", WM8903_DRC_0, 15, 1, 0),
662SOC_ENUM("DRC Compressor Slope R0", drc_slope_r0),
663SOC_ENUM("DRC Compressor Slope R1", drc_slope_r1),
af901ca1 664SOC_SINGLE_TLV("DRC Compressor Threshold Volume", WM8903_DRC_3, 5, 124, 1,
f1c0a02f
MB		 665 drc_tlv_thresh),
666SOC_SINGLE_TLV("DRC Volume", WM8903_DRC_3, 0, 30, 1, drc_tlv_amp),
667SOC_SINGLE_TLV("DRC Minimum Gain Volume", WM8903_DRC_1, 2, 3, 1, drc_tlv_min),
668SOC_SINGLE_TLV("DRC Maximum Gain Volume", WM8903_DRC_1, 0, 3, 0, drc_tlv_max),
669SOC_ENUM("DRC Attack Rate", drc_attack),
670SOC_ENUM("DRC Decay Rate", drc_decay),
671SOC_ENUM("DRC FF Delay", drc_ff_delay),
672SOC_SINGLE("DRC Anticlip Switch", WM8903_DRC_0, 1, 1, 0),
673SOC_SINGLE("DRC QR Switch", WM8903_DRC_0, 2, 1, 0),
af901ca1 674SOC_SINGLE_TLV("DRC QR Threshold Volume", WM8903_DRC_0, 6, 3, 0, drc_tlv_max),
f1c0a02f
MB		 675SOC_ENUM("DRC QR Decay Rate", drc_qr_decay),
676SOC_SINGLE("DRC Smoothing Switch", WM8903_DRC_0, 3, 1, 0),
677SOC_SINGLE("DRC Smoothing Hysteresis Switch", WM8903_DRC_0, 0, 1, 0),
af901ca1 678SOC_ENUM("DRC Smoothing Threshold", drc_smoothing),
f1c0a02f
MB		 679SOC_SINGLE_TLV("DRC Startup Volume", WM8903_DRC_0, 6, 18, 0, drc_tlv_startup),
680
681SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8903_ADC_DIGITAL_VOLUME_LEFT,
61bf35b9 682 WM8903_ADC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
f1c0a02f
MB		 683SOC_ENUM("ADC Companding Mode", adc_companding),
684SOC_SINGLE("ADC Companding Switch", WM8903_AUDIO_INTERFACE_0, 3, 1, 0),
685
291ce18c
MB		 686SOC_DOUBLE_TLV("Digital Sidetone Volume", WM8903_DAC_DIGITAL_0, 4, 8,
687 12, 0, digital_sidetone_tlv),
688
f1c0a02f 689/* DAC */
dcf9ada3 690SOC_ENUM("DAC OSR", dac_osr),
f1c0a02f
MB		 691SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8903_DAC_DIGITAL_VOLUME_LEFT,
692 WM8903_DAC_DIGITAL_VOLUME_RIGHT, 1, 120, 0, digital_tlv),
693SOC_ENUM("DAC Soft Mute Rate", soft_mute),
694SOC_ENUM("DAC Mute Mode", mute_mode),
695SOC_SINGLE("DAC Mono Switch", WM8903_DAC_DIGITAL_1, 12, 1, 0),
f1c0a02f
MB		 696SOC_ENUM("DAC Companding Mode", dac_companding),
697SOC_SINGLE("DAC Companding Switch", WM8903_AUDIO_INTERFACE_0, 1, 1, 0),
00aa0fac
AB		 698SOC_SINGLE_TLV("DAC Boost Volume", WM8903_AUDIO_INTERFACE_0, 9, 3, 0,
699 dac_boost_tlv),
69fff9bb
MB		 700SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
701 wm8903_get_deemph, wm8903_put_deemph),
f1c0a02f
MB		 702
703/* Headphones */
704SOC_DOUBLE_R("Headphone Switch",
705 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
706 8, 1, 1),
707SOC_DOUBLE_R("Headphone ZC Switch",
708 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
709 6, 1, 0),
710SOC_DOUBLE_R_TLV("Headphone Volume",
711 WM8903_ANALOGUE_OUT1_LEFT, WM8903_ANALOGUE_OUT1_RIGHT,
712 0, 63, 0, out_tlv),
713
714/* Line out */
715SOC_DOUBLE_R("Line Out Switch",
716 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
717 8, 1, 1),
718SOC_DOUBLE_R("Line Out ZC Switch",
719 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
720 6, 1, 0),
721SOC_DOUBLE_R_TLV("Line Out Volume",
722 WM8903_ANALOGUE_OUT2_LEFT, WM8903_ANALOGUE_OUT2_RIGHT,
723 0, 63, 0, out_tlv),
724
725/* Speaker */
726SOC_DOUBLE_R("Speaker Switch",
727 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 8, 1, 1),
728SOC_DOUBLE_R("Speaker ZC Switch",
729 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT, 6, 1, 0),
730SOC_DOUBLE_R_TLV("Speaker Volume",
731 WM8903_ANALOGUE_OUT3_LEFT, WM8903_ANALOGUE_OUT3_RIGHT,
732 0, 63, 0, out_tlv),
733};
734
f1c0a02f
MB		 735static const struct snd_kcontrol_new linput_mode_mux =
736 SOC_DAPM_ENUM("Left Input Mode Mux", linput_mode_enum);
737
738static const struct snd_kcontrol_new rinput_mode_mux =
739 SOC_DAPM_ENUM("Right Input Mode Mux", rinput_mode_enum);
740
741static const struct snd_kcontrol_new linput_mux =
742 SOC_DAPM_ENUM("Left Input Mux", linput_enum);
743
744static const struct snd_kcontrol_new linput_inv_mux =
745 SOC_DAPM_ENUM("Left Inverting Input Mux", linput_inv_enum);
746
747static const struct snd_kcontrol_new rinput_mux =
748 SOC_DAPM_ENUM("Right Input Mux", rinput_enum);
749
750static const struct snd_kcontrol_new rinput_inv_mux =
751 SOC_DAPM_ENUM("Right Inverting Input Mux", rinput_inv_enum);
752
291ce18c
MB		 753static const struct snd_kcontrol_new lsidetone_mux =
754 SOC_DAPM_ENUM("DACL Sidetone Mux", lsidetone_enum);
755
756static const struct snd_kcontrol_new rsidetone_mux =
757 SOC_DAPM_ENUM("DACR Sidetone Mux", rsidetone_enum);
758
97945c46
SW		 759static const struct snd_kcontrol_new adcinput_mux =
760 SOC_DAPM_ENUM("ADC Input", adcinput_enum);
761
1e113bf9
MB		 762static const struct snd_kcontrol_new lcapture_mux =
763 SOC_DAPM_ENUM("Left Capture Mux", lcapture_enum);
764
765static const struct snd_kcontrol_new rcapture_mux =
766 SOC_DAPM_ENUM("Right Capture Mux", rcapture_enum);
767
768static const struct snd_kcontrol_new lplay_mux =
769 SOC_DAPM_ENUM("Left Playback Mux", lplay_enum);
770
771static const struct snd_kcontrol_new rplay_mux =
772 SOC_DAPM_ENUM("Right Playback Mux", rplay_enum);
773
f1c0a02f
MB		 774static const struct snd_kcontrol_new left_output_mixer[] = {
775SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_LEFT_MIX_0, 3, 1, 0),
776SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_LEFT_MIX_0, 2, 1, 0),
777SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 1, 1, 0),
4b4fffdd 778SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_LEFT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 779};
780
781static const struct snd_kcontrol_new right_output_mixer[] = {
782SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 3, 1, 0),
783SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 2, 1, 0),
784SOC_DAPM_SINGLE_W("Left Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 1, 1, 0),
4b4fffdd 785SOC_DAPM_SINGLE_W("Right Bypass Switch", WM8903_ANALOGUE_RIGHT_MIX_0, 0, 1, 0),
f1c0a02f
MB		 786};
787
788static const struct snd_kcontrol_new left_speaker_mixer[] = {
789SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 3, 1, 0),
790SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 2, 1, 0),
791SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0, 1, 1, 0),
792SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_LEFT_0,
4b4fffdd 793 0, 1, 0),
f1c0a02f
MB		 794};
795
796static const struct snd_kcontrol_new right_speaker_mixer[] = {
797SOC_DAPM_SINGLE("DACL Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 3, 1, 0),
798SOC_DAPM_SINGLE("DACR Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0, 2, 1, 0),
799SOC_DAPM_SINGLE("Left Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
800 1, 1, 0),
801SOC_DAPM_SINGLE("Right Bypass Switch", WM8903_ANALOGUE_SPK_MIX_RIGHT_0,
4b4fffdd 802 0, 1, 0),
f1c0a02f
MB		 803};
804
805static const struct snd_soc_dapm_widget wm8903_dapm_widgets[] = {
806SND_SOC_DAPM_INPUT("IN1L"),
807SND_SOC_DAPM_INPUT("IN1R"),
808SND_SOC_DAPM_INPUT("IN2L"),
809SND_SOC_DAPM_INPUT("IN2R"),
810SND_SOC_DAPM_INPUT("IN3L"),
811SND_SOC_DAPM_INPUT("IN3R"),
97945c46 812SND_SOC_DAPM_INPUT("DMICDAT"),
f1c0a02f
MB		 813
814SND_SOC_DAPM_OUTPUT("HPOUTL"),
815SND_SOC_DAPM_OUTPUT("HPOUTR"),
816SND_SOC_DAPM_OUTPUT("LINEOUTL"),
817SND_SOC_DAPM_OUTPUT("LINEOUTR"),
818SND_SOC_DAPM_OUTPUT("LOP"),
819SND_SOC_DAPM_OUTPUT("LON"),
820SND_SOC_DAPM_OUTPUT("ROP"),
821SND_SOC_DAPM_OUTPUT("RON"),
822
5032dc34 823SND_SOC_DAPM_SUPPLY("MICBIAS", WM8903_MIC_BIAS_CONTROL_0, 0, 0, NULL, 0),
f1c0a02f
MB		 824
825SND_SOC_DAPM_MUX("Left Input Mux", SND_SOC_NOPM, 0, 0, &linput_mux),
826SND_SOC_DAPM_MUX("Left Input Inverting Mux", SND_SOC_NOPM, 0, 0,
827 &linput_inv_mux),
828SND_SOC_DAPM_MUX("Left Input Mode Mux", SND_SOC_NOPM, 0, 0, &linput_mode_mux),
829
830SND_SOC_DAPM_MUX("Right Input Mux", SND_SOC_NOPM, 0, 0, &rinput_mux),
831SND_SOC_DAPM_MUX("Right Input Inverting Mux", SND_SOC_NOPM, 0, 0,
832 &rinput_inv_mux),
833SND_SOC_DAPM_MUX("Right Input Mode Mux", SND_SOC_NOPM, 0, 0, &rinput_mode_mux),
834
835SND_SOC_DAPM_PGA("Left Input PGA", WM8903_POWER_MANAGEMENT_0, 1, 0, NULL, 0),
836SND_SOC_DAPM_PGA("Right Input PGA", WM8903_POWER_MANAGEMENT_0, 0, 0, NULL, 0),
837
97945c46
SW		 838SND_SOC_DAPM_MUX("Left ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
839SND_SOC_DAPM_MUX("Right ADC Input", SND_SOC_NOPM, 0, 0, &adcinput_mux),
840
1e113bf9
MB		 841SND_SOC_DAPM_ADC("ADCL", NULL, WM8903_POWER_MANAGEMENT_6, 1, 0),
842SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
843
844SND_SOC_DAPM_MUX("Left Capture Mux", SND_SOC_NOPM, 0, 0, &lcapture_mux),
845SND_SOC_DAPM_MUX("Right Capture Mux", SND_SOC_NOPM, 0, 0, &rcapture_mux),
846
847SND_SOC_DAPM_AIF_OUT("AIFTXL", "Left HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
848SND_SOC_DAPM_AIF_OUT("AIFTXR", "Right HiFi Capture", 0, SND_SOC_NOPM, 0, 0),
f1c0a02f 849
291ce18c
MB		 850SND_SOC_DAPM_MUX("DACL Sidetone", SND_SOC_NOPM, 0, 0, &lsidetone_mux),
851SND_SOC_DAPM_MUX("DACR Sidetone", SND_SOC_NOPM, 0, 0, &rsidetone_mux),
852
1e113bf9
MB		 853SND_SOC_DAPM_AIF_IN("AIFRXL", "Left Playback", 0, SND_SOC_NOPM, 0, 0),
854SND_SOC_DAPM_AIF_IN("AIFRXR", "Right Playback", 0, SND_SOC_NOPM, 0, 0),
855
856SND_SOC_DAPM_MUX("Left Playback Mux", SND_SOC_NOPM, 0, 0, &lplay_mux),
857SND_SOC_DAPM_MUX("Right Playback Mux", SND_SOC_NOPM, 0, 0, &rplay_mux),
858
859SND_SOC_DAPM_DAC("DACL", NULL, WM8903_POWER_MANAGEMENT_6, 3, 0),
860SND_SOC_DAPM_DAC("DACR", NULL, WM8903_POWER_MANAGEMENT_6, 2, 0),
f1c0a02f
MB		 861
862SND_SOC_DAPM_MIXER("Left Output Mixer", WM8903_POWER_MANAGEMENT_1, 1, 0,
863 left_output_mixer, ARRAY_SIZE(left_output_mixer)),
864SND_SOC_DAPM_MIXER("Right Output Mixer", WM8903_POWER_MANAGEMENT_1, 0, 0,
865 right_output_mixer, ARRAY_SIZE(right_output_mixer)),
866
867SND_SOC_DAPM_MIXER("Left Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 1, 0,
868 left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
869SND_SOC_DAPM_MIXER("Right Speaker Mixer", WM8903_POWER_MANAGEMENT_4, 0, 0,
870 right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
871
1b877cb5
DL		 872SND_SOC_DAPM_PGA_S("Left Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
873 1, 0, NULL, 0),
874SND_SOC_DAPM_PGA_S("Right Headphone Output PGA", 0, WM8903_POWER_MANAGEMENT_2,
13a9983e
MB		 875 0, 0, NULL, 0),
876
1b877cb5 877SND_SOC_DAPM_PGA_S("Left Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 1, 0,
13a9983e 878 NULL, 0),
1b877cb5 879SND_SOC_DAPM_PGA_S("Right Line Output PGA", 0, WM8903_POWER_MANAGEMENT_3, 0, 0,
13a9983e
MB		 880 NULL, 0),
881
882SND_SOC_DAPM_PGA_S("HPL_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 7, 0, NULL, 0),
883SND_SOC_DAPM_PGA_S("HPL_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 6, 0, NULL, 0),
1b877cb5
DL		 884SND_SOC_DAPM_PGA_S("HPL_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 5, 0, NULL, 0),
885SND_SOC_DAPM_PGA_S("HPL_ENA", 1, WM8903_ANALOGUE_HP_0, 4, 0, NULL, 0),
13a9983e
MB		 886SND_SOC_DAPM_PGA_S("HPR_RMV_SHORT", 4, WM8903_ANALOGUE_HP_0, 3, 0, NULL, 0),
887SND_SOC_DAPM_PGA_S("HPR_ENA_OUTP", 3, WM8903_ANALOGUE_HP_0, 2, 0, NULL, 0),
1b877cb5
DL		 888SND_SOC_DAPM_PGA_S("HPR_ENA_DLY", 2, WM8903_ANALOGUE_HP_0, 1, 0, NULL, 0),
889SND_SOC_DAPM_PGA_S("HPR_ENA", 1, WM8903_ANALOGUE_HP_0, 0, 0, NULL, 0),
13a9983e
MB		 890
891SND_SOC_DAPM_PGA_S("LINEOUTL_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 7, 0,
892 NULL, 0),
893SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 6, 0,
894 NULL, 0),
1b877cb5
DL		 895SND_SOC_DAPM_PGA_S("LINEOUTL_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 5, 0,
896 NULL, 0),
897SND_SOC_DAPM_PGA_S("LINEOUTL_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 4, 0,
13a9983e
MB		 898 NULL, 0),
899SND_SOC_DAPM_PGA_S("LINEOUTR_RMV_SHORT", 4, WM8903_ANALOGUE_LINEOUT_0, 3, 0,
900 NULL, 0),
901SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_OUTP", 3, WM8903_ANALOGUE_LINEOUT_0, 2, 0,
902 NULL, 0),
1b877cb5
DL		 903SND_SOC_DAPM_PGA_S("LINEOUTR_ENA_DLY", 2, WM8903_ANALOGUE_LINEOUT_0, 1, 0,
904 NULL, 0),
905SND_SOC_DAPM_PGA_S("LINEOUTR_ENA", 1, WM8903_ANALOGUE_LINEOUT_0, 0, 0,
13a9983e
MB		 906 NULL, 0),
907
c5b6a9fe
MB		 908SND_SOC_DAPM_SUPPLY("DCS Master", WM8903_DC_SERVO_0, 4, 0, NULL, 0),
909SND_SOC_DAPM_PGA_S("HPL_DCS", 3, SND_SOC_NOPM, 3, 0, wm8903_dcs_event,
910 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
911SND_SOC_DAPM_PGA_S("HPR_DCS", 3, SND_SOC_NOPM, 2, 0, wm8903_dcs_event,
912 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
913SND_SOC_DAPM_PGA_S("LINEOUTL_DCS", 3, SND_SOC_NOPM, 1, 0, wm8903_dcs_event,
914 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
915SND_SOC_DAPM_PGA_S("LINEOUTR_DCS", 3, SND_SOC_NOPM, 0, 0, wm8903_dcs_event,
916 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
f1c0a02f
MB		 917
918SND_SOC_DAPM_PGA("Left Speaker PGA", WM8903_POWER_MANAGEMENT_5, 1, 0,
919 NULL, 0),
920SND_SOC_DAPM_PGA("Right Speaker PGA", WM8903_POWER_MANAGEMENT_5, 0, 0,
921 NULL, 0),
922
42768a12
MB		 923SND_SOC_DAPM_SUPPLY("Charge Pump", WM8903_CHARGE_PUMP_0, 0, 0,
924 wm8903_cp_event, SND_SOC_DAPM_POST_PMU),
c2aef4ff 925SND_SOC_DAPM_SUPPLY("CLK_DSP", WM8903_CLOCK_RATES_2, 1, 0, NULL, 0),
2c8be5a2 926SND_SOC_DAPM_SUPPLY("CLK_SYS", WM8903_CLOCK_RATES_2, 2, 0, NULL, 0),
f1c0a02f
MB		 927};
928
ecd01512 929static const struct snd_soc_dapm_route wm8903_intercon[] = {
f1c0a02f 930
2c8be5a2 931 { "CLK_DSP", NULL, "CLK_SYS" },
5032dc34 932 { "MICBIAS", NULL, "CLK_SYS" },
2c8be5a2
MB		 933 { "HPL_DCS", NULL, "CLK_SYS" },
934 { "HPR_DCS", NULL, "CLK_SYS" },
935 { "LINEOUTL_DCS", NULL, "CLK_SYS" },
936 { "LINEOUTR_DCS", NULL, "CLK_SYS" },
937
f1c0a02f
MB		 938 { "Left Input Mux", "IN1L", "IN1L" },
939 { "Left Input Mux", "IN2L", "IN2L" },
940 { "Left Input Mux", "IN3L", "IN3L" },
941
942 { "Left Input Inverting Mux", "IN1L", "IN1L" },
943 { "Left Input Inverting Mux", "IN2L", "IN2L" },
944 { "Left Input Inverting Mux", "IN3L", "IN3L" },
945
946 { "Right Input Mux", "IN1R", "IN1R" },
947 { "Right Input Mux", "IN2R", "IN2R" },
948 { "Right Input Mux", "IN3R", "IN3R" },
949
950 { "Right Input Inverting Mux", "IN1R", "IN1R" },
951 { "Right Input Inverting Mux", "IN2R", "IN2R" },
952 { "Right Input Inverting Mux", "IN3R", "IN3R" },
953
954 { "Left Input Mode Mux", "Single-Ended", "Left Input Inverting Mux" },
955 { "Left Input Mode Mux", "Differential Line",
956 "Left Input Mux" },
957 { "Left Input Mode Mux", "Differential Line",
958 "Left Input Inverting Mux" },
959 { "Left Input Mode Mux", "Differential Mic",
960 "Left Input Mux" },
961 { "Left Input Mode Mux", "Differential Mic",
962 "Left Input Inverting Mux" },
963
964 { "Right Input Mode Mux", "Single-Ended",
965 "Right Input Inverting Mux" },
966 { "Right Input Mode Mux", "Differential Line",
967 "Right Input Mux" },
968 { "Right Input Mode Mux", "Differential Line",
969 "Right Input Inverting Mux" },
970 { "Right Input Mode Mux", "Differential Mic",
971 "Right Input Mux" },
972 { "Right Input Mode Mux", "Differential Mic",
973 "Right Input Inverting Mux" },
974
975 { "Left Input PGA", NULL, "Left Input Mode Mux" },
976 { "Right Input PGA", NULL, "Right Input Mode Mux" },
977
97945c46
SW		 978 { "Left ADC Input", "ADC", "Left Input PGA" },
979 { "Left ADC Input", "DMIC", "DMICDAT" },
980 { "Right ADC Input", "ADC", "Right Input PGA" },
981 { "Right ADC Input", "DMIC", "DMICDAT" },
982
1e113bf9
MB		 983 { "Left Capture Mux", "Left", "ADCL" },
984 { "Left Capture Mux", "Right", "ADCR" },
985
986 { "Right Capture Mux", "Left", "ADCL" },
987 { "Right Capture Mux", "Right", "ADCR" },
988
989 { "AIFTXL", NULL, "Left Capture Mux" },
990 { "AIFTXR", NULL, "Right Capture Mux" },
991
97945c46 992 { "ADCL", NULL, "Left ADC Input" },
c2aef4ff 993 { "ADCL", NULL, "CLK_DSP" },
97945c46 994 { "ADCR", NULL, "Right ADC Input" },
c2aef4ff
MB		 995 { "ADCR", NULL, "CLK_DSP" },
996
1e113bf9
MB		 997 { "Left Playback Mux", "Left", "AIFRXL" },
998 { "Left Playback Mux", "Right", "AIFRXR" },
999
1000 { "Right Playback Mux", "Left", "AIFRXL" },
1001 { "Right Playback Mux", "Right", "AIFRXR" },
1002
291ce18c
MB		 1003 { "DACL Sidetone", "Left", "ADCL" },
1004 { "DACL Sidetone", "Right", "ADCR" },
1005 { "DACR Sidetone", "Left", "ADCL" },
1006 { "DACR Sidetone", "Right", "ADCR" },
1007
1e113bf9 1008 { "DACL", NULL, "Left Playback Mux" },
291ce18c 1009 { "DACL", NULL, "DACL Sidetone" },
c2aef4ff 1010 { "DACL", NULL, "CLK_DSP" },
1e113bf9
MB		 1011
1012 { "DACR", NULL, "Right Playback Mux" },
291ce18c 1013 { "DACR", NULL, "DACR Sidetone" },
c2aef4ff 1014 { "DACR", NULL, "CLK_DSP" },
f1c0a02f
MB		 1015
1016 { "Left Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1017 { "Left Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1018 { "Left Output Mixer", "DACL Switch", "DACL" },
1019 { "Left Output Mixer", "DACR Switch", "DACR" },
1020
1021 { "Right Output Mixer", "Left Bypass Switch", "Left Input PGA" },
1022 { "Right Output Mixer", "Right Bypass Switch", "Right Input PGA" },
1023 { "Right Output Mixer", "DACL Switch", "DACL" },
1024 { "Right Output Mixer", "DACR Switch", "DACR" },
1025
1026 { "Left Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1027 { "Left Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1028 { "Left Speaker Mixer", "DACL Switch", "DACL" },
1029 { "Left Speaker Mixer", "DACR Switch", "DACR" },
1030
1031 { "Right Speaker Mixer", "Left Bypass Switch", "Left Input PGA" },
1032 { "Right Speaker Mixer", "Right Bypass Switch", "Right Input PGA" },
1033 { "Right Speaker Mixer", "DACL Switch", "DACL" },
1034 { "Right Speaker Mixer", "DACR Switch", "DACR" },
1035
1036 { "Left Line Output PGA", NULL, "Left Output Mixer" },
1037 { "Right Line Output PGA", NULL, "Right Output Mixer" },
1038
1039 { "Left Headphone Output PGA", NULL, "Left Output Mixer" },
1040 { "Right Headphone Output PGA", NULL, "Right Output Mixer" },
1041
1042 { "Left Speaker PGA", NULL, "Left Speaker Mixer" },
1043 { "Right Speaker PGA", NULL, "Right Speaker Mixer" },
1044
1b877cb5
DL		 1045 { "HPL_ENA", NULL, "Left Headphone Output PGA" },
1046 { "HPR_ENA", NULL, "Right Headphone Output PGA" },
1047 { "HPL_ENA_DLY", NULL, "HPL_ENA" },
1048 { "HPR_ENA_DLY", NULL, "HPR_ENA" },
1049 { "LINEOUTL_ENA", NULL, "Left Line Output PGA" },
1050 { "LINEOUTR_ENA", NULL, "Right Line Output PGA" },
1051 { "LINEOUTL_ENA_DLY", NULL, "LINEOUTL_ENA" },
1052 { "LINEOUTR_ENA_DLY", NULL, "LINEOUTR_ENA" },
13a9983e 1053
c5b6a9fe
MB		 1054 { "HPL_DCS", NULL, "DCS Master" },
1055 { "HPR_DCS", NULL, "DCS Master" },
1056 { "LINEOUTL_DCS", NULL, "DCS Master" },
1057 { "LINEOUTR_DCS", NULL, "DCS Master" },
1058
13a9983e
MB		 1059 { "HPL_DCS", NULL, "HPL_ENA_DLY" },
1060 { "HPR_DCS", NULL, "HPR_ENA_DLY" },
1061 { "LINEOUTL_DCS", NULL, "LINEOUTL_ENA_DLY" },
1062 { "LINEOUTR_DCS", NULL, "LINEOUTR_ENA_DLY" },
1063
1064 { "HPL_ENA_OUTP", NULL, "HPL_DCS" },
1065 { "HPR_ENA_OUTP", NULL, "HPR_DCS" },
1066 { "LINEOUTL_ENA_OUTP", NULL, "LINEOUTL_DCS" },
1067 { "LINEOUTR_ENA_OUTP", NULL, "LINEOUTR_DCS" },
1068
1069 { "HPL_RMV_SHORT", NULL, "HPL_ENA_OUTP" },
1070 { "HPR_RMV_SHORT", NULL, "HPR_ENA_OUTP" },
1071 { "LINEOUTL_RMV_SHORT", NULL, "LINEOUTL_ENA_OUTP" },
1072 { "LINEOUTR_RMV_SHORT", NULL, "LINEOUTR_ENA_OUTP" },
1073
1074 { "HPOUTL", NULL, "HPL_RMV_SHORT" },
1075 { "HPOUTR", NULL, "HPR_RMV_SHORT" },
1076 { "LINEOUTL", NULL, "LINEOUTL_RMV_SHORT" },
1077 { "LINEOUTR", NULL, "LINEOUTR_RMV_SHORT" },
f1c0a02f
MB		 1078
1079 { "LOP", NULL, "Left Speaker PGA" },
1080 { "LON", NULL, "Left Speaker PGA" },
1081
1082 { "ROP", NULL, "Right Speaker PGA" },
1083 { "RON", NULL, "Right Speaker PGA" },
42768a12 1084
f1ca493b
AB		 1085 { "Charge Pump", NULL, "CLK_DSP" },
1086
42768a12
MB		 1087 { "Left Headphone Output PGA", NULL, "Charge Pump" },
1088 { "Right Headphone Output PGA", NULL, "Charge Pump" },
1089 { "Left Line Output PGA", NULL, "Charge Pump" },
1090 { "Right Line Output PGA", NULL, "Charge Pump" },
f1c0a02f
MB		 1091};
1092
f1c0a02f
MB		 1093static int wm8903_set_bias_level(struct snd_soc_codec *codec,
1094 enum snd_soc_bias_level level)
1095{
f1c0a02f
MB		 1096 switch (level) {
1097 case SND_SOC_BIAS_ON:
66daaa59 1098 break;
22f226dd 1099
f1c0a02f 1100 case SND_SOC_BIAS_PREPARE:
66daaa59
MB		 1101 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1102 WM8903_VMID_RES_MASK,
1103 WM8903_VMID_RES_50K);
f1c0a02f
MB		 1104 break;
1105
1106 case SND_SOC_BIAS_STANDBY:
ce6120cc 1107 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
22f226dd
MB		 1108 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1109 WM8903_POBCTRL | WM8903_ISEL_MASK |
1110 WM8903_STARTUP_BIAS_ENA |
1111 WM8903_BIAS_ENA,
1112 WM8903_POBCTRL |
1113 (2 << WM8903_ISEL_SHIFT) |
1114 WM8903_STARTUP_BIAS_ENA);
1115
1116 snd_soc_update_bits(codec,
1117 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1118 WM8903_SPK_DISCHARGE,
1119 WM8903_SPK_DISCHARGE);
1120
1121 msleep(33);
1122
1123 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1124 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1125 WM8903_SPKL_ENA | WM8903_SPKR_ENA);
1126
1127 snd_soc_update_bits(codec,
1128 WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0,
1129 WM8903_SPK_DISCHARGE, 0);
1130
1131 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1132 WM8903_VMID_TIE_ENA |
1133 WM8903_BUFIO_ENA |
1134 WM8903_VMID_IO_ENA |
1135 WM8903_VMID_SOFT_MASK |
1136 WM8903_VMID_RES_MASK |
1137 WM8903_VMID_BUF_ENA,
1138 WM8903_VMID_TIE_ENA |
1139 WM8903_BUFIO_ENA |
1140 WM8903_VMID_IO_ENA |
1141 (2 << WM8903_VMID_SOFT_SHIFT) |
1142 WM8903_VMID_RES_250K |
1143 WM8903_VMID_BUF_ENA);
1144
1145 msleep(129);
1146
1147 snd_soc_update_bits(codec, WM8903_POWER_MANAGEMENT_5,
1148 WM8903_SPKL_ENA | WM8903_SPKR_ENA,
1149 0);
1150
1151 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1152 WM8903_VMID_SOFT_MASK, 0);
1153
1154 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1155 WM8903_VMID_RES_MASK,
1156 WM8903_VMID_RES_50K);
1157
1158 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1159 WM8903_BIAS_ENA | WM8903_POBCTRL,
1160 WM8903_BIAS_ENA);
f1c0a02f 1161
f1c0a02f
MB		 1162 /* By default no bypass paths are enabled so
1163 * enable Class W support.
1164 */
f0fba2ad 1165 dev_dbg(codec->dev, "Enabling Class W\n");
524d7692
MB		 1166 snd_soc_update_bits(codec, WM8903_CLASS_W_0,
1167 WM8903_CP_DYN_FREQ |
1168 WM8903_CP_DYN_V,
1169 WM8903_CP_DYN_FREQ |
1170 WM8903_CP_DYN_V);
f1c0a02f
MB		 1171 }
1172
66daaa59
MB		 1173 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1174 WM8903_VMID_RES_MASK,
1175 WM8903_VMID_RES_250K);
f1c0a02f
MB		 1176 break;
1177
1178 case SND_SOC_BIAS_OFF:
b4d06f45
MB		 1179 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1180 WM8903_BIAS_ENA, 0);
1181
1182 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1183 WM8903_VMID_SOFT_MASK,
1184 2 << WM8903_VMID_SOFT_SHIFT);
1185
1186 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1187 WM8903_VMID_BUF_ENA, 0);
1188
1189 msleep(290);
1190
1191 snd_soc_update_bits(codec, WM8903_VMID_CONTROL_0,
1192 WM8903_VMID_TIE_ENA | WM8903_BUFIO_ENA |
1193 WM8903_VMID_IO_ENA | WM8903_VMID_RES_MASK |
1194 WM8903_VMID_SOFT_MASK |
1195 WM8903_VMID_BUF_ENA, 0);
1196
1197 snd_soc_update_bits(codec, WM8903_BIAS_CONTROL_0,
1198 WM8903_STARTUP_BIAS_ENA, 0);
f1c0a02f
MB		 1199 break;
1200 }
1201
ce6120cc 1202 codec->dapm.bias_level = level;
f1c0a02f
MB		 1203
1204 return 0;
1205}
1206
1207static int wm8903_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1208 int clk_id, unsigned int freq, int dir)
1209{
1210 struct snd_soc_codec *codec = codec_dai->codec;
b2c812e2 1211 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1212
1213 wm8903->sysclk = freq;
1214
1215 return 0;
1216}
1217
1218static int wm8903_set_dai_fmt(struct snd_soc_dai *codec_dai,
1219 unsigned int fmt)
1220{
1221 struct snd_soc_codec *codec = codec_dai->codec;
8d50e447 1222 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
f1c0a02f
MB		 1223
1224 aif1 &= ~(WM8903_LRCLK_DIR | WM8903_BCLK_DIR | WM8903_AIF_FMT_MASK |
1225 WM8903_AIF_LRCLK_INV | WM8903_AIF_BCLK_INV);
1226
1227 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1228 case SND_SOC_DAIFMT_CBS_CFS:
1229 break;
1230 case SND_SOC_DAIFMT_CBS_CFM:
1231 aif1 |= WM8903_LRCLK_DIR;
1232 break;
1233 case SND_SOC_DAIFMT_CBM_CFM:
1234 aif1 |= WM8903_LRCLK_DIR | WM8903_BCLK_DIR;
1235 break;
1236 case SND_SOC_DAIFMT_CBM_CFS:
1237 aif1 |= WM8903_BCLK_DIR;
1238 break;
1239 default:
1240 return -EINVAL;
1241 }
1242
1243 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1244 case SND_SOC_DAIFMT_DSP_A:
1245 aif1 |= 0x3;
1246 break;
1247 case SND_SOC_DAIFMT_DSP_B:
1248 aif1 |= 0x3 | WM8903_AIF_LRCLK_INV;
1249 break;
1250 case SND_SOC_DAIFMT_I2S:
1251 aif1 |= 0x2;
1252 break;
1253 case SND_SOC_DAIFMT_RIGHT_J:
1254 aif1 |= 0x1;
1255 break;
1256 case SND_SOC_DAIFMT_LEFT_J:
1257 break;
1258 default:
1259 return -EINVAL;
1260 }
1261
1262 /* Clock inversion */
1263 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1264 case SND_SOC_DAIFMT_DSP_A:
1265 case SND_SOC_DAIFMT_DSP_B:
1266 /* frame inversion not valid for DSP modes */
1267 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1268 case SND_SOC_DAIFMT_NB_NF:
1269 break;
1270 case SND_SOC_DAIFMT_IB_NF:
1271 aif1 |= WM8903_AIF_BCLK_INV;
1272 break;
1273 default:
1274 return -EINVAL;
1275 }
1276 break;
1277 case SND_SOC_DAIFMT_I2S:
1278 case SND_SOC_DAIFMT_RIGHT_J:
1279 case SND_SOC_DAIFMT_LEFT_J:
1280 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1281 case SND_SOC_DAIFMT_NB_NF:
1282 break;
1283 case SND_SOC_DAIFMT_IB_IF:
1284 aif1 |= WM8903_AIF_BCLK_INV | WM8903_AIF_LRCLK_INV;
1285 break;
1286 case SND_SOC_DAIFMT_IB_NF:
1287 aif1 |= WM8903_AIF_BCLK_INV;
1288 break;
1289 case SND_SOC_DAIFMT_NB_IF:
1290 aif1 |= WM8903_AIF_LRCLK_INV;
1291 break;
1292 default:
1293 return -EINVAL;
1294 }
1295 break;
1296 default:
1297 return -EINVAL;
1298 }
1299
8d50e447 1300 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
f1c0a02f
MB		 1301
1302 return 0;
1303}
1304
1305static int wm8903_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1306{
1307 struct snd_soc_codec *codec = codec_dai->codec;
1308 u16 reg;
1309
8d50e447 1310 reg = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f
MB		 1311
1312 if (mute)
1313 reg |= WM8903_DAC_MUTE;
1314 else
1315 reg &= ~WM8903_DAC_MUTE;
1316
8d50e447 1317 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, reg);
f1c0a02f
MB		 1318
1319 return 0;
1320}
1321
1322/* Lookup table for CLK_SYS/fs ratio. 256fs or more is recommended
1323 * for optimal performance so we list the lower rates first and match
1324 * on the last match we find. */
1325static struct {
1326 int div;
1327 int rate;
1328 int mode;
1329 int mclk_div;
1330} clk_sys_ratios[] = {
1331 { 64, 0x0, 0x0, 1 },
1332 { 68, 0x0, 0x1, 1 },
1333 { 125, 0x0, 0x2, 1 },
1334 { 128, 0x1, 0x0, 1 },
1335 { 136, 0x1, 0x1, 1 },
1336 { 192, 0x2, 0x0, 1 },
1337 { 204, 0x2, 0x1, 1 },
1338
1339 { 64, 0x0, 0x0, 2 },
1340 { 68, 0x0, 0x1, 2 },
1341 { 125, 0x0, 0x2, 2 },
1342 { 128, 0x1, 0x0, 2 },
1343 { 136, 0x1, 0x1, 2 },
1344 { 192, 0x2, 0x0, 2 },
1345 { 204, 0x2, 0x1, 2 },
1346
1347 { 250, 0x2, 0x2, 1 },
1348 { 256, 0x3, 0x0, 1 },
1349 { 272, 0x3, 0x1, 1 },
1350 { 384, 0x4, 0x0, 1 },
1351 { 408, 0x4, 0x1, 1 },
1352 { 375, 0x4, 0x2, 1 },
1353 { 512, 0x5, 0x0, 1 },
1354 { 544, 0x5, 0x1, 1 },
1355 { 500, 0x5, 0x2, 1 },
1356 { 768, 0x6, 0x0, 1 },
1357 { 816, 0x6, 0x1, 1 },
1358 { 750, 0x6, 0x2, 1 },
1359 { 1024, 0x7, 0x0, 1 },
1360 { 1088, 0x7, 0x1, 1 },
1361 { 1000, 0x7, 0x2, 1 },
1362 { 1408, 0x8, 0x0, 1 },
1363 { 1496, 0x8, 0x1, 1 },
1364 { 1536, 0x9, 0x0, 1 },
1365 { 1632, 0x9, 0x1, 1 },
1366 { 1500, 0x9, 0x2, 1 },
1367
1368 { 250, 0x2, 0x2, 2 },
1369 { 256, 0x3, 0x0, 2 },
1370 { 272, 0x3, 0x1, 2 },
1371 { 384, 0x4, 0x0, 2 },
1372 { 408, 0x4, 0x1, 2 },
1373 { 375, 0x4, 0x2, 2 },
1374 { 512, 0x5, 0x0, 2 },
1375 { 544, 0x5, 0x1, 2 },
1376 { 500, 0x5, 0x2, 2 },
1377 { 768, 0x6, 0x0, 2 },
1378 { 816, 0x6, 0x1, 2 },
1379 { 750, 0x6, 0x2, 2 },
1380 { 1024, 0x7, 0x0, 2 },
1381 { 1088, 0x7, 0x1, 2 },
1382 { 1000, 0x7, 0x2, 2 },
1383 { 1408, 0x8, 0x0, 2 },
1384 { 1496, 0x8, 0x1, 2 },
1385 { 1536, 0x9, 0x0, 2 },
1386 { 1632, 0x9, 0x1, 2 },
1387 { 1500, 0x9, 0x2, 2 },
1388};
1389
1390/* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */
1391static struct {
1392 int ratio;
1393 int div;
1394} bclk_divs[] = {
1395 { 10, 0 },
f1c0a02f
MB		 1396 { 20, 2 },
1397 { 30, 3 },
1398 { 40, 4 },
1399 { 50, 5 },
f1c0a02f
MB		 1400 { 60, 7 },
1401 { 80, 8 },
1402 { 100, 9 },
f1c0a02f
MB		 1403 { 120, 11 },
1404 { 160, 12 },
1405 { 200, 13 },
1406 { 220, 14 },
1407 { 240, 15 },
f1c0a02f
MB		 1408 { 300, 17 },
1409 { 320, 18 },
1410 { 440, 19 },
1411 { 480, 20 },
1412};
1413
1414/* Sample rates for DSP */
1415static struct {
1416 int rate;
1417 int value;
1418} sample_rates[] = {
1419 { 8000, 0 },
1420 { 11025, 1 },
1421 { 12000, 2 },
1422 { 16000, 3 },
1423 { 22050, 4 },
1424 { 24000, 5 },
1425 { 32000, 6 },
1426 { 44100, 7 },
1427 { 48000, 8 },
1428 { 88200, 9 },
1429 { 96000, 10 },
1430 { 0, 0 },
1431};
1432
f1c0a02f 1433static int wm8903_hw_params(struct snd_pcm_substream *substream,
dee89c4d
MB		 1434 struct snd_pcm_hw_params *params,
1435 struct snd_soc_dai *dai)
f1c0a02f 1436{
e6968a17 1437 struct snd_soc_codec *codec = dai->codec;
b2c812e2 1438 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f
MB		 1439 int fs = params_rate(params);
1440 int bclk;
1441 int bclk_div;
1442 int i;
1443 int dsp_config;
1444 int clk_config;
1445 int best_val;
1446 int cur_val;
1447 int clk_sys;
1448
8d50e447
MB		 1449 u16 aif1 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_1);
1450 u16 aif2 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_2);
1451 u16 aif3 = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_3);
1452 u16 clock0 = snd_soc_read(codec, WM8903_CLOCK_RATES_0);
1453 u16 clock1 = snd_soc_read(codec, WM8903_CLOCK_RATES_1);
1454 u16 dac_digital1 = snd_soc_read(codec, WM8903_DAC_DIGITAL_1);
f1c0a02f 1455
9e79261f
MB		 1456 /* Enable sloping stopband filter for low sample rates */
1457 if (fs <= 24000)
1458 dac_digital1 |= WM8903_DAC_SB_FILT;
1459 else
1460 dac_digital1 &= ~WM8903_DAC_SB_FILT;
1461
f1c0a02f
MB		 1462 /* Configure sample rate logic for DSP - choose nearest rate */
1463 dsp_config = 0;
1464 best_val = abs(sample_rates[dsp_config].rate - fs);
1465 for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1466 cur_val = abs(sample_rates[i].rate - fs);
1467 if (cur_val <= best_val) {
1468 dsp_config = i;
1469 best_val = cur_val;
1470 }
1471 }
1472
f0fba2ad 1473 dev_dbg(codec->dev, "DSP fs = %dHz\n", sample_rates[dsp_config].rate);
f1c0a02f
MB		 1474 clock1 &= ~WM8903_SAMPLE_RATE_MASK;
1475 clock1 |= sample_rates[dsp_config].value;
1476
1477 aif1 &= ~WM8903_AIF_WL_MASK;
1478 bclk = 2 * fs;
6139ea27
MB		 1479 switch (params_width(params)) {
1480 case 16:
f1c0a02f
MB		 1481 bclk *= 16;
1482 break;
6139ea27 1483 case 20:
f1c0a02f
MB		 1484 bclk *= 20;
1485 aif1 |= 0x4;
1486 break;
6139ea27 1487 case 24:
f1c0a02f
MB		 1488 bclk *= 24;
1489 aif1 |= 0x8;
1490 break;
6139ea27 1491 case 32:
f1c0a02f
MB		 1492 bclk *= 32;
1493 aif1 |= 0xc;
1494 break;
1495 default:
1496 return -EINVAL;
1497 }
1498
f0fba2ad 1499 dev_dbg(codec->dev, "MCLK = %dHz, target sample rate = %dHz\n",
f1c0a02f
MB		 1500 wm8903->sysclk, fs);
1501
1502 /* We may not have an MCLK which allows us to generate exactly
1503 * the clock we want, particularly with USB derived inputs, so
1504 * approximate.
1505 */
1506 clk_config = 0;
1507 best_val = abs((wm8903->sysclk /
1508 (clk_sys_ratios[0].mclk_div *
1509 clk_sys_ratios[0].div)) - fs);
1510 for (i = 1; i < ARRAY_SIZE(clk_sys_ratios); i++) {
1511 cur_val = abs((wm8903->sysclk /
1512 (clk_sys_ratios[i].mclk_div *
1513 clk_sys_ratios[i].div)) - fs);
1514
1515 if (cur_val <= best_val) {
1516 clk_config = i;
1517 best_val = cur_val;
1518 }
1519 }
1520
1521 if (clk_sys_ratios[clk_config].mclk_div == 2) {
1522 clock0 |= WM8903_MCLKDIV2;
1523 clk_sys = wm8903->sysclk / 2;
1524 } else {
1525 clock0 &= ~WM8903_MCLKDIV2;
1526 clk_sys = wm8903->sysclk;
1527 }
1528
1529 clock1 &= ~(WM8903_CLK_SYS_RATE_MASK |
1530 WM8903_CLK_SYS_MODE_MASK);
1531 clock1 |= clk_sys_ratios[clk_config].rate << WM8903_CLK_SYS_RATE_SHIFT;
1532 clock1 |= clk_sys_ratios[clk_config].mode << WM8903_CLK_SYS_MODE_SHIFT;
1533
f0fba2ad 1534 dev_dbg(codec->dev, "CLK_SYS_RATE=%x, CLK_SYS_MODE=%x div=%d\n",
f1c0a02f
MB		 1535 clk_sys_ratios[clk_config].rate,
1536 clk_sys_ratios[clk_config].mode,
1537 clk_sys_ratios[clk_config].div);
1538
f0fba2ad 1539 dev_dbg(codec->dev, "Actual CLK_SYS = %dHz\n", clk_sys);
f1c0a02f
MB		 1540
1541 /* We may not get quite the right frequency if using
1542 * approximate clocks so look for the closest match that is
1543 * higher than the target (we need to ensure that there enough
1544 * BCLKs to clock out the samples).
1545 */
1546 bclk_div = 0;
1547 best_val = ((clk_sys * 10) / bclk_divs[0].ratio) - bclk;
1548 i = 1;
1549 while (i < ARRAY_SIZE(bclk_divs)) {
1550 cur_val = ((clk_sys * 10) / bclk_divs[i].ratio) - bclk;
1551 if (cur_val < 0) /* BCLK table is sorted */
1552 break;
1553 bclk_div = i;
1554 best_val = cur_val;
1555 i++;
1556 }
1557
1558 aif2 &= ~WM8903_BCLK_DIV_MASK;
1559 aif3 &= ~WM8903_LRCLK_RATE_MASK;
1560
f0fba2ad 1561 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n",
f1c0a02f
MB		 1562 bclk_divs[bclk_div].ratio / 10, bclk,
1563 (clk_sys * 10) / bclk_divs[bclk_div].ratio);
1564
1565 aif2 |= bclk_divs[bclk_div].div;
1566 aif3 |= bclk / fs;
1567
69fff9bb
MB		 1568 wm8903->fs = params_rate(params);
1569 wm8903_set_deemph(codec);
1570
8d50e447
MB		 1571 snd_soc_write(codec, WM8903_CLOCK_RATES_0, clock0);
1572 snd_soc_write(codec, WM8903_CLOCK_RATES_1, clock1);
1573 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_1, aif1);
1574 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_2, aif2);
1575 snd_soc_write(codec, WM8903_AUDIO_INTERFACE_3, aif3);
1576 snd_soc_write(codec, WM8903_DAC_DIGITAL_1, dac_digital1);
f1c0a02f
MB		 1577
1578 return 0;
1579}
1580
7245387e
MB		 1581/**
1582 * wm8903_mic_detect - Enable microphone detection via the WM8903 IRQ
1583 *
1584 * @codec: WM8903 codec
1585 * @jack: jack to report detection events on
1586 * @det: value to report for presence detection
1587 * @shrt: value to report for short detection
1588 *
1589 * Enable microphone detection via IRQ on the WM8903. If GPIOs are
1590 * being used to bring out signals to the processor then only platform
1591 * data configuration is needed for WM8903 and processor GPIOs should
1592 * be configured using snd_soc_jack_add_gpios() instead.
1593 *
1594 * The current threasholds for detection should be configured using
1595 * micdet_cfg in the platform data. Using this function will force on
1596 * the microphone bias for the device.
1597 */
1598int wm8903_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
1599 int det, int shrt)
1600{
b2c812e2 1601 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
69266866 1602 int irq_mask = WM8903_MICDET_EINT | WM8903_MICSHRT_EINT;
7245387e
MB		 1603
1604 dev_dbg(codec->dev, "Enabling microphone detection: %x %x\n",
1605 det, shrt);
1606
1607 /* Store the configuration */
1608 wm8903->mic_jack = jack;
1609 wm8903->mic_det = det;
1610 wm8903->mic_short = shrt;
1611
1612 /* Enable interrupts we've got a report configured for */
1613 if (det)
1614 irq_mask &= ~WM8903_MICDET_EINT;
1615 if (shrt)
1616 irq_mask &= ~WM8903_MICSHRT_EINT;
1617
1618 snd_soc_update_bits(codec, WM8903_INTERRUPT_STATUS_1_MASK,
1619 WM8903_MICDET_EINT | WM8903_MICSHRT_EINT,
1620 irq_mask);
1621
3088e3b4 1622 if (det || shrt) {
69266866
MB		 1623 /* Enable mic detection, this may not have been set through
1624 * platform data (eg, if the defaults are OK). */
1625 snd_soc_update_bits(codec, WM8903_WRITE_SEQUENCER_0,
1626 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
1627 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1628 WM8903_MICDET_ENA, WM8903_MICDET_ENA);
1629 } else {
1630 snd_soc_update_bits(codec, WM8903_MIC_BIAS_CONTROL_0,
1631 WM8903_MICDET_ENA, 0);
1632 }
7245387e
MB		 1633
1634 return 0;
1635}
1636EXPORT_SYMBOL_GPL(wm8903_mic_detect);
1637
8abd16a6
MB		 1638static irqreturn_t wm8903_irq(int irq, void *data)
1639{
e373cbfb
MB		 1640 struct wm8903_priv *wm8903 = data;
1641 int mic_report, ret;
1642 unsigned int int_val, mask, int_pol;
8abd16a6 1643
e373cbfb
MB		 1644 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1_MASK,
1645 &mask);
1646 if (ret != 0) {
1647 dev_err(wm8903->dev, "Failed to read IRQ mask: %d\n", ret);
1648 return IRQ_NONE;
1649 }
1650
1651 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_STATUS_1, &int_val);
1652 if (ret != 0) {
1653 dev_err(wm8903->dev, "Failed to read IRQ status: %d\n", ret);
1654 return IRQ_NONE;
1655 }
1656
1657 int_val &= ~mask;
8abd16a6 1658
7245387e 1659 if (int_val & WM8903_WSEQ_BUSY_EINT) {
e373cbfb 1660 dev_warn(wm8903->dev, "Write sequencer done\n");
8abd16a6
MB		 1661 }
1662
7245387e
MB		 1663 /*
1664 * The rest is microphone jack detection. We need to manually
1665 * invert the polarity of the interrupt after each event - to
1666 * simplify the code keep track of the last state we reported
1667 * and just invert the relevant bits in both the report and
1668 * the polarity register.
1669 */
1670 mic_report = wm8903->mic_last_report;
e373cbfb
MB		 1671 ret = regmap_read(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1672 &int_pol);
1673 if (ret != 0) {
1674 dev_err(wm8903->dev, "Failed to read interrupt polarity: %d\n",
1675 ret);
1676 return IRQ_HANDLED;
1677 }
7245387e 1678
1435b940 1679#ifndef CONFIG_SND_SOC_WM8903_MODULE
2bbb5d66 1680 if (int_val & (WM8903_MICSHRT_EINT | WM8903_MICDET_EINT))
e373cbfb 1681 trace_snd_soc_jack_irq(dev_name(wm8903->dev));
1435b940 1682#endif
2bbb5d66 1683
7245387e 1684 if (int_val & WM8903_MICSHRT_EINT) {
e373cbfb 1685 dev_dbg(wm8903->dev, "Microphone short (pol=%x)\n", int_pol);
7245387e
MB		 1686
1687 mic_report ^= wm8903->mic_short;
1688 int_pol ^= WM8903_MICSHRT_INV;
1689 }
1690
1691 if (int_val & WM8903_MICDET_EINT) {
e373cbfb 1692 dev_dbg(wm8903->dev, "Microphone detect (pol=%x)\n", int_pol);
7245387e
MB		 1693
1694 mic_report ^= wm8903->mic_det;
1695 int_pol ^= WM8903_MICDET_INV;
1696
1697 msleep(wm8903->mic_delay);
1698 }
1699
e373cbfb
MB		 1700 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_POLARITY_1,
1701 WM8903_MICSHRT_INV | WM8903_MICDET_INV, int_pol);
7245387e
MB		 1702
1703 snd_soc_jack_report(wm8903->mic_jack, mic_report,
1704 wm8903->mic_short | wm8903->mic_det);
1705
1706 wm8903->mic_last_report = mic_report;
1707
8abd16a6
MB		 1708 return IRQ_HANDLED;
1709}
1710
f1c0a02f
MB		 1711#define WM8903_PLAYBACK_RATES (SNDRV_PCM_RATE_8000 |\
1712 SNDRV_PCM_RATE_11025 | \
1713 SNDRV_PCM_RATE_16000 | \
1714 SNDRV_PCM_RATE_22050 | \
1715 SNDRV_PCM_RATE_32000 | \
1716 SNDRV_PCM_RATE_44100 | \
1717 SNDRV_PCM_RATE_48000 | \
1718 SNDRV_PCM_RATE_88200 | \
1719 SNDRV_PCM_RATE_96000)
1720
1721#define WM8903_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\
1722 SNDRV_PCM_RATE_11025 | \
1723 SNDRV_PCM_RATE_16000 | \
1724 SNDRV_PCM_RATE_22050 | \
1725 SNDRV_PCM_RATE_32000 | \
1726 SNDRV_PCM_RATE_44100 | \
1727 SNDRV_PCM_RATE_48000)
1728
1729#define WM8903_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1730 SNDRV_PCM_FMTBIT_S20_3LE |\
1731 SNDRV_PCM_FMTBIT_S24_LE)
1732
85e7652d 1733static const struct snd_soc_dai_ops wm8903_dai_ops = {
6335d055
EM		 1734 .hw_params = wm8903_hw_params,
1735 .digital_mute = wm8903_digital_mute,
1736 .set_fmt = wm8903_set_dai_fmt,
1737 .set_sysclk = wm8903_set_dai_sysclk,
1738};
1739
f0fba2ad
LG		 1740static struct snd_soc_dai_driver wm8903_dai = {
1741 .name = "wm8903-hifi",
f1c0a02f
MB		 1742 .playback = {
1743 .stream_name = "Playback",
1744 .channels_min = 2,
1745 .channels_max = 2,
1746 .rates = WM8903_PLAYBACK_RATES,
1747 .formats = WM8903_FORMATS,
1748 },
1749 .capture = {
1750 .stream_name = "Capture",
1751 .channels_min = 2,
1752 .channels_max = 2,
1753 .rates = WM8903_CAPTURE_RATES,
1754 .formats = WM8903_FORMATS,
1755 },
6335d055 1756 .ops = &wm8903_dai_ops,
0d960e88 1757 .symmetric_rates = 1,
f1c0a02f 1758};
f1c0a02f 1759
84b315ee 1760static int wm8903_suspend(struct snd_soc_codec *codec)
f1c0a02f 1761{
f1c0a02f
MB		 1762 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
1763
1764 return 0;
1765}
1766
f0fba2ad 1767static int wm8903_resume(struct snd_soc_codec *codec)
f1c0a02f 1768{
45e96755 1769 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f 1770
ee244ce4 1771 regcache_sync(wm8903->regmap);
f1c0a02f 1772
45e96755 1773 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
f1c0a02f
MB		 1774
1775 return 0;
1776}
1777
7cfe5617
SW		 1778#ifdef CONFIG_GPIOLIB
1779static inline struct wm8903_priv *gpio_to_wm8903(struct gpio_chip *chip)
1780{
1781 return container_of(chip, struct wm8903_priv, gpio_chip);
1782}
1783
1784static int wm8903_gpio_request(struct gpio_chip *chip, unsigned offset)
1785{
1786 if (offset >= WM8903_NUM_GPIO)
1787 return -EINVAL;
1788
1789 return 0;
1790}
1791
1792static int wm8903_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
1793{
1794 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
7cfe5617 1795 unsigned int mask, val;
385bd937 1796 int ret;
7cfe5617
SW		 1797
1798 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK;
1799 val = (WM8903_GPn_FN_GPIO_INPUT << WM8903_GP1_FN_SHIFT) |
1800 WM8903_GP1_DIR;
1801
0bf79ef2
SW		 1802 ret = regmap_update_bits(wm8903->regmap,
1803 WM8903_GPIO_CONTROL_1 + offset, mask, val);
385bd937
AL		 1804 if (ret < 0)
1805 return ret;
1806
1807 return 0;
7cfe5617
SW		 1808}
1809
1810static int wm8903_gpio_get(struct gpio_chip *chip, unsigned offset)
1811{
1812 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
0bf79ef2 1813 unsigned int reg;
7cfe5617 1814
0bf79ef2 1815 regmap_read(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset, &reg);
7cfe5617
SW		 1816
1817 return (reg & WM8903_GP1_LVL_MASK) >> WM8903_GP1_LVL_SHIFT;
1818}
1819
1820static int wm8903_gpio_direction_out(struct gpio_chip *chip,
1821 unsigned offset, int value)
1822{
1823 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
7cfe5617 1824 unsigned int mask, val;
385bd937 1825 int ret;
7cfe5617
SW		 1826
1827 mask = WM8903_GP1_FN_MASK | WM8903_GP1_DIR_MASK | WM8903_GP1_LVL_MASK;
1828 val = (WM8903_GPn_FN_GPIO_OUTPUT << WM8903_GP1_FN_SHIFT) |
1829 (value << WM8903_GP2_LVL_SHIFT);
1830
0bf79ef2
SW		 1831 ret = regmap_update_bits(wm8903->regmap,
1832 WM8903_GPIO_CONTROL_1 + offset, mask, val);
385bd937
AL		 1833 if (ret < 0)
1834 return ret;
1835
1836 return 0;
7cfe5617
SW		 1837}
1838
1839static void wm8903_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1840{
1841 struct wm8903_priv *wm8903 = gpio_to_wm8903(chip);
7cfe5617 1842
0bf79ef2
SW		 1843 regmap_update_bits(wm8903->regmap, WM8903_GPIO_CONTROL_1 + offset,
1844 WM8903_GP1_LVL_MASK,
1845 !!value << WM8903_GP1_LVL_SHIFT);
7cfe5617
SW		 1846}
1847
1848static struct gpio_chip wm8903_template_chip = {
1849 .label = "wm8903",
1850 .owner = THIS_MODULE,
1851 .request = wm8903_gpio_request,
1852 .direction_input = wm8903_gpio_direction_in,
1853 .get = wm8903_gpio_get,
1854 .direction_output = wm8903_gpio_direction_out,
1855 .set = wm8903_gpio_set,
1856 .can_sleep = 1,
1857};
1858
0bf79ef2 1859static void wm8903_init_gpio(struct wm8903_priv *wm8903)
7cfe5617 1860{
c0eb27cf 1861 struct wm8903_platform_data *pdata = wm8903->pdata;
7cfe5617
SW		 1862 int ret;
1863
1864 wm8903->gpio_chip = wm8903_template_chip;
1865 wm8903->gpio_chip.ngpio = WM8903_NUM_GPIO;
0bf79ef2 1866 wm8903->gpio_chip.dev = wm8903->dev;
7cfe5617 1867
db817784 1868 if (pdata->gpio_base)
7cfe5617
SW		 1869 wm8903->gpio_chip.base = pdata->gpio_base;
1870 else
1871 wm8903->gpio_chip.base = -1;
1872
1873 ret = gpiochip_add(&wm8903->gpio_chip);
1874 if (ret != 0)
0bf79ef2 1875 dev_err(wm8903->dev, "Failed to add GPIOs: %d\n", ret);
7cfe5617
SW		 1876}
1877
0bf79ef2 1878static void wm8903_free_gpio(struct wm8903_priv *wm8903)
7cfe5617 1879{
88d5e520 1880 gpiochip_remove(&wm8903->gpio_chip);
7cfe5617
SW		 1881}
1882#else
0bf79ef2 1883static void wm8903_init_gpio(struct wm8903_priv *wm8903)
7cfe5617
SW		 1884{
1885}
1886
0bf79ef2 1887static void wm8903_free_gpio(struct wm8903_priv *wm8903)
7cfe5617
SW		 1888{
1889}
1890#endif
1891
f0fba2ad 1892static int wm8903_probe(struct snd_soc_codec *codec)
f1c0a02f 1893{
f0fba2ad 1894 struct wm8903_priv *wm8903 = snd_soc_codec_get_drvdata(codec);
f1c0a02f 1895
7cfe5617 1896 wm8903->codec = codec;
8d50e447 1897
f1c0a02f
MB		 1898 /* power on device */
1899 wm8903_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1900
5d6be5aa 1901 return 0;
f1c0a02f
MB		 1902}
1903
f0fba2ad
LG		 1904/* power down chip */
1905static int wm8903_remove(struct snd_soc_codec *codec)
f1c0a02f 1906{
f0fba2ad 1907 wm8903_set_bias_level(codec, SND_SOC_BIAS_OFF);
f99847a6 1908
f0fba2ad
LG		 1909 return 0;
1910}
f1c0a02f 1911
f0fba2ad
LG		 1912static struct snd_soc_codec_driver soc_codec_dev_wm8903 = {
1913 .probe = wm8903_probe,
1914 .remove = wm8903_remove,
1915 .suspend = wm8903_suspend,
1916 .resume = wm8903_resume,
1917 .set_bias_level = wm8903_set_bias_level,
c5b6a9fe 1918 .seq_notifier = wm8903_seq_notifier,
f4a10837
MB		 1919 .controls = wm8903_snd_controls,
1920 .num_controls = ARRAY_SIZE(wm8903_snd_controls),
ecd01512
MB		 1921 .dapm_widgets = wm8903_dapm_widgets,
1922 .num_dapm_widgets = ARRAY_SIZE(wm8903_dapm_widgets),
1923 .dapm_routes = wm8903_intercon,
1924 .num_dapm_routes = ARRAY_SIZE(wm8903_intercon),
f0fba2ad 1925};
f1c0a02f 1926
ee244ce4
MB		 1927static const struct regmap_config wm8903_regmap = {
1928 .reg_bits = 8,
1929 .val_bits = 16,
1930
1931 .max_register = WM8903_MAX_REGISTER,
1932 .volatile_reg = wm8903_volatile_register,
1933 .readable_reg = wm8903_readable_register,
1934
1935 .cache_type = REGCACHE_RBTREE,
1936 .reg_defaults = wm8903_reg_defaults,
1937 .num_reg_defaults = ARRAY_SIZE(wm8903_reg_defaults),
1938};
1939
9d35f3e1
SW		 1940static int wm8903_set_pdata_irq_trigger(struct i2c_client *i2c,
1941 struct wm8903_platform_data *pdata)
1942{
1943 struct irq_data *irq_data = irq_get_irq_data(i2c->irq);
1944 if (!irq_data) {
1945 dev_err(&i2c->dev, "Invalid IRQ: %d\n",
1946 i2c->irq);
1947 return -EINVAL;
1948 }
1949
1950 switch (irqd_get_trigger_type(irq_data)) {
1951 case IRQ_TYPE_NONE:
6664ee11 1952 default:
9d35f3e1
SW		 1953 /*
1954 * We assume the controller imposes no restrictions,
1955 * so we are able to select active-high
1956 */
1957 /* Fall-through */
1958 case IRQ_TYPE_LEVEL_HIGH:
1959 pdata->irq_active_low = false;
1960 break;
1961 case IRQ_TYPE_LEVEL_LOW:
1962 pdata->irq_active_low = true;
1963 break;
9d35f3e1
SW		 1964 }
1965
1966 return 0;
1967}
1968
5d680b3a
SW		 1969static int wm8903_set_pdata_from_of(struct i2c_client *i2c,
1970 struct wm8903_platform_data *pdata)
1971{
1972 const struct device_node *np = i2c->dev.of_node;
1973 u32 val32;
1974 int i;
1975
1976 if (of_property_read_u32(np, "micdet-cfg", &val32) >= 0)
1977 pdata->micdet_cfg = val32;
1978
1979 if (of_property_read_u32(np, "micdet-delay", &val32) >= 0)
1980 pdata->micdet_delay = val32;
1981
1982 if (of_property_read_u32_array(np, "gpio-cfg", pdata->gpio_cfg,
1983 ARRAY_SIZE(pdata->gpio_cfg)) >= 0) {
1984 /*
1985 * In device tree: 0 means "write 0",
1986 * 0xffffffff means "don't touch".
1987 *
1988 * In platform data: 0 means "don't touch",
1989 * 0x8000 means "write 0".
1990 *
1991 * Note: WM8903_GPIO_CONFIG_ZERO == 0x8000.
1992 *
1993 * Convert from DT to pdata representation here,
1994 * so no other code needs to change.
1995 */
1996 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
1997 if (pdata->gpio_cfg[i] == 0) {
1998 pdata->gpio_cfg[i] = WM8903_GPIO_CONFIG_ZERO;
1999 } else if (pdata->gpio_cfg[i] == 0xffffffff) {
2000 pdata->gpio_cfg[i] = 0;
2001 } else if (pdata->gpio_cfg[i] > 0x7fff) {
2002 dev_err(&i2c->dev, "Invalid gpio-cfg[%d] %x\n",
2003 i, pdata->gpio_cfg[i]);
2004 return -EINVAL;
2005 }
2006 }
2007 }
2008
2009 return 0;
2010}
2011
7a79e94e
BP		 2012static int wm8903_i2c_probe(struct i2c_client *i2c,
2013 const struct i2c_device_id *id)
f0fba2ad 2014{
c0eb27cf 2015 struct wm8903_platform_data *pdata = dev_get_platdata(&i2c->dev);
f0fba2ad 2016 struct wm8903_priv *wm8903;
b7c95d91 2017 int trigger;
20c5fd39 2018 bool mic_gpio = false;
b7c95d91 2019 unsigned int val, irq_pol;
20c5fd39 2020 int ret, i;
f1c0a02f 2021
2950cd22
MB		 2022 wm8903 = devm_kzalloc(&i2c->dev, sizeof(struct wm8903_priv),
2023 GFP_KERNEL);
f0fba2ad
LG		 2024 if (wm8903 == NULL)
2025 return -ENOMEM;
0bf79ef2 2026 wm8903->dev = &i2c->dev;
8abd16a6 2027
7d116684 2028 wm8903->regmap = devm_regmap_init_i2c(i2c, &wm8903_regmap);
ee244ce4
MB		 2029 if (IS_ERR(wm8903->regmap)) {
2030 ret = PTR_ERR(wm8903->regmap);
2031 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2032 ret);
2033 return ret;
2034 }
2035
f0fba2ad 2036 i2c_set_clientdata(i2c, wm8903);
d58d5d55 2037
c0eb27cf
SW		 2038 /* If no platform data was supplied, create storage for defaults */
2039 if (pdata) {
2040 wm8903->pdata = pdata;
2041 } else {
2042 wm8903->pdata = devm_kzalloc(&i2c->dev,
2043 sizeof(struct wm8903_platform_data),
2044 GFP_KERNEL);
2045 if (wm8903->pdata == NULL) {
2046 dev_err(&i2c->dev, "Failed to allocate pdata\n");
2047 return -ENOMEM;
2048 }
9d35f3e1
SW		 2049
2050 if (i2c->irq) {
2051 ret = wm8903_set_pdata_irq_trigger(i2c, wm8903->pdata);
2052 if (ret != 0)
2053 return ret;
2054 }
5d680b3a
SW		 2055
2056 if (i2c->dev.of_node) {
2057 ret = wm8903_set_pdata_from_of(i2c, wm8903->pdata);
2058 if (ret != 0)
2059 return ret;
2060 }
c0eb27cf
SW		 2061 }
2062
20c5fd39
MB		 2063 pdata = wm8903->pdata;
2064
7d46a528
MB		 2065 ret = regmap_read(wm8903->regmap, WM8903_SW_RESET_AND_ID, &val);
2066 if (ret != 0) {
2067 dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
2068 goto err;
2069 }
2070 if (val != 0x8903) {
2071 dev_err(&i2c->dev, "Device with ID %x is not a WM8903\n", val);
2072 ret = -ENODEV;
2073 goto err;
2074 }
2075
2076 ret = regmap_read(wm8903->regmap, WM8903_REVISION_NUMBER, &val);
2077 if (ret != 0) {
2078 dev_err(&i2c->dev, "Failed to read chip revision: %d\n", ret);
2079 goto err;
2080 }
2081 dev_info(&i2c->dev, "WM8903 revision %c\n",
2082 (val & WM8903_CHIP_REV_MASK) + 'A');
2083
2084 /* Reset the device */
2085 regmap_write(wm8903->regmap, WM8903_SW_RESET_AND_ID, 0x8903);
2086
0bf79ef2
SW		 2087 wm8903_init_gpio(wm8903);
2088
20c5fd39
MB		 2089 /* Set up GPIO pin state, detect if any are MIC detect outputs */
2090 for (i = 0; i < ARRAY_SIZE(pdata->gpio_cfg); i++) {
2091 if ((!pdata->gpio_cfg[i]) ||
2092 (pdata->gpio_cfg[i] > WM8903_GPIO_CONFIG_ZERO))
2093 continue;
2094
2095 regmap_write(wm8903->regmap, WM8903_GPIO_CONTROL_1 + i,
2096 pdata->gpio_cfg[i] & 0x7fff);
2097
2098 val = (pdata->gpio_cfg[i] & WM8903_GP1_FN_MASK)
2099 >> WM8903_GP1_FN_SHIFT;
2100
2101 switch (val) {
2102 case WM8903_GPn_FN_MICBIAS_CURRENT_DETECT:
2103 case WM8903_GPn_FN_MICBIAS_SHORT_DETECT:
2104 mic_gpio = true;
2105 break;
2106 default:
2107 break;
2108 }
2109 }
2110
2111 /* Set up microphone detection */
2112 regmap_write(wm8903->regmap, WM8903_MIC_BIAS_CONTROL_0,
2113 pdata->micdet_cfg);
2114
2115 /* Microphone detection needs the WSEQ clock */
2116 if (pdata->micdet_cfg)
2117 regmap_update_bits(wm8903->regmap, WM8903_WRITE_SEQUENCER_0,
2118 WM8903_WSEQ_ENA, WM8903_WSEQ_ENA);
2119
2120 /* If microphone detection is enabled by pdata but
2121 * detected via IRQ then interrupts can be lost before
2122 * the machine driver has set up microphone detection
2123 * IRQs as the IRQs are clear on read. The detection
2124 * will be enabled when the machine driver configures.
2125 */
2126 WARN_ON(!mic_gpio && (pdata->micdet_cfg & WM8903_MICDET_ENA));
2127
2128 wm8903->mic_delay = pdata->micdet_delay;
2129
b7c95d91
MB		 2130 if (i2c->irq) {
2131 if (pdata->irq_active_low) {
2132 trigger = IRQF_TRIGGER_LOW;
2133 irq_pol = WM8903_IRQ_POL;
2134 } else {
2135 trigger = IRQF_TRIGGER_HIGH;
2136 irq_pol = 0;
2137 }
2138
2139 regmap_update_bits(wm8903->regmap, WM8903_INTERRUPT_CONTROL,
2140 WM8903_IRQ_POL, irq_pol);
2141
2142 ret = request_threaded_irq(i2c->irq, NULL, wm8903_irq,
2143 trigger | IRQF_ONESHOT,
2144 "wm8903", wm8903);
2145 if (ret != 0) {
2146 dev_err(wm8903->dev, "Failed to request IRQ: %d\n",
2147 ret);
2148 return ret;
2149 }
2150
2151 /* Enable write sequencer interrupts */
2152 regmap_update_bits(wm8903->regmap,
2153 WM8903_INTERRUPT_STATUS_1_MASK,
2154 WM8903_IM_WSEQ_BUSY_EINT, 0);
2155 }
2156
a89c3e95
MB		 2157 /* Latch volume update bits */
2158 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_LEFT,
2159 WM8903_ADCVU, WM8903_ADCVU);
2160 regmap_update_bits(wm8903->regmap, WM8903_ADC_DIGITAL_VOLUME_RIGHT,
2161 WM8903_ADCVU, WM8903_ADCVU);
2162
2163 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_LEFT,
2164 WM8903_DACVU, WM8903_DACVU);
2165 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_VOLUME_RIGHT,
2166 WM8903_DACVU, WM8903_DACVU);
2167
2168 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_LEFT,
2169 WM8903_HPOUTVU, WM8903_HPOUTVU);
2170 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT1_RIGHT,
2171 WM8903_HPOUTVU, WM8903_HPOUTVU);
2172
2173 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_LEFT,
2174 WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2175 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT2_RIGHT,
2176 WM8903_LINEOUTVU, WM8903_LINEOUTVU);
2177
2178 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_LEFT,
2179 WM8903_SPKVU, WM8903_SPKVU);
2180 regmap_update_bits(wm8903->regmap, WM8903_ANALOGUE_OUT3_RIGHT,
2181 WM8903_SPKVU, WM8903_SPKVU);
2182
2183 /* Enable DAC soft mute by default */
2184 regmap_update_bits(wm8903->regmap, WM8903_DAC_DIGITAL_1,
2185 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE,
2186 WM8903_DAC_MUTEMODE | WM8903_DAC_MUTE);
2187
f0fba2ad
LG		 2188 ret = snd_soc_register_codec(&i2c->dev,
2189 &soc_codec_dev_wm8903, &wm8903_dai, 1);
ee244ce4
MB		 2190 if (ret != 0)
2191 goto err;
2950cd22 2192
ee244ce4
MB		 2193 return 0;
2194err:
f0fba2ad
LG		 2195 return ret;
2196}
f1c0a02f 2197
7a79e94e 2198static int wm8903_i2c_remove(struct i2c_client *client)
f0fba2ad 2199{
ee244ce4
MB		 2200 struct wm8903_priv *wm8903 = i2c_get_clientdata(client);
2201
b7c95d91
MB		 2202 if (client->irq)
2203 free_irq(client->irq, wm8903);
0bf79ef2 2204 wm8903_free_gpio(wm8903);
f0fba2ad 2205 snd_soc_unregister_codec(&client->dev);
ee244ce4 2206
f1c0a02f
MB		 2207 return 0;
2208}
2209
f18b4e2e
SW		 2210static const struct of_device_id wm8903_of_match[] = {
2211 { .compatible = "wlf,wm8903", },
2212 {},
2213};
2214MODULE_DEVICE_TABLE(of, wm8903_of_match);
2215
f1c0a02f 2216static const struct i2c_device_id wm8903_i2c_id[] = {
f0fba2ad
LG		 2217 { "wm8903", 0 },
2218 { }
f1c0a02f
MB		 2219};
2220MODULE_DEVICE_TABLE(i2c, wm8903_i2c_id);
2221
2222static struct i2c_driver wm8903_i2c_driver = {
2223 .driver = {
4b592c91 2224 .name = "wm8903",
f1c0a02f 2225 .owner = THIS_MODULE,
f18b4e2e 2226 .of_match_table = wm8903_of_match,
f1c0a02f 2227 },
f0fba2ad 2228 .probe = wm8903_i2c_probe,
7a79e94e 2229 .remove = wm8903_i2c_remove,
f1c0a02f
MB		 2230 .id_table = wm8903_i2c_id,
2231};
2232
5c86ea44 2233module_i2c_driver(wm8903_i2c_driver);
64089b84 2234
f1c0a02f
MB		 2235MODULE_DESCRIPTION("ASoC WM8903 driver");
2236MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.cm>");
2237MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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